Coding method, decoding method, coder, and decoder

This application is based on Japanese Patent Applications No. 2012-223569, No. 2012-223570, No. 2012-223571, No. 2012-223572, and No. 2012-223573, the contents of which are hereby incorporated by reference.

The present invention relates to an encoding method, a decoding method, an encoder, and a decoder using low-density parity check convolutional codes (LDPC-CCs) having coding rates no smaller than 1/2 and not satisfying (n−1)/n (where n is an integer no smaller than two), and LDPC-CCs using improved tail-biting schemes (LDPC block codes using LDPC-CC).

In recent years, attention has been attracted to a low-density parity-check (LDPC) code as an error correction code that provides high error correction capability with a feasible circuit scale. Because of its high error correction capability and ease of implementation, an LDPC code has been adopted in an error correction coding scheme for IEEE802.11n high-speed wireless LAN systems, digital broadcasting systems, and so forth.

An LDPC code is an error correction code defined by low-density parity check matrix H. Furthermore, the LDPC code is a block code having the same block length as the number of columns N of check matrix H (see Non-Patent Literature 1, Non-Patent Literature 2, Non-Patent Literature 3). For example, random LDPC code, QC-LDPC code (QC: Quasi-Cyclic) are proposed.

Studies are being carried out on LDPC-CC (Low-Density Parity Check Convolutional Codes) capable of performing encoding or decoding on an information sequence of an arbitrary length for LDPC code (hereinafter, LDPC-BC: Low-Density Parity Check Block Code) of a block code (e.g. see Non-Patent Literature 4 and Non-Patent Literature 5).

LDPC-CC is a convolutional code defined by a low-density parity check matrix. For example, parity check matrix H T [0, n] of LDPC-CC having a coding rate of R=1/2 (=b/c) is shown in FIG. 1 . Here, element h 1 (m) (t) of H T [0, n] takes zero or one. All elements other than h 1 (m) (t) are zeroes. M represents the LDPC-CC memory length, and n represents the length of an LDPC-CC codeword. As shown in FIG. 1 , a characteristic of an LDPC-CC check matrix is that it is a parallelogram-shaped matrix in which ones are placed only in diagonal terms of the matrix and neighboring elements, and the bottom-left and top-right elements of the matrix are zero.

An LDPC-CC encoder defined by parity check matrix H T [0, n] where h 1 (0) (t)=1 and h 2 (0) (t)=1 is represented by FIG. 2 . As shown in FIG. 2 , an LDPC-CC encoder is formed with 2×(M+1) shift registers having a bit length of c and a mod 2 adder (exclusive OR operator). Thus, a feature of the LDPC-CC encoder is that it can be realized with a very simple circuit compared to a circuit that performs multiplication of a generator matrix or an LDPC-BC encoder that performs calculation based on a backward (forward) substitution method. Also, since the encoder in FIG. 2 is a convolutional code encoder, it is not necessary to divide an information sequence into fixed-length blocks when encoding, and an information sequence of any length can be encoded.

Patent Literatures 1 and 2 describe an LDPC-CC generating method based on a parity check polynomial. In particular, Patent Literature 1 describes a method of generating an LDPC-CC using parity check polynomials having a time-varying period of two, a time-varying period of three, a time-varying period of four, and a time-varying period of a multiple of three. In particular, Patent Literature 2 describes a relationship between time-varying periods and parity check polynomials.

Patent Literature

[Patent Literature 1]

Japanese Patent Application Publication No. 2009-246926

[Patent Literature 2]

International Application WO 2011/058760

Non-Patent Literature

[Non-Patent Literature 1]

R. G. Gallager, “Low-density parity check codes,” IRE Trans. Inform. Theory, IT-8, pp. 21-28, 1962.

[Non-Patent Literature 2]

D. J. C. Mackay, “Good error-correcting codes based on very sparse matrices,” IEEE Trans. Inform. Theory, vol. 45, no. 2, pp. 399-431, March 1999.

[Non-Patent Literature 3]

M. P. C. Fossorier, “Quasi-cyclic low-density parity-check codes from circulant permutation matrices,” IEEE Trans. Inform. Theory, vol. 50, no. 8, pp. 1788-1793, November 2001.

[Non-Patent Literature 4]

A. J. Feltstrom, and K. S. Zigangirov, “Time-varying periodic convolutional codes with low-density parity-check matrix,” IEEE Trans. Inform. Theory, vol. 45, no. 6, pp. 2181-2191, September 1999.

[Non-Patent Literature 5]

R. M. Tanner, D. Sridhara, A. Sridharan, T. E. Fuja, and D. J. Costello Jr., “LDPC block and convolutional codes based on circulant matrices,” IEEE Trans. Inform. Theory, vol. 50, no. 12, pp. 2966-2984, December 2004.

[Non-Patent Literature 6]

M. P. C. Fossorier, M. Mihaljevic, and H. Imai, “Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,” IEEE Trans. Commun., vol. 47, no. 5, pp. 673-680, May 1999.

[Non-Patent Literature 7]

J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and X.-Yu Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun., vol. 53, no. 8, pp. 1288-1299, August 2005.

[Non-Patent Literature 8]

J. Zhang, and M. P. C. Fossorier, “Shuffled iterative decoding,” IEEE Trans. Commun., vol. 53, no. 2, pp. 209-213, February 2005.

[Non-Patent Literature 9]

G. Miller, and D. Burshtein, “Bounds on the maximum likelihood decoding error probability of low-density parity check codes,” IEEE Trans. Inf. Theory, vol. 47, no. 7, pp. 2696-2710, November 2001.

[Non-Patent Literature 10]

R. G. Gallager, “A simple derivation of the coding theorem and some applications,” IEEE Trans. Inf. Theory, vol. IT-11, no. 1, pp. 3-18, January 1965.

[Non-Patent Literature 11]

A. J. Viterbi, “Error bounds for convolutional codes and an asymptotically optimum decoding algorithm,” IEEE Trans. Inf. Theory, vol. IT-13, no. 2, pp. 260-269, April 1967.

[Non-Patent Literature 12]

A. J. Viterbi, and J. K. Omura, “Principles of digital communication and coding,” McGraw-Hill, New York, 1979.

[Non-Patent Literature 13]

Y. Murakami, S. Okamura, S. Okasaka, T. Kishigami, and M. Orihashi, “LDPC convolutional codes based on parity check polynomials with time period of 3,” IEICE Trans. Fundamentals, vol. E-92, no. 10, pp. 2479-2483, October 2009.

[Non-Patent Literature 14]

M. B. S. Tavares, K. S. Zigangirov, and G. P. Fettweis, “Tail-biting LDPC convolutional codes,” Proc. of IEEE ISIT 2007, pp. 2341-2345, June 2007.

[Non-Patent Literature 15]

H. H. Ma, and J. K. Wolf, “On tail biting convolutional codes,” IEEE Trans. Commun., vol. com-34, no. 2, pp. 104-111, February 1986.

[Non-Patent Literature 16]

C. Weiss, C. Bettstetter, and S. Riedel, “Code construction and decoding of parallel concatenated tail-biting codes,” IEEE Trans. Inform. Theory, vol. 47, no. 1, pp. 366-386, January 2001.

[Non-Patent Literature 17]

J. Zhang, and M. P. C Fossorier, “A modified weighted bit-flipping decoding of low density parity-check codes,” IEEE Communications Letters, vol. 8, no. 3, pp. 165-167, 2004.

[Non-Patent Literature 18]

IEEE Standard for Local and Metropolitan Area Networks, IEEEP802.16e/D12, October 2005.

Technical Problem

Although Patent Literatures 1 and 2 describe a code generation method for an LDPC-CC of coding rate (n−1)/n (where n is an integer no smaller than two) based on a parity check polynomial, Patent Literatures 1 and 2 lack disclosure of a method of generating an LDPC-CC of a coding rate no smaller than 1/2 and not satisfying (n−1)/n (where n is an integer no smaller than two), and an LDPC-CC based on a parity check polynomial that uses an improved tail-biting scheme (LDPC block codes using LDPC-CC)

It is therefore an object of the present invention to provide an encoding method, a decoding method, an encoder, and a decoder for an LDPC-CC of a coding rate no smaller than 1/2 and not satisfying (n−1)/n (where n is an integer no smaller than two), and an LDPC-CC based on a parity check polynomial that uses an improved tail-biting scheme (LDPC block codes using LDPC-CC)

Solution to Problem

One aspect of the present invention is an encoding method of generating, by performing encoding of coding rate (n−1)/n on (n−1) information sequences (information sequences X 1 to X n−1 ) based on a predetermined parity check matrix having m×z rows and n×m×z columns (where n is an integer no smaller than two, m is an even number no smaller than two, and z is a natural number), an encoded sequence composed of the (n−1) information sequences and a parity check sequence P. The predetermined parity check matrix is either a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low density parity check (LDPC) convolutional code that uses a plurality of parity check polynomials, and the second parity check matrix is generated by performing at least one of row permutation and column permutation on the first parity check matrix. An eth parity check polynomial satisfying zero of the LDPC convolutional code (where e is an integer no smaller than zero and no greater than m×z−1) is expressible by using a specific mathematical expression.

One aspect of the present invention is a decoding method of decoding an encoded sequence encoded by employing a predetermined encoding method. The predetermined encoding method generates, by performing encoding of coding rate (n−1)/n on (n−1) information sequences (information sequences X 1 to X n−1 ) based on a predetermined parity check matrix having m×z rows and n×m×z columns (where n is an integer no smaller than two, m is an even number no smaller than two, and z is a natural number), an encoded sequence composed of the (n−1) information sequences and a parity check sequence P. The predetermined parity check matrix is either a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low density parity check (LDPC) convolutional code that uses a plurality of parity check polynomials, and the second parity check matrix is generated by performing at least one of row permutation and column permutation on the first parity check matrix. An eth parity check polynomial satisfying zero of the LDPC convolutional code (where e is an integer no smaller than zero and no greater than m×z−1) is expressible by using a specific mathematical expression.

Advantageous Effects of Invention

The present invention can achieve high error correction capability, and can thereby secure high data quality.

FIG. 1 shows an LDPC-CC check matrix.

FIG. 2 shows a configuration of an LDPC-CC encoder.

FIG. 3 shows a parity check matrix of a (7, 5) convolutional code.

FIG. 4 shows an example of the configuration of LDPC-CC check matrix having a coding rate of (n−1)/n and a time-varying period of six.

FIG. 5 shows an example of an LDPC-CC tree having a time-varying period of six.

FIG. 6 shows an example of an LDPC-CC tree having a time-varying period of six.

FIG. 7 shows an example of the configuration of LDPC-CC check matrix having a coding rate of (n−1)/n and a time-varying period of seven.

FIG. 8 shows an example of an LDPC-CC tree having a time-varying period of seven.

FIG. 9 shows a circuit example of encoder having a coding rate of 1/2.

FIG. 10 shows a circuit example of encoder having a coding rate of 1/2.

FIG. 11 shows a circuit example of encoder having a coding rate of 1/2.

FIG. 12 shows an example of the configuration of an LDPC-CC encoding section.

FIG. 13 shows a zero-termination method.

FIG. 14 shows an example of check matrix when zero-termination is performed.

FIG. 15 shows a relationship between check nodes corresponding to parity check polynomials #α and #β, and a variable node.

FIG. 16 shows a sub-matrix generated by extracting only parts relating to X 1 (D) of parity check matrix H.

FIG. 17 shows an example of LDPC-CC tree having a time-varying period of seven.

FIG. 18 shows an example of LDPC-CC tree having a time-varying period of h as a time-varying period of six.

FIG. 19 shows an example of LDPC-CC check matrix.

FIG. 20 shows an example of the configuration of check matrix when tail-biting is performed.

FIG. 21 shows an example of the configuration of check matrix when tail-biting is performed.

FIG. 22 is an overall diagram of a communication system.

FIG. 23 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 24 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 25 is an overall diagram of a communication system.

FIG. 26 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 27 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 28 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 29 shows an example of the configuration of partial matrix of check matrix when improved tail-biting is performed.

FIG. 30 shows an example of the configuration of partial matrix of check matrix when improved tail-biting is performed.

FIG. 31 shows an example of the configuration of check matrix when improved tail-biting is performed.

FIG. 32 shows an example of the configuration of a transmitting device when interleaving is performed on a transmission sequence.

FIG. 33 shows an example of the configuration of check matrix equivalent to check matrix when improved tail-biting is performed.

FIG. 34 shows an example of the configuration of a receiving device when interleaving is performed on a transmission sequence.

FIG. 35 shows an example of the configuration of check matrix corresponding to transmission sequence of jth block of LDPC code of coding rate nm/n.

FIG. 36 shows an example of the configuration of check matrix obtained by performing row permutation on check matrix corresponding to transmission sequence of jth block of LDPC code of coding rate nm/n.

FIG. 37 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 38 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 39 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 40 shows an example of the configuration of an encoder for LDPC-CC of coding rate 2/4 that is based on a parity check polynomial.

FIG. 41 is a diagram for explaining a zero-termination method.

FIG. 42 is a diagram for explaining a zero-termination method.

FIG. 43 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 when tail-biting is performed.

FIG. 44 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 when improved tail-biting is performed.

FIG. 45 shows an example of the configuration of check matrix for LDPC-CC of coding rate 2/4 when improved tail-biting is performed.

FIG. 46 is an overall diagram of a communication system.

FIG. 47 shows an example of time-domain frame configuration of a transmission signal transmitted by a transmitting device.

FIG. 48 shows an example of the configuration of sections generating a modulation signal in a transmitting device in a base station (broadcast station, access point, etc.,) when switching between transmission schemes is possible.

FIG. 49 is a diagram for explaining an example differing from that in FIG. 48 .

FIG. 50 is a diagram for explaining an example differing from that in FIG. 48 .

FIG. 51 shows an example of a configuration differing from FIG. 50 .

FIG. 52 shows an example of time and frequency domain frame configurations when a single stream is transmitted.

FIG. 53 shows an example of time and frequency domain frame configurations when two stream are transmitted.

FIG. 54 is a system configuration diagram including a device executing transmission method and reception method.

FIG. 55 illustrates a sample configuration of a reception device executing a reception method.

FIG. 56 illustrates a sample configuration for multiplexed data.

FIG. 57 is a schematic diagram illustrating an example of the manner in which the multiplexed data are multiplexed.

FIG. 58 illustrates an example of storage in a video stream.

FIG. 59 illustrates the format of TS packets ultimately written into the multiplexed data.

FIG. 60 describes the details of PMT data structure.

FIG. 61 illustrates the configuration of file information for the multiplexed data.

FIG. 62 illustrates the configuration of stream attribute information.

FIG. 63 illustrates the configuration of a sample audiovisual output device.

FIG. 64 illustrates a sample broadcasting system using a method of switching between precoding matrices according to a rule.

FIG. 65 illustrates an optical disc device.

FIG. 66 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 67 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 68 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 69 shows an example of the configuration of an encoder for LDPC-CC of coding rate 3/5 that is based on a parity check polynomial.

FIG. 70 is a diagram for explaining a zero-termination method.

FIG. 71 is a diagram for explaining a zero-termination method.

FIG. 72 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 when tail-biting is performed.

FIG. 73 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 when improved tail-biting is performed.

FIG. 74 shows an example of the configuration of check matrix for LDPC-CC of coding rate 3/5 when improved tail-biting is performed.

FIG. 75 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 76 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 77 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 78 shows an example of the configuration of an encoder for LDPC-CC of coding rate 5/7 that is based on a parity check polynomial.

FIG. 79 is a diagram for explaining a zero-termination method.

FIG. 80 is a diagram for explaining a zero-termination method.

FIG. 81 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 when tail-biting is performed.

FIG. 82 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 when improved tail-biting is performed.

FIG. 83 shows an example of the configuration of check matrix for LDPC-CC of coding rate 5/7 when improved tail-biting is performed.

FIG. 84 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 85 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 86 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 87 shows an example of the configuration of an encoder for LDPC-CC of coding rate 7/9 that is based on a parity check polynomial.

FIG. 88 is a diagram for explaining a zero-termination method.

FIG. 89 is a diagram for explaining a zero-termination method.

FIG. 90 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 when tail-biting is performed.

FIG. 91 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 when improved tail-biting is performed.

FIG. 92 shows an example of the configuration of check matrix for LDPC-CC of coding rate 7/9 when improved tail-biting is performed.

FIG. 93 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 94 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 95 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 and time-varying period 2×m that is based on a parity check polynomial.

FIG. 96 shows an example of the configuration of an encoder for LDPC-CC of coding rate 13/15 that is based on a parity check polynomial.

FIG. 97 is a diagram for explaining a zero-termination method.

FIG. 98 is a diagram for explaining a zero-termination method.

FIG. 99 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 when tail-biting is performed.

FIG. 100 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 when improved tail-biting is performed.

FIG. 101 shows an example of the configuration of check matrix for LDPC-CC of coding rate 13/15 when improved tail-biting is performed.

Embodiments of the present invention are described below, with reference to the accompanying drawings.

Before describing specific configurations and operations of the embodiments, an LDPC-CC based on parity check polynomials described in Patent Literatures 1 and 2 is described first.

For example, a convolutional code of a coding rate of 1/2 and generator polynomial G=[1G 1 (D)/G 0 (D)] will be considered as an example. Here, G 1 represents a feed-forward polynomial and G 0 represents a feedback polynomial. If a polynomial representation of an information sequence (data) is X(D), and a polynomial representation of a parity sequence is P(D), a parity check polynomial is represented as shown in expression 1 below.

[Math. 1]

G 1 ( D ) X ( D )+ G 0 ( D ) P ( D )=0  (1)

where D is a delay operator.

FIG. 3 shows information relating to a (7, 5) convolutional code. A (7, 5) convolutional code generator polynomial is represented as G=[1(D 2 +1)/(D 2 +D+1)]. Therefore, a parity check polynomial is as shown in expression 2 below.

[Math. 2]

( D 2 +1) X ( D )+( D 2 +D+ 1) P ( D )=0  (2)

Here, data at point in time i are represented by Xi, and parity bit by P i , and transmission sequence Wi is represented as W i =(X i , P i ). Then, transmission vector w is represented as w=(X 1 , P 1 , X 2 , P 2 , . . . , X 1 , P i . . . ) T . Thus, from expression 2, parity check matrix H can be represented as shown in FIG. 3 . At this time, the relational expression in expression 3 below holds true.

[Math. 3]

Hw= 0  (3)

Therefore, with parity check matrix H, the decoding side can perform decoding using belief propagation (BP) decoding, min-sum decoding similar to BP decoding, offset BP decoding, normalized BP decoding, shuffled BP decoding, scheduled layered BP decoding, or suchlike belief propagation, as shown in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, and Non-Patent Literature 8.

[LDPC-CC of Coding Rate (n−1)/n (where n is an Integer No Smaller than Two) Based on Parity Check Polynomial]

The following describes a code configuration method of an LDPC-CC based on a parity check polynomial having a time-varying period greater than three and having excellent error correction capability.

[Time-Varying Period of Six]

First, an LDPC-CC having a time-varying period of six is described as an example.

Consider expression 4-0 through 4-5 as parity check polynomials (that satisfy 0) of an LDPC-CC having a coding rate of (n−1)/n (n is an integer no smaller than two) and a time-varying period of six.

[Math. 4]

( D a#0,1,1 +D a#0,1,2 +D a#0,1,3 ) X 1 +( D )+( D a#0,2,1 +D a#0,2,2 +D a#0,2,3 ) X 2 ( D )+ . . . +( D a#0,n−1,1 +D a#0,n−1,2 +D a#0,n−1,3 ) X n−1 ( D )+( D b#0,1 +D b#0,2 +D b#0,3 ) P ( D )=0  (4-0)

( D a#1,1,1 +D a#1,1,2 +D a#1,1,3 ) X 1 +( D )+( D a#1,2,1 +D a#1,2,2 +D a#1,2,3 ) X 2 ( D )+ . . . +( D a#1,n−1,1 +D a#1,n−1,2 +D a#1,n−1,3 ) X n−1 ( D )+( D b#1,1 +D b#1,2 +D b#1,3 ) P ( D )=0  (4-1)

( D a#2,1,1 +D a#2,1,2 +D a#2,1,3 ) X 1 +( D )+( D a#2,2,1 +D a#2,2,2 +D a#2,2,3 ) X 2 ( D )+ . . . +( D a#2,n−1,1 +D a#2,n−1,2 +D a#2,n−1,3 ) X n−1 ( D )+( D b#2,1 +D b#2,2 +D b#2,3 ) P ( D )=0  (4-2)

( D a#3,1,1 +D a#3,1,2 +D a#3,1,3 ) X 1 +( D )+( D a#3,2,1 +D a#3,2,2 +D a#3,2,3 ) X 2 ( D )+ . . . +( D a#3,n−1,1 +D a#3,n−1,2 +D a#3,n−1,3 ) X n−1 ( D )+( D b#3,1 +D b#3,2 +D b#3,3 ) P ( D )=0  (4-3)

( D a#4,1,1 +D a#4,1,2 +D a#4,1,3 ) X 1 +( D )+( D a#4,2,1 +D a#4,2,2 +D a#4,2,3 ) X 2 ( D )+ . . . +( D a#4,n−1,1 +D a#4,n−1,2 +D a#4,n−1,3 ) X n−1 ( D )+( D b#4,1 +D b#4,2 +D b#4,3 ) P ( D )=0  (4-4)

( D a#5,1,1 +D a#5,1,2 +D a#5,1,3 ) X 1 +( D )+( D a#5,2,1 +D a#5,2,2 +D a#5,2,3 ) X 2 ( D )+ . . . +( D a#5,n−1,1 +D a#5,n−1,2 +D a#5,n−1,3 ) X n−1 ( D )+( D b#5,1 +D b#5,2 +D b#5,3 ) P ( D )=0  (4-5)

Here, X 1 (D), X 2 (D), . . . , X n−1 (D) are polynomial representations of data (information) X 1 , X 2 , . . . , X n−1 , P(D) is a polynomial representation of parity, and D is a delay operator. In expression 4-0 through 4-5, when, for example, the coding rate is 1/2, only the terms of X 1 (D) and P(D) are present and the terms of X 2 (D), . . . , X n−1 (D) are not present. Similarly, when the coding rate is 2/3, only the terms of X 1 (D), X 2 (D) and P(D) are present and the terms of X 3 (D), . . . , X n−1 (D) are not present. The other coding rates may also be considered in a similar manner.

Here, expression 4-0 through 4-5 are assumed to have such parity check polynomials that three terms are present in each of X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D).

Furthermore, in expression 4-0 through 4-5, it is assumed that the following holds true for X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D).

In expression 4-q, it is assumed that a #q,p,1 , a #q,p,2 and a #q,p,3 are natural numbers and a #q,p,1 ≠a# q,p,2 , a #q,p,1 ≠a #p,q,3 and a #q,p,2 ≠a #q,p,3 hold true. Furthermore, it is assumed that b #q,1 , b #q,2 and b #q,3 are natural numbers and b #q,1 ≠b #q,2 , b #q,1 ≠b #q,3 and b #q,1 ≠b #q,3 hold true (q=0, 1, 2, 3, 4, 5; p=1, 2, . . . , n−1).

The parity check polynomial of expression 4-q is called check equation #q and the sub-matrix based on the parity check polynomial of expression 4-q is called qth sub-matrix H q . Next, consider an LDPC-CC of a time-varying period of six generated from zeroth sub-matrix H 0 , first sub-matrix H 1 , second sub-matrix H 2 , third sub-matrix H 3 , fourth sub-matrix H 4 and fifth sub-matrix H 5 .

In an LDPC-CC having a time-varying period of six and a coding rate of (n−1)/n (where n is an integer no smaller than two), the parity bit and information bits at point in time i are represented by Pi and X i,1 , X i,2 , . . . , X i,n−1 , respectively. If i%6g=k (where k=0, 1, 2, 3, 4, 5) is assumed at this time, a parity check polynomial of expression 4-(k) holds true. For example, if i=8, i%6g=2 (k=2), expression 5 holds true.

[Math. 5]

( D a#2,1,1 +D a#2,1,2 +D a#2,1,3 ) X 8,1 +( D a#2,2,1 +D a#2,2,2 +D a#2,2,3 ) X 8,2 + . . . +( D a#2,n−1,1 +D a#2,n−1,2 +D a#2,n−1,3 ) X 8,n−1 +( D b#2,1 +D b#2,2 +D b#2,3 ) P 8 =0  (5)

It is assumed that a #q,1,3 =0 and b #q,3 =0 (q=0, 1, 2, 3, 4, 5) so as to simplify the relationship between the parity bits and information bits in expression 4-0 through 4-5 and sequentially find the parity bits when tail-biting is not performed. Therefore, the parity check polynomials (that satisfy 0) of expression 4-0 through 4-5 are represented as shown in expression 6-0 through expression 6-5.

[Math. 6]

( D a#0,1,1 +D a#0,1,2 +1) X 1 +( D )+( D a#0,2,1 +D a#0,2,2 +1) X 2 ( D )+ . . . +( D a#0,n−1,1 +D a#0,n−1,2 +1) X n−1 ( D )+( D b#0,1 +D b#0,2 +1) P ( D )=0  (6-0)

( D a#1,1,1 +D a#1,1,2 +1) X 1 +( D )+( D a#1,2,1 +D a#1,2,2 +1) X 2 ( D )+ . . . +( D a#1,n−1,1 +D a#1,n−1,2 +1) X n−1 ( D )+( D b#1,1 +D b#1,2 +1) P ( D )=0  (6-1)

( D a#2,1,1 +D a#2,1,2 +1) X 1 +( D )+( D a#2,2,1 +D a#2,2,2 +1) X 2 ( D )+ . . . +( D a#2,n−1,1 +D a#2,n−1,2 +1) X n−1 ( D )+( D b#2,1 +D b#2,2 +1) P ( D )=0  (6-2)

( D a#3,1,1 +D a#3,1,2 +1) X 1 +( D )+( D a#3,2,1 +D a#3,2,2 +1) X 2 ( D )+ . . . +( D a#3,n−1,1 +D a#3,n−1,2 +1) X n−1 ( D )+( D b#3,1 +D b#3,2 +1) P ( D )=0  (6-3)

( D a#4,1,1 +D a#4,1,2 +1) X 1 +( D )+( D a#4,2,1 +D a#4,2,2 +1) X 2 ( D )+ . . . +( D a#4,n−1,1 +D a#4,n−1,2 +1) X n−1 ( D )+( D b#4,1 +D b#4,2 +1) P ( D )=0  (6-4)

( D a#5,1,1 +D a#5,1,2 +1) X 1 +( D )+( D a#5,2,1 +D a#5,2,2 +1) X 2 ( D )+ . . . +( D a#5,n−1,1 +D a#5,n−1,2 +1) X n−1 ( D )+( D b#5,1 +D b#5,2 +1) P ( D )=0  (6-5)

Furthermore, it is assumed that zeroth sub-matrix H 0 , first sub-matrix H 1 , second sub-matrix H 2 , third sub-matrix H 3 , fourth sub-matrix H 4 and fifth sub-matrix H 5 are represented as shown in expression 7-0 through expression 7-5.

In expression 7-0 through expression 7-5, n continuous ones correspond to the terms of X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D) in each of expression 6-0 through expression 6-5.

Here, parity check matrix H can be represented as shown in FIG. 4 . As shown in FIG. 4 , a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 4 ).

Assuming transmission vector u as u=(X 1,0 , X 2,0 , . . . , X n−1,0 , P 0 , X 1,1 , X 2,1 , . . . , X n−1,1 , P 1 , . . . , X 1,k , X 2,k , . . . , X n−1,k , P k , . . . ) T , Hu=0 holds true. (Here, the zero in Hu=0 indicates that vector Hu is a (column) vector all elements of which are zeroes.)

Here, examples of conditions for the parity check polynomials in expression 6-0 through expression 6-5 are described under which high error correction capability can be achieved.

Condition #1-1 and Condition #1-2 below are important for the terms relating to X 1 (D), X 2 (D), . . . , X n−1 (D). In the following conditions, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6.

<Condition #1-1>

<Condition #1-2>

By designating Condition #1-1 and Condition #1-2 as constraint conditions, the LDPC-CC that satisfies the constraint conditions becomes a regular LDPC code, and can thereby achieve high error correction capability.

Next, other important constraint conditions are described.

<Conditions #2-1>

In Condition #1-1, v p=1 , v p=2 , v p=3 , v p=4 , . . . , v p=k , . . . , v p=n−2 , v p=n−1 , and w are set to one, four, and five. That is, v p=k (k=1, 2, . . . , n−1) and w are set to one and natural numbers other than divisors of a time-varying period of six.

<Condition #2-2>

In Condition #1-2, y p=1 , y p=2 , y p=3 , y p=4 , . . . , y p=k , . . . , y p=n−2 , y p=n−1 , and z are set to one, four, and five. That is, y p=k (k=1, 2, . . . , n−1) and z are set to one and natural numbers other than divisors of a time-varying period of six

By adding the constraint conditions of Condition #2-1 and Condition #2-2 or the constraint conditions of Condition #2-1 or Condition #2-2, it is possible to use time-varying periods effectively. This point is described in detail with reference to the accompanying drawings.

For simplicity of explanation, a case is considered where X 1 (D) in parity check polynomials 6-0 to 6-5 of an LDPC-CC having a time-varying period of six and a coding rate of (n−1)/n based on parity check polynomials has two terms. At this time, the parity check polynomials are represented as shown in expression 8-0 through expression 8-5.

[Math. 8]

( D a#0,1,1 +1) X 1 +( D )+( D a#0,2,1 +D a#0,2,2 +1) X 2 ( D )+ . . . +( D a#0,n−1,1 +D a#0,n−1,2 +1) X n−1 ( D )+( D b#0,1 +D b#0,2 +1) P ( D )=0  (8-0)

( D a#1,1,1 +1) X 1 +( D )+( D a#1,2,1 +D a#1,2,2 +1) X 2 ( D )+ . . . +( D a#1,n−1,1 +D a#1,n−1,2 +1) X n−1 ( D )+( D b#1,1 +D b#1,2 +1) P ( D )=0  (8-1)

( D a#2,1,1 +1) X 1 +( D )+( D a#2,2,1 +D a#2,2,2 +1) X 2 ( D )+ . . . +( D a#2,n−1,1 +D a#2,n−1,2 +1) X n−1 ( D )+( D b#2,1 +D b#2,2 +1) P ( D )=0  (8-2)

( D a#3,1,1 +1) X 1 +( D )+( D a#3,2,1 +D a#3,2,2 +1) X 2 ( D )+ . . . +( D a#3,n−1,1 +D a#3,n−1,2 +1) X n−1 ( D )+( D b#3,1 +D b#3,2 +1) P ( D )=0  (8-3)

( D a#4,1,1 +1) X 1 +( D )+( D a#4,2,1 +D a#4,2,2 +1) X 2 ( D )+ . . . +( D a#4,n−1,1 +D a#4,n−1,2 +1) X n−1 ( D )+( D b#4,1 +D b#4,2 +1) P ( D )=0  (8-4)

( D a#5,1,1 +1) X 1 +( D )+( D a#5,2,1 +D a#5,2,2 +1) X 2 ( D )+ . . . +( D a#5,n−1,1 +D a#5,n−1,2 +1) X n−1 ( D )+( D b#5,1 +D b#5,2 +1) P ( D )=0  (8-5)

Here, a case is considered where v p=k (k=1, 2, . . . , n−1) and w are set to three. Three is a divisor of a time-varying period of six.

FIG. 5 shows a tree of check nodes and variable nodes when only information X 1 is focused upon when it is assumed that v v1 and w are set to three and (a #0,1,1 %6=a #1,1,1 %6=a #2,1,1 %6=a #3,1,1 %6=a #4,1,1 %6=a #5,1,1 %6=3).

The parity check polynomial of expression 8-q is termed check equation #q. In FIG. 5 , a tree is drawn from check equation #0. In FIG. 5 , the symbols ∘ (single circle) and ⊚ (double circle) represent variable nodes, and the symbol □ (square) represents a check node. The symbol ∘ (single circle) represents a variable node relating to X 1 (D) and the symbol ⊚ (double circle) represents a variable node relating to D a#q,1,1 X 1 (D). Furthermore, the symbol □ (square) described as #Y (Y=0, 1, 2, 3, 4, 5) means a check node corresponding to a parity check polynomial of expression 8-Y.

In FIG. 5 , values that do not satisfy Condition #2-1, that is, v p=1 , v p=2 , v p=3 , v p=4 , . . . , v p=k , . . . , v p=n−2 , v p=n−1 (k=1, 2, . . . , n−1) and w are set to a divisor other than one among divisors of time-varying period of six (w=3).

In this case, as shown in FIG. 5 , #Y only have limited values such as zero or three at check nodes. That is, even if the time-varying period is increased, belief is propagated only from a specific parity check polynomial, which means that the effect of having increased the time-varying period is not achieved.

In other words, the condition for #Y to have only limited values is to set v p=1 , v p=2 , v p=3 , v p=4 , . . . , v p=k , . . . , v p=n−2 , v p=n−1 (k=1, 2, . . . , n−1) and w to a divisor other than one among divisors of a time-varying period of six.

By contrast, FIG. 6 shows a tree when v p=k (k=1, 2, . . . , n−1) and w are set to one in the parity check polynomial. When v p=k (k=1, 2, . . . , n−1) and w are set to one, the condition of Condition #2-1 is satisfied.

As shown in FIG. 6 , when the condition of Condition #2-1 is satisfied, #Y takes all values from zero to five at check nodes. That is, when the condition of Condition #2-1 is satisfied, belief is propagated by all parity check polynomials corresponding to the values of #Y. As a result, even when the time-varying period is increased, belief is propagated from a wide range and the effect of having increased the time-varying period can be achieved. That is, it is clear that Condition #2-1 is an important condition to achieve the effect of having increased the time-varying period. Similarly, Condition #2-2 becomes an important condition to achieve the effect of having increased the time-varying period.

[Time-Varying Period of Seven]

When the above is taken into consideration, the time-varying period being a prime number is an important condition to achieve the effect of having increased the time-varying period.

Consider expression 9-0 through 9-6 as parity check polynomials (that satisfy 0) of an LDPC-CC having a coding rate of (n−1)/n (n is an integer no smaller than two) and a time-varying period of seven.

[Math. 9]

( D a#0,1,1 +D a#0,1,2 +1) X 1 +( D )+( D a#0,2,1 +D a#0,2,2 +1) X 2 ( D )+ . . . +( D a#0,n−1,1 +D a#0,n−1,2 +1) X n−1 ( D )+( D b#0,1 +D b#0,2 +1) P ( D )=0  (9-0)

( D a#1,1,1 +D a#1,1,2 +1) X 1 +( D )+( D a#1,2,1 +D a#1,2,2 +1) X 2 ( D )+ . . . +( D a#1,n−1,1 +D a#1,n−1,2 +1) X n−1 ( D )+( D b#1,1 +D b#1,2 +1) P ( D )=0  (9-1)

( D a#2,1,1 +D a#2,1,2 +1) X 1 +( D )+( D a#2,2,1 +D a#2,2,2 +1) X 2 ( D )+ . . . +( D a#2,n−1,1 +D a#2,n−1,2 +1) X n−1 ( D )+( D b#2,1 +D b#2,2 +1) P ( D )=0  (9-2)

( D a#3,1,1 +D a#3,1,2 +1) X 1 +( D )+( D a#3,2,1 +D a#3,2,2 +1) X 2 ( D )+ . . . +( D a#3,n−1,1 +D a#3,n−1,2 +1) X n−1 ( D )+( D b#3,1 +D b#3,2 +1) P ( D )=0  (9-3)

( D a#4,1,1 +D a#4,1,2 +1) X 1 +( D )+( D a#4,2,1 +D a#4,2,2 +1) X 2 ( D )+ . . . +( D a#4,n−1,1 +D a#4,n−1,2 +1) X n−1 ( D )+( D b#4,1 +D b#4,2 +1) P ( D )=0  (9-4)

( D a#5,1,1 +D a#5,1,2 +1) X 1 +( D )+( D a#5,2,1 +D a#5,2,2 +1) X 2 ( D )+ . . . +( D a#5,n−1,1 +D a#5,n−1,2 +1) X n−1 ( D )+( D b#5,1 +D b#5,2 +1) P ( D )=0  (9-5)

( D a#6,1,1 +D a#6,1,2 +1) X 1 +( D )+( D a#6,2,1 +D a#6,2,2 +1) X 2 ( D )+ . . . +( D a#6,n−1,1 +D a#6,n−1,2 +1) X n−1 ( D )+( D b#6,1 +D b#6,2 +1) P ( D )=0  (9-6)

In expression 9-q, it is assumed that a #q,p,1 and a #q,p,2 are natural numbers no smaller than one, and a #q,p,1 ≠a #q,p,2 holds true. Furthermore, it is assumed that b #q,1 and b #q,2 are natural numbers no smaller than one, and b #q,1 ≠b #q,2 holds true (q=0, 1, 2, 3, 4, 5, 6; p=1, 2, . . . , n−1).

In an LDPC-CC having a time-varying period of seven and a coding rate of (n−1)/n (where n is an integer no smaller than two), the parity bit and information bits at point in time i are represented by Pi and X i,1 , X i,2 , . . . , X i,n−1 respectively. If i%7=k (where k=0, 1, 2, 3, 4, 5, 6) is assumed at this time, the parity check polynomial of expression 9-(k) holds true.

For example, if i=8, i%7=1 (k=1), expression 10 holds true.

[Math. 10]

( D a#1,1,1 +D a#1,1,2 +1) X 8,1 +( D a#1,2,1 +D a#1,2,2 +1) X 8,2 + . . . +( D a#1,n−1,1 +D a#1,n−1,2 +1) X 8,n−1 +( D b#1,1 +D b#1,2 +1) P 8 =0  (10)

Furthermore, when the sub-matrix (vector) of expression 9-g is assumed to be H g , the parity check matrix can be created using the method described in [LDPC-CC based on parity check polynomial]. Here, the 0th sub-matrix, first sub-matrix, second sub-matrix, third sub-matrix, fourth sub-matrix, fifth sub-matrix and sixth sub-matrix are represented as shown in expression 11-0 through expression 11-6.

In expression 11-0 through expression 11-6, n continuous ones correspond to the terms of X 1 (D), X 2 (D), . . . , X n−1 (D), and P(D) in each of expression 9-0 through expression 9-6.

Here, parity check matrix H can be represented as shown in FIG. 7 . As shown in FIG. 7 , a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 7 ). When transmission vector u is assumed to be u=(X 1,0 , X 2,0 , . . . , X n−1,0 , P 0 , X 1,1 , X 2,1 , . . . , X n−1,1 , P 1 , . . . , X 1,k , X 2,k , . . . , X n−1,k , P k , . . . ) T , Hu=0 holds true. (Here, the zero in Hu=0 indicates that vector Hu is a column vector all elements of which are zeroes.) Here, the condition for the parity check polynomials in expression 9-0 through expression 9-6 to achieve high error correction capability is as follows as in the case of the time-varying period of six. In the following conditions, % means a modulo, and for example, α%7 represents a remainder after dividing α by seven.

<Condition #1-1′>

<Condition #1-2′>

By designating Condition #1-1′ and Condition #1-2′ constraint conditions, the LDPC-CC that satisfies the constraint conditions becomes a regular LDPC code, and can thereby achieve high error correction capability.

In the case of a time-varying period of six, achieving high error correction capability further requires Condition #2-1 and Condition #2-2, or Condition #2-1, or Condition #2-2. By contrast, when the time-varying period is a prime number as in the case of a time-varying period of seven, the condition corresponding to Condition #2-1 and Condition #2-2, or Condition #2-1, or Condition #2-2 required in the case of the time-varying period of six, is unnecessary.

That is to say,

in Condition #1-1′, values of v p=1 , v p=2 , v p=3 , v p=4 , . . . , v p=k . . . , v p=n−2 , v p=n−1 (k=1, 2, . . . , n−1) and w may be one of values 0, 1, 2, 3, 4, 5 and 6.

Also,

in Condition #1-2′, values of y p=1 , y p=2 , y p=3 , y p=4 , . . . , y p=k , . . . , y p=n−2 , y p=n−1 (k=1, 2, . . . , n−1) and z may be one of values 0, 1, 2, 3, 4, 5, and 6.

The reason is described below.

For simplicity of explanation, a case is considered where X 1 (D) in parity check polynomials 9-0 to 9-6 of an LDPC-CC having a time-varying period of seven and a coding rate of (n−1)/n based on parity check polynomials has two terms. In this case, the parity check polynomials are represented as shown in expression 12-0 through expression 12-6.

[Math. 12]

( D a#0,1,1 +1) X 1 +( D )+( D a#0,2,1 +D a#0,2,2 +1) X 2 ( D )+ . . . +( D a#0,n−1,1 +D a#0,n−1,2 +1) X n−1 ( D )+( D b#0,1 +D b#0,2 +1) P ( D )=0  (12-0)

( D a#1,1,1 +1) X 1 +( D )+( D a#1,2,1 +D a#1,2,2 +1) X 2 ( D )+ . . . +( D a#1,n−1,1 +D a#1,n−1,2 +1) X n−1 ( D )+( D b#1,1 +D b#1,2 +1) P ( D )=0  (12-1)

( D a#2,1,1 +1) X 1 +( D )+( D a#2,2,1 +D a#2,2,2 +1) X 2 ( D )+ . . . +( D a#2,n−1,1 +D a#2,n−1,2 +1) X n−1 ( D )+( D b#2,1 +D b#2,2 +1) P ( D )=0  (12-2)

( D a#3,1,1 +1) X 1 +( D )+( D a#3,2,1 +D a#3,2,2 +1) X 2 ( D )+ . . . +( D a#3,n−1,1 +D a#3,n−1,2 +1) X n−1 ( D )+( D b#3,1 +D b#3,2 +1) P ( D )=0  (12-3)

( D a#4,1,1 +1) X 1 +( D )+( D a#4,2,1 +D a#4,2,2 +1) X 2 ( D )+ . . . +( D a#4,n−1,1 +D a#4,n−1,2 +1) X n−1 ( D )+( D b#4,1 +D b#4,2 +1) P ( D )=0  (12-4)

( D a#5,1,1 +1) X 1 +( D )+( D a#5,2,1 +D a#5,2,2 +1) X 2 ( D )+ . . . +( D a#5,n−1,1 +D a#5,n−1,2 +1) X n−1 ( D )+( D b#5,1 +D b#5,2 +1) P ( D )=0  (12-5)

( D a#6,1,1 +1) X 1 +( D )+( D a#6,2,1 +D a#6,2,2 +1) X 2 ( D )+ . . . +( D a#6,n−1,1 +D a#6,n−1,2 +1) X n−1 ( D )+( D b#6,1 +D b#6,2 +1) P ( D )=0  (12-6)

Here, a case is considered where v p=k (k=1, 2, . . . , n−1) and w are set to two.

FIG. 8 shows a tree of check nodes and variable nodes when only information X 1 is focused upon when v p=1 and w are set to two and a# 0,1,1 %7=a# 1,1,1 %7=a# 2,1,1 %7=a# 3,1,1 %7=a# 4,1,1 %7=a# 5,1,1 %7=a# 6,1,1 %7=2.

The parity check polynomial of expression 12-q is termed check equation #q. In FIG. 8 , a tree is drawn from check equation #0. In FIG. 8 , the symbols ∘ (single circle) and ⊚ (double circle) represent variable nodes, and the symbol □ (square) represents a check node. The symbol ∘ (single circle) represents a variable node relating to X 1 (D) and the symbol ⊚ (double circle) represents a variable node relating to D a#q,1,1 X 1 (D) Furthermore, the symbol □ (square) described as #Y (Y=0, 1, 2, 3, 4, 5, 6) means a check node corresponding to a parity check polynomial of expression 12-Y.

In the case of a time-varying period of six, for example, as shown in FIG. 5 , there may be cases where #Y only has a limited value and check nodes are only connected to limited parity check polynomials. By contrast, when the time-varying period is seven (a prime number) such as a time-varying period of seven, as shown in FIG. 8 , #Y have all values from zero to six and check nodes are connected to all parity check polynomials. Thus, belief is propagated by all parity check polynomials corresponding to the values of #Y. As a result, even when the time-varying period is increased, belief is propagated from a wide range and it is possible to achieve the effect of having increased the time-varying period. Although FIG. 8 shows the tree when a #q,1,1 %7 (q=0, 1, 2, 3, 4, 5, 6) is set to two, check nodes can be connected to all the applicable parity check polynomials if a #q,1,1 %7 is set to any value other than zero.

Thus, it is clear that if the time-varying period is set to a prime number in this way, constraint conditions relating to parameter settings for achieving high error correction capability are drastically relaxed compared to a case where the time-varying period is not a prime number. When the constraint conditions are relaxed, adding another constraint condition enables higher error correction capability to be achieved. Such a code configuration method is described below.

[Time-Varying Period of q (q is a Prime Number Greater than Three): Expression 13]

First, a case will be considered where a gth (g=0, 1, . . . , q−1) parity check polynomial of a coding rate of (n−1)/n and a time-varying period of q (q is a prime number greater than three) is represented as shown in expression 13.

[Math. 13]

( D a#g,1,1 +D a#g,1,2 +1) X 1 ( D )+( D a#g,2,1 +D a#g,2,2 +1) X 2 ( D )+ . . . +( D a#g,n−1,1 +D a#g,n−1,2 +1) X n−1 ( D )+( D b#g,1 +D b#g,2 +1) P ( D )=0  (13)

In expression 13, it is also assumed that a #g,p,1 and a #g,p,2 are natural numbers no smaller than one and that a #g,p,1 ≠a #g,p,2 holds true. Furthermore, it is also assumed that b #g,1 and b #g,2 are natural numbers no smaller than one and that b #g,1 ≠b #g,2 holds true (g=0, 1, 2, . . . , q−2, q−1; p=1, 2, . . . , n−1).

In the same way as the above description, Condition #3-1 and Condition #3-2 described below are one of important requirements for an LDPC-CC to achieve high error correction capability. In the following conditions, % means a modulo, and for example, a % q represents a remainder after dividing α by q.

<Condition #3-1>

<Condition #3-2>

In addition, when Condition #4-1 or Condition #4-2 holds true for a set of (v p=1 , y p=1 ), (v p=2 , y p=2 ), (v p=3 , y p=3 ), . . . (v p=k ,y p=k ), . . . (v p=n−2 , y p=n−2 ), (v p=n−1 , y p=n−1 ), and (w, z), high error correction capability can be achieved. Here, k=1, 2, . . . , n−1.

<Condition #4-1>

Consider (v p=i , y p=i ) and (v p=j , y p=j ), where it is assumed that i=1, 2, . . . , n−1, j=1, 2, . . . , n−1, and i≠j. At this time, i and j (i≠j) are present where (v p=i , y p=i )≠(v p=j , y p=j ) and (v p=i , y p=i )≠(y p=j , v p=j ) hold true.

<Condition #4-2>

Consider (v p=i , y p=i ) and (w, z), where it is assumed that i=1, 2, . . . , n−1. At this time, i is present where (v p=i , y p=i )≠(w, z) and (v p=i , y p=i )≠(z, w) hold true.

By making more severe the constraint conditions of Condition #4-1 and Condition #4-2, it is more likely to be able to generate an LDPC-CC of a time-varying period of q (q is a prime number no smaller than three) with higher error correction capability. The condition is that Condition #5-1 and Condition #5-2, or Condition #5-1, or Condition #5-2 should hold true.

<Condition #5-1>

Consider (v p=i , y p=i ) and (v p=j , y p=j ), where i=1, 2, . . . , n−1, j=1, 2, . . . , n−1, and i≠j. At this time, (v p=i , y p=i )≠(v p=j , y p=j ) and (v p=i , y p=i )≠(y p=j , v p=j ) hold true for all i and j (i≠j).

<Condition #5-2>

Consider (v p=i , y p=i ) and (w, z), where i=1, 2, . . . , n−1. Here, (v p=i , y p=i )≠(w, z) and (v p=i , y p=i )≠(z, w) hold true for all i.

Furthermore, when v p=i ≠y p=i (i=1, 2, . . . , n−1) and w≠z hold true, it is possible to suppress the occurrence of short loops in a Tanner graph.

In addition, when 2n<q, if (v p=i , y p=i ) and (z, w) have different values, it is more likely to be able to generate an LDPC-CC of a time-varying period of q (q is a prime number greater than three) with higher error correction capability.

Furthermore, when 2n≥q, if (v p=i , y p=i ) and (z, w) are set so that all values of 0, 1, 2, . . . , q−1 are present, it is more likely to be able to generate an LDPC-CC having a time-varying period of q (q is a prime number greater than three) with higher error correction capability.

In the above description, expression 13 having three terms in X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D) has been handled as the gth parity check polynomial of an LDPC-CC having a time-varying period of q (q is a prime number greater than three). In expression 13, it is also likely to be able to achieve high error correction capability when the number of terms of any of X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D) is one or two. For example, the following method is available as the method of setting the number of terms of X 1 (D) to one or two. In the case of a time-varying period of q, there are q parity check polynomials that satisfy zero and the number of terms of X 1 (D) is set to one or two for all the q parity check polynomials that satisfy zero. Alternatively, instead of setting the number of terms of X 1 (D) to one or two for all the q parity check polynomials that satisfy zero, the number of terms of X 1 (D) may be set to one or two for any number (equal to or less than q−1) of parity check polynomials that satisfy zero. The same applies to X 2 (D), . . . , X n−1 (D) and P(D). In this case, satisfying the above-described condition constitutes an important condition in achieving high error correction capability. However, the condition relating to the deleted terms is unnecessary.

Furthermore, high error correction capability may also be likely to be achieved even when the number of terms of any of X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D) is four or more. For example, the following method is available as the method of setting the number of terms of X 1 (D) to four or more. In the case of a time-varying period of q, there are q parity check polynomials that satisfy zero and the number of terms of X 1 (D) is set to four or more for all the q parity check polynomials that satisfy zero. Alternatively, instead of setting the number of terms of X1(D) to four or more for all the q parity check polynomials that satisfy zero, the number of terms of X 1 (D) may be set to four or more for any number (equal to or less than q−1) of parity check polynomials that satisfy zero. The same applies to X 2 (D), . . . , X n−1 (D) and P(D). Here, the above-described condition is excluded for the added terms.

[Time-Varying Period of h (h is a Non-Prime Integer Greater than Three): Expression 14]

Next, a code configuration method when time-varying period h is a non-prime integer greater than three will be considered.

First, a case will be considered where the gth (g=0, 1, . . . , h−1) parity check polynomial of a coding rate of (n−1)/n and a time-varying period of h (h is a non-prime integer greater than three) is represented as shown in expression 14.

[Math. 14]

( D a#g,1,1 +D a#g,1,2 +1) X 1 ( D )+( D a#g,2,1 +D a#g,2,2 +1) X 2 ( D )+ . . . +( D a#g,n−1,1 +D a#g,n−1,2 +1) X n−1 ( D )+( D b#g,1 +D b#g,2 +1) P ( D )=0  (14)

In expression 14, it is assumed that a #g,p,1 and a #g,p,2 are natural numbers no smaller than one and a #g,p,1 ≠a #g,p,2 holds true. Furthermore, it is assumed that b #g,1 and b #g,2 are natural numbers no smaller than one and b #g,1 ≠b #g,2 holds true (g=0, 1, 2, . . . , h−2, h−1; p=1, 2, . . . , n−1).

In the same way as the above description, Condition #6-1 and Condition #6-2 described below are one of important requirements for an LDPC-CC to achieve high error correction capability. In the following conditions, % means a modulo, and for example, α%h represents a remainder after dividing α by h.

<Condition #6-1>

<Condition #6-2>

In addition, as described above, high error correction capability can be achieved by adding Condition #7-1 or Condition #7-2.

<Condition #7-1>

In Condition #6-1, v p=1 , v p=2 , v p=3 , v p=4 , . . . , v p=k , . . . , v p=n−2 , v p=n−1 (k=1, 2, . . . , n−1) and w are set to one and are natural numbers other than divisors of a time-varying period of h.

<Condition #7-2>

In Condition #6-2, y p=1 , y p=2 , y p=3 , y p=4 , . . . , y p=k , . . . , y p=n−2 , y p=n−1 (k=1, 2, . . . , n−1) and z are set to one and are natural numbers other than divisors of a time-varying period of h.

Then, Consider a set of (v p=1 , y p=1 ), (v p=2 , y p=2 ), (v p=3 , y p=3 ), . . . (v p=k , y p=k ), . . . , (v p=n−2 , y p=n−2 ), (v p=n−1 , y p=n−1 ) and (w, z). Here, it is assumed that k=1, 2, . . . , n−1. If Condition #8-1 or Condition #8-2 holds true, higher error correction capability can be achieved.

<Condition #8-1>

Consider (v p=i , y p=i ) and (v p=j , y p=j ), where it is assumed that i=1, 2, . . . , n−1, j=1, 2, . . . , n−1 and i≠j. At this time, there are i and j (i≠j) for which (v p=i , y p=i )≠(v p=j , y p=j ) and (v p=i , y p=i )≠(y p=j , v p=j ) hold true.

<Condition #8-2>

Consider (v p=i , y p=i ) and (w, z), where it is assumed that i=1, 2, . . . , n−1. At this time, there is i for which (v p=i , y p=i )≠(w, z) and (v p=i , y p=i )≠(z, w) hold true.

Furthermore, by making more severe the constraint conditions of Condition #8-1 and condition #8-2, it is more likely to be able to generate an LDPC-CC of a time-varying period of h (h is a non-prime integer no smaller than three) with higher error correction capability. The condition is that Condition #9-1 and Condition #9-2, Condition #9-1, or Condition #9-2 should hold true.

<Condition #9-1>

Consider (v p=i , y p=i ) and (v p=j , y p=j ), where it is assumed that i=1, 2, . . . , n−1, j=1, 2, . . . , n−1 and i≠j. At this time, (v p=i , y p=i )≠(v p=j , y p=j ) and (v p=i , y p=i )≠(y p=j , v p=j ) hold true for all i and j (i≠j).

<Condition #9-2>

Consider (v p=i , y p=i ) and (w, z), where it is assumed that i=1, 2, . . . , n−1. At this time, (v p=i , y p=i )≠(w, z) and (v p=i , y p=i )≠(z, w) hold true for all i.

Furthermore, when v p=i ≠y p=i (i=1, 2, . . . , n−1) and w≠z hold true, it is possible to suppress the occurrence of short loops in a Tanner graph.

In the above description, expression 14 having three terms in X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D) has been handled as the gth parity check polynomial of an LDPC-CC having a time-varying period of h (h is a non-prime integer greater than three). In expression 14, it is also likely to be able to achieve high error correction capability when the number of terms of any of X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D) is one or two. For example, the following method is available as the method of setting the number of terms of X 1 (D) to one or two. In the case of a time-varying period of h, there are h parity check polynomials that satisfy zero and the number of terms of X 1 (D) is set to one or two for all the h parity check polynomials that satisfy zero. Alternatively, instead of setting the number of terms of X 1 (D) to one or two for all the h parity check polynomials that satisfy zero, the number of terms of X 1 (D) may be set to one or two for any number (equal to or less than h−1) of parity check polynomials that satisfy zero. The same applies to X 2 (D), . . . , X n−1 (D) and P(D). In this case, satisfying the above-described condition constitutes an important condition in achieving high error correction capability. However, the condition relating to the deleted terms is unnecessary.

Moreover, even when the number of terms of any of X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D) is four or more, it is also likely to be able to achieve high error correction capability. For example, the following method is available as the method of setting the number of terms of X 1 (D) to four or more. In the case of a time-varying period of h, there are h parity check polynomials that satisfy zero, and the number of terms of X 1 (D) is set to four or more for all the h parity check polynomials that satisfy zero. Alternatively, instead of setting the number of terms of X 1 (D) to four or more for all the h parity check polynomials that satisfy zero, the number of terms of X 1 (D) may be set to four or more for any number (equal to or less than h−1) of parity check polynomials that satisfy zero. The same applies to X 2 (D), . . . , X n−1 (D) and P(D). At this time, the above-described condition is excluded for the added terms.

The following describes an LDPC-CC encoding method and the configuration of an encoder based on the parity check polynomials described above.

First, consider an LDPC-CC having a coding rate of 1/2 and a time-varying period of three as an example. Parity check polynomials of a time-varying period of three are provided below.

[Math. 15]

( D 2 +D 1 +1) X 1 ( D )++( D 3 +D 1 +1) P ( D )=0  (15-0)

( D 3 +D 1 +1) X 1 ( D )+( D 2 +D 1 +1) P ( D )=0  (15-1)

( D 3 +D 2 +1) X 1 ( D )+( D 3 +D 2 +1) P ( D )=0  (15-2)

At this time, P(D) is obtained as shown below.

[Math. 16]

P ( D )=( D 2 +D 1 +1) X 1 ( D )+( D 3 +D 1 ) P ( D )  (16-0)

P ( D )=( D 3 +D 1 +1) X 1 ( D )+( D 2 +D 1 ) P ( D )  (16-1)

P ( D )=( D 3 +D 2 +1) X 1 ( D )+( D 3 +D 2 ) P ( D )  (16-2)

Then, expression 16-0 through expression 16-2 are represented as follows:

[Math. 17]

P [ i ]= X 1 [ i ]⊕ X 1 [ i− 1]⊕ X 1 [ i− 2]⊕ P [ i− 1]⊕ P [ i− 3]  (17-1)

P [ i ]= X 1 [ i ]⊕ X 1 [ i− 1]⊕ X 1 [ i− 3]⊕ P [ i− 1]⊕ P [ i− 2]  (17-2)

P [ i ]= X 1 [ i ]⊕ X 1 [ i− 2]⊕ X 1 [ i− 3]⊕ P [ i− 2]⊕ P [ i− 3]  (17-3)

where the symbol ⊕ represents the exclusive OR operator.

Here, FIG. 9 shows the circuit corresponding to expression 17-0, FIG. 10 shows the circuit corresponding to expression 17-1 and FIG. 11 shows the circuit corresponding to expression 17-2. (Here, it is assumed that tail-biting is not performed.)

At point in time i=3k, the parity bit at point in time i is obtained through the circuit shown in FIG. 9 corresponding to expression 16-0, that is, expression 17-0. At point in time i=3k+1, the parity bit at point in time i is obtained through the circuit shown in FIG. 10 corresponding to expression 16-1, that is, expression 17-1. At point in time i=3k+2, the parity bit at point in time i is obtained through the circuit shown in FIG. 11 corresponding to expression 16-2, that is, expression 17-2. Therefore, the encoder can adopt the configuration of FIG. 12 . In FIG. 12 , a weight control section 130 outputs signals for controlling weight as time elapses. Further, 112 - 0 through 112 -M and 122 - 0 through 122 -M in FIG. 12 change weight as time elapses, based on these signals for controlling weight.

Encoding can be performed also when the time-varying period is other than three and the coding rate is (n−1)/n in the same way as that described above. For example, the gth (g=0, 1, . . . , q−1) parity check polynomial of an LDPC-CC having a time-varying period of q and a coding rate of (n−1)/n is represented as shown in expression 13, and therefore P(D) is represented as follows, where q is not limited to a prime number.

[Math. 18]

P ( D )=( D a#g,1,1 +D a#g,1,2 +1) X 1 ( D )+( D a#g,2,1 +D a#g,2,2 +1) X 2 ( D )+ . . . +( D a#g,n−1,1 +D a#g,n−1,2 +1) X n−1 ( D )+( D b#g,1 +D b#g,2 +1) P ( D )  (18)

When expressed in the same way as expression 17-0 through expression 17-2, expression 18 is represented as follows:

[Math. 19]

P [ i ]= X 1 [ i ]⊕ X 1 [ i− a #g,1,1 ]⊕ X 1 [ i− a #g,1,2 ]⊕ X 2 [ i ]⊕ X 2 [ i− a #g,2,1 ]⊕ X 2 [ i− a #g,2,2 ]⊕ . . . ⊕ X n−1 [ i ]⊕ X n−1 [ i− a #g,n−1,1 ]⊕ X n−1 [ i− a #g,n−1,2 ]⊕ P [ i− b #g,1 ]⊕ P [ i− b #g,2 ]  (19)

where the symbol ⊕ represents the exclusive OR operator.

Here, X r [i] (r=1, 2, . . . , n−1) represents an information bit at point in time i and P[i] represents a parity bit at point in time i.

Therefore, when i%q=k at point in time i, the parity bit at point in time i in expression 18 and expression 19 can be achieved using a formula resulting from substituting k for g in expression 18 and expression 19.

Since an LDPC-CC is a kind of convolutional code, securing belief in decoding of information bits requires termination or tail-biting, or performing tail-biting. Here, a case is considered where termination is performed (hereinafter, information-zero-termination, or simply zero-termination).

FIG. 13 is a diagram illustrating information-zero-termination for an LDPC-CC having a coding rate of (n−1)/n. It is assumed that information bits X 1 , X 2 , . . . , X n−1 and parity bit P at point in time i (i=0, 1, 2, 3, . . . , s) are represented by X 1,i , X 2,i , . . . , X n−1,i , and parity bit P i , respectively. As shown in FIG. 13 , X n−1,s is assumed to be the final bit of the information to transmit.

If the encoder performs encoding only until point in time s and the transmitting apparatus on the encoding side performs transmission only up to P s to the receiving apparatus on the decoding side, receiving quality of information bits of the decoder considerably deteriorates. To solve this problem, encoding is performed assuming information bits from final information bit X n−1,s onward (hereinafter virtual information bits) to be zeroes, and a parity bit ( 1303 ) is generated.

To be more specific, as shown in FIG. 13 , the encoder performs encoding assuming X 1,k , X 2,k , . . . , X n−1,k (k=t1, t2, . . . , tm) to be zeroes and obtains P t1 , P t2 , . . . , P tm . After transmitting X 1,s , X 2,s , . . . , X n−1,s , and P s at point in time s, the transmitting apparatus on the encoding side transmits P t1 , P t2 , . . . , P tm . The decoder performs decoding taking advantage of knowing that virtual information bits are zeroes from point in time s onward.

In termination such as information-zero-termination, for example, LDPC-CC encoder 100 in FIG. 12 performs encoding assuming the initial state of the register is zero. As another interpretation, when encoding is performed from point in time i=0, if, for example, z is less than zero in expression 19, encoding is performed assuming X 1 [z], X 2 [z], . . . , X n−1 [z], and P[z] to be zeroes.

Assuming a sub-matrix (vector) in expression 13 to be H g , a gth sub-matrix can be represented as shown below.

Here, n continuous ones correspond to the terms of X 1 (D), X 2 (D), . . . , X n−1 (D) and P(D) in expression 13.

Therefore, when termination is used, the LDPC-CC check matrix having a coding rate of (n−1)/n and a time-varying period of q represented by expression 13 is represented as shown in FIG. 14 .

As shown in FIG. 14 , a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 14 ). However, an element to the left of the first column (H′ 1 in the example of FIG. 14 ) is not reflected in the parity check matrix (see FIG. 14 ). When transmission vector u is assumed to be u=(X 1,0 , X 2,0 , . . . , X n−1,0 , P 0 , X 1,1 , X 2,1 , . . . , X n−1,1 , P 1 , . . . , X 1,k , X 2,k , . . . , X n−1,1 , P k , . . . ) T , Hu=0 holds true. (Here, the zero in Hu=0 indicates that vector Hu is a column vector all elements of which are zeroes.)

As described above, the encoder receives information bits X r [i] (r=1, 2, . . . , n−1) at point in time i as input, generates parity bit P[i] at point in time i using expression 19, outputs parity bit [i], and can thereby perform encoding of the LDPC-CC described in embodiment 1.

The following describes a conventional time-varying LDPC-CC having a coding rate of R=(n−1)/n (where n is an integer no smaller than two). Information bits of X 1 , X 2 , . . . and X n−1 and parity bit P at point in time j are represented by X 1,j , X 2,j , . . . , X n−1,j , and P j , respectively. Vector u j at point in time j is represented by u j =(X 1,j , X 2,j , . . . , X n−1,j , P j ) Furthermore, the encoded sequence is represented by u=(u 0 , u 1 , . . . , u j , . . . ) T . Assuming D to be a delay operator, the polynomial of information bits X 1 , X 2 , . . . , X n−1 is represented by X 1 (D), X 2 (D), . . . , X n−1 (D) and the polynomial of parity bit P is represented by P(D). At this time, consider a parity check polynomial that satisfies zero represented as shown in expression 21.

[Math. 21]

( D a 1,1 +D a 1,2 + . . . +D a 1,r1 +1) X 1 ( D )+( D a 2,1 +D a 2,2 + . . . +D a 2,r2 +1) X 2 ( D )+ . . . +( D a n−1,1 +D a n−1,2 + . . . +D a n−1,r1 +1) X n−1 ( D )+( D b 1 +D b 2 + . . . +D b ε +1) P ( D )=0  (21)

In expression 21, it is assumed that a p,q (p=1, 2, . . . , n−1; q=1, 2, . . . , r p ) and b s (s=1, 2, . . . , ε) are natural numbers. Furthermore, a p,y ≠a p,z is satisfied for ∀ (y, z) of y, z=1, 2, . . . , r p , y≠z. Furthermore, b y ≠b z is satisfied for ∀ (y, z) of y, z=1, 2, . . . , ε, y≠z. Here, ∀ is the universal quantifier.

To create an LDPC-CC having a coding rate of R=(n−1)/n and a time-varying period of m, a parity check polynomial based on expression 21 is provided. At this time, an ith (i=0, 1, . . . , m−1) parity check polynomial is represented as shown in expression 22.

[Math. 22]

A X1,i ( D ) X 1 ( D )+ A X2,i ( D ) X 2 ( D )+ . . . + A Xn−1,i ( D ) X n−1 ( D )+ B i ( D ) P ( D )=0  (22)

In expression 22, maximum orders of D of A Xδ,i (D) (δ=1, 2, . . . , n−1) and B i (D) are represented by Γ Xδ,i and Γ P,i , respectively. A maximum value of Γ Xδ,i and Γ P,i is assumed to be Γ i . A maximum value of Γ i (i=0, 1, . . . , m−1) is assumed to be Γ. When encoded sequence u is taken into consideration, using Γ, vector h i corresponding to an ith parity check matrix is represented as shown in expression 23.

[Math. 23]

h i =[ h i,Γ ,h i,Γ-1 , . . . ,h i,1 ,h i,0 ]  (23)

In expression 23, h i,v (v=0, 1, . . . , Γ) is a vector of 1×n and represented as shown in expression 24.

[Math. 24]

h i,v =[α i,v,X1 ,α i,v,X2 , . . . ,α i,v,Xn−1 ,β i,v ]  (24)

This is because the parity check polynomial of expression 22 has α i,v,Xw D v X w (D) and α i,v D v P(D) (w=1, 2, . . . , n−1, and α i,v,Xw , β i,v ε[0, 1]). At this time, the parity check polynomial that satisfies zero of expression 22 has D 0 X 1 (D), D 0 X 2 (D), . . . , D 0 X n−1 (D) and D 0 P(D), and therefore satisfies expression 25.

In expression 25, Λ(k)=Λ(k+m) is satisfied for ∀ k, where Λ(k) corresponds to h i on a kth row of the parity check matrix.

Using expression 23, expression 24 and expression 25, an LDPC-CC parity check matrix based on the parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m is represented as shown in expression 26.

[ Math . ⁢ 26 ] H =   [ ⋱ ⋱ h 0 , Γ h 0 , Γ - 1 … … … … … h 0 , 0 h 1 , Γ … … … … … h 1 , 1 h 1 , 0 ⋱ ⋱ h m - 1 , Γ h m - 1 , Γ - 1 … … … … … h m - 1 , 0 h 0 , Γ … … … … … h 0 , 1 h 0 , 0 ⋱ ⋱ h m - 1 , Γ … … … … … … h m - 1 , 0 ⋱ ⋱ ] ( 26 )

[Overview of LDPC-CC Based on Parity Check Polynomial]

The following describes important items relating to an LDPC-CC based on a parity check polynomial having a time-varying period greater than three.

An LDPC-CC is a code defined by a low-density parity check matrix as in the case of an LDPC-BC, can be defined by a time-varying parity check matrix of an infinite length, but can actually be considered with a periodically time-varying parity check matrix.

Assuming that a parity check matrix is H and a syndrome former is H T , H T of an LDPC-CC having a coding rate of R=d/c (d<c) can be represented as shown in expression 27.

In expression 27, H T i (t) (i=0, 1, . . . , m s ) is a c×(c−d) periodic sub-matrix and if the period is assumed to be T s , H T i (t)=H T i (t+T s ) holds true for ∀ i and ∀ t. Furthermore, M s is a memory size.

The LDPC-CC defined by expression 27 is a time-varying convolutional code and this code is called a time-varying LDPC-CC. As for decoding, BP decoding is performed using parity check matrix H. When encoded sequence vector u is assumed, the following relational expression holds true.

[Math. 28]

Hu= 0  (28)

An information sequence is obtained by performing BP decoding using the relational expression in expression 28.

<LDPC-CC Based on Parity Check Polynomial>

Consider a systematic convolutional code of a coding rate of R=1/2 of generator matrix G=[1G 1 (D)/G 0 (D)]. At this time, G 1 represents a feed forward polynomial and G 0 represents a feedback polynomial.

Assuming a polynomial representation of an information sequence is X(D) and a polynomial representation of a parity sequence is P(D), a parity check polynomial that satisfies zero can be represented as shown below.

[Math. 29]

G 1 ( D ) X ( D )+ G 0 ( D ) P ( D )=0  (29)

Here, the parity check polynomial is provided as expression 30 that satisfies expression 29.

[Math. 30]

( D a 1 +D a 2 + . . . +D a r +1) X ( D )+( D b 1 +D b 2 + . . . +D b s +1) P ( D )=0  (30)

In expression 30, a p and b q are integers no smaller than one (p=1, 2, . . . , r; q=1, 2, . . . , s), terms of D 0 are present in X(D) and P(D). The code defined by a parity check matrix based on the parity check polynomial that satisfies zero of expression 30 becomes a time-invariant LDPC-CC.

An m (m is an integer no smaller than two) number of different parity check polynomials based on expression 30 are provided. The parity check polynomial that satisfies zero is represented as shown below.

[Math. 31]

A i ( D ) X ( D )+ B i ( D ) P ( D )=0  (31)

At this time, i=0, 1, . . . , m−1.

The data and parity at point in time j are represented by X j and P j as u j =(X j , P j ). It is then assumed that the parity check polynomial that satisfies zero of expression 32 holds true.

[Math. 32]

A k ( D ) X ( D )+ B k ( D ) P ( D )=0( k=j mod m )  (32)

Parity P j at point in time j can then be determined from expression 32. The code defined by the parity check matrix generated based on the parity check polynomial that satisfies zero of expression 32 becomes an LDPC-CC having a time-varying period of m (TV-m-LDPC-CC: Time-Varying LDPC-CC with a time period of m).

At this time, there are terms of D° in P(D) of the time-invariant LDPC-CC defined in expression 30 and TV-m-LDPC-CC defined in expression 32, where b j is an integer no smaller than zero. Therefore, there is a characteristic that parity can be easily found sequentially by means of a register and exclusive OR (when tail-biting is not performed).

The decoding section creates parity check matrix H from expression 30 using the time-invariant LDPC-CC and creates parity check matrix H from expression 32 using the TV-m-LDPC-CC. The decoding section performs BP decoding on encoded sequence u=(u 0 , u 1 , . . . , u j , . . . ) T using expression 28 and obtains an information sequence.

Next, consider a time-invariant LDPC-CC and TV-m-LDPC-CC of a coding rate of (n−1)/n (where n is an integer no smaller than two). It is assumed that information sequence X 1 , X 2 , . . . , X n−1 and parity P at point in time j are represented by X 2,j , . . . , X n−1,j , and P j respectively, and u j =(X 1,j , X 2,j , . . . , X n−1,j , P j ). When it is assumed that a polynomial representation of information sequence X 1 , X 2 , . . . , X n−1 is X 1 (D), X 2 (D), . . . , X n−1 (D), the parity check polynomial that satisfies zero is represented as shown below.

[Math. 33]

( D a 1,1 +D a 1,2 + . . . +D a 1,r1 +1) X 1 ( D )+( D a 2,1 +D a 2,2 + . . . +D a 2,r2 +1) X 2 ( D )+ . . . +( D a n−1,1 +D a n−1,2 + . . . +D a n−1,rn−1 +1) X n−1 ( D )+( D b 1 +D b 2 + . . . +D b s +1) P ( D )=0  (33)

In expression 33, a p,i is an integer no smaller than one (p=1, 2, . . . , n−1; i=1, 2, . . . r p ), and satisfies a p,y ≠a p,z ( ∀ (y, z)|y, z=1, 2, . . . , r p , y≠z) and b≠b z ( ∀ (y, z)|y, z=1, 2, . . . , ε, y≠z).

m (m is an integer no smaller than two) different parity check polynomials based on expression 33 are provided. A parity check polynomial that satisfies zero is represented as shown below.

[Math. 34]

A X1,i ( D ) X 1 ( D )+ A X2,i ( D ) X 2 ( D )+ . . . + A Xn−1,i ( D ) X n−1 ( D )+ B i ( D ) P ( D )=0  (34)

where i=0, 1, . . . , m−1.

It is then assumed that expression 35 holds true for X 1,j , X 2,j , . . . , X n−1,j , and P j of information X 1 , X 2 , . . . , X n−1 and parity P at point in time j.

[Math. 35]

A X1,k ( D ) X 1 ( D )+ A X2,k ( D ) X 2 ( D )+ . . . + A Xn−1,k ( D ) X n−1 ( D )+ B k ( D ) P ( D )=0( k=j mod m )  (35)

At this time, the codes based on expression 33 and expression 35 become time-invariant LDPC-CC and TV-m-LDPC-CC having a coding rate of (n−1)/n.

The following describes a regular TV-m-LDPC-CC.

A #qth parity check polynomial of a TV-m-LDPC-CC of a coding rate of (n−1)/n that satisfies zero is provided as shown below (q=0, 1, . . . , m−1).

[Math. 36]

( D a #q,1,1 +D a #q,1,2 + . . . +D a #q,1,r1 ) X 1 ( D )+( D a #q,2,1 +D a #q,2,2 + . . . +D a #q,2,r2 ) X 2 ( D )+ . . . +( D a #q,n−1,1 +D a #q,n−1,2 + . . . +D a #q,n−1,rn−1 ) X n−1 ( D )+( D b #q,1 +D b #q,2 + . . . +D b #q,s ) P ( D )=0  (36)

In expression 36, a #q,p,i is an integer no smaller than zero (p=1, 2, . . . , n−1; i=1, 2, . . . , r p ) and satisfies a #q,p,y ≠a #q,p,z ( ∀ (y,z)|y, z=1, 2, . . . , r p , y≠z) and b #q,y ≠b #q,z ( ∀ (y,z)|y, z=1, 2, . . . , ε, y≠z).

The following features are then provided.

Feature 1:

There is a relationship as shown below between the term of D a#α,p,i X p (D) of parity check polynomial #α, the term of D a#β,p,j X p (D) of parity check polynomial #β (α, β=0, 1, . . . , m−1; p=1, 2, . . . , n−1; i, j=1, 2, . . . , r p ) and between the term of D b#α,i P(D) of parity check polynomial #α and the term of D b#β,j P(D) of parity check polynomial #β (α, β=0, 1, . . . , m−1 (β≥α); i, j=1, 2, . . . , r p ).

<1> When β=α:

When {a #α,p,i modm=a #β,p,j modm}∩{i≠j} holds true, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15 .

When {b #α,i modm=b #β,j modm}∩{i≠j} holds true, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15 .

When β≠α:

It is assumed that β−α=L.

1) When a #α,p,i modm<a #β,p,j modm

When (a #β,p,j modm)−(a #α,p,i modm)=L, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15 .

2) When a α,p,i modm>a #β,p,j modm

When (a #β,p,j modm)−(a #α,p,i modm)=L+m, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15 .

3) When b #α,i modm<b #β,j modm

When (b #β,j modm)−(b #α,i modm)=L, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15 .

4) When b #α,i modm>b #β,j modm

When (b #β,j modm)−(b #α,i modm)=L+m, variable node $1 is present which forms edges of both a check node corresponding to parity check polynomial #α and a check node corresponding to parity check polynomial #β as shown in FIG. 15 .

Theorem 1 holds true for cycle length six (CL6: cycle length of six) of a TV-m-LDPC-CC.

Theorem 1: The following two conditions are provided for a parity check polynomial that satisfies zero of the TV-m-LDPC-CC:

There are p and q that satisfy C#1.1: a #q,p,i modm=a #q,p,j modm=a #q,p,k modm, where i≠j, i≠k and j≠k.

There is q that satisfies C#1.2: =b #q,i modm=b #q,j modm=b #q,k modm, where i≠k and j≠k.

There is at least one CL6 when C#1.1 or C#1.2 is satisfied.

Proof:

If it is possible to prove that at least one CL6 is present when a #0,1,i mod m=a #0,1,j modm=a #0,1,k modm when p=1 and q=0, it is possible to prove that at least one CL6 is present also for X 2 (D), . . . , X n−1 (D), P(D) by substituting X 2 (D), . . . , X n−1 (D), P(D) for X 1 (D), if C#1.1 and C#1.2 hold true when q=0.

Furthermore, when q=0 if the above description can be proved, it is possible to prove that at least one CL6 is present also when q=1, . . . , m−1 if C#1.1 and C#1.2 hold true, in the same way of thinking.

Therefore, when p=1, q=0, if a #0,1,i modm=a #0,1,j modm=a #0,1,k modm holds true, it is possible to prove that at least one CL6 is present.

In X 1 (D) when q=0 is assumed for a parity check polynomial that satisfies zero of the TV-m-LDPC-CC in expression 36, if two or fewer terms are present, C#1.1 is never satisfied.

In X 1 (D) when q=0 is assumed for a parity check polynomial that satisfies zero of the TV-m-LDPC-CC in expression 36, if three terms are present and a #q,p,i mod m=a #q,p,j modm=a #q,p,k modm is satisfied, the parity check polynomial that satisfies zero of q=0 can be represented as shown in expression 37.

[Math. 37]

( D a #0,1,1 +D a #0,1,2 +D a #0,1,3 ) X 1 ( D )+( D a #0,2,1 +D a #0,2,2 + . . . +D a #0,2,r2 ) X 2 ( D )+ . . . +( D a #0,n−1,1 +D a #0,n−1,2 + . . . +D a #0,n−1,rn−1 ) X n−1 ( D )++( D b #0,1 +D b #0,2 + . . . +D b #0,s ) P ( D )=( D a #0,1,3 +mγ+mδ +D a #0,1,3 +mδ +D a #0,1,3 ) X 1 ( D )+( D a #0,2,1 +D a #0,2,2 + . . . +D a #0,2,r2 ) X 2 ( D )+ . . . +( D a #0,n−1,1 +D a #0,n−1,2 + . . . +D a #0,n−1,rn−1 ) X n−1 ( D )++( D b #0,1 +D b #0,2 + . . . +D b #0,s ) P ( D )=0  (37)

Here, even when a #0,1,1> a #0,1,2> a #0,1,3 is assumed, generality is not lost, and γ and δ become natural numbers. At this time, in expression 37, when q=0, the term relating to X 1 (D), that is, (D a#0,1,3+mγ+mδ +D a#0,1,3+mδ +D a#0,1,3 ) X 1 (D) is focused upon. At this time, a sub-matrix generated by extracting only a portion relating to X 1 (D) in parity check matrix H is represented as shown in FIG. 16 . In FIG. 16 , h 1,X1 , h 2,X1 , . . . , h m−1,X1 are vectors generated by extracting only portions relating to X 1 (D) when q=1, 2, . . . , m−1 in the parity check polynomial that satisfies zero of expression 37, respectively.

At this time, the relationship as shown in FIG. 16 holds true because <1> of feature 1 holds true. Therefore, CL6 formed with a one shown by the symbol Δ as shown in FIG. 16 is always generated only in a sub-matrix generated by extracting only a portion relating to X 1 (D) of the parity check matrix in expression 37 regardless of γ and δ values.

When four or more X 1 (D)-related terms are present, three terms are selected from among four or more terms and if a #0,1,i modm=a #0,1,j modm=a #0,1,k modm holds true in the selected three terms, CL6 is formed as shown in FIG. 16 .

As shown above, when q=0, if a #0,1,i modm=a #0,1,j modm= a#0,1,k modm holds true about X 1 (D), CL6 is present.

Furthermore, by also substituting X 1 (D) for X 2 (D), . . . , X n−1 (D), P(D), at least one CL6 occurs when C#1.1 or C#1.2 holds true.

Furthermore, in the same way of thinking, also for when q=1, . . . , m−1, at least one CL6 is present when C#1.1 or C#1.2 is satisfied.

Therefore, in the parity check polynomial that satisfies zero of expression 37, when C#1.1 or C#1.2 holds true, at least one CL6 is generated.

□ (end of proof)

The #qth parity check polynomial that satisfies zero of a TV-m-LDPC-CC having a coding rate of (n−1)/n, which will be described hereinafter, is provided below based on expression 30 (q=0, . . . , m−1):

[Math. 38]

( D a #q,1,1 +D a #q,1,2 +D a #q,1,3 ) X 1 ( D )+( D a #q,2,1 +D a #q,2,2 +D a #q,2,3 ) X 2 ( D )+ . . . +( D a #q,n−1,1 +D a #q,n−1,2 +D a #q,n−1,3 ) X n−1 ( D )+( D b #q,1 +D b #q,2 +D b #q,3 ) P ( D )=0  (38)

Here, in expression 38, it is assumed that there are three terms in X i (D), X 2 (D), . . . , X n−1 (D) and P(D), respectively.

According to theorem 1, to suppress the occurrence of CL6, it is necessary to satisfy {a#q,p,1 modm≠a#q,p,2 modm}∩{a#q,p,1 modm≠a#q,p,3 modm}∩{a#q,p,2 mod m≠a#q,p,3 modm} in Xq(D) of expression 38. Similarly, it is necessary to satisfy {b#q,1 modm≠b#q,2 modm}∩{b#q,1 modm≠b#q,3 modm}∩{b#q,2 mod m≠b#q,3 modm} in P(D) of expression 38. ∩ represents an intersection.

Then, according to feature 1, the following condition is considered as an example of the condition to be a regular LDPC code.

C#2: for ∀ q, (a #q,p,1 modm, a #q,p,2 modm, a #q,p,3 modM)=(N p,1 , N p,2 , N p,3 )∩(b #q,1 mod m, b #q,2 modm, b #q,3 modm)=(M 1 , M 2 , M 3 ) holds true. However, {a #q,p,1 mod m≠a #q,p,2 modm}∩{a #q,p,1 modm≠a #q,p,3 modm}∩{a #q,p,2 modm≠a #q,p,3 modm} and {b #q,1 modm≠b #q,2 modm}∩{b #q,1 modm≠b #q,3 modm}∩{b #q,2 modm≠b #q,3 modm} is satisfied. Here, the symbol ∀ of ∀ q is a universal quantifier and ∀ q means all q.

The following discussion will treat a regular TV-m-LDPC-CC that satisfies the condition of C#2.

[Code Design of Regular TV-m-LDPC-CC]

Non-Patent Literature 9 shows a decoding error rate when a uniformly random regular LDPC code is subjected to maximum likelihood decoding in a binary-input output-symmetric channel and shows that Gallager's belief function (see Non-Patent Literature 10) can be achieved by a uniformly random regular LDPC code. However, when BP decoding is performed, it is unclear whether or not Gallager's belief function can be achieved by a uniformly random regular LDPC code.

As it happens, an LDPC-CC belongs to a convolutional code. Non-Patent Literature 11 and Non-Patent Literature 12 describe the belief function of the convolutional code and describe that the belief depends on a constraint length. Since the LDPC-CC is a convolutional code, it has a structure specific to a convolutional code in a parity check matrix, but when the time-varying period is increased, positions at which ones of the parity check matrix exist approximate to uniform randomness. However, since the LDPC-CC is a convolutional code, the parity check matrix has a structure specific to a convolutional code and the positions at which ones exist depend on the constraint length.

From these results, inference of inference #1 on a code design is provided in a regular TV-m-LDPC-CC that satisfies the condition of C#2.

Inference #1:

When BP decoding is used, if time-varying period m of a TV-m-LDPC-CC increases in a regular TV-m-LDPC-CC that satisfies the condition of C#2, uniform randomness is approximated for positions at which ones exist in the parity check matrix and a code of high error correction capability is obtained.

The method of realizing inference #1 will be discussed below.

[Feature of Regular TV-m-LDPC-CC]

A feature will be described that holds true when drawing a tree about expression 38 which is a #qth parity check polynomial that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2 having a coding rate of (n−1)/n, which will be treated in the present discussion.

Feature 2:

In a regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is a prime number, consider a case where C#3.1 holds true with attention focused on one of X 1 (D), . . . , X n−1 (D).

C#3.1: In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, a #q,p,i modm≠a #q,p,j modm holds true in X p (D) for ∀ q (q=0, . . . , m−1), where i≠j.

In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to D a#q,p,i X p (D) and D a#q,p,j X p (D) that satisfy C#3.1.

At this time, according to feature 1, there are check nodes corresponding to all #0 to #m−1 parity check polynomials for ∀ q in a tree whose starting point is a check node corresponding to a #qth parity check polynomial that satisfies zero of expression 38.

Similarly, when time-varying period m is a prime number in a regular TV-m-LDPC-CC that satisfies the condition of C#2, consider a case where C#3.2 holds true with attention focused on the term of P(D).

C#3.2: In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, b #q,i modm≠b #q,j modm holds true in P(D) for ∀ q, where i≠j.

In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to D b#q,i P(D) and D b#q,j P(D) that satisfy C#3.2.

At this time, according to feature 1, there are check nodes corresponding to all #0 to #m−1 parity check polynomials for ∀ q in a tree whose starting point is a check node corresponding to a #qth parity check polynomial that satisfies zero of expression 38.

Example: In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, it is assumed that time-varying period m=7 (prime number) and (b #q,1 , b #q,2 )=(2, 0) holds true for ∀ q. Therefore, C#3.2 is satisfied.

When a tree is drawn exclusively for variable nodes corresponding to D b#q,1 P(D) and D b#q,2 P(D), a tree whose starting point is a check node corresponding to a #0th parity check polynomial that satisfies zero of expression 38 is represented as shown in FIG. 17 . As is clear from FIG. 17 , time-varying period m=7 satisfies feature 2.

Feature 3:

In a regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is not a prime number, consider a case where C#4.1 holds true with attention focused on one of X 1 (D), . . . , X n−1 (D).

C#4.1: In parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2, when a #q,p,i modm≥a #q,p,j modm in X p (D) for ∀ q, |a #q,p,i modm-a #q,p,j modm| is a divisor other than one of m, where i≠j.

In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to D a#q,p,i X p (D) and D a#q,p,j X p (D) that satisfy C#4.1. At this time, according to feature 1, in the tree whose starting point corresponds to the #q-th parity check polynomial that satisfies zero of expression 38, there is no check node corresponding to all #0 to #m−1 parity check polynomials for ∀ q.

Similarly, in the regular TV-m-LDPC-CC that satisfies the condition of C#2, consider a case where C#4.2 holds true when time-varying period m is not a prime number with attention focused on the term of P(D).

C#4.2: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, when b #q,i modm≥b #q,j modm in P(D) for ∀ q, |b #q,i modm−b #q,j modm| is a divisor other than one of m, where i≠j.

In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to D b#q,i P(D) and D b#q,j P(D) that satisfy C#4.2. At this time, according to feature 1, in the tree whose starting point is a check node corresponds to the #qth parity check polynomial that satisfies zero of expression 38, there are not all check nodes corresponding to #0 to #m−1 parity check polynomials for ∀ q.

Example: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, it is assumed that time-varying period m=6 (not a prime number) and (b #q,1 , b #q,2 )=(3, 0) holds true for ∀ q. Therefore, C#4.2 is satisfied.

When a tree is drawn exclusively for variable nodes D b#q,1 P(D) and D b#q,2 P(D), a tree whose starting point is a check node corresponding to #0th parity check polynomial that satisfies zero of expression 38 is represented as shown in FIG. 18 . As is clear from FIG. 18 , time-varying period m=6 satisfies feature 3.

Next, in the regular TV-m-LDPC-CC that satisfies the condition of C#2, a feature will be described which particularly relates to when time-varying period m is an even number.

Feature 4:

In the regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is an even number, consider a case where C#5.1 holds true with attention focused on one of X 1 (D), . . . , X n−1 (D).

C#5.1: In parity check polynomial (82) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, when a #q,p,i modm≥a #q,p,j modm in X p (D) for ∀ q, |a #q,p,i modm-a #q,p,j modm| is an even number, where i≠j.

In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to D a#q,p,i X p (D) and D a#q,p,j X p (D) that satisfy C#5.1. At this time, according to feature 1, when q is an odd number, there are only check nodes corresponding to odd-numbered parity check polynomials in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38. On the other hand, when q is an even number, there are only check nodes corresponding to even-numbered parity check polynomials in a tree whose starting point is a check node corresponding to the #q-th parity check polynomial that satisfies zero of expression 38.

Similarly, in the regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is an even number, consider a case where C#5.2 holds true with attention focused on the term of P(D).

C#5.2: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, when b #q,i modm≥b #q,j modm in P(D) for ∀ q, |b #q,i modm−b #q,j modM is an even number, where i≠j.

In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to D b#q,i P(D) and D b#q,j P(D) that satisfy C#5.2. At this time, according to feature 1, when q is an odd number, only check nodes corresponding to odd-numbered parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38. On the other hand, when q is an even number, only check nodes corresponding to even-numbered parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38.

[Design Method of Regular TV-m-LDPC-CC]

A design policy will be considered for providing high error correction capability in the regular TV-m-LDPC-CC that satisfies the condition of C#2. Here, a case of C#6.1, C#6.2, or the like will be considered.

C#6.1: In parity check polynomial (82) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to D a#q,p,i X p (D) and D a#q,p,j X p (D) (where i≠j). At this time, all check nodes corresponding to #0 to #m−1 parity check polynomials for ∀ q are not present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38.

C#6.2: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to D b#q,i P(D) and D b#q,j P(D) (where i≠j). At this time, all check nodes corresponding to #0 to #m−1 parity check polynomials for ∀ q are not present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38.

In such cases as C#6.1 and C#6.2, since all check nodes corresponding to #0 to #m−1 parity check polynomials for ∀ q are not present, the effect in inference #1 when the time-varying period is increased is not obtained. Therefore, with the above description taken into consideration, the following design policy is given to provide high error correction capability.

[Design Policy]: In the Regular TV-m-LDPC-CC that Satisfies the Condition of C#2, a Condition of C#7.1 is Provided with Attention Focused on One of X 1 (D), . . . , X n−1 (D).

C#7.1: A case will be considered where a tree is drawn exclusively for variable nodes corresponding to D a#q,p,i X p (D) and D a#q,p,j X p (D) in parity check polynomial (38) that satisfies zero of a regular TV-m-LDPC-CC that satisfies the condition of C#2 (where i≠j). At this time, check nodes corresponding to all #0 to #m−1 parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38 for ∀ q.

Similarly, in the regular TV-m-LDPC-CC that satisfies the condition of C#2, the condition of C#7.2 is provided with attention focused on the term of P(D).

C#7.2: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, a case will be considered where a tree is drawn exclusively for variable nodes corresponding to D b#q,i P(D) and D b#q,j P(D) (where i≠j). At this time, check nodes corresponding to all #0 to #m−1 parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38 for ∀ q.

In the present design policy, it is assumed that C#7.1 holds true for ∀ (i, j) and also holds true for ∀ p, and C#7.2 holds true for ∀ (i, j).

Inference #1 is then satisfied.

Next, a theorem relating to the design policy will be described.

Theorem 2: Satisfying the design policy requires a #q,p,i modm≠a #q,p,j modm and b #q,i modm≠b #q,j modm to be satisfied, where i≠j.

Proof: When a tree is drawn exclusively for variable nodes corresponding to D a#q,p,i X p (D) and D a#q,p,j X p (D) in expression 38 of the parity check polynomial that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, if theorem 2 is satisfied, check nodes corresponding to all #0 to #m−1 parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38. This holds true for all p.

Similarly, when a tree is drawn exclusively for variable nodes corresponding to D b#q,i P(D) and D b#q,j P(D) in expression 38 of the parity check polynomial that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, if theorem 2 is satisfied, check nodes corresponding to all #0 to #m−1 parity check polynomials are present in a tree whose starting point is a check node corresponding to the #qth parity check polynomial that satisfies zero of expression 38.

Therefore, theorem 2 is proven.

□ (end of proof)

Theorem 3: In the regular TV-m-LDPC-CC that satisfies the condition of C#2, when time-varying period m is an even number, there is no code that satisfies the design policy.

Proof: In parity check polynomial (38) that satisfies zero of the regular TV-m-LDPC-CC that satisfies the condition of C#2, when p=1, if it is possible to prove that the design policy is not satisfied, this means that theorem 3 has been proven. Therefore, the proof is continued assuming p=1.

In the regular TV-m-LDPC-CC that satisfies the condition of C#2, (N p,1 , N p,2 , N p,3 )=(o, o, o)∪(o, o, e)∪(o, e, e)∪(e, e, e) can represent all cases. Here, o represents an odd number and e represents an even number. Therefore, (N p,1 , N p,2 , N p,3 )=(o, o, o)∪(o, o, e)∪(o, e, e)∪(e, e, e) shows that C#7.1 is not satisfied. U represents a union.

When (Np, 1 , Np, 2 , Np, 3 )=(o, o, o), C#5.1 is satisfied so that i, j=1, 2, 3 (i≠j) is satisfied in C#5.1 no matter what the value of the set of (i, j) may be.

When (Np, 1 , Np, 2 , Np, 3 )=(o, o, e), C#5.1 is satisfied when (i, j)=(1, 2) in C#5.1.

When (Np, 1 , Np, 2 , Np, 3 )=(o, e, e), C#5.1 is satisfied when (i, j)=(2, 3) in C#5.1.

When (Np, 1 , Np, 2 , Np, 3 )=(e, e, e), C#5.1 is satisfied so that i, j=1, 2, 3 (i≠j) is satisfied in C#5.1 no matter what the value of the set of (i, j) may be.

Therefore, when (Np, 1 , Np, 2 , Np, 3 )=(o, o, o)∪(o, o, e)∪(o, e, e)∪(e, e, e), there are always sets of (i, j) that satisfy C#5.1. Thus, theorem 3 has been proven according to feature 4.

□ (end of proof)

Therefore, to satisfy the design policy, time-varying period m must be an odd number. Furthermore, to satisfy the design policy, the following conditions are effective according to feature 2 and feature 3.

Time-varying period m is a prime number. Time-varying period m is an odd number and the number of divisors of m is small.

Especially, when the condition that time-varying period m is an odd number and the number of divisors of m is small is taken into consideration, the following cases can be considered as examples of conditions under which codes of high error correction capability are likely to be achieved: (Note that the following cases are mere examples, and codes of high error correction capability may be achieved under other conditions.)

(1) The time-varying period m is assumed to be α×β,

where α and β are odd numbers other than one and are prime numbers.

(2) The time-varying period m is assumed to be α n ,

where α is an odd number other than one and is a prime number, and n is an integer no smaller than two.

(3) The time-varying period m is assumed to be α×β×γ,

where α, β, and γ are odd numbers other than one and are prime numbers.

However, when z mod m (z is an integer no smaller than zero) is computed, there are m values that can be taken, and therefore the number of values taken when z mod m is computed increases as m increases. Therefore, when m is increased, it is easier to satisfy the above-described design policy. However, when time-varying period m is assumed to be an even number, this does not mean that a code having high error correction capability cannot be obtained.

The following describes tail-biting in an LDPC-CC. An LDPC-CC based on parity check polynomials described in Non-Patent Literature 13 is described first, as an example.

A time-varying LDPC-CC having a coding rate of R=(n−1)/n based on parity check polynomials is described below. At time j, the information bits X 1 , X 2 , . . . , X n−1 and the parity bit P are respectively represented as X 1,j , X 2,j , . . . , X n−1,j and P j . Thus, vector u j at time j is expressed as u j =(X 1,j , X 2,j , . . . , X n−1,j , P j ). Also, the encoded sequence is expressed as u=(u 0 , u 1 , . . . , u j , . . . ) T . Given a delay operator D, the polynomial of the information bits X 1 , X 2 , . . . , X n−1 is expressed as X 1 (D), X 2 (D), . . . , X n−1 (D), and the polynomial of the parity bit P is expressed as P(D). Thus, a parity check polynomial satisfying zero is expressed by expression 39.

[Math. 39]

( D a 1,1 +D a 1,2 + . . . +D a 1,r1 +1) X 1 ( D )+( D a 2,3 +D a 2,2 + . . . +D a 2,r2 +1) X 2 ( D )+ . . . +( D a n−1,1 +D a n−1,2 + . . . +D a n−1,rn−1 +1) X n−1 ( D )+( D b 1 +D b 2 + . . . +D b ε +1) P ( D )=0  (39)

In expression 39, a p,q (p=1, 2, . . . , n−1; q=1, 2, . . . , r p ) and b s (s=1, 2, . . . , ε) are natural numbers. Also, for ∀ (y, z) where y, z=1, 2, . . . , r, y≠z, a p,y ≠a p,z holds. Also, for ∀ (y, z) where y, z=1, 2, . . . , ε, y≠z, b y ≠b z holds.

In order to create an LDPC-CC having a time-varying period of m and a coding rate of R=(n−1)/n, a parity check polynomial that satisfies zero based on expression 39 is prepared. A parity check polynomial that satisfies zero for the ith (i=0, 1, . . . , m−1) is expressed as follows in expression 40.

[Math. 40]

A X1,i ( D ) X 1 ( D )+ A X2,i ( D ) X 2 ( D )+ . . . + A Xn−1,i ( D ) X n−1 ( D )+ B i ( D ) P ( D )=0  (40)

In expression 40, the maximum degrees of D in A Xδ,i (D) (δ=1, 2, . . . , n−1) and B i (D) are, respectively, Γ Xδ,i and Γ P,i . The maximum values of Γ Xδ,i and Γ P,i are Γ i . The maximum value of Γ i (i=0, 1, . . . , m−1) is Γ. Taking the encoded sequence u into consideration and using Γ, vector h i corresponding to the ith parity check polynomial is expressed as follows in expression 41.

[Math. 41]

h i =[ h i,Γ ,h i,Γ-1 , . . . ,h i,1 ,h i,0 ]  (41)

In expression 41, h i,v (v=0, 1, . . . , Γ) is a 1×n vector expressed as [α i,v,X1 , α i,v,X2 , . . . , α i,v,Xn−1 , β i,v ]. This is because, for the parity check polynomial of expression 41, α i,v,Xw D v X w (D) and β i,v D v P(D) (w=1, 2, . . . , n−1, and α i,v,Xw ,β i,v ε[0,1]). In such cases, the parity check polynomial that satisfies zero for expression 41 has terms D 0 X 1 (D), D 0 X 2 (D), . . . , D 0 X n−1 (D) and D 0 P(D), thus satisfying expression 42.

Using expression 42, the check matrix of the LDPC-CC based on the parity check polynomial having a time-varying period of m and a coding rate of R=(n−1)/n is expressed as follows in expression 43.

In expression 43, Λ(k)=Λ(k+m) is satisfied for ∀ k. Here, Λ(k) corresponds to h i at the kth row of the parity check matrix.

Although expression 39 is handled, above, as a parity check polynomial serving as a base, no limitation to the format of expression 39 is intended. For example, instead of expression 39, a parity check polynomial satisfying zero for expression 44 may be used.

[Math. 44]

( D a 1,1 +D a 1,2 + . . . +D a 1,r1 ) X 1 ( D )+( D a 2,1 +D a 2,2 + . . . +D a 2,r2 ) X 2 ( D )+ . . . +( D a n−1,1 +D a n−1,2 + . . . +D a n−1,rn−1 ) X n−1 ( D )+( D b 1 +D b 2 + . . . +D b ε ) P ( D )=0  (44)

In expression 44, a p,q (p=1, 2, . . . , n−1; q=1, 2, . . . , r p ) and b s (s=1, 2, . . . , δ) are natural numbers. Also, for ∀ (y, z) where y, z=1, 2, . . . , r p , y≠z, a p,y ≠a p,z holds. Also, for ∀ (y, z) where y, z=1, 2, . . . , ε, y≠z, b y ≠b z holds.

The following describes a tail-biting scheme for the present embodiment, using time-varying LDPC-CC based on the above-described parity check polynomial.

[Tail-Biting Scheme]

For the LDPC-CC based on the above-discussed parity check polynomials, the gth (g=0, 1, . . . , q−1) that satisfies zero for a time-varying period of q is expressed below as a parity check polynomial (see expression 40) of expression 45.

[Math. 45]

( D a#g,1,1 +D a#g,1,2 +1) X 1 ( D )+( D a#g,2,1 +D a#g,2,2 +1) X 2 ( D )+ . . . +( D a#g,n−1,1 +D a#g,n−1,2 +1) X n−1 ( D )+( D b#g,1 +D b#g,2 +1) P ( D )=0  (45)

Let a #g,p,1 and a #g,p,2 be natural numbers, and let a #g,p,1 ≠a #g,p,2 hold true. Furthermore, let b #g,1 and b #g,2 be natural numbers, and let b #g,1 ≠b #g,2 hold true (g=0, 1, 2, . . . , q−1; p=1, 2, . . . , n−1). For simplicity, the quantity of terms X 1 (D), X 2 (D), . . . X n−1 (D) and P(D) is three.

Assuming a sub-matrix (vector) in a parity check matrix to be H g , a gth sub-matrix can be represented as expression 46, shown below.

In expression 46, the n consecutive ones correspond to the terms X 1 (D), X 2 (D), X n−1 (D) and P(D) in each form of expression 45.

Here, parity check matrix H can be represented as shown in FIG. 19 . As shown in FIG. 19 , a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 19 ). In addition, a sub-matrix is shifted n columns to the right between an (i+1)th row and ith row in parity check matrix H. Thus, the data at time k for information X 1 , X 2 , . . . , X n−1 and parity P are respectively given as X 1,k , X 2,k , . . . , X n−1,k, , and P k . When transmission vector u is given as u=(X 1,0 , X 2,0 , . . . , X n−1,0 , P 0 , X 1,1 , X 2,1 , . . . , X n−1,1 , P 1 , . . . , X 1,k , X 2,k , . . . , X n−1,k , P k , . . . ) T , Hu=0 holds true. (Here, the zero in Hu=0 indicates that vector Hu is a (column) vector all elements of which are zeroes.)

In Non-Patent Literature 14, a check matrix is described for when tail-biting is employed. The parity check matrix is given as follows.

In expression 47, H is the check matrix and H T is the syndrome former. Also, H T i (t) (i=0, 1, . . . , M s ) is a c×(c−b) sub-matrix, and M s is the memory size.

FIG. 19 and expression 47 show that, for the LDPC-CC having a coding rate of (n−1)/n and a time-varying period of q that is based on the parity check polynomial, the parity check matrix H required for decoding that obtains greater error-correction capability strongly prefers the following conditions.

<Condition #1>

The number of rows in the parity check matrix is a multiple of q.

Accordingly, the number of columns in the parity check matrix is a multiple of n×q. Here, the (for example) log-likelihood ratio needed upon decoding is the log-likelihood ratio of the bit portion that is a multiple of n×q.

Here, the parity check polynomial that satisfies zero for the LDPC-CC having a coding rate of (n−1)/n and a time-varying period of q required by Condition #1 is not limited to that of expression 45, but may also be the time-varying LDPC-CC based on expression 39 or 44.

Incidentally, for the parity check polynomial, when there is only one parity term P(D), expression 47 is expressible as expression 48.

[Math. 48]

( D a#g,1,1 +D a#g,1,2 +1) X 1 ( D )+( D a#g,2,1 +D a#g,2,2 +1) X 2 ( D )+ . . . +( D a#g,n−1,1 +D a#g,n−1,2 +1) X n−1 ( D )+ P ( D )=0  (48)

Such a time-varying period LDPC-CC is a type of feed-forward convolutional code. Thus, a coding scheme given by Non-Patent Literature 15 or Non-Patent Literature 16 can be applied as the coding scheme used when tail-biting is used. The procedure is as shown below.

<Procedure 1>

For example, the time-varying LDPC-CC defined by expression 48 has a term P(D) expressed as follows.

[Math. 49]

P ( D )=( D a#g,1,1 +D a#g,1,2 +1) X 1 ( D )+( D a#g,2,1 +D a#g,2,2 +1) X 2 ( D )+ . . . +( D a#g,n−1,1 +D a#g,n−1,2 +1) X n−1 ( D )  (49)

Then, expression 49 is represented as follows.

[Math. 50]

P [ i ]= X 1 [ i ]⊕ X 1 [ i− a #g,1,1 ]⊕ X 1 [ i− a #g,1,2 ]⊕ X 2 [ i ]⊕ X 2 [ i− a #g,2,1 ]⊕ X 2 [ i− a #g,2,2 ]⊕ . . . ⊕ X n−1 [ i ]⊕ X n−1 [ i− a #g,n−1,1 ]⊕ X n−1 [ i− a #g,n−1,2 ]  (50)

where ⊕ represents the exclusive OR operator.

Accordingly, at time i, when (i−1)%q=k (% represents the modulo operator), parity is calculated in expression 49 and expression 50 at time i when g=k. The registers are initialized to values of zero. That is, using expression 49, when (i−1)%q=k at time i (i=1, 2, . . . ), then in expression 49, the parity at time i is calculated for g=k. In expression 49, for terms X 1 [z], X 2 [z], . . . , X n−1 [z] and P[z], any term for which z is less than one is taken as a zero and expression 49 is used for coding. Calculations proceed up to the final parity bit. The state of each register of the encoder at this time is stored.

<Procedure 2>

Coding is performed a second time from time i=1 from the state of the registers stored during Procedure 1 (that is, for terms X 1 [z], X 2 [z], . . . , X n−1 [Z], and P[z] of expression 49, the values obtained using Procedure 1 are used where z is less than one) and parity is calculated.

The parity bit and information bits obtained at this time constitute an encoded sequence when tail-biting is performed.

However, upon comparison of feed-forward LDPC-CCs and feedback LDPC-CCs under conditions of having the same coding rate and substantially similar constraint lengths, the feedback LDPC-CCs have a stronger tendency to exhibit strong error-correction capability but present difficulties in calculating the encoded sequence (i.e., calculating the parity). The following presents a new tail-biting scheme as a solution to this problem, enabling simple encoded sequence (parity) calculation.

First, a parity check matrix for performing tail-biting with an LDPC-CC based on a parity check polynomial is described.

For example, for the LDPC-CC based on the parity check polynomial having a time-varying period of q and a coding rate of (n−1)/n as defined by expression 45, the information terms X 1 , X 2 , . . . , X n−1 and the parity term P are represented at time i as X 1,i , X 2,i , . . . , X n−1,i , and P 1 . Then, in order to satisfy Condition #1, tail-biting is performed such that i=1, 2, 3, . . . , q, . . . , q×N−q+1, q×N−q+2, q×N−q+3, q×N.

Here, N is a natural number, the transmission sequence u is u=(X 1,1 , X 2,1 , . . . , X n−1,1 , P 0 , X 1,2 , X 2,2 , . . . , X n−1,2 , P 2 , . . . , X 1,k , X 2,k , . . . , X n−1,k , P k , . . . , X 1,q×N , X 2,q×N , . . . , X n−1,q×N , P q×N ) T , and Hu=0 all hold true. (Here, the zero in Hu=0 indicates that vector Hu is a (column) vector all elements of which are zeroes.)

The configuration of the parity check matrix is described using FIGS. 20 and 21 .

Assuming a sub-matrix (vector) in expression 45 to be Hg, a gth sub-matrix can be represented as expression 51, shown below.

In expression 51, the n consecutive ones correspond to the terms X 1 (D), X 2 (D), X n−1 (D), and P(D) in each form of expression 45.

Among the parity check matrix corresponding to the transmission sequence u defined above, the parity check matrix in the vicinity of time q×N are represented by FIG. 20 . As shown in FIG. 20 , a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 20 ).

Also, in FIG. 20 , the q×Nth (i.e., the last) row of the parity check matrix has reference sign 2001 , and corresponds to the (q−1)th parity check polynomial that satisfies zero in order to satisfy Condition #1. The q×N−1th row of the parity check matrix has reference sign 2002 , and corresponds to the (q−2)th parity check polynomial that satisfies zero in order to satisfy Condition #1. Reference sign 2003 represents a column group corresponding to time q×N. Column group 2003 is arranged in the order X 1,q×N , X 2,q×N , . . . , X n−1,q×N , P q×N . Reference sign 2004 represents a column group corresponding to time q×N−1. Column group 2004 is arranged in the order X 1,q×N−1 , X 2,q×N−1 , . . . , X n−1,q×N−1 , P q×N−1 .

Next, by reordering the transmission sequence, the parity check matrix corresponding to u=( . . . , X 1,q×N−1 , X 2,q×N−1 , . . . , X n−1,q×N−1 , P q×N−1 , X 1,q×N , X 2,q×N , . . . , X n−1,q×N , P q×N , X 1,0 , X 2,1 , . . . , X n−1,1 , P 1 , X 1,2 , X 2,2 , . . . , X n−1,2 , P 2 , . . . ) T in the vicinity of times q×N—1, q×N, 1, 2 is the parity check matrix shown in FIG. 21 . Here, the parity check matrix portion shown in FIG. 21 is a characteristic portion when tail-biting is performed. The configuration thereof is identical to the configuration shown in expression 47. As shown in FIG. 21 , a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and (i+1)th row in parity check matrix H (see FIG. 21 ).

Also, in FIG. 21 , when expressed as a parity check matrix like that of FIG. 20 , reference sign 2105 corresponds to the (q×N×n)th column and, when similarly expressed as a parity check matrix like that of FIG. 20 , reference sign 2106 corresponds to the first column.

Reference sign 2107 represents a column group corresponding to time q×N−1. Column group 2107 is arranged in the order X 1,q×N−1 , X 2,q×N−1 , . . . , X n−1,q×N−1 , P q×N−1 . Reference sign 2108 represents a column group corresponding to time q×N. Column group 2108 is arranged in the order X 1,q×N , X 2,q×N , . . . , X n−1,q×N , Pq×N. Reference sign 2109 represents a column group corresponding to time 1. Column group 2109 is arranged in the order X 1,1 , X 2,1 , . . . , X n−1,1 , P 1 . Reference sign 2110 represents a column group corresponding to time 2. Column group 2110 is arranged in the order X 1,2 , X 2,2 , . . . , X n−1,2 , P 2 .

When expressed as a parity check matrix like that of FIG. 20 , reference sign 2111 corresponds to the (q×N)th row, and when similarly expressed as a parity check matrix like that of FIG. 20 , reference sign 2112 corresponds to the first row.

In FIG. 21 , the characteristic portion of the parity check matrix on which tail-biting is performed is the portion left of reference sign 2113 and below reference sign 2114 (See also expression 47).

When expressed as a parity check matrix like that of FIG. 20 , and when Condition #1 is satisfied, the rows begin with a row corresponding to a parity check polynomial that satisfies a zeroth zero, and the rows end with a parity check polynomial that satisfies a (q−1)th zero. This point is critical for obtaining better error-correction capability. In practice, the time-varying LDPC-CC is designed such that the code thereof produces a small number of cycles of length each being of a short length on a Tanner graph. As the description of FIG. 21 makes clear, in order to ensure a small number of cycles of length each being of a short length on a Tanner graph when tail-biting is performed, maintaining conditions like those of FIG. 21 , i.e., maintaining Condition #1, is critical.

However, in a communication system, when tail-biting is performed, circumstances occasionally arise in which some shenanigans are required in order to satisfy Condition #1 for the block length (or information length) requested by the system. This point is explained by way of example.

FIG. 22 is an overall diagram of the communication system. The communication system is configured to include a transmitting device 2200 and a receiving device 2210 .

The transmitting device 2200 is in turn configured to include an encoder 2201 and a modulation section 2202 . The encoder 2201 receives information as input, performs encoding, and generates and outputs a transmission sequence. Then, the modulation section 2202 receives the transmission sequence as input, performs predetermined processing such as mapping, quadrature modulation, frequency conversion, and amplification, and outputs a transmission signal. The transmission signal arrives at the receiving device 2210 via a communication medium (radio, power line, light or the like).

The receiving device 2210 is configured to include a receiving section 2211 , a log-likelihood ratio generation section 2212 , and a decoder 2213 . The receiving section 2211 receives a received signal as input, performs processing such as amplification, frequency conversion, quadrature demodulation, channel estimation, and demapping, and outputs a baseband signal and a channel estimation signal. The log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input, generates a log-likelihood ratio in bit units, and outputs a log-likelihood ratio signal. The decoder 2213 receives the log-likelihood ratio signal as input, performs iterative decoding using, specifically, BP (Belief Propagation) decoding (see Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, and Non-Patent Literature 8), and outputs an estimated transmission sequence or (and) an estimated information sequence.

For example, consider an LDPC-CC having a coding rate of 1/2 and a time-varying period of 12 as an example. Assuming that tail-biting is performed at this time, the set information length (coding length) is designated 16384. The information bits are designated X 1,1 , X 1,2 , X 1,3 , . . . , X 1,16384 . If parity bits are determined without any shenanigans, P 1 , P 2 , P3, . . . , P 16384 are determined. However, despite a parity check matrix being created for transmission sequence u=(X 1,1 , P 1 , X 1,2 , P 2 , . . . , X 1,16384 , P 16384 ), Condition #1 is not satisfied. Therefore, X 1,16385 , X 1,16386 , X 1,16387 , and X 1,16388 may be added to the transmission sequence so as to determine P 16385 , P 16386 , P 16387 , and P 16388 . Here, the encoder (transmitting device) is set such that, for example, X 1,16385 =0, X 1,16386 =0, X 1,16387 =0, and X 1,16388 =0, then performs decoding to obtain P 16385 , P 16386 , P 16387 , and P 16388 . However, for the encoder (transmitting device) and the decoder (receiving device), when mutually agreed-upon settings are in place such that X 1,16385 =0, X 1,16386 =0, X 1,16387 =0, and X 1,16388 =0, there is no need to transmit X 1,16385 , X 1,16386 , X 1,16387 , and X 1,16388 .

Accordingly, the encoder takes the information sequence X=(X 1,1 , X 1,2 , X 1,3 , . . . , X 1,16384 , X 1,16385 , X 1,16386 , X 1,16387 , X 1,16388 )=(X 1,1 , X 1,2 , X 1,3 , . . . , X 1,16384 , 0, 0, 0, 0) as input, and obtains the sequence (X 1,1 , P 1 , X 1,2 , P 2 , . . . , X 1,16384 , P 16384 , X 1,16385 , P 16385 , X 1,16386 , P 16386 , X 1,16387 , P 16387 , X 1,16388 , P 16388 )=(X 1,1 , P 1 , X 1,2 , P 2 , . . . , X 1,16384 , P 16384 , 0, P 16385 , 0, P 16386 , 0, P 16387 , 0, P 16388 ) therefrom. Then, the encoder (transmitting device) and the decoder (receiving device) delete the known zeroes, such that the transmitting device transmits the transmission sequence as (X 1,1 , P 1 , X 1,2 , P 2 , . . . , X 1,16384 , P 16384 , P 16385 , P 16386 , P 16387 , P 16388 ).

The receiving device 2210 obtains, for example, the log-likelihood ratios for each transmission sequence of LLR(X 1,1 ), LLR(P 1 ), LLR(X 1,2 ), LLR(P 2 ), . . . , LLR(X 1,16384 ), LLR(P 16384 ), LLR(P 16385 ), LLR(P 16386 ), LLR(P 16387 ), LLR(P 16388 ).

Then, the log-likelihood ratios LLR(X 1,16385 )=LLR(0), LLR(X 1,16386 )=LLR(0), LLR(X 1,16387 )=LLR(0), LLR(X 1,16388 )=LLR(0) of the zero-value terms X 1,16385 , X 1,16386 , X 1,16387 , and X 1,16388 not transmitted by the transmitting device 2200 are generated, obtaining LLR(X 1,1 ), LLR(P 1 ), LLR(X 1,2 ), LLR(P 2 ), . . . , LLR(X 1,16384 ), LLR(P 16384 ), LLR(X 1,16385 )=LLR(0), LLR(P 16385 ), LLR(X 1,16386 )=LLR(0), LLR(P 16386 ), LLR(X 1,16387 )=LLR(0), LLR(P 16387 ), LLR(X 1,16388 )=LLR(0), and LLR(P 16388 ). As such, the estimated transmission sequence and the estimated information sequence are obtainable by using the 16388×32776 parity check matrix of the LDPC-CC having a time-varying period of 12 and a coding rate of 1/2 and performing decoding using belief propagation, such as BP decoding described in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, and Non-Patent Literature 8, min-sum decoding that approximates BP decoding, offset BP decoding, Normalized BP decoding, or shuffled BP decoding.

As the example makes clear, for an LDPC-CC having a time-varying period of q and a coding rate of (n−1)/n and for which tail-biting is performed, when the receiving device performs decoding, the decoding proceeds with a parity check matrix that satisfies Condition #1. Accordingly, the decoder holds a parity check matrix in which (rows)×(columns)=(q×M)×(q×n×M) (where M is a natural number).

The corresponding encoder uses a number of information bits needed for coding that corresponds to q×(n−1)×M. Accordingly, q×M bits of parity are computed. In contrast, when the number of information bits input to the encoder is less than q×(n−1)×M, the encoder inserts known bits (for example, zeroes (or ones)) into inter-device transmissions (between the encoder and the decoder) such that the total number of information bits is q×(n−1)×M. Thus, q×M bits of parity are computed. Here, the transmitting device transmits the parity bits computed from the information bits with the inserted known bits deleted. (However, although the known bits are normally transmitted with q×(n−1)×M bits of information and q×M bits of parity, the presence of known bits may lead to a decrease in transmission speeds).

The following describes a periodic time-varying LDPC-CC that is based on a parity check polynomial and that uses improved tail-biting of coding rate (n−1)/n (where n is an integer no smaller than two) described in Patent Literature 2.

[Periodic Time-Varying LDPC-CC Based on Parity Check Polynomial and Using Improved Tail-Biting of Coding Rate (n−1)/n (where n is an Integer No Smaller than Two)]

First, explanation is provided of a problem present in a conventional LDPC convolutional code using a tail-biting scheme.

Here, explanation is provided of a time-varying LDPC-CC having a coding rate of R=(n−1)/n based on a parity check polynomial. Information bits X 1 , X 2 , . . . , X n−1 and parity bit P at time j are respectively expressed as X 1,j , X 2,j , . . . , X n−1,j and P j . Further, a vector u j at time j is expressed as u j =(X 1,j , X 2,j , . . . , X n−1,j , P j ). Also, an encoded sequence is expressed as u=(u 0 , u 1 , . . . , u j , . . . ) T . Given a delay operator D, a polynomial expression of the information bits X 1 , X 2 , . . . , X n−1 is X 1 (D), X 2 (D), . . . , X n−1 (D), and a polynomial expression of the parity bit P is P(D). Here, a parity check polynomial that satisfies zero, according to expression 52, is considered.

[Math. 52]

( D a 1,1 +D a 1,2 + . . . +D a 1,r1 +1) X 1 ( D )+( D a 2,1 +D a 2,2 + . . . +D a 2,r2 +1) X 2 ( D )+ . . . +( D a n−1,1 +D a n−1,2 + . . . +D a n−1,rn−1 +1) X n−1 ( D )+( D b 1 +D b 2 + . . . +D b ε +1) P ( D )=0  (52)

In expression 52, a p,q (p=1, 2, . . . , n−1; q=1, 2, . . . , r p ) and b s (s=1, 2, . . . , ε) are natural numbers. Also, for ∀ (y, z) where y, z=1, 2, . . . , r p and y≠z, a p,y ≠a p,z holds true. Also, for ∀ (y, z) where y, z=1, 2, . . . , ε and y≠z, b y ≠b z holds true. In order to create an LDPC-CC having a time-varying period of m, m parity check polynomials that satisfy zero are prepared. Here, the m parity check polynomials that satisfy zero are referred to as a parity check polynomial #0, a parity check polynomial #1, a parity check polynomial #2, . . . , a parity check polynomial #(m−2), and a parity check polynomial #(m−1). Based on parity check polynomials that satisfy zero, according to expression 52, the number of terms of X p (D) (p=1, 2, . . . , n−1) is equal in the parity check polynomial #0, the parity check polynomial #1, the parity check polynomial #2, . . . , the parity check polynomial #(m−2), and the parity check polynomial #(m−1), and the number of terms of P(D) is equal in the parity check polynomial #0, the parity check polynomial #1, the parity check polynomial #2, . . . , the parity check polynomial #(m−2), and the parity check polynomial #(m−1). However, expression 52 merely provides one example of a parity check polynomial that satisfies zero, and the number of terms of Xp(D) (p=1, 2, . . . , n−1) need not be equal in the parity check polynomial #0, the parity check polynomial #1, the parity check polynomial #2, . . . , the parity check polynomial #(m−2), and the parity check polynomial #(m−1), and the number of terms of P(D) need not be equal in the parity check polynomial #0, the parity check polynomial #1, the parity check polynomial #2, . . . , the parity check polynomial #(m−2), and the parity check polynomial #(m−1).

In order to create an LDPC-CC having a coding rate of R=(n−1)/n and a time-varying period of m, parity check polynomials that satisfy zero are prepared. An ith parity check polynomial (i=0, 1, . . . , m−1) that satisfies zero, according to expression 52, is expressed as shown in expression 53.

[Math. 53]

A X1,i ( D ) X 1 ( D )+ A X2,i ( D ) X 2 ( D )+ . . . + A Xn−1,i ( D ) X n−1 ( D )+ B i ( D ) P ( D )=0  (53)

In expression 53, the maximum degrees of D in A Xδ,i (D) (δ=1, 2, . . . , n−1) and B i (D) are respectively expressed as Γ Xδ,i and Γ P,i . Further, the maximum values of Γ Xδ,i and Γ P,i are Γi. Also, the maximum value of Γi (i=0, 1, . . . , m−1) is Γ. When taking the encoded sequence u into consideration and when using Γ, a vector h i corresponding to the ith parity check polynomial is expressed as shown in expression 54.

[Math. 54]

h i =[ h i,Γ ,h i,Γ-1 , . . . ,h i,1 ,h i,0 ]  (54)

In expression 54, h i,v (v=0, 1, . . . , Γ) is a vector having one row and n columns and is expressed as rot [α i,v,X1 , α i,v,X2 , . . . , α i,v,Xn−1 , β 1,v ]. This is because a parity check polynomial, according to expression 53, has α i,v,Xw D v X w (D) and β i,v D v P(D) (w=1, 2, . . . , n—1, and α i,v,Xw , β i,v ε[0,1]). In such a case, a parity check polynomial that satisfies zero, according to expression 53, has terms D 0 X 1 (D), D 0 X 2 (D), . . . , D 0 X n−1 (D) and D 0 P(D), thus satisfying expression 55.

When using expression 55, a parity check matrix for an LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m is expressed as shown in expression 56.

In expression 56, Λ(k)=Λ(k+m) is satisfied for ∀ k. Here, Λ(k) corresponds to h i of a kth row of the parity check matrix.

Although explanation is provided above while referring to expression 52 as a parity check polynomial serving as a basis, no limitation to the format of expression 52 is intended. For example, instead of a parity check polynomial according to expression 52, a parity check polynomial that satisfies zero, according to expression 57, may be used.

[Math. 57]

( D a 1,1 +D a 1,2 + . . . +D a 1,r1 ) X 1 ( D )+( D a 2,1 +D a 2,2 + . . . +D a 2,r2 ) X 2 ( D )+ . . . +( D a n−1,1 +D a n−1,2 + . . . +D a n−1,rn−1 ) X n−1 ( D )+( D b 1 +D b 2 + . . . +D b ε ) P ( D )=0  (57)

In expression 57, a p,q (p=1, 2, . . . , n−1; q=1, 2, . . . , r p ) and b s (s=1, 2, . . . , ε) are natural numbers. Also, for ∀ (y, z) where y, z=1, 2, . . . , r p and y≠z, a p,y ≠a p,z holds true. Also, for ∀ (y, z) where y, z=1, 2, . . . , ε and y≠z, b y ≠b z holds true.

Here, an ith parity check polynomial (i=0, 1, . . . , m−1) that satisfies zero for an LDPC-CC having a coding rate of R=(n−1)/n and a time-varying period of m is expressed as shown below.

[Math. 58]

A X1,i ( D ) X 1 ( D )+ A X2,i ( D ) X 2 ( D )+ . . . + A Xn−1,i ( D ) X n−1 ( D )+( D b 1,i + . . . +D b ε,i +1) P ( D )=0  (58)

Here, b s,i (s=1, 2, . . . ,) is a natural number, and for ∀ (y, z) where y, z=1, 2, . . . , ε and y≠z, b y,i ≠b z,i holds true. Also, ε is a natural number. Accordingly, there are two or more terms of P(D) in an ith parity check polynomial (i=0, 1, . . . , m−1) that satisfies zero, which serves as a parity check polynomial that satisfies zero for an LDPC-CC having a coding rate of R=(n−1)/n and a time-varying period of m.

In the following, a case is considered where tail-biting is performed when there are two or more terms of P(D) in an ith parity check polynomial (i=0, 1, . . . , m−1) that satisfies zero, which serves as a parity check polynomial that satisfies zero for an LDPC-CC having a coding rate of R=(n−1)/n and a time-varying period of m. In such a case, an encoder obtains a parity P from information bits X 1 , X 2 , . . . , X n−1 by performing encoding.

Here, when assuming a transmission vector u to be u=(X 1,1 , X 2,1 , . . . , X n−1,1 , P 1 , X 1,2 , X 2,2 , . . . , X n−1,2 , P 2 , . . . , X 1,k , X 2,k , . . . , X n−1,k , P k , . . . ) T and assuming a parity check matrix for an LDPC-CC having a coding rate of R=(n−1)/n and a time-varying period of m using the tail-biting scheme to be H, Hu=0 holds true. (here, the zero in Hu=0 indicates that all elements of the vector are zeros.) Accordingly, parities P 1 , P 2 , . . . , P k , . . . , can be obtained by solving simultaneous equations for Hu=0. However, one problem is that a great amount of computation (i.e., a great circuit scale) is required for obtaining the parities since there are two or more terms of P(D).

Taking this into consideration, there is a tail-biting scheme using a feed-forward LDPC-CC having a time-varying period of m in order to reduce the amount of computation (i.e., circuit scale) required for obtaining parities. However, as is commonly known, the use of a feed-forward LDPC-CC is problematic in that a feed-forward LDPC-CC has relatively low error correction capability (when comparing a feed-forward LDPC-CC and a feedback LDPC-CC having substantially similar constraint lengths, it is more likely that the feedback LDPC-CC has higher error correction capability than the feed-forward LDPC-CC).

In view of the two problems presented above, Patent Literature 2 describes an LDPC-CC using an improved tail-biting scheme that achieves high error correction capability and a reduced amount of computation performed by an encoder (i.e., a reduced circuit scale of an encoder).

Explanation is provided in the following of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme that is described in Patent Literature 2. Note that in the following, n is assumed to be a natural number no smaller than two.

As a basis (i.e., a basic structure) of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme that is described in Patent Literature 2, an LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m is used.

An ith parity check polynomial (i=0, 1, . . . , m−1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC described in Patent Literature 2, is expressed as shown in expression 59.

Here, k=1, 2, . . . , n−2, n−1 (k is an integer no smaller than one and less than or equal to n−1), i=1, 2, . . . , m−1 (i is an integer no smaller than zero and less than or equal to m−1), and A Xk,i (D)≠0 holds true for all conforming k and i. Also, b 1,i is a natural number.

Accordingly, there are two terms P(D) in the ith parity check polynomial (i=0, 1, . . . , m−1) that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC described in Patent Literature 2. This is one important requirement for enabling finding parities sequentially and reducing computation amount (i.e., reducing circuit scale).

Note that the following function is defined for a polynomial part of a parity check polynomial that satisfies zero, according to expression 59.

Here, the two methods presented below realize a time-varying period of m.

Method 1:

[Math. 61]

F v ( D )≠ F w ( D )∀ v∀w v,w= 0,1,2, . . . , m− 2, m− 1; v≠w   (61)

In the above expression, v is an integer no smaller than zero and less than or equal to m−1, w is an integer no smaller than zero and less than or equal to m−1, v≠w, and F v (D)≠F w (D) holds true for all conforming v and w.

Method 2:

[Math. 62]

F v ( D )≠ F w ( D )  (62)

In the above expression, v is an integer no smaller than zero and less than or equal to m−1, w is an integer no smaller than zero and less than or equal to m−1, v≠w, and values of v and w that satisfy expression 62 exist. In addition, expression 63 also holds true.

[Math. 63]

F v ( D )= F w ( D )  (63)

In the above expression, v is an integer no smaller than zero and less than or equal to m−1, w is an integer no smaller than zero and less than or equal to m−1, vow, values of v and w that satisfy expression 63 exist. However, a time-varying period is m is realized.

Next, a relationship is described between a time-varying period m of a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme that is described in Patent Literature 2, and a block size of the proposed LDPC-CC having a coding rate of R=(n−1)/n using the tail-biting scheme.

Concerning this point, the following conditions are important when performing tail-biting on the LDPC-CC based on a parity check polynomial (a parity check polynomial that satisfies zero as defined in expression 59) having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC described in Patent Literature 2, in order to achieve higher error correction capability.

<Condition #A1>

The number of rows in a parity check matrix is a multiple of m. Thus, the number of columns in the parity check matrix is a multiple of n×m. According to this condition, (for example) a log-likelihood ratio that is necessary when performing decoding is a log-likelihood ratio of the number of columns in the parity check matrix.

However, a parity check polynomial that satisfies zero for the LDPC-CC having a time-varying period of m and a coding rate of (n−1)/n, which serves as the basic structure of the proposed LCPC-CC, and requires Condition #A1 is not limited to expression 59.

Further, the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 also satisfies Condition #A1. (Note that detailed explanation of the difference between the proposed LDPC-CC having a coding rate of R=(n−1)/n using the tail-biting scheme and the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC described in Patent Literature 2, is provided in the following.) Thus, when assuming that a parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is H pro , the number of columns of H pro can be expressed as n×m×z (where z is a natural number). Accordingly, a transmission sequence (encoded sequence (codeword)) composed of an sth block of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,1,k , X s,2,k , . . . , X s,n−1,k , P pro,s,k , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z ) T (where k=1, 2, . . . , m×z−1), and H pro v s =0 holds true (here, the zero in H pro v s =0 indicates that all elements of the vector are zeros). Here, X s,j,k represents an information bit X j (j is an integer no smaller than one and less than or equal to n−1), and P pro,s,k represents a bit of parity P. Further, the number of rows of H pro , which is the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, is m×z.

Next, explanation is provided of requirements that enable finding parities sequentially in the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

When drawing a tree as in each of FIGS. 5, 6, 8, 17, and 18 , which is composed of only terms corresponding to parities of parity check polynomials that satisfy zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, it is required that check nodes corresponding to all parity check polynomials from the zeroth to the (m−1)th parity check polynomials, according to expression 59, appear in such a tree, as in each of FIGS. 6, 8, and 17 . As such, the following conditions are considered as being effective.

<Condition #A2-1>

In a parity check polynomial that satisfies zero, according to expression 59, i is an integer greater than equal to zero and less than or equal to m−1, j is an integer greater than equal to zero and less than or equal to m−1, i≠j, and b 1,1 %m=b 1,j %m=β (where β is a fixed value that is a natural number) holds true for all conforming i and j.

<Condition #A2-2>

When expressing a set of divisors of m other than one as R, β is not to belong to R.

In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

Note that, in addition to the above-described condition that, when expressing a set of divisors of m other than one as R, β is not to belong to R, it is desirable that the new condition below be satisfied.

<Condition #A2-3>

β belongs to a set of integers no smaller than one and less than or equal to m−1, and β also satisfies the following condition.

When expressing a set of values w obtained by extracting all values w satisfying β/w=g (where g is a natural number) as S, an intersection R∩S produces an empty set. The set R has been defined in Condition #A2-2.

Condition #A2-3 is also expressible as Condition #A2-3′.

<Condition #A2-3′>

β belongs to a set of integers no smaller than one and less than or equal to m−1, and β also satisfies the following condition.

When expressing a set of divisors of β as S, an intersection R∩S produces an empty set.

Condition #A2-3 and Condition #A2-3′ are also expressible as Condition #A2-3″.

<Condition #A2-3″>

β belongs to a set of integers no smaller than one and less than or equal to m−1, and β also satisfies the following condition.

The greatest common divisor of 13 and m is one.

A supplementary explanation of the above is provided. According to Condition #A2-1, β is an integer no smaller than one and less than or equal to m−1. Also, when β satisfies both Condition #A2-2 and Condition #A2-3, β is not a divisor of m other than one, and β is not a value expressible as an integral multiple of a divisor of m other than one.

In the following, explanation is provided while referring to an example. Assume a time-varying period of m=6. Then, according to Condition #A2-1, β={1, 2, 3, 4, 5} since β is a natural number.

Further, according to Condition #A2-2, when expressing a set of divisors of m other than one as R, β is not to belong to R. As such, R={2, 3, 6} (since, among the divisors of six, one is excluded from the set R). As such, when 13 satisfies both Condition #A2-1 and Condition #A2-2, β={1, 4, 5}.

Next, Condition #A2-3 is considered (similar as when considering Condition #A2-3′ or Condition #A2-3″). First, since β belongs to a set of integers no smaller than one and less than or equal to m−1, β={1, 2, 3, 4, 5}.

Further, when expressing a set of values w obtained by extracting all values w that satisfy β/w=g (where g is a natural number) as S, the intersection R∩S produces an empty set. Here, as explained above, the set R={2, 3, 6}.

When β=1, the set S={1}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

When β=2, the set S={1, 2}. As such, R∩S={2}, and Condition #A2-3 is not satisfied.

When β=3, the set S={1, 3}. As such, R∩S={3}, and Condition #A2-3 is not satisfied.

When β=4, the set S={1, 2, 4}. As such, R∩S={2}, and Condition #A2-3 is not satisfied.

When β=5, the set S={1, 5}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

As such, β satisfies both Condition #A2-1 and Condition #A2-3 when β={1, 5}.

In the following, explanation is provided while referring to another example. Assume a time-varying period of m=7. Then, since β is a natural number according to Condition #A2-1, β={1, 2, 3, 4, 5, 6}.

Further, according to Condition #A2-2, when expressing a set of divisors of m other than one as R, β is not to belong to R. Here, R={7} (since, among the divisors of seven, one is excluded from the set R). As such, when 13 satisfies both Condition #A2-1 and Condition #A2-2,13={1, 2, 3, 4, 5, 6}.

Next, Condition #A2-3 is considered. First, since 13 is an integer no smaller than one and less than or equal to m−1, β={1, 2, 3, 4, 5, 6}.

Next, when expressing a set of values w obtained by extracting all values w that satisfy β/w=g (where g is a natural number) as S, the intersection R∩S produces an empty set. Here, as explained above, the set R={7}.

When β=1, the set S={1}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

When β=2, the set S={1, 2}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

When β=3, the set S={1, 3}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

When β=4, the set S={1, 2, 4}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

When β=5, the set S={1, 5}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

When β=6, the set S={1, 2, 3, 6}. As such, the intersection R∩S produces an empty set, and Condition #A2-3 is satisfied.

As such, β satisfies both Condition #A2-1 and Condition #A2-3 when β={1, 2, 3, 4, 5, 6}.

In addition, as described in Non-Patent Literature 2, the possibility of high error correction capability being achieved is high if there is randomness in the positions at which ones are present in a parity check matrix. So as to make this possible, it is desirable that the following conditions be satisfied.

<Condition #A2-4>

In a parity check polynomial that satisfies zero, according to expression 59, i is an integer greater than equal to zero and no greater than m−1, j is an integer greater than equal to zero and no greater than m−1, i≠j, b 1,i %m=b 1,j %m=β (where β is a fixed value that is a natural number) holds true for all conforming i and j.

Also, v is an integer no smaller than zero and less than or equal to m−1, w is an integer no smaller than zero and less than or equal to m−1, v≠w, and values of v and w that satisfy b 1,v ≠b 1,w exist.

However, note that even when Condition #A2-4 is not satisfied, high error correction capability may be achieved. In addition, the following conditions can be considered so as to increase the randomness as described above.

<Condition #A2-5>

In a parity check polynomial that satisfies zero, according to expression 59, i is an integer greater than equal to zero and no greater than m−1, j is an integer greater than equal to zero and no greater than m−1, i≠j, and b 1,i %m=b 1,j %m=β (where β is a fixed value that is a natural number) holds true for all conforming i and j.

Also, v is an integer no smaller than zero and less than or equal to m−1, w is an integer no smaller than zero and less than or equal to m−1, v≠w, and b 1,v ≠b 1,w holds true for all conforming v and w.

However, note that even when Condition #A2-5 is not satisfied, high error correction capability may be achieved.

Further, when taking into consideration that the proposed code is a convolutional code, the possibility is high of higher error correction capability being achieved for relatively long constraint lengths. Considering this point, it is desirable that the following condition be satisfied.

<Condition #A2-6>

The condition is not satisfied that, in a parity check polynomial that satisfies zero, according to expression 59, i is an integer greater than equal to zero and no greater than m−1, and b 1,i =1 holds true for all conforming i.

However, note that even when Condition #A2-6 is not satisfied, high error correction capability may be achieved.

In the following, explanation is provided of the description above that, as the basis (i.e., the basic structure) of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m is used.

Description regarding tail-biting schemes has been provided above.

First, a parity check matrix is considered for a periodic time-varying LDPC-CC formed by using only a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m.

FIG. 23 illustrates a configuration of a parity check matrix H for the periodic time-varying LDPC-CC using tail-biting formed by performing tail-biting by using only a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m. Since Condition #A1 is satisfied in FIG. 23 , the number of rows of the parity check matrix H is m×z and the number of columns of the parity check matrix H is n×m×z.

The first row of the parity check matrix H in FIG. 23 can be obtained by converting a zeroth parity check polynomial among the zeroth to (m−1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the zeroth parity check polynomial). As such, the first row of the parity check matrix H in FIG. 23 is indicated as a “row corresponding to zeroth parity check polynomial”.

The second row of the parity check matrix H in FIG. 23 can be obtained by converting the first parity check polynomial among the zeroth to (m−1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the first parity check polynomial). As such, the second row of the parity check matrix H in FIG. 23 is indicated as a “row corresponding to first parity check polynomial”.

The (m−1)th row of the parity check matrix H in FIG. 23 can be obtained by converting the (m−2)th parity check polynomial among the zeroth to (m−1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (m−2)th parity check polynomial). As such, the (m−1)th row of the parity check matrix H in FIG. 23 is indicated as a “row corresponding to (m−2)th parity check polynomial”.

The mth row of the parity check matrix H in FIG. 23 can be obtained by converting the (m−1)th parity check polynomial among the zeroth to (m−1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (m−1)th parity check polynomial). As such, the mth row of the parity check matrix H in FIG. 23 is indicated as a “row corresponding to (m−1)th parity check polynomial”.

The (m×z−1)th row of the parity check matrix H in FIG. 23 can be obtained by converting the (m−2)th parity check polynomial among the zeroth to (m−1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (m−2)th parity check polynomial).

The (m×z)th row of the parity check matrix H in FIG. 23 can be obtained by converting the (m−1)th parity check polynomial among the zeroth to (m−1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (m−1)th parity check polynomial).

As such, a kth row (where k is an integer no smaller than one and less than or equal to (m×z)) of the parity check matrix H in FIG. 23 can be obtained by converting the (k−1)%mth parity check polynomial among the zeroth to (m−1)th parity check polynomials that satisfy zero, according to expression 59 (i.e., can be obtained by generating a vector having one row and n×m×z columns from the (k−1)%mth parity check polynomial).

To prepare for the explanation to be provided in the following, a mathematical expression is provided of the parity check matrix H in FIG. 23 for the periodic time-varying LDPC-CC using tail-biting formed by performing tail-biting by using only a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m. When assuming a vector having one row and n×m×z columns of the kth row of the parity check matrix H to be a vector h k , the parity check matrix H in FIG. 23 is expressed as shown in expression A13.

In the following, explanation is provided of a parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent-Literature 2.

FIG. 24 illustrates one example configuration of a parity check matrix H pro for the DPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent-Literature 2. Note that the parity check matrix H pro for LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent-Literature 2 satisfies Condition #A1.

When assuming a vector having one row and n×m×z columns in a kth row of the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 to be a vector g k , the parity check matrix H pro in FIG. 24 is expressed as shown in expression 64-2.

Note that, the transmission sequence (encoded sequence (codeword)) composed of an sth block of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,1,k , X s,2,k , . . . , X s,n−1,k , P pro,s,k , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×Z ) T (where k=1, 2, . . . , m×z−1, m×z), and H pro v s =0 holds true (here, the zero in H pro v s =0 indicates that all elements of the vector are zeros). Here, X s,j,k represents an information bit X j (j is an integer no smaller than one and less than or equal to n−1) and P pro,s,k represents a bit of parity P.

In FIG. 24 , which illustrates one example of the configuration of the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, the rows of the parity check matrix H pro other than the first row, or that is, the configuration of the second row to the (m×z)th row of the parity check matrix H pro in FIG. 24 is identical to the configuration of the second row to the (m×z)th row of the parity check matrix H in FIG. 23 (refer to FIGS. 23 and 24 ). As such, a first row 2401 in FIG. 24 is indicated as a “row corresponding to zero'th parity check polynomial” (further explanation concerning this point is provided in the following). Accordingly, the following relational expression holds true from expression 64-1 and expression 64-2.

[Math. 65]

g i =h i   (65)

(i is an integer greater than equal to two and less than or equal to m×z, and expression 65 holds true for all conforming i)

Further, the following expression holds true when i equals one.

[Math. 66]

g 1 ≠h 1   (66)

Accordingly, the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as shown in expression 67.

Note that, in expression 67, expression 66 holds true.

Next, explanation is provided of a configuration method of g 1 in expression 67 for enabling finding parities sequentially and achieving high error correction capability.

One example of a configuration method of g 1 in expression 67 for enabling finding parities sequentially and achieving high error correction capability can be created by using a parity check polynomial that satisfies zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC described in Patent Literature 2.

Since g 1 is the first row of the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, (row number−1)% m=(1−1)% m=0. As such, g 1 is created from a parity check polynomial that satisfies zero that is obtained by transforming the zeroth parity check polynomial that satisfies zero among the parity check polynomials that satisfy zero, according to expression 59, for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC described in Patent Literature 2.

One example of a parity check polynomial that satisfies zero for generating a vector g 1 of the first row of the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is expressed as shown in expression 69, by using expression 59.

Accordingly, a vector having one row and n×m×z columns that is created by performing tail-biting on expression 69 is the vector g 1 .

Note that in the following, a parity check polynomial that satisfies zero, according to expression 69, is referred to as a parity check polynomial Y that satisfies zero.

Accordingly, the first row of the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained by transforming the parity check polynomial Y that satisfies zero, according to expression 69 (that is, a vector g 1 =c 1 having one row and n×m×z columns can be obtained).

The transmission sequence (encoded sequence (codeword)) composed of an sth block of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,1,k , X s,2,k , . . . , X s,n−1,k , P pro,s,k , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z ) T , and m×z parity check polynomials that satisfy zero are necessary for obtaining this transmission sequence v s . Here, a parity check polynomial that satisfies zero appearing eth, when the m×z parity check polynomials that satisfy zero are arranged in sequential order, is referred to as an eth parity check polynomial that satisfies zero (where e is an integer no smaller than zero and less than or equal to m×z−1). As such, the m×z parity check polynomials that satisfy zero are arranged in the following order.

zeroth: zeroth parity check polynomial that satisfies zero

first: first parity check polynomial that satisfies zero

second: second parity check polynomial that satisfies zero

eth: eth parity check polynomial that satisfies zero

(m×z−2)th: (m×z−2)th parity check polynomial that satisfies zero

(m×z−1)th: (m×z−1)th parity check polynomial that satisfies zero

As such, the transmission sequence (encoded sequence (codeword)) v s of an sth block of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained. (Note that, as can be seen from the above, when expressing the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 as shown in expression 64-2, a vector composed of the (e+1)th row of the parity check matrix H pro corresponds to the eth parity check polynomial that satisfies zero.)

Then, in the proposed LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2,

the zeroth parity check polynomial that satisfies zero is the parity check polynomial Y that satisfies zero, according to expression 69,

the first parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 59,

the second parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 59,

the (m−2)th parity check polynomial that satisfies zero is the (m−2)th parity check polynomial that satisfies zero, according to expression 59,

the (m−1)th parity check polynomial that satisfies zero is the (m−1)th parity check polynomial that satisfies zero, according to expression 59,

the mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 59,

the (m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 59,

the (m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 59,

the (2m−2)th parity check polynomial that satisfies zero is the (m−2)th parity check polynomial that satisfies zero, according to expression 59,

the (2m−1)th parity check polynomial that satisfies zero is the (m−1)th parity check polynomial that satisfies zero, according to expression 59,

the 2mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 59,

the (2m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 59,

the (2m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 59,

the (m×z−2)th parity check polynomial that satisfies zero is the (m−2)th parity check polynomial that satisfies zero, according to expression 59, and

the (m×z−1)th parity check polynomial that satisfies zero is the (m−1)th parity check polynomial that satisfies zero, according to expression 59.

That is, the zeroth parity check polynomial that satisfies zero is the parity check polynomial Y that satisfies zero, according to expression 69, and the eth parity check polynomial that satisfies zero (where e is an integer no smaller than one and less than or equal to m×z−1) is the e%mth parity check polynomial that satisfies zero, according to expression 59.

Further, when the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 satisfies Conditions #A1, #A2-1, and #A2-2 as described in the present embodiment, multiple parities can be found sequentially, and therefore, an advantageous effect of a reduction in the amount of computation (a reduction in circuit scale) can be achieved.

Note that, when Conditions #A1, #A2-1, #A2-2, and #A2-3 are satisfied, an advantageous effect is achieved such that a great number of parities can be found sequentially. (Alternatively, the same advantageous effect can be achieved when Conditions #A1, #A2-1, #A2-2, and #A2-3′ are satisfied or when Conditions #A1, #A2-1, #A2-2, and #A2-3″ are satisfied.)

In the following, explanation is provided of what is meant by enabling finding parities sequentially.

In the example described above, since H pro v s =0 holds true for the transmission sequence (encoded sequence (codeword)) v s composed of an sth block of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, which is expressed as v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,1,k , X s,2,k , . . . , X s,n−1,k , P pro,s,1 , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z ) T (where k=1, 2, . . . , m×z−1,m×z), g 1 v s =0 holds true from expression 67. Since g 1 is obtained by transforming the parity check polynomial Y that satisfies zero, according to expression 69, P pro,s,1 can be calculated from g 1 v s =0 (P pro,s,1 can be determined since there is only one term of P(D) in a parity check polynomial that satisfies zero, according to expression 69).

Since X s,j,k is a known bit (i.e., a bit before encoding) for all j that is an integer no smaller than one and less than n−1 and all k that is an integer no smaller than one and less than or equal to m×z, and since P pro,s,1 is already obtained, g a[2] v s =0 holds true for g a[2] (refer to expression 64-2) that is a vector in the a[2]th row (a[2]≠1) of H pro and v s , and therefore, P pro,s,a[2] can be calculated.

Further, since X s,j,k is a known bit (i.e., a bit before encoding) for all j that is an integer no smaller than one and less than n−1 and all k that is an integer no smaller than one and less than or equal to m×z, and since P pro,s,a[2] is already obtained, g a[3] v s =0 holds true for g a[3] (refer to expression 64-2) that is a vector in the a[3]th row (a[3]≠1 and a[3]≠a[2]) of H pro and v s , and therefore, P pro,s,a[3] can be calculated.

Similarly, since X s,j,k is a known bit (i.e., a bit before encoding) for all j that is an integer no smaller than one and less than n−1 and all k that is an integer no smaller than one and less than or equal to m×z, and since P pro,s,a[3] is already obtained, g a[4] v s =0 holds true for g a[4] (refer to expression 64-2) that is a vector in the a[4]th row (a[4]≠1, a[4]≠a[2], and a[4]≠a[3]) of H pro and v s , and therefore, P pro,s,a[4] can be calculated.

By repeating the operations as described above, multiple parities P pro,s,k can be calculated. In the explanation provided above, the repetitive execution of such operations is referred to as finding parities sequentially, which has an advantageous effect such that circuit scale of an encoder (amount of computation performed by an encoder) can be reduced due to the multiple parities P pro,s,k being obtainable without calculation of complex simultaneous equations. Note that, when P pro,s,k can be calculated for all k that is an integer no smaller than one and less than or equal to m×z by repetitively performing similar operations as those described above, an advantageous effect is achieved such that circuit scale (amount of computation) can be reduced to be extremely small.

Note that in the description provided above, high error correction capability may be achieved when at least one of Conditions #A2-4, #A2-5, and #A2-6 is satisfied, but high error correction capability may also be achieved when none of Conditions #A2-4, #A2-5, and #A2-6 is satisfied.

As description has been provided above, the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, at the same time as achieving high error correction capability, enables finding multiple parities sequentially, and therefore, achieves an advantageous effect of reducing circuit scale of an encoder.

Note that, in a parity check polynomial that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis (i.e., the basic structure) of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, high error correction capability may be achieved by setting the number of terms of either one of or all of information X 1 (D), X 2 (D), . . . , X n−2 (D), and X n−1 (D) to two or more or three or more. Further, in such a case, to achieve the effect of having an increased time-varying period when a Tanner graph is drawn, the time-varying period m is beneficially an odd number, and further, the conditions as provided in the following are effective, for example.

(1) The time-varying period m is a prime number.

(2) The time-varying period m is an odd number, and the number of divisors of m is small.

(3) The time-varying period m is assumed to be α×β,

where α and β are odd numbers other than one and are prime numbers.

(4) The time-varying period m is assumed to be α n ,

where α is an odd number other than one and is a prime number, and n is an integer no smaller than two.

(5) The time-varying period m is assumed to be α×β×γ,

where α, β, and γ are odd numbers other than one and are prime numbers.

(6) The time-varying period m is assumed to be α×β×γ×δ,

where, α, β, γ, and δ are odd numbers other than one and are prime numbers.

(7) The time-varying period m is assumed to be A u ×B v ,

where, A and B are odd numbers other than one and are prime numbers, A≠B, and u and v are integers no smaller than one.

(8) The time-varying period m is assumed to be A u ×B v ×C w ,

where, A, B, and C are odd numbers other than one and are prime numbers, A≠B, A≠C, and B≠C, and u, v, and w are integers no smaller than one.

(9) The time-varying period m is assumed to be A u ×B v ×C w ×D x ,

where, A, B, C, and D are odd numbers other than one and are prime numbers, A≠B, A≠C, A≠D, B≠C, B≠D, and C≠D, and u, v, w, and x are integers no smaller than one.

However, it is not necessarily true that a code having high error-correction capability cannot be obtained when the time-varying period m is an even number, and for example, the conditions as shown below may be satisfied when the time-varying period m is an even number.

(10) The time-varying period m is assumed to be 2 g ×K,

where, K is a prime number, and g is an integer no smaller than one.

(11) The time-varying period m is assumed to be 2 g ×L,

where, L is an odd number and the number of divisors of L is small, and g is an integer no smaller than one.

(12) The time-varying period m is assumed to be 2 g ×α×β,

where, α and β are odd numbers other than one and are prime numbers, and g is an integer no smaller than one.

(13) The time-varying period m is assumed to be 2 g ×α n ,

where, α is an odd number other than one and is a prime number, n is an integer no smaller than two, and g is an integer no smaller than one.

(14) The time-varying period m is assumed to be 2 g ×α×β×γ,

where, α, β, and γ are odd numbers other than one and are prime numbers, and g is an integer no smaller than one.

(15) The time-varying period m is assumed to be 2 g ×α×β×γ×δ,

where, α, β, γ, and δ are odd numbers other than one and are prime numbers, and g is an integer no smaller than one.

(16) The time-varying period m is assumed to be 2 g ×A u ×B v ,

where, A and B are odd numbers other than one and are prime numbers, A≠B, u and v are integers no smaller than one, and g is an integer no smaller than one.

(17) The time-varying period m is assumed to be 2 g ×A u ×B v ×C w ,

where, A, B, and C are odd numbers other than one and are prime numbers, A≠B, A≠C, and B≠C, u, v, and w are integers no smaller than one, and g is an integer no smaller than one.

(18) The time-varying period m is assumed to be 2 g ×A u ×B v ×C w ×D x ,

where, A, B, C, and D are odd numbers other than one and are prime numbers, A≠B, A≠C, A≠D, B≠C, B≠D, and C≠D, u, v, w, and x are integers no smaller than one, and g is an integer no smaller than one.

As a matter of course, high error-correction capability may also be achieved when the time-varying period m is an odd number that does not satisfy the above conditions (1) through (9). Similarly, high error-correction capability may also be achieved when the time-varying period m is an even number that does not satisfy the above conditions (10) through (18).

In addition, when the time-varying period m is small, error floor may occur at a high bit error rate particularly for a small coding rate. When the occurrence of error floor is problematic in implementation in a communication system, a broadcasting system, a storage, a memory etc., it is desirable that the time-varying period m be set so as to be greater than three. However, when within a tolerable range of a system, the time-varying period m may be set so as to be less than or equal to three.

Next, explanation is provided of configurations and operations of an encoder and a decoder supporting the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

In the following, one example case is considered where the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is used in a communication system. When the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is applied to a communication system, an encoder and a decoder for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 are characterized for being configured and operating based on the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 and the relation H pro v s =0.

Here, explanation is provided while referring to the overall diagram of the communication system in FIG. 25 .

An encoder 2511 of a transmitting device 2501 takes an information sequence of an sth block (X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , . . . , X s,1,k , X s,2,k , . . . , X s,n−1,k , . . . , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z ) as input, performs encoding based on the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 and the relation H pro v s =0, and generates and outputs the transmission sequence (encoded sequence (codeword)) v s of the sth block of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, which is expressed as v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,1,k , X s,2,k , . . . , X s,n−1,k , P pro,s,k , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z ) T . Here, note that, as explanation has been provided above, the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is characterized for enabling finding parities sequentially.

A decoder 2523 of a receiving device 2520 in FIG. 25 takes as input a log-likelihood ratio of each bit of, for instance, the transmission sequence (encoded sequence (codeword)) v s c of the sth block, which is expressed as v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,1,k , X s,2,k , . . . , X s,n−1,k , P pro,s,k , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z ) T , output from a log-likelihood ratio generation section 2522 , performs decoding according to the parity check matrix H pro for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, and thereby obtains and outputs an estimation transmission sequence (an estimation encoded sequence) (a reception sequence). Here, the decoding performed by the decoder 2523 may be Belief Propagation (BP) decoding as described in, for instance, Non-Patent Literatures 4, 6, 7, and 8, including simple BP decoding such as min-sum decoding, offset BP decoding, and Normalized BP decoding, and Shuffled BP decoding and Layered BP decoding in which scheduling is performed with respect to the row operations (Horizontal operations) and the column operations (Vertical operations), or may be decoding for an LDPC code such as bit-flipping decoding described in Non-Patent Literature 17, etc.

Note that, although explanation has been provided on operations of an encoder and a decoder by taking a communication system as one example in the above, an encoder and a decoder may be used in the field of storages, memories, etc.

[Periodic Time-Varying LDPC-CC Based on Parity Check Polynomial and Using Improved Tail-Biting of Coding Rate (n−1)/n (where n is an Integer No Smaller than Two)]

The following provides a specific example of a configuration of a parity check matrix for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

When assuming that a parity check matrix for the proposed LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2 is H pro , the number of columns of H pro can be expressed as n×m×z (where z is a natural number) (here, note that m is the time-varying period of the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n, which serves as the basis of the proposed LDPC-CC).

Accordingly, a transmission sequence (encoded sequence (codeword)) composed of an n×m×z number of bits of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,1,m×z−1 , X s,2,m×z−1 , . . . , X s,n−1,m×z−1 , P pro,s,m×z−1 , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z ) T =(λ pro,s,1 , λ pro,s,2 , . . . , X pro,s,m×z−1 , λ pro,s,m×z ) T , and H pro v s =0 holds true (here, the zero in H pro v s =0 indicates that all elements of the vector are zeros). Here, X s,j,k represents an information bit X j (j is an integer no smaller than one and less than or equal to n−1), P pro,s,k represents the parity bit of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, and λ pro,s,k =(X s,1,k , X s,2,k , . . . , X s,n−1,k , P pro,s,k ) (accordingly, λ pro,s,k =(X s,1,k , P pro,s,k ) when n=2, λ pro,s,k =(X s,1,k , X s,2,k , P pro,s,k ) when n=3, λ pro,s,k =(X s,1,k , X s,2,k , X s,3,k , P pro,s,k ) when n=4, λ pro,s,k =(X s,1,k , X s,2,k , X s,3,k , X s,4,k , P pro,s,k ) when n=5, and λ pro,s,k =(X s,1,k , X s,2,k , X s,3,k , X s,4,k , X s,5,k , P pro,s,k ) when n=6). Here, k=1, 2, . . . , m×z−1, m×z, or that is, k is an integer no smaller than one and less than or equal to m×z. Further, the number of rows of H pro , which is the parity check matrix for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, is m×z.

In addition, as explained above, an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, can be expressed as shown in expression 59.

Here, an ith parity check polynomial that satisfies zero, according to expression 59, is expressed as shown in expression 70.

In expression 70, a p,i,q (p=1, 2, . . . , n—1 (p is an integer no smaller than one and less than or equal to n−1); q=1, 2, . . . , r p (q is an integer no smaller than one and less than or equal to r p )) is a natural number. Also, when y, z=1, 2, . . . , r p (y and z are integers no smaller than one and less than or equal to r p ) and y≠z, and a p,i,y ≠a p,i,z holds true for conforming ∀ (y, z) (for all conforming y and z).

Further, in order to achieve high error correction capability, each of r 1 , r 2 , . . . , r n−2 , r n−1 is set to three or greater (k is an integer no smaller than one and less than or equal to n−1, and r k is three or greater for all conforming k). In other words, k is an integer no smaller than one and less than or equal to n−1 in expression 70, and the number of terms of X k (D) is four or greater for all conforming k. Also, b 1,i is a natural number.

As such, expression 69, which is a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, is expressed as shown in expression 71 (is expressed by using the zeroth parity check polynomial that satisfies zero, according to expression 70).

Note that the zeroth parity check polynomial (that satisfies zero), according to expression 70, that is used for generating expression 71 is expressed as shown in expression 72.

As described above, the transmission sequence (encoded sequence (codeword)) composed of an n×m×z number of bits of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,1,m×z−1 , X s,2,m×z−1 , . . . , X s,n−1,m×z−1 , P pro,s,m×z−1 , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z ) T =(λ pro,s,1 , λ pro,s,2 , . . . , λ pro,s,m×z−1 , λ pro,s,m×z ) T , and m×z parity check polynomials that satisfy zero are necessary for obtaining this transmission sequence v s . Here, a parity check polynomial that satisfies zero appearing eth, when the m×z parity check polynomials that satisfy zero are arranged in sequential order, is referred to as an eth parity check polynomial that satisfies zero (where e is an integer no smaller than zero and less than or equal to m×z−1). As such, the m×z parity check polynomials that satisfy zero are arranged in the following order.

zeroth: zeroth parity check polynomial that satisfies zero

first: first parity check polynomial that satisfies zero

second: second parity check polynomial that satisfies zero

eth: eth parity check polynomial that satisfies zero

(m×z−2)th: (m×z−2)th parity check polynomial that satisfies zero

(m×z−1)th: (m×z−1)th parity check polynomial that satisfies zero

As such, the transmission sequence (encoded sequence (codeword)) v s of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained. (Note that a vector composed of the (e+1)th row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 corresponds to the eth parity check polynomial that satisfies zero.)

From the explanation provided above, in the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2,

the zeroth parity check polynomial that satisfies zero is a parity check polynomial that satisfies zero, according to expression 71,

the first parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,

the second parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (m−2)th parity check polynomial that satisfies zero is the (m−2)th parity check polynomial that satisfies zero, according to expression 70,

the (m−1)th parity check polynomial that satisfies zero is the (m−1)th parity check polynomial that satisfies zero, according to expression 70,

the mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 70,

the (m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,

the (m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (2m−2)th parity check polynomial that satisfies zero is the (m−2)th parity check polynomial that satisfies zero, according to expression 70,

the (2m−1)th parity check polynomial that satisfies zero is the (m−1)th parity check polynomial that satisfies zero, according to expression 70,

the 2mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 70,

the (2m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,

the (2m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (m×z−2)th parity check polynomial that satisfies zero is the (m−2)th parity check polynomial that satisfies zero, according to expression 70, and

the (m×z−1)th parity check polynomial that satisfies zero is the (m−1)th parity check polynomial that satisfies zero, according to expression 70.

That is, the zeroth parity check polynomial that satisfies zero is the parity check polynomial that satisfies zero, according to expression 71, and the eth parity check polynomial that satisfies zero (where e is an integer no smaller than one and less than or equal to m×z−1) is the e%mth parity check polynomial that satisfies zero, according to expression 70.

In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

Next, detailed explanation is provided of a configuration of a parity check matrix in the case described above.

As described above, a transmission sequence (encoded sequence (codeword)) composed of an n×m×z number of bits of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC), which is definable by expression 70 and expression 71, having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,n−1,m×z−1 , X s,n−2,m×z−1 , . . . , X s,n−1,m×z−1 , P pro,s,m×z−1 , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z ) T =(λ pro,s,1 , λ pro,s,2 , . . . , λ pro,s,m×z−1 , λ pro,s,m×z ) T , and H pro v s =0 holds true (here, the zero in H pro v s =0 indicates that all elements of the vector are zeros). Here, X s,j,k represents an information bit (j is an integer no smaller than one and less than or equal to n−1), P pro,s,k represents the parity bit of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, and λ pro,s,k =(X s,1,k , X s,2,k , . . . , X s,n−1,k , P pro,s,k ) (accordingly, λ pro,s,k =(X s,1,k , P pro,s,k ) when n=2, λ pro,s,k =(X s,1,k , X s,2,k , P pro,s,k ) when n=3, λ pro,s,k =(X s,1,k , X s,2,k , X s,3,k , P pro,s,k ) when n=4, λ pro,s,k =(X s,1,k , X s,2,k , X s,3,k , X s,4,k , P pro,s,k ) when n=5, and λ pro,s,k +(X s,1,k , X s,2,k , X s,3,k , X s,4,k , X s,5,k , P pro,s,k ) when n=6). Here, k=1, 2, . . . , m×z−1, m×z, or that is, k is an integer no smaller than one and less than or equal to m×z. Further, the number of rows of H pro , which is the parity check matrix for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, is m×z.

In the following, explanation is provided of a configuration, when tail-biting is performed according to the improved tail-biting scheme, of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 while referring to FIGS. 26 and 27 .

When assuming a sub-matrix (vector) corresponding to the parity check polynomial shown in expression 70, which is the ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, to be H i , an ith sub-matrix H i is expressed as shown in expression 73.

In expression 73, the n consecutive ones correspond to the terms D 0 X 1 (D)=1×X 1 (D), D 0 X 2 (D)=1×X 2 (D), . . . , D 0 X n−1 (D)=1×X n−1 (D) (that is, D 0 X k (D)=1×X k (D), where k is an integer no smaller than one and less than or equal to n−1), and D 0 P(D)=1×P(D) in each form of expression 70.

A parity check matrix H pro in the vicinity of time m×z, among the parity check matrix H pro corresponding to the above-defined transmission sequence v s for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 when tail-biting is performed according to the improved tail-biting scheme, is shown in FIG. 26 . As shown in FIG. 26 , a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and an (i+1)th row in the parity check matrix H pro (see FIG. 26 ).

Also, in FIG. 26 , a reference sign 2601 indicates the (m×z)th (i.e., the last) row of the parity check matrix H pro , and corresponds to the (m−1)th parity check polynomial that satisfies zero, according to expression 70, as described above. Similarly, a reference sign 2602 indicates the (m×z−1)th row of the parity check matrix H pro , and corresponds to the (m−2)th parity check polynomial that satisfies zero, according to expression 70, as described above. Further, a reference sign 2603 indicates a column group corresponding to time point m×z, and the column group of the reference sign 2603 is arranged in the order of: X s,1,m×z ; X s,2,m×z ; X s,n−1,m×z ; . . . , and P pro,s,m×z . A reference sign 2604 indicates a column group corresponding to time point m×z−1, and the column group of the reference sign 2604 is arranged in the order of: X s,1,m×z−1 ; X s,2,m×z−1 ; X s,n−1,m×z−1 ; and P pro,s,m×z−1 .

Next, a parity check matrix H pro in the vicinity of times m×z−1, m×z, 1, 2, among the parity check matrix H pro corresponding to a reordered transmission sequence, specifically v s =( . . . , X s,1,m×z−1 , X s,2,m×z−1 , . . . , X s,n−1,m×z−1 , P pro,s,m×z−1 , X s,1,m×z , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z , . . . , X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . ,) T is shown in FIG. 27 . In this case, the portion of the parity check matrix H pro shown in FIG. 27 is the characteristic portion of the parity check matrix H pro when tail-biting is performed according to the improved tail-biting scheme. As shown in FIG. 27 , a configuration is employed in which a sub-matrix is shifted n columns to the right between an ith row and an (i+1)th row in the parity check matrix H pro when the transmission sequence is reordered (refer to FIG. 27 ).

Also, in FIG. 27 , when the parity check matrix is expressed as shown in FIG. 26 , a reference sign 2705 indicates a column corresponding to a (m×z×n)th column and a reference sign 2706 indicates a column corresponding to the first column.

A reference sign 2707 indicates a column group corresponding to time point m×z−1, and the column group of the reference sign 2707 is arranged in the order of: X s,1,m×z−1 ; X s,2,m×z−1 ; . . . , X s,n−1,m×z−1 ; and P pro,s,m×z−1 . Further, a reference sign 2708 indicates a column group corresponding to time point m×z, and the column group of the reference sign 2708 is arranged in the order of: X s,1,m×z ; X s,2,m×z ; . . . , X s,n−1,m×z ; and P pro,s,m×z . A reference sign 2709 indicates a column group corresponding to time point one, and the column group of the reference sign 2709 is arranged in the order of: X s,1,1 ; X s,2,1 ; . . . , X s,n−1,1 ; and P pro,s,1 . A reference sign 2710 indicates a column group corresponding to time point two, and the column group of the reference sign 2710 is arranged in the order of: X s,1,2 ; X s,2,2 ; . . . , X s,n−1,2 ; and P pro,s,2 .

When the parity check matrix is expressed as shown in FIG. 26 , a reference sign 2711 indicates a row corresponding to a (m×z)th row and a reference sign 2712 indicates a row corresponding to the first row. Further, the characteristic portions of the parity check matrix H when tail-biting is performed according to the improved tail-biting scheme are the portion left of the reference sign 2713 and below the reference sign 2714 in FIG. 27 and the portion corresponding to the first row indicated by the reference sign 2712 in FIG. 27 when the parity check matrix is expressed as shown in FIG. 26 .

When assuming a sub-matrix (vector) corresponding to expression 71, which is the parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, to be Ω 0 , Ω 0 can be expressed as shown in expression 74.

In expression 74, the n consecutive ones correspond to the terms D 0 X 1 (D)=1×X 1 (D), D 0 X 2 (D)=1×X 2 (D), . . . , D 0 X n−1 (D)=1×X n−1 (D) (that is, D 0 X k (D)=1×X k (D), where k is an integer no smaller than one and less than or equal to n−1), and D 0 P(D)=1×P(D) in each form of expression 71.

Then, the row corresponding to the first row indicated by the reference sign 2712 in FIG. 27 when the parity check matrix is expressed as shown in FIG. 26 can be expressed by using expression 74 (refer to reference sign 2712 in FIG. 27 ). Further, the rows other than the row corresponding to the reference sign 2712 in FIG. 27 (i.e., the row corresponding to the first row when the parity check matrix is expressed as shown in FIG. 26 ) are rows each corresponding to one of the parity check polynomials that satisfy zero according to expression 70, which is the ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (as explanation has been provided above).

To provide a supplementary explanation of the above, although not shown in FIG. 26 , in the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 as expressed in FIG. 26 , a vector obtained by extracting the first row of the parity check matrix H pro is a vector corresponding to expression 71, which is a parity check polynomial that satisfies zero.

Further, a vector composed of the (e+1)th row (where e is an integer no smaller than one and less than or equal to m×z−1) of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 as expressed in FIG. 26 , corresponds to an e%mth parity check polynomial that satisfies zero, according to expression 70, which is the ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

In the description provided above, for ease of explanation, explanation has been provided of the parity check matrix for the LDPC-CC in the present embodiment, which is definable by expression 70 and expression 71, having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. However, a parity check matrix for the LDPC-CC, which is definable by expression 59 and expression 68, having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated in a similar manner as described above.

Next, explanation is provided of a parity check polynomial matrix that is equivalent to the above-described parity check matrix for the LDPC-CC, which is definable by expression 70 and expression 71, having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

In the above, explanation has been provided of the configuration of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 where the transmission sequence (encoded sequence (codeword)) of an sth block is v s =(X s,1,1 , X s,2,1 , . . . , X s,n−1,1 , P pro,s,1 , X s,1,2 , X s,2,2 , . . . , X s,n−1,2 , P pro,s,2 , . . . , X s,1,m×z−1 , X s,2,m×z−1 , . . . , X s,n−1,m×z−1 , P pro,s,m×z−1 , X s,2,m×z , . . . , X s,n−1,m×z , P pro,s,m×z ) T =(λ pro,s,1 , λ pro,s,2 , . . . , λ pro,s,m×z−1 , λ pro,s,m×z ) T , and H pro v s =0 holds true (here, the zero in H pro v s =0 indicates that all elements of the vector are zeros). In the following, explanation is provided of a configuration of a parity check matrix H pro _ m for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 where H pro _ m u s =0 holds true (here, the zero in H pro _ m u s =0 indicates that all elements of the vector are zeros) when a transmission sequence (encoded sequence (codeword)) of an sth block is expressed as u s =(X s,1,1 , X s,1,2 , . . . , X s,1,m×z , X s,2,1 , X s,2,2 , . . . , X s,2,m×z , . . . , X s,n−2,1 , X s,n−2,2 , . . . , X s,n−2,m×z , X s,n−1,1 , X s,n−1,2 , . . . , X s,n−1,m×z , P pro,s,1 , P pro,s,2 , . . . , P pro,s,m×z ) T =(Λ X1,s , Λ X2,s , Λ X3,s , . . . , ΛX n−2,s , Λ Xn−1,s , Λ pro,s ) T .

Here, note that Λ Xk,s is expressible as Λ Xk,s =(X s,k,1 , X s,k,2 , X s,k,3 , . . . , X s,k,m×z−2 , X s,k,m×z−1 , X s,k,m×z ) (where k is an integer no smaller than one and less than or equal to n−1) and Λ pro,s is expressible as Λ pro,s =(P pro,s,1 , P pro,s,2 , P pro,s,3 , . . . , P pro,s,m×z−2 , P pro,s,m×z−1 , P pro,s,m×z ). Accordingly, for example, u s =Λ X1,s , Λ pro,s ) T when n=2, u s =(Λ X1,s , Λ X2,s , Λ pro,s ) T when n=3, u s =(Λ X1,s , Λ X2,s , Λ X3,s , Λ pro,s ) T when n=4, u s =(Λ X1,s , Λ X2,s , Λ X3,s , Λ X4,s , Λ pro,s ) T when n=5, u s =(Λ X1,s , Λ X2,s , Λ X3,s , Λ X4,s , Λ X5,s , Λ pro,s ) T when n=6, u s =(Λ X1,s , Λ X2,s , Λ X3,s , Λ X4,s , Λ X5,s , Λ X6,s , Λ pro,s ) T when n=7, and u s =(Λ X1,s , Λ X2,s , Λ X3,s , Λ X4,s , Λ X5,s , Λ X6,s , Λ X7,s , Λ pro,s ) T when n=8.

Here, since an m×z number of information bits X 1 are included in one block, an m×z number of information bits X 2 are included in one block, . . . , an m×z number of information bits X n−2 are included in one block, an m×z number of information bits X n−1 , are included in one block (as such, an m×z number of information bits X k are included in one block (where k is an integer no smaller than one and less than or equal to n−1)), and an m×z number of parity bits P pro are included in one block, the parity check matrix H pro _ m for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be expressed as H pro _ m =[H x,1 , H x,2 , . . . , H x,n−2 , H x,n−1 , H p ] as shown in FIG. 28 .

Further, since the transmission sequence (encoded sequence (codeword)) of an sth block is expressed as u s =(X s,1,1 , X s,1,2 , . . . , X s,1,m×z , X s,2,1 , X s,2,2 , . . . , X s,2,m×z , . . . , X s,n−2,1 , X s,n−2,2 , . . . , X s,n−2,m×z , X s,n−1,1 , X s,n−1,2 , . . . , X s,n−1,m×z , P pro,s,1 , P pro,s,2 , . . . , P pro,s,m×z ) T =(Λ X1,s , Λ X2,s , Λ X3,s , . . . , Λ Xn−2,s , Λ Xn−1,s , Λ pro,s ) T , H x,1 is a partial matrix pertaining to information X 1 , H x,2 is a partial matrix pertaining to information X 2 , . . . , H x,n−2 is a partial matrix pertaining to information X n−2 , H x,n−1 is a partial matrix pertaining to information X n−1 (as such, H x,k is a partial matrix pertaining to information X k (where k is an integer no smaller than one and less than or equal to n−1)), and H p is a partial matrix pertaining to a parity P pro . In addition, as shown in FIG. 28 , the parity check matrix H pro _ m is a matrix having m×z rows and n×m×z columns, the partial matrix H x,1 pertaining to information X 1 is a matrix having m×z rows and m×z columns, the partial matrix H x,2 pertaining to information X 2 is a matrix having m×z rows and m×z columns, . . . , the partial matrix H x,n−2 pertaining to information X n−2 is a matrix having m×z rows and m×z columns, the partial matrix H x,n−1 pertaining to information X n−1 is a matrix having m×z rows and m×z columns (as such, the partial matrix H x,k pertaining to information X k is a matrix having m×z rows and m×z columns (where k is an integer no smaller than one and less than or equal to n−1)), and the partial matrix H p pertaining to the parity P pro is a matrix having m×z rows and m×z columns.

The transmission sequence (encoded sequence (codeword)) composed of an n×m×z number of bits of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is u s =(X s,1,1 , X s,1,2 , . . . , X s,1,m×z , X s,2,1 , X s,2,2 , . . . , X s,2,m×z , . . . , X s,n−2,1 , X s,n−2,2 , . . . , X s,n−2,m×z , X s,n−1,1 , X s,n−1,2 , . . . , X s,n−1,m×z , P pro,s,1 , P pro,s,2 , . . . , P pro,s,m×z ) T =(Λ X1,s , Λ X2,s , Λ X3,s , . . . , Λ Xn−2,s , Λ Xn−1,s , Λ pro,s ) T , and m×z parity check polynomials that satisfy zero are necessary for obtaining this transmission sequence u s . Here, a parity check polynomial that satisfies zero appearing eth, when the m×z parity check polynomials that satisfy zero are arranged in sequential order, is referred to as an eth parity check polynomial that satisfies zero (where e is an integer no smaller than zero and less than or equal to m×z−1). As such, the m×z parity check polynomials that satisfy zero are arranged in the following order.

zeroth: zeroth parity check polynomial that satisfies zero

first: first parity check polynomial that satisfies zero

second: second parity check polynomial that satisfies zero

eth: eth parity check polynomial that satisfies zero

(m×z−2)th: (m×z−2)th parity check polynomial that satisfies zero

(m×z−1)th: (m×z−1)th parity check polynomial that satisfies zero

As such, the transmission sequence (encoded sequence (codeword)) u s of an sth block of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained. (Note that a vector composed of the (e+1)th row of the parity check matrix H pro _ m for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 corresponds to the eth parity check polynomial that satisfies zero.)

Accordingly, in the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2,

the zeroth parity check polynomial that satisfies zero is a parity check polynomial that satisfies zero, according to expression 71,

the first parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,

the second parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (m−2)th parity check polynomial that satisfies zero is the (m−2)th parity check polynomial that satisfies zero, according to expression 70,

the (m−1)th parity check polynomial that satisfies zero is the (m−1)th parity check polynomial that satisfies zero, according to expression 70,

the mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 70,

the (m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,

the (m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (2m−2)th parity check polynomial that satisfies zero is the (m−2)th parity check polynomial that satisfies zero, according to expression 70,

the (2m−1)th parity check polynomial that satisfies zero is the (m−1)th parity check polynomial that satisfies zero, according to expression 70,

the 2mth parity check polynomial that satisfies zero is the zeroth parity check polynomial that satisfies zero, according to expression 70,

the (2m+1)th parity check polynomial that satisfies zero is the first parity check polynomial that satisfies zero, according to expression 70,

the (2m+2)th parity check polynomial that satisfies zero is the second parity check polynomial that satisfies zero, according to expression 70,

the (m×z−2)th parity check polynomial that satisfies zero is the (m−2)th parity check polynomial that satisfies zero, according to expression 70, and

the (m×z−1)th parity check polynomial that satisfies zero is the (m−1)th parity check polynomial that satisfies zero, according to expression 70.

That is, the zeroth parity check polynomial that satisfies zero is the parity check polynomial that satisfies zero, according to expression 71, and the eth parity check polynomial that satisfies zero (where e is an integer no smaller than one and less than or equal to m×z−1) is the e%mth parity check polynomial that satisfies zero, according to expression 70.

In the present embodiment (in fact, commonly applying to the entirety of the present disclosure), % means a modulo, and for example, α%q represents a remainder after dividing α by q (where α is an integer no smaller than zero, and q is a natural number).

FIG. 29 shows a configuration of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

According to the explanation provided above, a vector composing the first row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the zeroth parity check polynomial that satisfies zero, or that is, the parity check polynomial that satisfies zero, according to expression 71.

Similarly, a vector composing the second row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the first parity check polynomial that satisfies zero, or that is, the first parity check polynomial that satisfies zero, according to expression 70.

A vector composing the third row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the second parity check polynomial that satisfies zero, or that is, the second parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (m−1)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m−2)th parity check polynomial that satisfies zero, or that is, the (m−2)th parity check polynomial that satisfies zero, according to expression 70.

A vector composing the mth row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m−1)th parity check polynomial that satisfies zero, or that is, the (m−1)th parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (m+1)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the mth parity check polynomial that satisfies zero, or that is, the zeroth parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (m+2)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m+1)th parity check polynomial that satisfies zero, or that is, the first parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (m+3)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m+2)th parity check polynomial that satisfies zero, or that is, the second parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (2m−1)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (2m−2)th parity check polynomial that satisfies zero, or that is, the (m−2)th parity check polynomial that satisfies zero, according to expression 70.

A vector composing the 2mth row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (2m−1)th parity check polynomial that satisfies zero, or that is, the (m−1)th parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (2m+1)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the 2mth parity check polynomial that satisfies zero, or that is, the zeroth parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (2m+2)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (2m+1)th parity check polynomial that satisfies zero, or that is, the first parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (2m+3)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (2m+2)th parity check polynomial that satisfies zero, or that is, the second parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (m×z−1)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m×z−2)th parity check polynomial that satisfies zero, or that is, the (m−2)th parity check polynomial that satisfies zero, according to expression 70.

A vector composing the (m×z)th row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the (m×z−1)th parity check polynomial that satisfies zero, or that is, the (m−1)th parity check polynomial that satisfies zero, according to expression 70.

As such, a vector composing the first row of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the zeroth parity check polynomial that satisfies zero, or that is, the parity check polynomial that satisfies zero, according to expression 71, and a vector composing the (e+1)th row (where e is an integer no smaller than one and less than or equal to m×z−1) of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be generated from a term pertaining to a parity of the eth parity check polynomial that satisfies zero, or that is, the e%mth parity check polynomial that satisfies zero, according to expression 70.

Here, note that m is the time-varying period of the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

FIG. 29 shows the configuration of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. In the following, an element at row i, column j of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is expressed as H p,comp [i][j] (where i and j are integers no smaller than one and less than or equal to m×z (i, j=1, 2, 3, . . . , m×z−1, m×z)). The following logically follows.

In the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, a parity check polynomial pertaining to the first row of the partial matrix H p pertaining to the parity P pro is expressed as shown in expression 71.

As such, when the first row of the partial matrix H p pertaining to the parity P pro has elements satisfying one, expression 75 holds true.

[Math. 75]

H p,comp [1][1]=1  (75)

Further, elements of H p,comp [1][j] in the first row of the partial matrix H p pertaining to the parity P pro other than those given by expression 75 are zeroes. That is, when j is an integer no smaller than one and less than or equal to m×z and satisfies k≠1, H p,comp [1][j]=0 holds true for all conforming j. Note that expression 75 expresses elements corresponding to D 0 P(D) (=P(D)) in expression 71 (refer to FIG. 29 ).

In the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, and further, when assuming that (s−1)%m=k (where % is the modulo operator (modulo)) holds true for an sth row (where s in an integer no smaller than two and less than or equal to m×z) of the partial matrix H p pertaining to the parity P pro , a parity check polynomial pertaining to the sth row of the partial matrix H p pertaining to the parity P pro is expressed as shown in expression 76, according to expression 70.

[Math. 76]

( D a1,k,1 +D a1,k,2 + . . . +D a1,k,r 1 +1) X 1 ( D )+( D a2,k,1 +D a2,k,2 + . . . +D a2,k,r 2 +1) X 2 ( D )+ . . . +( D an−1,k,1 +D an−1,k,2 + . . . +D an−1,k,r n−1 +1) X n−1 ( D )+( D b 1,k +1) P ( D )=0  (76)

As such, when the sth row of the partial matrix H p pertaining to the parity P pro has elements satisfying one, expression 77 holds true.

[Math. 77]

H p,comp [ s ][ s ]=1  (77)

Expressions. 78-1 and 78-2 also hold true.

[Math. 78]

when s−b 1,k ≥1:

H p,comp [ s ][ s−b 1,k ]=1  (78-1)

when s−b 1,k <1:

H p,comp [ s ][ s−b 1,k +m×z ]=1  (78-2)

Further, elements of H p,comp [s][j] in the sth row of the partial matrix H p pertaining to the parity P pro other than those given by expression 77, expression 78-1, and expression 78-2 are zeroes. That is, when s−b 1,k ≥1, j≠s, and j≠s−b 1,k , H p,comp [s][j]=0 holds true for all conforming j (where j is an integer no smaller than one and less than or equal to m×z). On the other hand, when s−b 1,k <1, j≠s, and j≠s−b 1,k +(m×z), H p,comp [s][j]=0 holds true for all conforming j (where j is an integer no smaller than one and less than or equal to m×z).

Note that expression 77 expresses elements corresponding to D 0 P(D) (=P(D)) in expression 76 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 29 ), the sorting in expression 78-1 and expression 78-2 applies since the partial matrix H p pertaining to the parity P pro has the first to (m×z)th rows, and in addition, also has the first to (m×z)th columns.

In addition, the relation between the rows of the partial matrix H p pertaining to the parity P pro in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 and the parity check polynomials shown in expression 70 and expression 71 is as shown in FIG. 29 , and is therefore similar to the relation shown in FIG. 24 , explanation of which being provided above.

Next, explanation is provided of values of elements composing a partial matrix H x,q pertaining to information X q in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (here, q is an integer no smaller than one and less than or equal to n−1).

FIG. 30 shows a configuration of the partial matrix H x,q pertaining to information X q in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

In the following, an element at row i, column j of the partial matrix H x,1 pertaining to information X 1 in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is expressed as H x,1,comp [i][j] (where i and j are integers no smaller than one and less than or equal to m×z (i, j=1, 2, 3, . . . , m×z−1, m×z)). The following logically follows.

In the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, a parity check polynomial pertaining to the first row of the partial matrix X 1 pertaining to information X 1 is expressed as shown in expression 71.

As such, when the first row of the partial matrix H x,1 pertaining to information X 1 has elements satisfying one, expression 79 holds true.

[Math. 79]

H x,1,comp [1][1]=1  (79)

Expression 80 also holds true since 1−a 1,0,y <1 (where a 1,0,y is a natural number).

[Math. 80]

H x,1,comp [1][1− a 1,0,y +m×z ]=1  (80)

Expression 80 is satisfied when y is an integer no smaller than one and less than or equal to r 1 (y=1, 2, . . . , r 1 −1, r 1 ). Further, elements of H x,1,comp [1][j] in the first row of the partial matrix H x,1 pertaining to information X 1 other than those given by expression 79 and expression 80 are zeroes. That is, H x,1,comp [1][j]=0 holds true for all j (j is an integer no smaller than one and less than or equal to m×z) satisfying the conditions of {j≠1} and {j≠1a 1,0,y +m×z for all y, where y is an integer no smaller than one and less than or equal to r 1 }.

Here, note that expression 79 expresses elements corresponding to D 0 X 1 (D) (=X 1 (D)) in expression 71 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 30 ), and expression 80 is satisfied since the partial matrix H x,1 pertaining to information X 1 has the first to (m×z)th rows, and in addition, also has the first to (m×z)th columns.

In the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, and further, when assuming that (s−1)%m=k (where % is the modulo operator (modulo)) holds true for an sth row (where s in an integer no smaller than two and less than or equal to m×z) of the partial matrix H x,1 pertaining to information X 1 , a parity check polynomial pertaining to the sth row of the partial matrix H x,1 pertaining to information X 1 is expressed as shown in expression 76, according to expression 70.

As such, when the first row of the partial matrix H x,1 pertaining to information X 1 has elements satisfying one, expression 81 holds true.

[Math. 81]

H x,1,comp [ s ][ s ]=1  (81)

Expressions. 82-1 and 82-2 also hold true.

[Math. 82]

when s−a 1,k,y ≥1:

H x,1,comp [ s ][ s−a 1,k,y ]=1  (82-1)

when s−a 1,k,y <1:

H x,1,comp [ s ][ s−a 1,k,y +m×z ]=1  (82-2)

(where y is an integer no smaller than one and less than or equal to r 1 (y=1, 2, . . . , r 1 −1, r 1 ))

Further, elements of H x,1,comp [s][j] in a sth row of the partial matrix H x,1 pertaining to information X 1 other than those given by expression 81, expression 82-1, and expression 82-2 are zeroes. That is, H x,1,comp [s][j]=0 holds true for all j (j is an integer no smaller than one and less than or equal to m×z) satisfying the conditions of {j≠s} and {j≠s−a 1,k,y when s−a 1,k,y ≥1, and j≠s−a 1,k,y +m×z when s−a 1,k,y <1, for all y, where y is an integer no smaller than one and less than or equal to r 1 }.

Here, note that expression 81 expresses elements corresponding to D 0 X 1 (D)(=X 1 (D)) in expression 76 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 30 ), and the sorting in expression 82-1 and expression 82-2 applies since the partial matrix H x,1 pertaining to information X 1 has the first to (m×z)th rows, and in addition, also has the first to (m×z)th columns.

In addition, the relation between the rows of the partial matrix H x,1 pertaining to information X 1 in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 and the parity check polynomials shown in expression 70 and expression 71 is as shown in FIG. 30 (where q=1), and is therefore similar to the relation shown in FIG. 24 , explanation of which being provided above.

In the above, explanation has been provided of the configuration of the partial matrix H x,1 pertaining to information X 1 in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. In the following, explanation is provided of a configuration of a partial matrix H x,q pertaining to information X q (where q is an integer no smaller than one and less than or equal to n−1) in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (Note that the configuration of the partial matrix H x,q can be explained in a similar manner as the configuration of the partial matrix H x,1 explained above).

FIG. 30 shows a configuration of the partial matrix H x,q pertaining to information X q in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

In the following, an element at row i, column j of the partial matrix H x,q pertaining to information X q in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is expressed as H x,q,comp [i][j] (where i and j are integers no smaller than one and less than or equal to m×z (i, j=1, 2, 3, . . . , m×z−1, m×z)). The following logically follows.

In the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, a parity check polynomial pertaining to the first row of the partial matrix H x,q pertaining to information X q is expressed as shown in expression 71.

As such, when the first row of the partial matrix H x,q pertaining to information X q has elements satisfying one, expression 83 holds true.

[Math. 83]

H x,q,comp [1][1]=1  (83)

Expression 84 also holds true since 1−a q,0,y <1 (where a q,0,y is a natural number).

[Math. 84]

H x,q,comp [1][1− a q,0,y +m×z ]=1  (84)

Expression 84 is satisfied when y is an integer no smaller than one and less than or equal to r q (where y=1, 2, . . . , r q −1, r q ).

Further, elements of H x,q,comp [1][j] in the first row of the partial matrix H x,q pertaining to information X q other than those given by expression 83 and expression 83 are zeroes. That is, H x,q,comp [1][j]=0 holds true for all j (j is an integer no smaller than one and less than or equal to m×z) satisfying the conditions of {j≠1} and {j≠1−a q,0,y +m×z for all y, where y is an integer no smaller than one and less than or equal to r q }.

Here, note that expression 83 expresses elements corresponding to D 0 X q (D) (=X q (D)) in expression 71 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 30 ), and expression 84 is satisfied since the partial matrix H x,q pertaining to information X q has the first to (m×z)th rows, and in addition, also has the first to (m×z)th columns.

In the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, when a parity check polynomial that satisfies zero satisfies expression 70 and expression 71, and further, when assuming that (s−1)%m=k (where % is the modulo operator (modulo)) holds true for an sth row (where s in an integer no smaller than two and less than or equal to m×z) of the partial matrix H x,q pertaining to information X q , a parity check polynomial pertaining to the sth row of the partial matrix H x,q pertaining to information X q is expressed as shown in expression 76, according to expression 70.

As such, when the sth row of the partial matrix H x,q pertaining to information X q has elements satisfying one, expression 85 holds true.

[Math. 85]

H x,q,comp [ s ][ s ]=1  (85)

Expressions. 86-1 and 86-2 also hold true.

[Math. 86]

when s−a q,k,y ≥1:

H x,q,comp [ s ][ s−a q,k,y ]=1  (86-1)

when s−a q,k,y <1:

H x,q,comp [ s ][ s−a q,k,y +m×z ]=1  (86-2)

(where y is an integer no smaller than one and less than or equal to r q (y=1, 2, . . . , r q −1, r q ))

Further, elements of H x,q,comp [s][j] in the sth row of the partial matrix H x,q pertaining to information X q other than those given by expression 85, expression 86-1, and expression 86-2 are zeroes. That is, H x,q,comp [s][j]=0 holds true for all j (j is an integer no smaller than one and less than or equal to m×z) satisfying the conditions of {j≠s} and {j≠s−a q,k,y when s−a q,k,y ≥1, and j≠s−a q,k,y +m×z when s−a q,k,y <1, for all y, where y is an integer no smaller than one and less than or equal to r q }.

Here, note that expression 85 expresses elements corresponding to D 0 X q (D) (=X q (D)) in expression 76 (corresponding to the ones in the diagonal component of the matrix shown in FIG. 30 ), and the sorting in expression 86-1 and expression 85-2 applies since the partial matrix H x,q pertaining to information X q has the first to (m×z)th rows, and in addition, also has the first to (m×z)th columns.

In addition, the relation between the rows of the partial matrix H x,q pertaining to information X q in the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 and the parity check polynomials shown in expression 70 and expression 71 is as shown in FIG. 30 , and is therefore similar to the relation shown in FIG. 24 , explanation of which being provided above.

In the above, explanation has been provided of the configuration of the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. In the following, explanation is provided of a generation method of a parity check matrix that is equivalent to the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

FIG. 31 illustrates the configuration of a parity check matrix H for an LDPC (block) code having a coding rate of (N−M)/N (where N>M>0). For example, the parity check matrix of FIG. 31 has M rows and N columns. In the following, explanation is provided under the assumption that the parity check matrix H of FIG. 31 represents the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (as such, H pro _ m =H (of FIG. 31 ), and in the following, H refers to the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2).

In FIG. 31 , the transmission sequence (codeword) for a jth block is v j T =(Y j,1 , Y j,2 , Y j,3 , . . . , Y j,N−2 , Y j,N−1 , Y j,N ) (for systematic codes, Y j,k (where k is an integer no smaller than one and less than or equal to N) is the information X or the parity P (parity P pro )).

Here, Hv j =0 is satisfied (where the zero in Hv j =0 indicates that all elements of the vector are zeroes, or that is, a kth row has a value of zero for all k (where k is an integer no smaller than one and less than or equal to M)).

Here, the element of the kth row (where k is an integer no smaller than one and less than or equal to M) of the transmission sequence v j for the jth block (in FIG. 31 , the element in a kth column of a transpose matrix v j T of the transmission sequence v j ) is Y j,k , and a vector extracted from a kth column of the parity check matrix H for the LDPC (block) code having a coding rate of (N−M)/N (where N>M>0) (i.e., the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2) is expressed as c k , as shown in FIG. 31 . Here, the parity check matrix H for the LDPC (block) code (i.e., the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2) is expressed as shown in expression 87.

[Math. 87]

H =[ c 1 c 2 c 3 . . . c N−2 c N−1 c N ]

FIG. 32 indicates a configuration when interleaving is applied to the transmission sequence (codeword) v j T for the jth block expressed as v j T =(Y j,1 , Y j,2 , Y j,3 , . . . , Y j,N−2 , Y j,N−1 , Y j,N ). In FIG. 32 , an encoding section 3202 takes information 3201 as input, performs encoding thereon, and outputs encoded data 3203 . For example, when encoding the LDPC (block) code having a coding rate (N−M)/N (where N>M>0) (i.e., the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2) as shown in FIG. 32 , the encoding section 3202 takes the information for the jth block as input, performs encoding thereon based on the parity check matrix H for the LDPC (block) code having a coding rate of (N−M)/N (where N>M>0) (i.e., the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2) as shown in FIG. 31 , and outputs the transmission sequence (codeword) v j T =(Y j,1 , Y j,2 , Y j,3 , . . . , Y j,N−2 , Y j,N−1 , Y j,N ) for the jth block.

Then, an accumulation and reordering section (interleaving section) 3204 takes the encoded data 3203 as input, accumulates the encoded data 3203 , performs reordering thereon, and outputs interleaved data 3205 . Accordingly, the accumulation and reordering section (interleaving section) 3204 takes the transmission sequence v j =(Y j,1 , Y j,2 , Y j,3 , . . . , Y j,N−2 , Y j,N−1 , Y j,N ) T for the jth block as input, and outputs a transmission sequence (codeword) v′ j =(Y j,32 , Y j,99 , Y j,23 , . . . , Y j,234 , Y j,3 , Y j,43 ) T as shown in FIG. 32 , which is a result of reordering being performed on the elements of the transmission sequence v j (here, note that v′ j is one example of a transmission sequence output by the accumulation and reordering section (interleaving section) 3204 ). Here, as discussed above, the transmission sequence v′ j is obtained by reordering the elements of the transmission sequence v j for the jth block. Accordingly, v′j is a vector having one row and n columns, and the N elements of v′j are such that one each of the terms Y j,1 , Y j,2 , Y j,3 , . . . , Y j,N−2 , Y j,N−1 , Y j,N is present.

Here, an encoding section 3207 as shown in FIG. 32 having the functions of the encoding section 3202 and the accumulation and reordering section (interleaving section) 3204 is considered. Accordingly, the encoding section 3207 takes the information 3201 as input, performs encoding thereon, and outputs the encoded data 3203 . For example, the encoding section 3207 takes the information of the jth block as input, and as shown in FIG. 32 , outputs the transmission sequence (codeword) v′ j =(Y j,32 , Y j,99 , Y j,23 , . . . , Y j,234 , Y j,3 , Y j,43 ) T . In the following, explanation is provided of a parity check matrix H′ for the LDPC (block) code having a coding rate of (N−M)/N (where N>M>0) corresponding to the encoding section 3207 (i.e., a parity check matrix H′ that is equivalent to the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2) while referring to FIG. 33 .

FIG. 33 a configuration of the parity check matrix H′ when the transmission sequence (codeword) is v′ j =(Y j,32 , Y j,99 , Y j,23 , . . . , Y j,234 , Y j,3 , Y j,43 ) T Here, the element in the first row of the transmission sequence v′ j for the jth block (the element in the first column of the transpose matrix v′ j T of the transmission sequence v′ j , in FIG. 33 ) is Y j,32 . Accordingly, a vector extracted from the first row of the parity check matrix H′, when using the above-described vector c k (k=1, 2, 3, . . . , N−2, N−1, N), is c 32 . Similarly, the element in the second row of the transmission sequence v′ j for the jth block (the element in the second column of the transpose matrix v′ j T of the transmission sequence v′ j in FIG. 33 ) is Y j,99 . Accordingly, a vector extracted from the second row of the parity check matrix H′ is c 99 . Further, as shown in FIG. 33 , a vector extracted from the third row of the parity check matrix H′ is c 23 , a vector extracted from the (N−2)th row of the parity check matrix H′ is c 234, a vector extracted from the (N−1)th row of the parity check matrix H′ is c 3 , and a vector extracted from the Nth row of the parity check matrix H′ is c 43 .

That is, when the element in the ith row of the transmission sequence v′j for the jth block (the element in the ith column of the transpose matrix v′ j T of the transmission sequence v′ j , in FIG. 33 ) is expressed as Y j,g (g=1, 2, 3, . . . , N−2, N−1, N), then the vector extracted from the ith column of the parity check matrix H′ is c g , when using the above-described vector c k .

Thus, the parity check matrix H′ for the transmission sequence (codeword) v′ j =(Y j,32 , Y j,99 , Y j,23 , . . . , Y j,234 , Y j,3 , Y j,43 ) T is expressed as shown in expression 88.

[Math. 88]

H ′=[ c 32 c 99 c 23 . . . c 234 c 3 c 43 ]  (88)

When the element in the ith row of the transmission sequence v′ j for the jth block (the element in the ith column of the transpose matrix v′ j T of the transmission sequence v′ j in FIG. 33 ) is represented as Y j,g (g=1, 2, 3, . . . , N−2, N−1, N), then the vector extracted from the ith column of the parity check matrix H′ is c g , when using the above-described vector c k . When the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence v′ j of the jth block is obtainable with no limitation to the above-given example.

Accordingly, when interleaving is applied to the transmission sequence (codeword) of the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, a parity check matrix of the interleaved transmission sequence (codeword) is obtained by performing reordering of columns (i.e., a column permutation) as described above on the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

As such, it naturally follows that the transmission sequence (codeword) (v j ) obtained by returning the interleaved transmission sequence (codeword) (v′ j ) to the original order is the transmission sequence (codeword) of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. Accordingly, by returning the interleaved transmission sequence (codeword) (v′ j ) and the parity check matrix H′ corresponding to the interleaved transmission sequence (codeword) (v′ j ) to their respective orders, the transmission sequence v j and the parity check matrix corresponding to the transmission sequence v j can be obtained, respectively. Further, the parity check matrix obtained by performing the reordering as described above is the parity check matrix H of FIG. 31 , or in other words, the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2.

FIG. 34 illustrates an example of a decoding-related configuration of a receiving device, when encoding of FIG. 32 has been performed. The transmission sequence obtained when the encoding of FIG. 32 is performed undergoes processing, in accordance with a modulation scheme, such as mapping, frequency conversion and modulated signal amplification, whereby a modulated signal is obtained. A transmitting device transmits the modulated signal. The receiving device then receives the modulated signal transmitted by the transmitting device to obtain a received signal. A log-likelihood ratio calculation section 3400 in FIG. 34 takes the received signal as input, calculates a log-likelihood ratio for each bit of the codeword, and outputs a log-likelihood ratio signal 3401 .

For example, assume that the transmitting device transmits a transmission sequence (codeword) v′ j =(Y j,32 , Y j,99 , Y j,23 , . . . , Y j,234 , Y j,3 , Y j,43 ) T for the jth block. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Y j,32 , the log-likelihood ratio for Y j,99 , the log-likelihood ratio for Y j,23 , . . . , the log-likelihood ratio for Y j,234 , the log-likelihood ratio for Y j,3 , and the log-likelihood ratio for Y j,43 , and outputs the log-likelihood ratios.

An accumulation and reordering section (deinterleaving section) 3402 takes the log-likelihood ratio signal 3401 as input, performs accumulation and reordering thereon, and outputs a deinterleaved log-likelihood ratio signal 3403 .

For example, the accumulation and reordering section (deinterleaving section) 3402 takes, as input, the log-likelihood ratio for Y j,32 , the log-likelihood ratio for Y j,99 , the log-likelihood ratio for Y j,23 , . . . , the log-likelihood ratio for Y j,234 , the log-likelihood ratio for Y j,3 , and the log-likelihood ratio for Y j,43 , performs reordering, and outputs the log-likelihood ratios in the order of: the log-likelihood ratio for Y j,1 , the log-likelihood ratio for Y j,2 , the log-likelihood ratio for Y j,3 , . . . , the log-likelihood ratio for Y j,N−2 , the log-likelihood ratio for Y j,N−1 , and the log-likelihood ratio for Y j,N in the stated order.

A decoder 3404 takes the deinterleaved log-likelihood ratio signal 3403 as input, performs belief propagation decoding, such as the BP decoding given in Non-Patent Literature 6 to 8, sum-product decoding, min-sum decoding, offset BP decoding, Normalized BP decoding, Shuffled BP decoding, and Layered BP decoding in which scheduling is performed, based on the parity check matrix H for the LDPC (block) code having a coding rate of (N−M)/N (where N>M>0) as shown in FIG. 31 (that is, based on the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2), and thereby obtains an estimation sequence 3405 (note that the decoder 3404 may perform decoding according to decoding methods other than belief propagation decoding).

For example, the decoder 3404 takes, as input, the log-likelihood ratio for Y j,1 , the log-likelihood ratio for Y j,2 , the log-likelihood ratio for Y j,3 , . . . , the log-likelihood ratio for Y j,N−2 , the log-likelihood ratio for Y j,N−1 , and the log-likelihood ratio for Y j,N in the stated order, performs belief propagation decoding based on the parity check matrix H for the LDPC (block) code having a coding rate of (N−M)/N (where N>M>0) as shown in FIG. 31 (that is, based on the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2), and obtains the estimation sequence (note that the decoder 3404 may perform decoding according to decoding methods other than belief propagation decoding).

In the following, a decoding-related configuration that differs from the above is described. The decoding-related configuration described in the following differs from the decoding-related configuration described above in that the accumulation and reordering section (deinterleaving section) 3402 is not included. The operations of the log-likelihood ratio calculation section 3400 are identical to those described above, and thus, explanation thereof is omitted in the following.

For example, assume that the transmitting device transmits a transmission sequence (codeword) v′ j =(Y j,32 , Y j,99 , Y j,23 , . . . , Y j,234 , Y j,3 , Y j,43 ) T for the jth block. Then, the log-likelihood ratio calculation section 3400 calculates, from the received signal, the log-likelihood ratio for Y j,32 , the log-likelihood ratio for Y j,99 , the log-likelihood ratio for Y j,23 , . . . , the log-likelihood ratio for Y j,234 , the log-likelihood ratio for Y j,3 , and the log-likelihood ratio for Y j,43 , and outputs the log-likelihood ratios (corresponding to 3406 in FIG. 34 ).

A decoder 3407 takes a log-likelihood ratio signal 3406 as input, performs belief propagation decoding, such as the BP decoding given in Non-Patent Literature 6 to 8, sum-product decoding, min-sum decoding, offset BP decoding, Normalized BP decoding, Shuffled BP decoding, and Layered BP decoding in which scheduling is performed, based on the parity check matrix H′ for the LDPC (block) code having a coding rate of (N−M)/N (where N>M>0) as shown in FIG. 33 (that is, based on the parity check matrix H′ that is equivalent to the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2), and thereby obtains an estimation sequence 3409 (note that the decoder 3407 may perform decoding according to decoding methods other than belief propagation decoding).

For example, the decoder 3407 takes, as input, the log-likelihood ratio for Y j,32 , the log-likelihood ratio for Y j,99 , the log-likelihood ratio for Y j,23 , . . . , the log-likelihood ratio for Y j,234 , the log-likelihood ratio for Y j,3 , and the log-likelihood ratio for Y j,43 in the stated order, performs belief propagation decoding based on the parity check matrix H′ for the LDPC (block) code having a coding rate of (N−M)/N (where N>M>0) as shown in FIG. 33 (that is, based on the parity check matrix H′ that is equivalent to the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2), and obtains the estimation sequence (note that the decoder 3407 may perform decoding according to decoding methods other than belief propagation decoding).

As explained above, even when the transmitted data is reordered due to the transmitting device interleaving the transmission sequence v j =(Y j,1 , Y j,2 , Y j,3 , . . . , Y j,N−2 , Y j,N−1 , Y j,N ) T for the jth block, the receiving device is able to obtain the estimation sequence by using a parity check matrix corresponding to the reordered transmitted data.

Accordingly, when interleaving is applied to the transmission sequence (codeword) of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, the receiving device uses, as a parity check matrix for the interleaved transmission sequence (codeword), a matrix obtained by performing reordering of columns (i.e., column permutation) as described above on the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. As such, the receiving device is able to perform belief propagation decoding and thereby obtain an estimation sequence without performing interleaving on the log-likelihood ratio for each acquired bit.

In the above, explanation is provided of the relation between interleaving applied to a transmission sequence and a parity check matrix. In the following, explanation is provided of reordering of rows (row permutation) performed on a parity check matrix.

FIG. 35 illustrates a configuration of a parity check matrix H corresponding to the transmission sequence (codeword) v j T =(Y j,1 , Y j,2 , Y j,3 , . . . , Y j,N−2 , Y j,N−1 , Y j,N ) for the jth block of the LDPC (block) code having a coding rate of (N−M)/N. For example, the parity check matrix H of FIG. 35 is a matrix having M rows and N columns. In the following, explanation is provided under the assumption that the parity check matrix H of FIG. 35 represents the parity check matrix H pro _ m for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (as such, H pro _ m =H (of FIG. 35 ), and in the following, H refers to the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2) (for systematic codes, Y j,k (where k is an integer no smaller than one and less than or equal to N) is the information X or the parity P (the parity P pro ), and is composed of (N−M) information bits and M parity bits). Here, Hv j =0 is satisfied (where the zero in Hv j =0 indicates that all elements of the vector are zeroes, or that is, a kth row has a value of zero for all k (where k is an integer no smaller than one and less than or equal to M)).

Further, a vector extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H of FIG. 35 is expressed as a vector z k . Here, the parity check matrix H for the LDPC (block) code (i.e., the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2) is expressed as shown in expression 89.

Next, a parity check matrix obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35 is considered.

FIG. 36 shows an example of a parity check matrix H′ obtained by performing reordering of rows (row permutation) on the parity check matrix H of FIG. 35 . The parity check matrix H′, similar as the parity check matrix shown in FIG. 35 , is a parity check matrix corresponding to the transmission sequence (codeword) v j T =(Y j,1 , Y j,2 , Y j,3 , . . . , Y j,N−2 , Y j,N−1 , Y j,N ) for the jth block of the LDPC (block) code having a coding rate of (N−M)/N (i.e., the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2) (or that is, a parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2).

The parity check matrix H′ of FIG. 36 is composed of vectors z k extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H of FIG. 35 . For example, in the parity check matrix H′, the first row is composed of vector z 130 , the second row is composed of vector z 24 , the third row is composed of vector z 45 , . . . , the (M−2)th row is composed of vector z 33 , the (M−1)th row is composed of vector z 9 , and the Mth row is composed of vector z 3 . Note that M row-vectors extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H′ are such that one each of the terms z 1 , z 2 , z 3 , . . . , z M−2 , z M−1 , z M is present.

The parity check matrix H′ for the LDPC (block) code (i.e., the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2) is expressed as shown in expression 90.

Here, H′v j =0 is satisfied (where the zero in H′v j =0 indicates that all elements of the vector are zeroes, or that is, a kth row has a value of zero for all k (where k is an integer no smaller than one and less than or equal to M)).

That is, for the transmission sequence v j T for the jth block, a vector extracted from the ith row of the parity check matrix H′ of FIG. 36 is expressed as c k (where k is an integer no smaller than one and less than or equal to M), and the M row-vectors extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H′ of FIG. 36 are such that one each of the terms z 1 , z 2 , z 3 , . . . , z M−2 , z M−1 , z M is present.

As described above, for the transmission sequence v j T for the jth block, a vector extracted from the ith row of the parity check matrix H′ of FIG. 36 is expressed as c k (where k is an integer no smaller than one and less than or equal to M), and the M row-vectors extracted from the kth row (where k is an integer no smaller than one and less than or equal to M) of the parity check matrix H′ of FIG. 36 are such that one each of the terms z 1 , z 2 , z 3 , . . . , z M−2 , z M−1 , z M is present. Note that, when the above is followed to create a parity check matrix, then a parity check matrix for the transmission sequence v j of the jth block is obtainable with no limitation to the above-given example.

Accordingly, even when the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 is being used, it does not necessarily follow that a transmitting device and a receiving device are using the parity check matrix explained above or the parity check matrix explained with reference to FIGS. 26 through 30 . As such, a transmitting device and a receiving device may use, in place of the parity check matrix explained above, a matrix obtained by performing reordering of columns (column permutation) as described above or a matrix obtained by performing reordering of rows (row permutation) as described above as a parity check matrix. Similarly, a transmitting device and a receiving device may use, in place of the parity check matrix explained with reference to FIGS. 26 through 30 , a matrix obtained by performing reordering of columns (column permutation) as described above or a matrix obtained by performing reordering of rows (row permutation) as described above as a parity check matrix.

In addition, a matrix obtained by performing both reordering of columns (column permutation) as described above and reordering of rows (row permutation) as described above on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 may be used as a parity check matrix.

In such a case, a parity check matrix H 1 is obtained by performing reordering of columns (column permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33 ). Subsequently, a parity check matrix H 2 is obtained by performing reordering of rows (row permutation) on the parity check matrix H 1 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36 ). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H 2 so obtained.

Alternatively, a parity check matrix H 1,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33 ). Subsequently, a parity check matrix H 2,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H 1,1 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36 ).

Further, a parity check matrix H 1,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H 2,1 . Finally, a parity check matrix H 2,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H 1,2 .

As described above, a parity check matrix H 2,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H 1,k is obtained by performing a kth (where k is an integer no smaller than two and less than or equal to s) reordering of columns (column permutation) on a parity check matrix H 2,k−1 . Then, a parity check matrix H 2,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H 1,k . Note that in the first iteration in such a case, a parity check matrix H 1,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. Then, a parity check matrix H 2,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H 1,1 .

In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H 2,s .

In another method, a parity check matrix H 3 is obtained by performing reordering of rows (row permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36 ). Subsequently, a parity check matrix H 4 is obtained by performing reordering of columns (column permutation) on the parity check matrix H 3 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33 ). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H 4 so obtained.

Alternatively, a parity check matrix H 3,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36 ). Subsequently, a parity check matrix H 4,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H 3,1 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33 ).

Further, a parity check matrix H 3,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H 4,1 . Finally, a parity check matrix H 4,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H 3,2 .

As described above, a parity check matrix H 4,s may be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H 3,k is obtained by performing a kth (where k is an integer no smaller than two and less than or equal to s) reordering of rows (row permutation) on a parity check matrix H 4,k−1 . Then, a parity check matrix H 4,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H 3,k . Note that in the first iteration in such a case, a parity check matrix H 3,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix explained above for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. Then, a parity check matrix H 4,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H 3,1 .

In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H 4,s .

Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 or the parity check matrix explained with reference to FIGS. 26 through 30 for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained from each of the parity check matrix H 2 , the parity check matrix H 2,s , the parity check matrix H 4 , and the parity check matrix H 4,s .

In addition, a matrix obtained by performing both reordering of columns (column permutation) as described above and reordering of rows (row permutation) as described above on the parity check matrix explained with reference to FIGS. 26 through 30 for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 may be used as a parity check matrix.

In such a case, a parity check matrix H 5 is obtained by performing reordering of columns (column permutation) on the parity check matrix explained with reference to FIGS. 26 through 30 for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33 ). Subsequently, a parity check matrix H 6 is obtained by performing reordering of rows (row permutation) on the parity check matrix H 5 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36 ). A transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H 6 so obtained.

Alternatively, a parity check matrix H 5,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix explained with reference to FIGS. 26 through 30 for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33 ). Subsequently, a parity check matrix H 6,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix H 5,1 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36 ).

Further, a parity check matrix H 5,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H 6,1 . Finally, a parity check matrix H 6,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H 5,2 .

As described above, a parity check matrix H 6,s may be obtained by repetitively performing reordering of columns (column permutation) and reordering of rows (row permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H 5,k is obtained by performing a kth (where k is an integer no smaller than two and less than or equal to s) reordering of columns (column permutation) on a parity check matrix H 6,k−1 . Then, a parity check matrix H 6,k is obtained by performing a kth reordering of rows (row permutation) on the parity check matrix H 5,k . Note that in the first iteration in such a case, a parity check matrix H 5,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix explained with reference to FIGS. 26 through 30 for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. Then, a parity check matrix H 6,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix H 5,1 .

In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H 6,s .

In another method, a parity check matrix H 7 is obtained by performing reordering of rows (row permutation) on the parity check matrix explained with reference to FIGS. 26 through 30 for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36 ). Subsequently, a parity check matrix H 8 is obtained by performing reordering of columns (column permutation) on the parity check matrix H 7 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33 ). In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H 8 so obtained.

Alternatively, a parity check matrix H 7,1 may be obtained by performing a first reordering of rows (row permutation) on the parity check matrix explained with reference to FIGS. 26 through 30 for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 (for example, through conversion from the parity check matrix shown in FIG. 35 to the parity check matrix shown in FIG. 36 ). Subsequently, a parity check matrix H 8,1 may be obtained by performing a first reordering of columns (column permutation) on the parity check matrix H 7,1 (for example, through conversion from the parity check matrix shown in FIG. 31 to the parity check matrix shown in FIG. 33 ).

Then, a parity check matrix H 7,2 may be obtained by performing a second reordering of rows (row permutation) on the parity check matrix H 8,1 . Finally, a parity check matrix H 8,2 may be obtained by performing a second reordering of columns (column permutation) on the parity check matrix H 7,2 .

As described above, a parity check matrix H 8 be obtained by repetitively performing reordering of rows (row permutation) and reordering of columns (column permutation) for s iterations (where s is an integer no smaller than two). In such a case, a parity check matrix H 7,k is obtained by performing a kth (where k is an integer no smaller than two and less than or equal to s) reordering of rows (row permutation) on a parity check matrix H 8,k−1 . Then, a parity check matrix H 8,k is obtained by performing a kth reordering of columns (column permutation) on the parity check matrix H 7,k . Note that in the first iteration in such a case, a parity check matrix H 7,1 is obtained by performing a first reordering of rows (row permutation) on the parity check matrix explained with reference to FIGS. 26 through 30 for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. Then, a parity check matrix H 8,1 is obtained by performing a first reordering of columns (column permutation) on the parity check matrix H 7,1 .

In such a case, a transmitting device and a receiving device may perform encoding and decoding by using the parity check matrix H 8,s .

Here, note that by performing reordering of rows (row permutation) and reordering of columns (column permutation), the parity check matrix for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 or the parity check matrix explained with reference to FIGS. 26 through 30 for the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2 can be obtained from each of the parity check matrix H 6 , the parity check matrix H 6,s , the parity check matrix H 8 , and the parity check matrix H 8,s .

Expression 70 and expression 71 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme. However, parity check polynomials usable for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme are not limited to those shown in expression 70 and expression 71. For instance, instead of the parity check polynomial shown in expression 70, a parity check polynomial as shown in expression 91 may used as an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

Here, a p,i,q (p=1, 2, . . . , n−1 (p is an integer no smaller than one and less than or equal to n−1); q=1, 2, . . . , r p (q is an integer no smaller than one and less than or equal to r p )) is assumed to be a natural number. Also, when y, z=1, 2, . . . , r p (y and z are integers no smaller than one and less than or equal to r p ) and y≠z, a p,i,y ≠a p,i,z holds true for conforming ∀ (y, z) (for all conforming y and z).

Further, in order to achieve high error correction capability, each of r 1 , r 2 , . . . , r n−2 , and r n−1 is set to four or greater (k is an integer no smaller than one and less than or equal to n−1, and r k is four or greater for all conforming k). In other words, k is an integer no smaller than one and less than or equal to n−1 in expression 91, and the number of terms of X k (D) is four or greater for all conforming k. Also, b 1,i is a natural number.

As such, expression 69, which is a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, is expressed as shown in expression 92 (is expressed by using the zeroth parity check polynomial that satisfies zero, according to expression 91).

Further, as another method, in an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, the number of terms of X k (D) (where k is an integer no smaller than one and less than or equal to n−1) may be set for each parity check polynomial. According to this method, for instance, instead of the parity check polynomial shown in expression 70, a parity check polynomial as shown in expression 93 may used as an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

Here, a p,i,q (p=1, 2, . . . , n−1 (p is an integer no smaller than one and less than or equal to n−1); q=1, 2, . . . , r p,i (q is an integer no smaller than one and less than or equal to r p,i ) is assumed to be a natural number. Also, when y, z=1, 2, . . . , r p,i (y and z are integers no smaller than one and less than or equal to r p,i ) and y≠z, a p,i,y ≠a p,i,z holds true for conforming ∀ (y, z) (for all conforming y and z). Also, b 1,i is a natural number. Note that expression 93 is characterized in that r p,i can be set for each i.

Further, in order to achieve high error correction capability, it is desirable that p is an integer no smaller than one and less than or equal to n−1, i is an integer no smaller than zero and less than or equal to m−1, and r p,i be set to one or greater for all conforming p and i.

As such, expression 69, which is a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, is expressed as shown in expression 94 (is expressed by using the zeroth parity check polynomial that satisfies zero, according to expression 93).

Further, as another method, in an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, the number of terms of X k (D) (where k is an integer no smaller than one and less than or equal to n−1) may be set for each parity check polynomial. According to this method, for instance, instead of the parity check polynomial shown in expression 70, a parity check polynomial as shown in expression 95 may used as an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

Here, a p,i,q (p=1, 2, . . . , n−1 (p is an integer no smaller than one and less than or equal to n−1); q=1, 2, . . . , r p,i (q is an integer no smaller than one and less than or equal to r p,i ) is assumed to be an integer no smaller than zero. Also, when y, z=1, 2, . . . , r p,i (y and z are integers no smaller than one and less than or equal to r p,i ) and y≠z, a p,i,y ≠a p,i,z holds true for conforming ∀ (y, z) (for all conforming y and z). Also, b 1,i is a natural number. Note that expression 95 is characterized in that r p,i can be set for each i.

Further, in order to achieve high error correction capability, it is desirable that p is an integer no smaller than one and less than or equal to n−1, i is an integer no smaller than zero and less than or equal to m−1, and r p,i be set to two or greater for all conforming p and i.

As such, expression 69, which is a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2, is expressed as shown in expression 96 (is expressed by using the zeroth parity check polynomial that satisfies zero, according to expression 95).

In the above, expression 70 and expression 71 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme. In the following, explanation is provided of examples of conditions to be applied to the parity check polynomials in expression 70 and expression 71 for achieving high error correction capability.

As explanation is provided above, in order to achieve high error correction capability, each of r 1 , r 2 , . . . , r n−2 , and r n−1 is set to three or greater (k is an integer no smaller than one and less than or equal to n−1, and r k is three or greater for all conforming k), or that is, in expression 70, k is an integer no smaller than one and less than or equal to n−1, and the number of terms of X k (D) is set to four or greater for all conforming k. In the following, explanation is provided of examples of conditions for achieving high error correction capability when each of r 1 , r 2 , . . . , r n−2 , and r n−1 is set to three or greater.

Here, note that since the parity check polynomial of expression 71 is created by using the zeroth parity check polynomial of expression 70, in expression 71, k is an integer no smaller than one and less than or equal to n−1, and the number of terms of X k (D) is four or greater for all conforming k. Further, as explained above, the parity check polynomial that satisfies zero, according to expression 70, becomes an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, and the parity check polynomial that satisfies zero, according to expression 71, becomes a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2.

Here, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X 1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme. Note that a column weight of a column α in a parity check matrix is defined as the number of ones existing among vector elements in a vector extracted from the column α.

<Condition #B-1-1>

a 1,0,1 %m=a 1,1,1 %m=a 1,2,1 %m=a 1,3,1 %m= . . . =a 1,g,1 %m= . . . =a 1,m−2,1 %m=a 1,m−1,1 %m=v 1,1 (where v 1,1 is a fixed value)

a 1,0,2 %m=a 1,1,2 %m=a 1,2,2 %m=a 1,3,2 %m= . . . =a 1,g,2 %m= . . . =a 1,m−2,2 %m=a 1,m−1,2 %m=v 1,2 (where v 1,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X 2 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

<Condition #B-1-2>

a 2,0,1 %m=a 2,1,1 %m=a 2,2,1 %m=a 2,3,1 %m= . . . =a 2,g,1 %m= . . . =a 2,m−2,1 %m=a 2,m−1,1 %m=v 2,1 (where v 2,1 is a fixed value)

a 2,0,2 %m=a 2,1,2 %m=a 2,2,2 %m=a 2,3,2 %m= . . . =a 2,g,2 %m= . . . =a 2,m−2,2 %m=a 2,m−1,2 %m=v 2,2 (where v 2,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Generalizing the above, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X k in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme (where k is an integer no smaller than one and less than or equal to n−1).

<Condition #B-1-k>

a k,0,1 %m=a k,1,1 %m=a k,2,1 %m=a k,3,1 %m= . . . =a k,g,1 %= . . . =a k,m−2,1 %m=a k,m−1,1 %m=v k,1 (where v k,1 is a fixed value)

a k,0,2 %m=a k,1,2 %m=a k,2,2 %m=a k,3,2 %m= . . . =a k,g,2 %m= . . . =a k,m−2,2 %m=a k,m−1,2 %m=v k,2 (where v k,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X n−1 in the parity check matrix H pro shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

<Condition #B-1-(n−1)>

a n−1,0,1 %m=a n−1,1,1 %m=a n−1,2,1 %m=a n−1,3,1 %m= . . . =a n−1,g,1 %m= . . . =a n−1,2,1 %m=a n−1,m−1,1 %m=v n−1,1 (where v n−1,1 is a fixed value)

a n−1,0,2 %m=a n−1,1,2 %m=a n−1,2,2 %m=a n−1,3,2 %m= . . . =a n−1,g,2 %m= . . . =a n−1,m−2,2 %m=a n−1,m−1,2 %m=v n−1,2 (where v n−1,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

In the above, % means a modulo, and for example, α%m represents a remainder after dividing α by m. Conditions #B-1-1 through #B-1-(n−1) are also expressible as follows. In the following, j is one or two.

<Condition #B-1′-1>

a 1,g,j %m=v 1,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v 1,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a 1,g,j %m=v 1,j (where v 1,j is a fixed value) holds true for all conforming g.)

<Condition #B-1′-2>

a 2,g,j %m=v 2,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v 2,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a 2,g,j %m=v 2,j (where v 2,j is a fixed value) holds true for all conforming g.)

The following is a generalization of the above.

<Condition #B-1′-k>

a k,g,j %m=v k,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v k,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a k,g,j %m=v k,j (where v k,j is a fixed value) holds true for all conforming g.)

(In the above, k is an integer no smaller than one and less than or equal to n−1.)

<Condition #B-1′-(n−1)>

a n−1,g,j %m=v n−1,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a n−1,g,j %m=v n−1,j (where v n−1,j is a fixed value) holds true for all conforming g.)

Further, high error correction capability is achievable when the following conditions are also satisfied.

<Condition #B-2-1>

v 1,1 ≠0, and v 1,2 ≠0 hold true,

and also,

v 1,1 ≠v 1,2 holds true.

<Condition #B-2-2>

v 2,1 ≠0, and v 2,2 ≠0 hold true,

and also,

v 2,1 ≠v 2,2 holds true.

The following is a generalization of the above.

<Condition #B-2-k>

v k,1 ≠0, and v k,2 ≠0 hold true,

and also,

v k,1 ≠v k,2 holds true.

(In the above, k is an integer no smaller than one and less than or equal to n−1.)

<Condition #B-2-(n−1)>

v n−1,1 ≠0, and v n−1,2 ≠0 hold true,

and also,

v n−1,1 ≠v n−1,2 holds true.

Further, since partial matrices pertaining to information X 1 through X n−1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme should be irregular, the following conditions are taken into consideration.

<Condition #B-3-1>

a 1,g,v %m=a 1,h,v %m for ∀g∀h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and a 1,g,v %m=a 1,h,v %m holds true for all conforming g and h.) . . . Condition #Xa-1

In the above, v is an integer no smaller than three and less than or equal to r 1 , and Condition #Xa-1 does not hold true for all v.

<Condition #B-3-2>

a 2,g,v %m=a 2,h,v %m for ∀g∀h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and a 2,g,v %m=a 2,h,v %m holds true for all conforming g and h.) . . . Condition #Xa-2

In the above, v is an integer no smaller than three and less than or equal to r 2 , and Condition #Xa-2 does not hold true for all v.

The following is a generalization of the above.

<Condition #B-3-k>

a k,g,v %m=a k,h,v %m for ∀g∀h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and a k,g,v %m=a k,h,v %m holds true for all conforming g and h.) . . . Condition #Xa-k

In the above, v is an integer no smaller than three and less than or equal to r k , and Condition #Xa-k does not hold true for all v.

(In the above, k is an integer no smaller than one and less than or equal to n−1.)

<Condition #B-3-(n−1)>

a n−1,g %m=a n−1,h,v %m for ∀g∀h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and a n−1,g %m=a n−1,h,v %m holds true for all conforming g and h.) . . . Condition #Xa-(n−1)

In the above, v is an integer no smaller than three and less than or equal to r n−1 , and Condition #Xa-(n−1) does not hold true for all v.

Conditions #B-3-1 through #B-3-(n−1) are also expressible as follows.

<Condition #B-3′-1>

a 1,g,v %m≠a 1,h,v %m for ∃g∃h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and values of g and h that satisfy a 1,g,v %m≠a 1,h,v %m exist.) . . . Condition #Ya-1

In the above, v is an integer no smaller than three and less than or equal to r 1 , and Condition #Ya-1 holds true for all conforming v.

<Condition #B-3′-2>

a 2,g,v %m≠a 2,h,v %m for ∃g∃h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and values of g and h that satisfy a 2,g,v %m≠a 2,h,v %m exist.) . . . Condition #Ya-2

In the above, v is an integer no smaller than three and less than or equal to r 2 , and Condition #Ya-2 holds true for all conforming v.

The following is a generalization of the above.

<Condition #B-3′-k>

a k,g,v %m≠a k,h,v %m for ∃g∃h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and values of g and h that satisfy a k,g,v %m≠a k,h,v %m exist.) . . . Condition #Ya-k

In the above, v is an integer no smaller than three and less than or equal to r k , and Condition #Ya-k holds true for all conforming v.

(In the above, k is an integer no smaller than one and less than or equal to n−1.)

<Condition #B-3′-(n−1)>

a n−1,g,v %m≠a n−1,h,v %m for ∃g∃h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and values of g and h that satisfy a n−1,g,v %m≠a n−1,h,v %m exist.) . . . Condition #Ya-(n−1)

In the above, v is an integer no smaller than three and less than or equal to r n−1 , and Condition #Ya-(n−1) holds true for all conforming v.

By ensuring that the conditions above are satisfied, a minimum column weight of each of a partial matrix pertaining to information X 1 , a partial matrix pertaining to information X 2 , . . . , a partial matrix pertaining to information X n−1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme is set to three. As such, the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, when satisfying the above conditions, produces an irregular LDPC code, and high error correction capability is achieved.

Based on the conditions above, an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, and achieving high error correction capability, can be generated. Note that, in order to easily obtain an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, and achieving high error correction capability, it is desirable that r 1 =r 2 = . . . =r n−2 =r n−1 =r (where r is three or greater) be satisfied.

In addition, it may be desirable that, when drawing a tree, check nodes corresponding to the parity check polynomials of expression 70 and expression 71, which are parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, appear in a great number as possible in the tree.

In order to ensure that check nodes corresponding to the parity check polynomials of expression 70 and expression 71 appear in a great number as possible in the above-described tree, it is desirable that v k,1 and v k,2 (where k is an integer no smaller than one and less than or equal to n−1) as described above satisfy the following conditions.

<Condition #B-4-1>

When expressing a set of divisors of m other than one as R, v k,1 is not to belong to R.

<Condition #B-4-2>

When expressing a set of divisors of m other than one as R, v k,2 is not to belong to R.

In addition to the above-described conditions, the following conditions may further be satisfied.

<Condition #B-5-1>

v k,1 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,1 also satisfies the following condition. When expressing a set of values w obtained by extracting all values w satisfying v k,1 /w=g (where g is a natural number) as S, an intersection R∩S produces an empty set. The set R has been defined in Condition #B-4-1.

<Condition #B-5-2>

v k,2 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,2 also satisfies the following condition. When expressing a set of values w obtained by extracting all values w satisfying v k,2 /w=g (where g is a natural number) as S, an intersection R∩S produces an empty set. The set R has been defined in Condition #B-4-2.

Condition #B-5-1 and Condition #B-5-2 are also expressible as Condition #B-5-1′ and Condition #B-5-2′, respectively.

<Condition #B-5-1′>

v k,1 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,1 also satisfies the following condition. When expressing a set of divisors of v k,1 as S, an intersection R∩S produces an empty set.

<Condition #B-5-2′>

v k,2 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,2 also satisfies the following condition. When expressing a set of divisors of v k,2 as S, an intersection R∩S produces an empty set.

Condition #B-5-1 and Condition #B-5-1′ are also expressible as Condition #B-5-1″, and Condition #B-5-2 and Condition #B-5-2′ are also expressible as Condition #B-5-2″.

<Condition #B-5-1″>

v k,1 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,1 also satisfies the following condition. The greatest common divisor of v k,1 and m is one.

<Condition #B-5-2″>

v k,2 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,2 also satisfies the following condition. The greatest common divisor of v k,2 and m is one.

In the above, expression 91 and expression 92 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme. In the following, explanation is provided of examples of conditions to be applied to the parity check polynomials in expression 91 and expression 92 for achieving high error correction capability.

As explained above, in order to achieve high error correction capability, each of r 1 , r 2 , . . . , r n−2 , and r n−1 is set to four or greater (k is an integer no smaller than one and less than or equal to n−1, and r k is three or greater for all conforming k). In other words, k is an integer no smaller than one and less than or equal to n−1 in expression 70, and the number of terms of X k (D) is four or greater for all conforming k.

In the following, explanation is provided of examples of conditions for achieving high error correction capability when each of r 1 , r 2 , . . . , r n−2 , and r n−1 is set to four or greater.

Here, note that since the parity check polynomial of expression 92 is created by using the zeroth parity check polynomial of expression 91, in expression 92, k is an integer no smaller than one and less than or equal to n−1, and the number of terms of X k (D) is four or greater for all conforming k.

Further, as explained above, the parity check polynomial that satisfies zero, according to expression 91, becomes an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, and the parity check polynomial that satisfies zero, according to expression 92, becomes a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2.

Here, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X 1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme. Note that a column weight of a column α in a parity check matrix is defined as the number of ones existing among vector elements in a vector extracted from the column α.

<Condition #B-6-1>

a 1,0,1 %m=a 1,1,1 %m=a 1,2,1 %m=a 1,3,1 %m= . . . =a 1,g,1 %m= . . . =a 1,m−2,1 %m=a 1,m−1,1 %m=v 1,1 (where v 1,1 is a fixed value)

a 1,0,2 %m=a 1,1,2 %m=a 1,2,2 %m=a 1,3,2 %m= . . . =a 1,g,2 %m= . . . =a 1,m−2,2 %m=a 1,m−1,2 %m=v 1,2 (where v 1,2 is a fixed value)

a 1,0,3 %m=a 1,1,3 %m=a 1,2,3 %m=a 1,3,3 %m= . . . =a 1,g,3 %m= . . . =a 1,m−2,3 %m=a 1,m−1,3 %m=v 1,3 (where v 1,3 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X 2 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

<Condition #B-6-2>

a 2,0,1 %m=a 2,1,1 %m=a 2,2,1 %m=a 2,3,1 %m= . . . =a 2,g,1 %m= . . . =a 2,m−2,1 %m=a 2,m−1,1 %m=v 2,1 (where v 2,1 is a fixed value)

a 2,0,2 %m=a 2,1,2 %m=a 2,2,2 %m=a 2,3,2 %m= . . . =a 2,g,2 %m= . . . =a 2,m−2,2 %m=a 2,m−1,2 %m=v 2,2 (where v 2,2 is a fixed value)

a 2,0,3 %m=a 2,1,3 %m=a 2,2,3 %m=a 2,3,3 %m= . . . =a 2,g,3 %m= . . . =a 2,m−2,3 %m=a 2,m−1,3 %m=v 2,3 (where v 2,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Generalizing the above, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X k in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme (where k is an integer no smaller than one and less than or equal to n−1).

<Condition #B-6-k>

a k,0,1 %m=a k,1,1 %m=a k,2,1 %m=a k,3,1 %m= . . . =a k,g,1 %= . . . =a k,m−2,1 %m=a k,m−1,1 %m=v k,1 (where v k,1 is a fixed value)

a k,0,2 %m=a k,1,2 %m=a k,2,2 %m=a k,3,2 %m= . . . =a k,g,2 %m= . . . =a k,m−2,2 %m=a k,m−1,2 %m=v k,2 (where v k,2 is a fixed value)

a k,0,3 %m=a k,1,3 %m=a k,2,3 %m=a k,3,3 %m= . . . =a k,g,3 %m= . . . =a k,m−2,3 %m=a k,m−1,3 %m=v k,3 (where v k,3 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X n−1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

<Condition #B-6-(n−1)>

a n−1,0,1 %m=a n−1,1,1 %m=a n−1,2,1 %m=a n−1,3,1 %m= . . . =a n−1,g,1 %m= . . . =a n−1,2,1 %m=a n−1,m−1,1 %m=v n−1,1 (where v n−1,1 is a fixed value)

a n−1,0,2 %m=a n−1,1,2 %m=a n−1,2,2 %m=a n−1,3,2 %m= . . . =a n−1,g,2 %m= . . . =a n−1,m−2,2 %m=a n−1,m−1,2 %m=v n−1,2 (where v n−1,2 is a fixed value)

a n−1,0,3 %m=a n−1,1,3 %m=a n−1,2,3 %m=a n−1,3,3 %m= . . . =a n−1,g,3 %m= . . . =a n−1,m−2,3 %m=a n−1,m−1,3 %m=v n−1,3 (where v n−1,3 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

In the above, % means a modulo, and for example, α%m represents a remainder after dividing α by m. Conditions #B-6-1 through #B-6-(n−1) are also expressible as follows. In the following, j is one, two, or three.

<Condition #B-6′-1>

a 1,g,j %m=v 1,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v 1,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a 1,g,j %m=v 1,j (where v 1,j is a fixed value) holds true for all conforming g.)

<Condition #B-6′-2>

a 2,g,j %m=v 2,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v 2,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a 2,g,v %m=v 2,j (where v 2,j is a fixed value) holds true for all conforming g.)

The following is a generalization of the above.

<Condition #B-6′-k>

a k,g,j %m=v k,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v k,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a k,g,j %m=v k,j (where v k,j is a fixed value) holds true for all conforming g.)

(In the above, k is an integer no smaller than one and less than or equal to n−1.)

<Condition #B-6′-(n−1)>

a n−1,g,j %m=v n−1,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a n−1,g,j %m=v n−1,j (where v n−1,j is a fixed value) holds true for all conforming g.)

Further, high error-correction capability is achievable when the following conditions are also satisfied.

<Condition #B-7-1>

v 1,1 ≠v 1,2 , v 1,1 ≠v 1,3 , v 1,2 ≠v 1,3 holds true.

<Condition #B-7-2>

v 2,1 ≠v 2,2 , v 2,1 ≠v 2,3 , v 2,2 ≠v 2,3 holds true.

The following is a generalization of the above.

<Condition #B-7-k>

v k,1 ≠v k,2 , v k,1 ≠v k,3 , v k,2 ≠v k,3 holds true.

(where, in the above, k is an integer no smaller than one and less than or equal to n−1)

<Condition #B-7-(n−1)>

v n−1,1 ≠v n−1,2 , v n−1,1 ≠v n−1,3 , v n−1,2 ≠v n−1,3 holds true.

Further, since the partial matrices pertaining to information X 1 through X n−1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme should be irregular, the following conditions are taken into consideration.

<Condition #B-8-1>

a 1,g,v %m=a 1,h,v %m for ∀g∀h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and a 1,g,v %m=a 1,h,v %m holds true for all conforming g and h.) . . . Condition #Xa-1

In the above, v is an integer no smaller than four and less than or equal to r 1 , and Condition #Xa-1 does not hold true for all v.

<Condition #B-8-2>

a 2,g,v %m=a 2,h,v %m for ∀g∀h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and a 2,g,v %m=a 2,h,v %m holds true for all conforming g and h.) . . . Condition #Xa-2

In the above, v is an integer no smaller than four and less than or equal to r 2 , and Condition #Xa-2 does not hold true for all v.

The following is a generalization of the above.

<Condition #B-8-k>

a k,g,v %m=a k,h,v %m for ∀g∀h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and a k,g,v %m=a k,h,v %m holds true for all conforming g and h.) . . . Condition #Xa-k

In the above, v is an integer no smaller than four and less than or equal to r k , and Condition #Xa-k does not hold true for all v.

(In the above, k is an integer no smaller than one and less than or equal to n−1.)

<Condition #B-8-(n−1)>

a n−1,g,v %m=a n−1,h,v %m for ∀g∀h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and a n−1,g,v %m=a n−1,h,v %m holds true for all conforming g and h.) . . . Condition #Xa-(n−1)

In the above, v is an integer no smaller than four and less than or equal to r n−1 , and Condition #Xa-(n−1) does not hold true for all v.

Conditions #B-8-1 through #B-8-(n−1) are also expressible as follows.

<Condition #B-8′-1>

a 1,g,v %m≠a 1,h,v %m for ∃g∃h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and values of g and h that satisfy a 1,g,v %m≠a 1,h,v %m exist.) . . . Condition #Ya-1

In the above, v is an integer no smaller than four and less than or equal to r 1 , and Condition #Ya-1 holds true for all conforming v.

<Condition #B-8′-2>

a 2,g,v %m≠a 2,h,v %m for ∃g∃h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and values of g and h that satisfy a 2,g,v %m≠a 2,h,v %m exist.) . . . Condition #Ya-2

In the above, v is an integer no smaller than four and less than or equal to r 2 , and Condition #Ya-2 holds true for all conforming v.

The following is a generalization of the above.

<Condition #B-8′-k>

a k,g,v %m≠a k,h,v %m for ∃g∃h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and values of g and h that satisfy a k,g,v %m≠a k,h,v %m exist.) . . . Condition #Ya-k

In the above, v is an integer no smaller than four and less than or equal to r k , and Condition #Ya-k holds true for all conforming v.

(In the above, k is an integer no smaller than one and less than or equal to n−1)

<Condition #B-8′-(n−1)>

a n−1,g,v %m≠a n−1,h,v %m for ∃g∃h, g, h=0, 1, 2, . . . , m−3, m−2, m−1; g≠h

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, h is an integer no smaller than zero and less than or equal to m−1, g≠h, and values of g and h that satisfy a n−1,g,v %m≠a n−1,h,v %m exist.) . . . Condition #Ya-(n−1)

In the above, v is an integer no smaller than four and less than or equal to and Condition #Ya-(n−1) holds true for all conforming v.

By ensuring that the conditions above are satisfied, a minimum column weight of each of a partial matrix pertaining to information X 1 , a partial matrix pertaining to information X 2 , . . . , a partial matrix pertaining to information X n−1 in the parity check matrix H pro _ m , shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme is set to three. As such, the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, when satisfying the above conditions, produces an irregular LDPC code, and high error correction capability is achieved.

Based on the conditions above, an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, and achieving high error correction capability, can be generated. Note that, in order to easily obtain an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, and achieving high error correction capability, it is desirable that r 1 =r 2 = . . . =r n−2 =r n−1 =r (where r is four or greater) be satisfied.

In the above, expression 93 and expression 94 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme. In the following, explanation is provided of examples of conditions to be applied to the parity check polynomials in expression 93 and expression 94 for achieving high error correction capability.

In order to achieve high error correction capability, when i is an integer no smaller than zero and less than or equal to m−1, each of r 1,i , r 2,i , . . . , r n−2,i , r n−1,i is set to two or greater for all conforming i. In the following, explanation is provided of conditions for achieving high error correction capability in the above-described case.

As described above, the parity check polynomial that satisfies zero, according to expression 93, becomes an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, and the parity check polynomial that satisfies zero, according to expression 94, becomes a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2.

Here, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X 1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme. Note that a column weight of a column α in a parity check matrix is defined as the number of ones existing among vector elements in a vector extracted from the column α.

<Condition #B-9-1>

a 1,0,1 %m=a 1,1,1 %m=a 1,2,1 %m=a 1,3,1 %m= . . . =a 1,g,1 %m= . . . =a 1,m−2,1 %m=a 1,m−1,1 %m=v 1,1 (where v 1,1 is a fixed value)

a 1,0,2 %m=a 1,1,2 %m=a 1,2,2 %m=a 1,3,2 %m= . . . =a 1,g,2 %m= . . . =a 1,m−2,2 %m=a 1,m−1,2 %m=v 1,2 (where v 1,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X 2 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

<Condition #B-9-2>

a 2,0,1 %m=a 2,1,1 %m=a 2,2,1 %m=a 2,3,1 %m= . . . =a 2,g,1 %m= . . . =a 2,m−2,1 %m=a 2,m−1,1 %m=v 2,1 (where v 2,1 is a fixed value)

a 2,0,2 %m=a 2,1,2 %m=a 2,2,2 %m=a 2,3,2 %m= . . . =a 2,g,2 %m= . . . =a 2,m−2,2 %m=a 2,m−1,2 %m=v 2,2 (where v 2,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Generalizing the above, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X k in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme (where k is an integer no smaller than one and less than or equal to n−1).

<Condition #B-9-k>

a k,0,1 %m=a k,1,1 %m=a k,2,1 %m=a k,3,1 %m= . . . =a k,g,1 %= . . . =a k,m−2,1 %m=a k,m−1,1 %m=v k,1 (where v k,1 is a fixed value)

a k,0,2 %m=a k,1,2 %m=a k,2,2 %m=a k,3,2 %m= . . . =a k,g,2 %m= . . . =a k,m−2,2 %m=a k,m−1,2 %m=v k,2 (where v k,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X n−1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

<Condition #B-9-(n−1)>

a n−1,0,1 %m=a n−1,1,1 %m=a n−1,2,1 %m=a n−1,3,1 %m= . . . =a n−1,g,1 %m= . . . =a n−1,2,1 %m=a n−1,m−1,1 %m=v n−1,1 (where v n−1,1 is a fixed value)

a n−1,0,2 %m=a n−1,1,2 %m=a n−1,2,2 %m=a n−1,3,2 %m= . . . =a n−1,g,2 %m= . . . =a n−1,m−2,2 %m=a n−1,m−1,2 %m=v n−1,2 (where v n−1,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

In the above, % means a modulo, and for example, α%m represents a remainder after dividing α by m. Conditions #B-9-1 through #B-9-(n−1) are also expressible as follows. In the following, j is one or two.

<Condition #B-9′-1>

a 1,g,j %m=v 1,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v 1,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a 1,g,j %m=v 1,j (where v 1,j is a fixed value) holds true for all conforming g.)

<Condition #B-9′-2>

a 2,g,j %m=v 2,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v 2,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a 2,g,j 1 /0m=v 2,j (where v 2,j is a fixed value) holds true for all conforming g.)

The following is a generalization of the above.

<Condition #B-9′-k>

a k,g,j %m=v k,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v k,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a k,g,v %m=v k,j (where v k,j is a fixed value) holds true for all conforming g.)

(In the above, k is an integer no smaller than one and less than or equal to n−1.)

<Condition #B-9′-(n−1)>

a n−1,g,j %m=v n−1,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a n−1,g,j %m=v n−1,j (where v n−1,j is a fixed value) holds true for all conforming g.)

Further, high error-correction capability is achievable when the following conditions are also satisfied.

<Condition #B-10-1>

v 1,1 ≠0, and v 1,2 ≠0 hold true,

and also,

v 1,1 ≠v 1,2 holds true.

<Condition #B-10-2>

v 2,1 ≠0, and v 2,2 ≠0 hold true,

and also,

v 2,1 ≠v 2,2 holds true.

The following is a generalization of the above.

<Condition #B-10-k>

v k,1 ≠0, and v k,2 ≠0 hold true,

and also,

v k,1 ≠v k,2 holds true.

(where, in the above, k is an integer no smaller than one and less than or equal to n−1)

<Condition #B-10-(n−1)>

v n−1,1 ≠0, and v n−1,2 ≠0 hold true,

and also,

v n−1,1 ≠v n−1,2 holds true.

By ensuring that the conditions above are satisfied, a minimum column weight of each of a partial matrix pertaining to information X 1 , a partial matrix pertaining to information X 2 , . . . , a partial matrix pertaining to information X n−1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme is set to three. As such, the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, when satisfying the above conditions, produces an irregular LDPC code, and high error correction capability is achieved.

In addition, it may be desirable that, when drawing a tree, check nodes corresponding to the parity check polynomials of expression 93 and expression 94, which are parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, appear in a great number as possible in the tree.

In order to ensure that check nodes corresponding to the parity check polynomials of expression 93 and expression 94 appear in a great number as possible in the above-described tree, it is desirable that v k,1 and v k,2 (where k is an integer no smaller than one and less than or equal to n−1) as described above satisfy the following conditions.

<Condition #B-11-1>

When expressing a set of divisors of m other than one as R, v k,1 is not to belong to R.

<Condition #B-11-2>

When expressing a set of divisors of m other than one as R, v k,2 is not to belong to R.

In addition to the above-described conditions, the following conditions may further be satisfied.

<Condition #B-12-1>

v k,1 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,1 also satisfies the following condition. When expressing a set of values w obtained by extracting all values w satisfying v k,1 /w=g (where g is a natural number) as S, an intersection R∩S produces an empty set. The set R has been defined in Condition #B-11-1.

<Condition #B-12-2>

v k,2 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,2 also satisfies the following condition. When expressing a set of values w obtained by extracting all values w satisfying v k,2 /w=g (where g is a natural number) as S, an intersection R∩S produces an empty set. The set R has been defined in Condition #B-11-2.

Condition #B-12-1 and Condition #B-12-2 are also expressible as Condition #B-12-1′ and Condition #B-12-2′, respectively.

<Condition #B-12-1′>

v k,1 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,1 also satisfies the following condition. When expressing a set of divisors of v k,1 as S, an intersection R∩S produces an empty set.

<Condition #B-12-2′>

v k,2 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,2 also satisfies the following condition. When expressing a set of divisors of v k,2 as S, an intersection R∩S produces an empty set.

Condition #B-12-1 and Condition #B-12-1′ are also expressible as Condition #B-12-1″, and Condition #B-12-2 and Condition #B-12-2′ are also expressible as Condition #B-12-2″.

<Condition #B-12-1″>

v k,1 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,1 also satisfies the following condition. The greatest common divisor of v k,1 and m is one.

<Condition #B-12-2″>

v k,2 belongs to a set of integers no smaller than one and less than or equal to m−1, and v k,2 also satisfies the following condition. The greatest common divisor of v k,2 and m is one.

In the above, expression 95 and expression 96 have been used as the parity check polynomials for forming the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme. In the following, explanation is provided of examples of conditions to be applied to the parity check polynomials in expression 95 and expression 96 for achieving high error correction capability.

In order to achieve high error correction capability, when i is an integer no smaller than zero and less than or equal to m−1, each of r 1 , r 2 , . . . , r n−2,i , r n−1,i is set to three or greater for all conforming i. In the following, explanation is provided of conditions for achieving high error correction capability in the above-described case.

As described above, the parity check polynomial that satisfies zero, according to expression 95, becomes an ith parity check polynomial (where i is an integer no smaller than zero and less than or equal to m−1) that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, and the parity check polynomial that satisfies zero, according to expression 96, becomes a parity check polynomial that satisfies zero for generating a vector of the first row of the parity check matrix H pro for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n (where n is an integer no smaller than two) using the improved tail-biting scheme described in Patent Literature 2.

Here, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X 1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme. Note that a column weight of a column α in a parity check matrix is defined as the number of ones existing among vector elements in a vector extracted from the column α.

<Condition #B-13-1>

a 1,0,1 %m=a 1,1,1 %m=a 1,2,1 %m=a 1,3,1 %m= . . . =a 1,g,1 %m= . . . =a 1,m−2,1 %m=a 1,m−1,1 %m=v 1,1 (where v 1,1 is a fixed value)

a 1,0,2 %m=a 1,1,2 %m=a 1,2,2 %m=a 1,3,2 %m= . . . =a 1,g,2 %m= . . . =a 1,m−2,2 %m=a 1,m−1,2 %m=v 1,2 (where v 1,2 is a fixed value)

a 1,0,3 %m=a 1,1,3 %m=a 1,2,3 %m=a 1,3,3 %m= . . . =a 1,g,3 %m= . . . =a 1,m−2,3 %m=a 1,m−1,3 %m=v 1,3 (where v 1,3 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in the partial matrix pertaining to information X 2 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

<Condition #B-13-2>

a 2,0,1 %m=a 2,1,1 %m=a 2,2,1 %m=a 2,3,1 %m= . . . =a 2,g,1 %m= . . . =a 2,m−2,1 %m=a 2,m−1,1 %m=v 2,1 (where v 2,1 is a fixed value)

a 2,0,2 %m=a 2,1,2 %m=a 2,2,2 %m=a 2,3,2 %m= . . . =a 2,g,2 %m= . . . =a 2,m−2,2 %m=a 2,m−1,2 %m=v 2,2 (where v 2,2 is a fixed value)

a 2,0,3 %m=a 2,1,3 %m=a 2,2,3 %m=a 2,3,3 %m= . . . =a 2,g,3 %m= . . . =a 2,m−2,3 %m=a 2,m−1,3 %m=v 2,3 (where v 2,2 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Generalizing the above, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X k in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme (where k is an integer no smaller than one and less than or equal to n−1).

<Condition #B-13-k>

a k,0,1 %m=a k,1,1 %m=a k,2,1 %m=a k,3,1 %m= . . . =a k,g,1 %= . . . =a k,m−2,1 %m=a k,m−1,1 %m=v k,1 (where v k,1 is a fixed value)

a k,0,2 %m=a k,1,2 %m=a k,2,2 %m=a k,3,2 %m= . . . =a k,g,2 %m= . . . =a k,m−2,2 %m=a k,m−1,2 %m=v k,2 (where v k,2 is a fixed value)

a k,0,3 %m=a k,1,3 %m=a k,2,3 %m=a k,3,3 %m= . . . =a k,g,3 %m= . . . =a k,m−2,3 %m=a k,m−1,3 %m=v k,3 (where v k,3 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

Similarly, high error-correction capability is achievable when the following conditions are taken into consideration in order to have a minimum column weight of three in a partial matrix pertaining to information X n−1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme.

<Condition #B-13-(n−1)>

a n−1,0,1 %m=a n−1,1,1 %m=a n−1,2,1 %m=a n−1,3,1 %m= . . . =a n−1,g,1 %m= . . . =a n−1,2,1 %m=a n−1,m−1,1 %m=v n−1,1 (where v n−1,1 is a fixed value)

a n−1,0,2 %m=a n−1,1,2 %m=a n−1,2,2 %m=a n−1,3,2 %m= . . . =a n−1,g,2 %m= . . . =a n−1,m−2,2 %m=a n−1,m−1,2 %m=v n−1,2 (where v n−1,2 is a fixed value)

a n−1,0,3 %m=a n−1,1,3 %m=a n−1,2,3 %m=a n−1,3,3 %m= . . . =a n−1,g,3 %m= . . . =a n−1,m−2,3 %m=a n−1,m−1,3 %m=v n−1,3 (where v n−1,3 is a fixed value)

(where, in the above, g is an integer no smaller than zero and less than or equal to m−1)

In the above, % means a modulo, and for example, α%m represents a remainder after dividing α by m. Conditions #B-13-1 through #B-13-(n−1) are also expressible as follows. In the following, j is one, two, or three.

<Condition #B-13′-1>

a 1,g,j %m=v 1,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v 1,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a 1,g,j %m=v 1,j (where v 1,j is a fixed value) holds true for all conforming g.)

<Condition #B-13′-2>

a 2,g,j %m=v 2,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v 2,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a 2,g,v %m=v 2,j (where v 2,j is a fixed value) holds true for all conforming g.)

The following is a generalization of the above.

<Condition #B-13′-k>

a k,g,j %m=v k,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where v k,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a k,g,j %m=v k,j (where v k,j is a fixed value) holds true for all conforming g.)

(In the above, k is an integer no smaller than one and less than or equal to n−1.)

<Condition #B-13′-(n−1)>

a n−1,g,j %m=v n−1,j for ∀g, g=0, 1, 2, . . . , m−3, m−2, m−1 (where y n−1,j is a fixed value)

(The above indicates that g is an integer no smaller than zero and less than or equal to m−1, and a n−1,g,j %m=v n−1,j (where v n−1,j is a fixed value) holds true for all conforming g.)

Further, high error-correction capability is achievable when the following conditions are also satisfied.

<Condition #B-14-1>

v 1,1 ≠v 1,2 , v 1,1 ≠v 1,3 , v 1,2 ≠v 1,3 holds true.

<Condition #B-14-2>

v 2,1 ≠v 2,2 , v 2,1 ≠v 2,3 , v 2,2 ≠v 2,3 holds true.

The following is a generalization of the above.

<Condition #B-14-k>

v k,1 ≠v k,2 , v k,1 ≠v k,3 , v k,2 ≠v k,3 holds true.

(where, in the above, k is an integer no smaller than one and less than or equal to n−1)

<Condition #B-14-(n−1)>

v n−1,1 ≠v n−1,2 , v n−1,1 ≠v n−1,3 , v n−1,2 ≠v n−1,3 holds true.

By ensuring that the conditions above are satisfied, a minimum column weight of each of a partial matrix pertaining to information X 1 , a partial matrix pertaining to information X 2 , . . . , a partial matrix pertaining to information X n−1 in the parity check matrix H pro _ m shown in FIG. 28 for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme is set to three. As such, the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, when satisfying the above conditions, produces an irregular LDPC code, and high error correction capability is achieved.

Description is provided on specific examples of the configuration of a parity check matrix for the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. An LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme, when generated as described above, may achieve high error correction capability. Due to this, an advantageous effect is realized such that a receiving device having a decoder, which may be included in a broadcasting system, a communication system, etc., is capable of achieving high data reception quality. Note that the configuration methods of codes described in the present embodiment are mere examples, and an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme generated according to a method different from those explained above may also achieve high error correction capability.

In the above, description is provided of an example of the LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2. In the example described above, explanation is provided of using a parity check polynomial that satisfies zero for the LDPC-CC based on a parity check polynomial having a coding rate of R=(n−1)/n and a time-varying period of m, which serves as the basis of the LDPC-CC having a coding rate of R=(n−1)/n using the improved tail-biting scheme described in Patent Literature 2, and further, of applying a specific parity check polynomial satisfying zero to the first row of a parity check matrix. Note that Patent Literature 2 also describes applying a specific parity check polynomial satisfying zero to a jth row of a parity check matrix (where j is a natural number).

While describing an LDPC-CC (an LDPC block code using LDPC-CC) having a coding rate of (n−1)/n (n being an integer no smaller than two) using an improved tail-biting scheme, Patent Literature 2 does not disclose an LDPC-CC (an LDPC block code using LDPC-CC) that uses an improved tail-biting scheme and does not satisfy coding rate (n−1)/n (n being an integer no smaller than two).

The present invention is related to an LDPC-CC (an LDPC block code using LDPC-CC) that uses an improved tail-biting scheme and does not satisfy coding rate (n−1)/n (n being an integer no smaller than two).

The present embodiment describes a method of configuring an LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, as one example of an LDPC-CC not satisfying coding rate (n−1)/n.

Although coding rate 2/4 equals coding rate 1/2, the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial pertaining to the present embodiment differs, in terms of generation method, from a conventional LDPC-CC of coding rate (n−1)/n or a conventional LDPC-CC of coding rate (n−1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

Bits of information bits X 1 , X 2 and parity bits P 1 , P 2 , at time point j, are expressed X 1,j , X 2,j and P 1,j , P 2,j respectively.

A vector u p at time point j, is expressed u j =(X 1,j , X 2,j , P 1,j , P 2,j ).

Given a delay operator D, polynomial expressions of the information bits X 1 , X 2 are X 1 (D), X 2 (D), and polynomial expressions of the parity bits P 1 , P 2 are P 1 (D), P 2 (D).

Further, consideration is given to an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial.

The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial.

First, because two parities P 1 and P 2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P 1 (D) and two for 1×P 2 (D).

In expression (97-1-1), (97-1-2), (97-2-1), (97-2-2), i is an integer no smaller than zero and no greater than m−1 (i=0, 1, . . . , m—2, m−1).

In expression (97-1-1), (97-1-2), (97-2-1), (97-2-2), α #(2i),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r #(2i),p (where r #(2i),p is a natural number)) and β #(2i),0 is a natural number, β #(2i),1 is a natural number, β #(2i),2 is an integer no smaller than zero, and β #(2i),3 is a natural number.

Further, y is an integer no smaller than one and no greater than r #(2i),p,z is an integer no smaller than one and no greater than r #2i,p , and α #(2i),p,y ≠α #(2i),p,z holds true for ∀ (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r #(2i),p,z is an integer no smaller than one and no greater than r #2i,p , and α #(2i),p,y ≠α #(2i),p,z holds true for all y and all z satisfying y≠z.)

Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (97-1-1) or expression (97-1-2) is referred to as “#(2i); first expression” for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (97-2-1) or expression (97-2-2) is referred to as “#(2i); second expression” for realizing a time-varying period 2m.

Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-1-1) or expression (97-1-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (97-1-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (97-1-2) where i=m−1 is prepared.

Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (97-2-1) or expression (97-2-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (97-2-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (97-2-2) where i=m−1 is prepared.

Similarly, because two parities P 1 and P 2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P 1 (D) and two for 1×P 2 (D).

In expression (98-1-1), (98-1-2), (98-2-1), (98-2-2), i is an integer no smaller than zero and no greater than m−1 (i=0, 1, . . . , m−2, m−1).

In expression (98-1-1), (98-1-2), (98-2-1), (98-2-2), α #(2i+1),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r #(2i+1),p (where r #(2i+1),p is a natural number)) and β #(2i+0),0 is a natural number, β #(2i+1),1 is a natural number, β #(2i+1),2 is an integer no smaller than zero, and β #(2i+1),3 is a natural number.

Further, y is an integer no smaller than one and no greater than r #(2i+1),p,z is an integer no smaller than one and no greater than r #(2i+1),p , and α #(2i+1),1 ≠α #(2i+1),p,z holds true for ∀ (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r #(2i+1),p,z is an integer no smaller than one and no greater than r #(2i+1),p , and α #(2i+1),p,y ≠α #(2i+1),p,z holds true for all y and all z satisfying y≠z.)

Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (98-1-1) or expression (98-1-2) is referred to as “#(2i+1); first expression” for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (98-2-1) or expression (98-2-2) is referred to as “#(2i+1); second expression” for realizing a time-varying period 2m.

Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-1-1) or expression (98-1-2) is prepared.

That is,

for i=0, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=2 is prepared;

for i−z, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (98-1-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (98-1-2) where i=m−1 is prepared.

Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (98-2-1) or expression (98-2-2) is prepared.

That is,

for i=0, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (98-2-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (98-2-2) where i=m−1 is prepared.

As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (97-1-1) or expression (97-1-2), parity check polynomials satisfying zero provided by expression (97-2-1) or expression (97-2-2), parity check polynomials satisfying zero provided by expression (98-1-1) or expression (98-1-2), and parity check polynomials satisfying zero provided by expression (98-2-1) or expression (98-2-2).

For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

The following describes the relationship between time point j and expression (97-1-1), (97-1-2), (97-2-1), (97-2-2), (98-1-1), (98-1-2), (98-2-1), and (98-2-2) (where j is an integer no smaller than zero).

The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m−1).

Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i=k in #(2i); first expression and #(2i); second expression, hold true.

Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m−1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

As already described above, a vector u j at time point j is expressed as u j =(X 1,j , X 2,j , P 1,j , P 2,j ) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

Accordingly, u=(u 1 , u 2 , u 3 , . . . , u y−1 , u y , u y+1 , . . . ) T =(X 1,1 , X 2,1 , P 1,1 , P 2,1 , X 1,2 , X 2,2 , P 1,2 , P 2,2 , X 1,3 X 2,3 P 1,3 , P 2,3 , . . . , X 1,y−1 , X 2,y−1 , P 1,y−1 , P 2,y−1 , X 1,y , X 2,y , P 1,y , P 2,y , X 1,y+1 , X 2,y+1 , P 1,y+1 , P 2,y+1 , . . . ) T . Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

FIG. 37 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

As illustrated in FIG. 37 :

“a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression”;

“a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression”;

“a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression”;

“a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression”;

“a vector for the 2×(2m−1)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−2); first expression”;

“a vector for the 2×(2m−1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−2); second expression”;

“a vector for the 2×(2m)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−1); first expression”;

“a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−1); second expression”;

“a vector for the 2×(2m+1)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression”;

“a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression”;

“a vector for the 2×(2m+2)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression”;

“a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression”;

“a vector for the 2×i−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i−1)%2m); first expression”; and

“a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i−1)%2m); second expression”, and so on (where i is an integer no smaller than one).

FIG. 38 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

As illustrated in FIG. 38 :

“a vector for the first column of the parity check matrix H is related to X 1 at time point 1”;

“a vector for the second column of the parity check matrix H is related to X 2 at time point 1”;

“a vector for the third column of the parity check matrix H is related to P 1 at time point 1”;

“a vector for the fourth column of the parity check matrix H is related to P 2 at time point 1”;

“a vector for the 4×(j−1)+1th column of the parity check matrix H is related to X 1 at time point j”;

“a vector for the 4×(j−1)+2th column of the parity check matrix H is related to X 2 at time point j”;

“a vector for the 4×(j−1)+3th column of the parity check matrix H is related to P 1 at time point j”; and

“a vector for the 4×(j−1)+4th column of the parity check matrix H is related to P 2 at time point j”, and so on (where j is an integer no smaller than one).

FIG. 39 indicates a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

The following focuses on 1×X 1 (D), 1×X 2 (D), 1×P 1 (D), 1×P 2 (D) in the parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expression (97-1-1), (97-1-2), (97-2-1), (97-2-2).

A vector for the first row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (97-1-1) or expression (97-1-2) (refer to FIG. 37 ).

In expression (97-1-1) and (97-1-2):

a term for 1×X 1 (D) exists; a term for 1×X 2 (D) does not exist; and a term for 1×P 1 (D) exists but a term for 1×P 2 (D) does not exist.

Further, the relationship between column numbers and X 1 , X 2 , P 1 , P 2 is as indicated in FIG. 38 . Based on the relationship indicated in FIG. 38 and the fact that a term for 1×X 1 (D) exists, a column related to X 1 in the vector for the first row in FIG. 39 is “1”. Further, based on the relationship indicated in FIG. 38 and the fact that a term for 1×X 2 (D) does not exist, a column related to X 2 in the vector for the first row in FIG. 39 is “0”. In addition, based on the relationship indicated in FIG. 38 and the fact that a term for 1×P 1 (D) exists but a term for 1×P 2 (D) does not exist, a column related to P 1 in the vector for the first row in FIG. 39 is “1”, and a column related to P 2 in the vector for the first row in FIG. 39 is “0”.

As such, the vector for the first row in FIG. 39 is “1010”, as indicated by 3900 - 1 in FIG. 39 .

A vector for the second row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (97-2-1) or expression (97-2-2) (refer to FIG. 37 ).

In expression (97-2-1) and (97-2-2):

a term for 1×X 1 (D) does not exist; a term for 1×X 2 (D) exists; and a term for 1×P 1 (D) may or may not exist but a term for 1×P 2 (D) exists.

Further, the relationship between column numbers and X 1 , X 2 , P 1 , P 2 is as indicated in FIG. 38 . Based on the relationship indicated in FIG. 38 and the fact that a term for 1×X 1 (D) does not exist, a column related to X 1 in the vector for the second row in FIG. 39 is “0”. Further, based on the relationship indicated in FIG. 38 and the fact that a term for 1×X 2 (D) exists, a column related to X 2 in the vector for the second row in FIG. 39 is “1”. In addition, based on the relationship indicated in FIG. 38 and the fact that a term for 1×P 1 (D) may or may not exist but a term for 1×P 2 (D) exists, a column related to P 1 in the vector for the second row in FIG. 39 is “Y”, and a column related to P 2 in the vector for the second row in FIG. 39 is “1”, where Y is either “0” or “1”.

As such, the vector for the second row in FIG. 39 is “01Y1”, as indicated by 3900 - 2 in FIG. 39 .

The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expression (98-1-1), (98-1-2), (98-2-1), (98-2-2).

A vector for the third row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (98-1-1) or expression (98-1-2) (refer to FIG. 37 ).

In expression (98-1-1) and (98-1-2):

a term for 1×X 1 (D) does not exist; a term for 1×X 2 (D) exists; and a term for 1×P 1 (D) exists but a term for 1×P 2 (D) does not exist.

Further, the relationship between column numbers and X 1 , X 2 , P 1 , P 2 is as indicated in FIG. 38 . Based on the relationship indicated in FIG. 38 and the fact that a term for 1×X 1 (D) does not exist, a column related to X 1 in the vector for the third row in FIG. 39 is “0”. Further, based on the relationship indicated in FIG. 38 and the fact that a term for 1×X 2 (D) exists, a column related to X 2 in the vector for the third row in FIG. 39 is “1”. In addition, based on the relationship indicated in FIG. 38 and the fact that a term for 1×P 1 (D) exists but a term for 1×P 2 (D) does not exist, a column related to P 1 in the vector for the third row in FIG. 39 is “1”, and a column related to P 2 in the vector for the third row in FIG. 39 is “0”.

As such, the vector for the third row in FIG. 39 is “0110”, as indicated by 3901 - 1 in FIG. 39 .

A vector for the fourth row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (98-2-1) or expression (98-2-2) (refer to FIG. 37 ).

In expression (98-2-1) and (98-2-2):

a term for 1×X 1 (D) exists; a term for 1×X 2 (D) does not exist; and a term for 1×P 1 (D) may or may not exist but a term for 1×P 2 (D) exists.

Further, the relationship between column numbers and X 1 , X 2 , P 1 , P 2 is as indicated in FIG. 38 . Based on the relationship indicated in FIG. 38 and the fact that a term for 1×X 1 (D) exists, a column related to X 1 in the vector for the fourth row in FIG. 39 is “1”. Further, based on the relationship indicated in FIG. 38 and the fact that a term for 1×X 2 (D) does not exist, a column related to X 2 in the vector for the fourth row in FIG. 39 is “0”. In addition, based on the relationship indicated in FIG. 38 and the fact that a term for 1×P 1 (D) may or may not exist but a term for 1×P 2 (D) exists, a column related to P 1 in the vector for the fourth row in FIG. 39 is “Y”, and a column related to P 2 in the vector for the fourth row in FIG. 39 is “1”.

As such, the vector for the fourth row in FIG. 39 is “10Y1”, as indicated by 3901 - 2 in FIG. 39 .

Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 39 .

That is, due to the parity check polynomials of expression (97-1-1), (97-1-2), (97-2-1), (97-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), “1010” exists in the 2×(2k+1)−1th row of the parity check matrix H, and “01Y1” exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 39 .

Further, due to the parity check polynomials of expression (98-1-1), (98-1-2), (98-2-1), (98-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), “0110” exists in the 2×(2k+2)−1th row of the parity check matrix H, and “10Y1” exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 39 .

Accordingly, as illustrated in FIG. 39 , when denoting a column number of a leftmost column corresponding to “1” in “1010” in a row where “1010” exists (e.g., 3900 - 1 in FIG. 39 ) as “a”, “0110” (e.g., 3901 - 1 in FIG. 39 ) exists in a row that is two rows below the row where “1010” exists, starting from column “a+4”.

Similarly, as illustrated in FIG. 39 , when denoting a column number of a leftmost column corresponding to “1” in “01Y1” in a row where “01Y1” exists (e.g., 3900 - 2 in FIG. 39 ) as “b”, “10Y1” (e.g., 3901 - 2 in FIG. 39 ) exists in a row that is two rows below the row where “01Y1” exists, starting from column “b+4”.

Similarly, as illustrated in FIG. 39 , when denoting a column number of a leftmost column corresponding to “1” in “0110” in a row where “0110” exists (e.g., 3901 - 1 in FIG. 39 ) as “c”, “1010” (e.g., 3902 - 1 in FIG. 39 ) exists in a row that is two rows below the row where “0110” exists, starting from column “c+4”.

Similarly, as illustrated in FIG. 39 , when denoting a column number of a leftmost column corresponding to “1” in “10Y1” in a row where “10Y1” exists (e.g., 3901 - 2 in FIG. 39 ) as “d”, “01Y1” (e.g., 3902 - 2 in FIG. 39 ) exists in a row that is two rows below the row where “10Y1” exists, starting from column “d+4”.

The following describes a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

In the following, H com [u][v] (where u and v are integers no smaller than one) denotes an element at row “u” column “v” of a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Based on description above provided with reference to FIG. 37 :

“a vector for the 2×g−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g−1)%2m); first expression”; and

“a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g−1)%2m); second expression” (where g is an integer no smaller than one).

Based on description above provided with reference to FIG. 38 :

“a vector for the 4×(j−1)+1th column of the parity check matrix H is related to X 1 at time point j”;

“a vector for the 4×(j−1)+2th column of the parity check matrix H is related to X 2 at time point j”;

“a vector for the 4×(j−1)+3th column of the parity check matrix H is related to P 1 at time point j”; and

“a vector for the 4×(j−1)+4th column of the parity check matrix H is related to P 2 at time point j” (where j is an integer no smaller than one).

Based on the above, the following describes component H com [2×g−1][v] in row 2×g−1 (where g is an integer no smaller than one) and component H com [2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

As already described above, a parity check polynomial satisfying zero of #((g−1)%2m); first expression can be used to generate a vector for row 2×g−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Further, a parity check polynomial satisfying zero of #((g−1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Accordingly, when g=2×f−1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f−1)−1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (97-1-1) or expression (97-1-2), can be used to generate a vector for row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Further, a parity check polynomial satisfying zero of #(((2×f−1)−1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (97-2-1) or expression (97-2-2), can be used to generate a vector for row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)−1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (98-1-1) or expression (98-1-2), can be used to generate a vector for row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Further, a parity check polynomial satisfying zero of #(((2×f)−1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (98-2-1) or expression (98-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Accordingly, (1) when g=2×f−1 (where f is an integer no smaller than one), when a vector for row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-1), (2×f−1)−1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g−1][v]=H com [2×(2×f−1)−1][v] in row 2×g−1, or that is, row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, w=1.

[Math. 99]

H com [2×(2× f− 1)−1][4×((2× f− 1)−0−1)+ w ]=1  (99-1)

When (2×f−1)−a #(2c),w,1 −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−α #(2c),w,1 −1)+ w ]=1  (99-2)

When (2×f−1)−α #(2c),w,2 −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−α #(2c),w,2 −1)+ w ]=1  (99-3)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0, u≠(2×f−1)−α #(2c),w,1 , and u≠(2×f−1)−α #(2c),w,2 }:

H com [2×(2× f− 1)−1][4×( u− 1)+ w ]=0  (99-4)

The following holds true for X 2 . In the following, z=2, and y is an integer no smaller than three and no greater than r #(2c),z .

[Math. 100]

When (2×f−1)−α #(2c),z,y −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−α #(2c),z,y −1)+ z ]=1  (100-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−α #(2c),z,y } (where y is an integer no smaller than three and no smaller than r #(2c),z ):

H com [2×(2× f− 1)−1][4×( u− 1)+ z ]=0  (100-2)

The following holds true for P 1 .

[Math. 101]

H com [2×(2× f− 1)−1][4×((2× f− 1)−0−1)+3]=1  (101-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0}:

H com [2×(2× f− 1)−1][4×( u− 1)+3]=0  (101-2)

The following holds true for P 2 .

[Math. 102]

When (2×f−1)−β #(2c),0 −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−β #(2c),0 −1)+4]=1  (102-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−β #(2c),0 }:

H com [2×(2× f− 1)−1][4×( u− 1)+4]=0  (102-2)

Further, (2) when g=2×f−1 (where f is an integer no smaller than one), when a vector for row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-1-2), ((2×f−1)−1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g−1][v]=H com [2×(2×f−1)−1][v] in row 2×g−1, or that is, row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, w=1.

[Math. 103]

H com [2×(2× f− 1)−1][4×((2× f− 1)−0−1)+ w ]=1  (103-1)

When (2×f−1)−α #(2c),w,1 −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−α #(2c),w,1 −1)− w ]=1  (103-2)

When (2×f−1)−α #(2c),w,2 −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−α #(2c),w,2 −1)+ w ]=1  (103-3)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0, u≠(2×f−1)−α #(2c),w,1 , and u≠(2×f−1)−α #(2c),w,2 }:

H com [2×(2× f− 1)−1][4×( u− 1)+ w ]=0  (103-4)

The following holds true for X 2 . In the following, z=2, and y is an integer no smaller than three and no greater than r #(2c),z .

[Math. 104]

When (2×f−1)−α #(2c),z,y −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−α #(2c),z,y −1)+ z ]=1  (104-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−α #(2c),z,y } (where y is an integer no smaller than three and no greater than r #(2c),z ):

H com [2×(2× f− 1)−1][4×( u− 1)+ z ]=0  (104-2)

The following holds true for P 1 .

[Math. 105]

H com [2×(2× f− 1)−1][4×((2× f− 1)−0−1)+3]=1  (105-1)

When (2×f−1)−β #(2c),1 −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−β #(2c),1 −1)+3]=1  (105-2)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0 and u≠(2×f−1)−β #(2c),1 }:

H com [2×(2× f− 1)−1][4×( u− 1)+3]=0  (105-3)

The following holds true for P 2 .

[Math. 106]

For all u being an integer no smaller than one:

H com [2×(2× f− 1)−1][4×( u− 1)+4]=0  (106)

Further, (3) when g=2×f−1 (where f is an integer no smaller than one), when a vector for row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-1), (2×f−1)−1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g][v]=H com [2×(2×f−1)][v] in row 2×g, or that is, row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, z=1, and y is an integer no smaller than three and no greater than r #(2c),z .

[Math. 107]

When (2×f−1)−α #(2c),z,y −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),z,y −1)+ z ]=1  (107-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−α #(2c),z,y } (where y is an integer no smaller than three and no greater than r #(2c),z ):

H com [2×(2× f− 1)][4×( u− 1)+ z ]=0  (107-2)

The following holds true for X 2 . In the following, w=2.

[Math. 108]

H com [2×(2× f− 1)][4×((2× f− 1)−0−1)+ w ]=1  (108-1)

When (2×f−1)−α #(2c),w,1 −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),w,1 −1)+ w ]=1  (108-2)

When (2×f−1)−α #(2c),w,2 −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),w,2 −1)+ w ]=1  (108-3)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0, u≠(2×f−1)−α #(2c),w,1 , and u≠(2×f−1)−α #(2c),w,2 }:

H com [2×(2× f− 1)][4×( u− 1)+ w ]=0  (108-4)

The following holds true for P 1 .

[Math. 109]

When (2×f−1)−β #(2c),2 −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−β #(2c),2 −1)+3]=1  (109-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−β #(2c),2 }:

H com [2×(2× f− 1)][4×( u− 1)+3]=0  (109-2)

The following holds true for P 2 .

[Math. 110]

H com [2×(2× f− 1)][4×((2× f− 1)−0−1)+4]=1  (110-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0}:

H com [2×(2× f− 1)][4×( u− 1)+4]=0  (110-2)

Further, (4) when g=2×f−1 (where f is an integer no smaller than one), when a vector for row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (97-2-2), (2×f−1)−1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (97-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g][v]=H com [2×(2×f−1)][v] in row 2×g, or that is, row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, z=1, and y is an integer no smaller than three and no greater than r #(2c),z .

[Math. 111]

When (2×f−1)−α #(2c),z,y −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),z,y −1)+ z ]=1  (111-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−α #(2c),z,y } (where y is an integer no smaller than three and no greater than r #(2c),z ):

H com [2×(2× f− 1)][4×( u− 1)+ z ]=0  (111-2)

The following holds true for X 2 . In the following, w=2.

[Math. 112]

H com [2×(2× f− 1)][4×((2× f− 1)−0−1)+ w ]=1  (112-1)

When (2×f−1)−α #(2c),w,1 −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),w,1 −1)+ w ]=1  (112-2)

When (2×f−1)−α #(2c),w,2 −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),w,2 −1)+ w ]=1  (112-3)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0, u≠(2×f−1)−α #(2c),w,1 , and u≠(2×f−1)−α #(2c),w,2 }:

H com [2×(2× f− 1)][4×( u− 1)+ w ]=0  (112-4)

The following holds true for P 1 .

[Math. 113]

For all u being an integer no smaller than one:

H com [2×(2× f− 1)][4×( u− 1)+3]=0  (113)

The following holds true for P 2 .

[Math. 114]

H com [2×(2× f− 1)][4×((2× f− 1)−0−1)+4]=1  (114-1)

When (2×f−1)−β #(2c),3 −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−β #(2c),3 −1)+4]=1  (114-2)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0 and u≠(2×f−1)−β #(2c),3 }:

H com [2×(2× f− 1)][4×( u− 1)+4]=0  (114-3)

Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-1), ((2×f)−1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g−1][v]=H com [2×(2×f)−1][v] in row 2×g−1, or that is, row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, z=1, and y is an integer no smaller than three and no greater than r #(2d+1),z .

[Math. 115]

When (2×f)−α #(d2+1),z,y −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),z,y −1)+ z ]=1  (115-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−α #(2d+1),z,y } (where y is an integer no smaller than three and no greater than r #(2d+1),z ):

H com [2×(2× f )−1][4×( u− 1)+ z ]=0  (115-2)

The following holds true for X 2 . In the following, w=2.

[Math. 116]

H com [2×(2× f )−1][4×((2× f )−0−1)+ w ]=1  (116-1)

When (2×f)−α #(2d+1),w,1 −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),w,1 −1)+ w ]=1  (116-2)

When (2×f)−α #(2d+1),w,2 −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),w,2 −1)+ w ]=1  (116-3)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0, u≠(2×f)−α #(2d+1),w,1 , and u≠(2×f)−α #(2d+1),w,2 }:

H com [2×(2× f )−1][4×( u− 1)+ w ]=0  (116-4)

The following holds true for P 1 .

[Math. 117]

H com [2×(2× f )−1][4×((2× f )−0−1)+3]=1  (117-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0}:

H com [2×(2× f )−1][4×( u− 1)+3]=0  (117-2)

The following holds true for P 2 .

[Math. 118]

When (2×f)−β #(2d+1),0 −1≥0:

H com [2×(2× f )−1][4×((2× f )−β #(2d+1),0 −1)+4]=1  (118-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−β #(2d+1),0 }:

H com [2×(2× f )−1][4×( u− 1)+4]=0  (118-2)

Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-1-2), ((2×f)−1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g−1][v]=H com [2×(2×f)−1][v] in row 2×g−1, or that is, row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, z=1, and y is an integer no smaller than three and no greater than r #(2d+1),z .

[Math. 119]

When (2×f)−α #(2d+1),z,y −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),z,y −1)+ z ]=1  (119-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−α #(2d+1),z,y } (where y is an integer no smaller than three and no greater than r #(2d+1),z ):

H com [2×(2× f )−1][4×( u− 1)+ z ]=0  (119-2)

The following holds true for X 2 . In the following, w=2.

[Math. 120]

H com [2×(2× f )−1][4×((2× f )−0−1)+ w ]=1  (120-1)

When (2×f)−α #(2d+1),w,1 −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),w,1 −1)+ w ]=1  (120-2)

When (2×f)−α #(2d+1),w,2 −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),w,2 −1)+ w ]=1  (120-3)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0, u≠(2×f)−α #(2d+1),w,1 , and u≠(2×f)−α #(2d+1),w,2 }:

H com [2×(2× f )−1][4×( u− 1)+ w ]=0  (120-4)

The following holds true for P 1 .

[Math. 121]

H com [2×(2× f )−1][4×((2× f )−0−1)+3]=1  (121-1)

When (2×f)−β #(2d+1),1 −1≥0:

H com [2×(2× f )−1][4×((2× f )−β #(2d+1),1 −1)+3]=1  (121-2)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0 and u≠(2×f)−β #(2d+1),1 }:

H com [2×(2× f )−1][4×( u− 1)+3]=0  (121-3)

The following holds true for P 2 .

[Math. 122]

For all u being an integer no smaller than one:

H com [2×(2× f )−1][4×( u− 1)+4]=0  (122)

Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-1), ((2×f)−1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g][v]=H com [2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, w=1.

[Math. 123]

H com [2×(2× f )][4×((2× f )−0−1)+ w ]=1  (123-1)

When (2×f)−α #(2d+1),w,1 −1≥0:

H com [2×(2× f )][4×((2× f )−α #(2d+1),w,1 −1)+ w ]=1  (123-2)

When (2×f)−α #(2d+1),w,2 −1≥0:

H com [2×(2× f )][4×(2× f )−α #(2d+1),w,2 −1)+ W ]=1  (123-3)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0, u≠(2×f)−α #(2d+1),w,1 , and u≠(2×f)−α #(2d+1),w,2 }:

H com [2×(2× f )][4×( u− 1)+ w ]=0  (123-4)

The following holds true for X 2 . In the following, z=2, and y is an integer no smaller than three and no greater than r #(2d+1),z .

[Math. 124]

When (2×f)−α #(2d+1),z,y −1≥0:

H cam [2×(2× f )][4×((2× f )−α #(2d+1),z,y −1)+ z ]=1  (124-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−α #(2d+1),z,y } (where y is an integer no smaller than three and no greater than r #(2d+1),z ):

H com [2×(2× f )][4×( u− 1)+ z ]=0  (124-2)

The following holds true for P 1 .

[Math. 125]

When (2×f)−β #(2d+1),2 −1≥0:

H com [2×(2× f )][4×((2× f )−β #(2d+1),2 −1)+3]=1  (125-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−α #(2d+1),2 }:

H com [2×(2× f )][4×( u− 1)+3]=0  (125-2)

The following holds true for P 2 .

[Math. 126]

H com [2×(2× f )][4×((2× f )−0−1)+4]=1  (126-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0}:

H com [2×(2× f )][4×( u− 1)+4]=0  (126-2)

Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (98-2-2), ((2×f)−1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (98-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g][v]=H com [2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, w=1.

[Math. 127]

H com [2×(2× f )][4×((2× f )−0−1)+ w ]=1  (127-1)

When (2×f)−α #(2d+1),w,1 −1≥0:

H com [2×(2× f )][4×((2× f )−α #(2d+1),w,1 −1)+ w ]=1  (127-2)

When (2×f)−α #(2d+1),w,2 −1≥0:

H com [2×(2× f )][4×((2× f )−α #(2d+1),w,2 −1)+ w ]=1  (127-3)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0, u≠(2×f)−α #(2d+1),w,1 , and u≠(2×f)−α #(2d+1),w,2 }:

H com [2×(2× f )][4×( u− 1)+ w ]=0  (127-4)

The following holds true for X 2 . In the following, z=2, and y is an integer no smaller than three and no greater than r #(2d+1),z .

[Math. 128]

When (2×f)−α #(2d+1),z,y −1≥0:

H com [2×(2× f )][4×((2× f )−α #(2d+1),z,y −1)+ z ]=1  (128-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−α #(2d+1),z,y } (Where y is an integer no smaller than three and no greater than r #(2d+1),z ):

H com [2×(2× f )][4×( u− 1)+ z ]=0  (128-2)

The following holds true for P 1 .

[Math. 129]

For all u being an integer no smaller than one:

H com [2×(2× f )][4×( u− 1)+3]=0  (129)

The following holds true for P 2 .

[Math. 130]

H com [2×(2× f )][4×((2× f )−0−1)+4]=1  (130-1)

When (2×f)−β #(2d+1),3 −1≥0:

H com [2×(2× f )][4×((2× f )−β #(2d+1),3 −1)+4]=1  (130-2)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0 and u≠(2×f)−β #(2d+1),3 }:

H com [2×(2× f )][4×( u− 1)+4]=0  (130-3)

As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

In the present embodiment, description is provided of a method of code configuration that is a generalization of the method described in embodiment 1 of configuring an LDPC-CC of coding rate 2/4 that is based on a parity check polynomial.

Bits of information bits X 1 , X 2 and parity bits P 1 , P 2 , at time point j, are expressed X 1,j , X 2,j and P 1,j , P 2,j , respectively.

A vector u j , at time point j, is expressed u j =(X 1,j , X 2,j , P 2,j ).

Given a delay operator D, polynomial expressions of the information bits X 1 , X 2 are X 1 (D), X 2 (D), and polynomial expressions of the parity bits P 1 , P 2 are P 1 (D), P 2 (D).

Further, consideration is given to an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial.

The following mathematical expressions are provided as parity check polynomials satisfying zero for an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial.

First, because two parities P 1 and P 2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P 1 (D) and two for 1×P 2 (D).

In expression (131-1-1), (131-1-2), (131-2-1), (131-2-2), i is an integer no smaller than zero and no greater than m−1 (i=0, 1, . . . , m−2, m−1).

In expression (131-1-1), (131-1-2), (131-2-1), (131-2-2), α #(2c),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r #(2i),p (where r #(2i),p is a natural number)) and β #(2i),0 is a natural number, β #(2i),1 is a natural number, β #(2i),2 is an integer no smaller than zero, and β #(2i),3 is a natural number.

Further, R #(2i),p is a natural number satisfying 1≤R #(2i),p <r #(2i),p .

Further, y is an integer no smaller than one and no greater than r #(2i),p,z is an integer no smaller than one and no greater than r #(2i),p , and α #(2i),p,y ≠α #(2i),p,z holds true for ∀ (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r #(2i),p,z is an integer no smaller than one and no greater than r #2i,p , and α #(2i),p,y ≠α #(2i),p,z holds true for all y and all z satisfying y≠z.

Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (131-1-1) or expression (131-1-2) is referred to as “#(2i); first expression” for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (131-2-1) or expression (131-2-2) is referred to as “#(2i); second expression” for realizing a time-varying period 2m.

Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (131-1-1) or expression (131-1-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (131-1-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (131-1-2) where i=m−1 is prepared.

Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (131-2-1) or expression (131-2-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (131-2-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (131-2-2) where i=m−1 is prepared.

Similarly, because two parities P 1 and P 2 exist, parity check polynomials satisfying zero are provided as described in the following, two for 1×P 1 (D) and two for 1×P 2 (D).

In expression (132-1-1), (132-1-2), (132-2-1), (132-2-2), i is an integer no smaller than zero and no greater than m−1 (i=0, 1, . . . , m−2, m−1).

In expression (132-1-1), (132-1-2), (132-2-1), (132-2-2), α #(2i+1),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r #(2i+1),p (where r #(2i+1),p is a natural number)) and β #(2i+1),0 is a natural number, β #(2i+1),1 is a natural number, β #(2i+1),2 is an integer no smaller than zero, and β #(2i+1),3 is a natural number.

Further, R #(2i+1),p is a natural number satisfying 1≤R #(2i+1),p <r #(2i+1),p .

Further, y is an integer no smaller than one and no greater than r #(2i+1),p,z is an integer no smaller than one and no greater than r #(2i+1),p , and α #(2i+1),p,y ≠α #(2i+1),p,z holds true for ∀ (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r #(2i+1),p,z is an integer no smaller than one and no greater than r #(2i+1),p , and α #(2i+1),p,y ≠α #(2i+1),p,z holds true for all y and all z satisfying y≠z.)

Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (132-1-1) or expression (132-1-2) is referred to as “#(2i+1); first expression” for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (132-2-1) or expression (132-2-2) is referred to as “#(2i+1); second expression” for realizing a time-varying period 2m.

Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (132-1-1) or expression (132-1-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (132-1-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (132-1-2) where i=m−1 is prepared.

Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (132-2-1) or expression (132-2-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (132-2-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (132-2-2) where i=m−1 is prepared.

As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (131-1-1) or expression (131-1-2), parity check polynomials satisfying zero provided by expression (131-2-1) or expression (131-2-2), parity check polynomials satisfying zero provided by expression (132-1-1) or expression (132-1-2), and parity check polynomials satisfying zero provided by expression (132-2-1) or expression (132-2-2).

For example, the time varying period 2×m can be formed by preparing a 4×m number of different parity check polynomials satisfying zero.

Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

The following describes the relationship between time point j and expression (131-1-1), (131-1-2), (131-2-1), (131-2-2), (132-1-1), (132-1-2), (132-2-1), and (132-2-2) (where j is an integer no smaller than zero).

The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m−1).

Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i=k in #(2i); first expression and #(2i); second expression, hold true.

Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m−1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

The following describes a method of configuring a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

As already described above, a vector u j at time point j is expressed as u j =(X 1,j , X 2,j , P 1,j , P 2,j ) (where j is an integer no smaller than zero). In the following, a case where u is a transmission vector is considered. Note that in the following, j is an integer no smaller than one, and thus j differs between the description having been provided above and the description provided in the following. (j is set as such to facilitate understanding of the correspondence between the column numbers and the row numbers of the parity check matrix.)

Accordingly, u=(u 1 , u 2 , u 3 , . . . , u y−1 , u y , u y+1 , . . . ) T =(X 1,1 , X 2,1 , P 1,1 , P 2,1 , X 1,2 , X 2,2 , P 1,2 , P 2,2 , X 1,3 , X 2,3 , P 1,3 , P 2,3 , . . . , X 1,y−1 , X 2,y−1 , P 1,y−1 , P 2,y−1 , X 1,y , X 2,y , P 1,y , P 2,y , X 1,y+1 , X 2,y+1 , P 1,y+1 , P 2,y+1 , . . . ) T . Further, when using H to denote a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, Hu=0 holds true (here, Hu=0 indicates that all elements of the vector Hu are zeroes).

FIG. 37 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the topmost row of the parity check matrix is considered as the first row. Further, row number is incremented by one each time moving to a lower row. Accordingly, the topmost row is considered as the first row, the row immediately below the first row is considered as the second row, and the subsequent rows are considered as the third row, the fourth row, and so on.

As illustrated in FIG. 37 :

“a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression”;

“a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression”;

“a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression”;

“a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression”;

“a vector for the 2×(2m−1)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−2); first expression”;

“a vector for the 2×(2m−1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−2); second expression”;

“a vector for the 2×(2m)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−1); first expression”;

“a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−1); second expression”;

“a vector for the 2×(2m+1)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression”;

“a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression”;

“a vector for the 2×(2m+2)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression”;

“a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression”;

“a vector for the 2×i−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i−1)%2m); first expression”; and

“a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i−1)%2m); second expression”, and so on (where i is an integer no smaller than one).

FIG. 38 indicates a configuration of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression. Accordingly, the leftmost column of the parity check matrix H pro _ m is considered as the first column. Further, column number is incremented by one each time moving to a rightward column. Accordingly, the leftmost column is considered as the first column, the column immediately to the right of the first column is considered as the second column, and the subsequent columns are considered as the third column, the fourth column, and so on.

As illustrated in FIG. 38 :

“a vector for the first column of the parity check matrix H is related to X 1 at time point 1”;

“a vector for the second column of the parity check matrix H is related to X 2 at time point 1”;

“a vector for the third column of the parity check matrix H is related to P 1 at time point 1”;

“a vector for the fourth column of the parity check matrix H is related to P 2 at time point 1”;

“a vector for the 4×(j−1)+1th column of the parity check matrix H is related to X 1 at time point j”;

“a vector for the 4×(j−1)+2th column of the parity check matrix H is related to X 2 at time point j”;

“a vector for the 4×(j−1)+3th column of the parity check matrix H is related to P 1 at time point j”; and

“a vector for the 4×(j−1)+4th column of the parity check matrix H is related to P 2 at time point j”, and so on (where j is an integer no smaller than one).

FIG. 39 indicates a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

The following focuses on 1×X 1 (D), 1×X 2 (D), 1×P 1 (D), 1×P 2 (D) in the parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

The parity check polynomials at time point j=1 are parity check polynomials when i=0 in expression (131-1-1), (131-1-2), (131-2-1), (131-2-2).

A vector for the first row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (131-1-1) or expression (131-1-2) (refer to FIG. 37 ).

In expression (131-1-1) and (131-1-2):

a term for 1×X 1 (D) exists; a term for 1×X 2 (D) does not exist; and a term for 1×P 1 (D) exists but a term for 1×P 2 (D) does not exist.

Further, the relationship between column numbers and X 1 , X 2 , P 1 , P 2 is as indicated in FIG. 38 . Based on the relationship indicated in FIG. 38 and the fact that an item for 1×X 1 (D) exists, a column related to X 1 in the vector for the first row in FIG. 39 is “1”. Further, based on the relationship indicated in FIG. 38 and the fact that an item for 1×X 2 (D) does not exist, a column related to X 2 in the vector for the first row in FIG. 39 is “0”. In addition, based on the relationship indicated in FIG. 38 and the fact that an item for 1×P 1 (D) exists but an item for 1×P 2 (D) does not exist, a column related to P 1 in the vector for the first row in FIG. 39 is “1”, and a column related to P 2 in the vector for the first row in FIG. 39 is “0”.

As such, the vector for the first row in FIG. 39 is “1010”, as indicated by 3900 - 1 in FIG. 39 .

A vector for the second row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (131-2-1) or expression (131-2-2) (refer to FIG. 37 ).

In expression (131-2-1) and (131-2-2):

a term for 1×X 1 (D) does not exist; a term for 1×X 2 (D) exists; and a term for 1×P 1 (D) may or may not exist but a term for 1×P 2 (D) exists.

Further, the relationship between column numbers and X 1 , X 2 , P 1 , P 2 is as indicated in FIG. 38 . Based on the relationship indicated in FIG. 38 and the fact that an item for 1×X 1 (D) does not exist, a column related to X 1 in the vector for the second row in FIG. 39 is “0”. Further, based on the relationship indicated in FIG. 38 and the fact that an item for 1×X 2 (D) exists, a column related to X 2 in the vector for the second row in FIG. 39 is “1”. In addition, based on the relationship indicated in FIG. 38 and the fact that an item for 1×P 1 (D) may or may not exist but an item for 1×P 2 (D) exists, a column related to P 1 in the vector for the second row in FIG. 39 is “Y”, and a column related to P 2 in the vector for the second row in FIG. 39 is “1”, where Y is either “0” or “1”.

As such, the vector for the second row in FIG. 39 is “01Y1”, as indicated by 3900 - 2 in FIG. 39 .

The parity check polynomials at time point j=2 are parity check polynomials when i=0 in expression (132-1-1), (132-1-2), (132-2-1), (132-2-2).

A vector for the third row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (132-1-1) or expression (132-1-2) (refer to FIG. 37 ).

In expression (132-1-1) and (132-1-2):

a term for 1×X 1 (D) does not exist; a term for 1×X 2 (D) exists; and a term for 1×P 1 (D) exists but a term for 1×P 2 (D) does not exist.

Further, the relationship between column numbers and X 1 , X 2 , P 1 , P 2 is as indicated in FIG. 38 . Based on the relationship indicated in FIG. 38 and the fact that an item for 1×X 1 (D) does not exist, a column related to X 1 in the vector for the third row in FIG. 39 is “0”. Further, based on the relationship indicated in FIG. 38 and the fact that an item for 1×X 2 (D) exists, a column related to X 2 in the vector for the third row in FIG. 39 is “1”. In addition, based on the relationship indicated in FIG. 38 and the fact that an item for 1×P 1 (D) exists but an item for 1×P 2 (D) does not exist, a column related to P 1 in the vector for the third row in FIG. 39 is “1”, and a column related to P 2 in the vector for the third row in FIG. 39 is “0”.

As such, the vector for the third row in FIG. 39 is “0110”, as indicated by 3901 - 1 in FIG. 39 .

A vector for the fourth row in FIG. 39 can be generated from a parity check polynomial when i=0 in expression (132-2-1) or expression (132-2-2) (refer to FIG. 37 ).

In expression (132-2-1) and (132-2-2):

a term for 1×X 1 (D) exists; a term for 1×X 2 (D) does not exist; and a term for 1×P 1 (D) may or may not exist but a term for 1×P 2 (D) exists.

Further, the relationship between column numbers and X 1 , X 2 , P 1 , P 2 is as indicated in FIG. 38 . Based on the relationship indicated in FIG. 38 and the fact that an item for 1×X 1 (D) exists, a column related to X 1 in the vector for the fourth row in FIG. 39 is “1”. Further, based on the relationship indicated in FIG. 38 and the fact that an item for 1×X 2 (D) does not exist, a column related to X 2 in the vector for the fourth row in FIG. 39 is “0”. In addition, based on the relationship indicated in FIG. 38 and the fact that an item for 1×P 1 (D) may or may not exist but an item for 1×P 2 (D) exists, a column related to P 1 in the vector for the fourth row in FIG. 39 is “Y”, and a column related to P 2 in the vector for the fourth row in FIG. 39 is “1”.

As such, the vector for the fourth row in FIG. 39 is “10Y1”, as indicated by 3901 - 2 in FIG. 39 .

Because it can be considered that the above similarly applies to cases where time point j=3, 4, 5, the parity check matrix H has the configuration indicated in FIG. 39 .

That is, due to the parity check polynomials of expression (131-1-1), (131-1-2), (131-2-1), (131-2-2) being used at time point j=2k+1 (where k is an integer no smaller than zero), “1010” exists in the 2×(2k+1)−1th row of the parity check matrix H, and “01Y1” exists in the 2×(2k+1)th row of the parity check matrix H, as illustrated in FIG. 39 .

Further, due to the parity check polynomials of expression (132-1-1), (132-1-2), (132-2-1), (132-2-2) being used at time point j=2k+2 (where k is an integer no smaller than zero), “0110” exists in the 2×(2k+2)−1th row of the parity check matrix H, and “10Y1” exists in the 2×(2k+2)th row of the parity check matrix H, as illustrated in FIG. 39 .

Accordingly, as illustrated in FIG. 39 , when denoting a column number of a leftmost column corresponding to “1” in “1010” in a row where “1010” exists (e.g., 3900 - 1 in FIG. 39 ) as “a”, “0110” (e.g., 3901 - 1 in FIG. 39 ) exists in a row that is two rows below the row where “1010” exists, starting from column “a+4”.

Similarly, as illustrated in FIG. 39 , when denoting a column number of a leftmost column corresponding to “1” in “01Y1” in a row where “01Y1” exists (e.g., 3900 - 2 in FIG. 39 ) as “b”, “10Y1” (e.g., 3901 - 2 in FIG. 39 ) exists in a row that is two rows below the row where “01Y1” exists, starting from column “b+4”.

Similarly, as illustrated in FIG. 39 , when denoting a column number of a leftmost column corresponding to “1” in “0110” in a row where “0110” exists (e.g., 3901 - 1 in FIG. 39 ) as “c”, “1010” (e.g., 3902 - 1 in FIG. 39 ) exists in a row that is two rows below the row where “0110” exists, starting from column “c+4”.

Similarly, as illustrated in FIG. 39 , when denoting a column number of a leftmost column corresponding to “1” in “10Y1” in a row where “10Y1” exists (e.g., 3901 - 2 in FIG. 39 ) as “d”, “01Y1” (e.g., 3902 - 2 in FIG. 39 ) exists in a row that is two rows below the row where “0110” exists, starting from column “d+4”.

The following describes a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial when tail-biting is not performed, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

In the following, H com [u][v] (where u and v are integers no smaller than one) denotes an element at row “u” column “v” of a parity check matrix for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Based on description above provided with reference to FIG. 37 :

“a vector for the 2×g−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g−1)%2m); first expression”; and

“a vector for the (2×g)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((g−1)%2m); second expression” (where g is an integer no smaller than one).

Based on description above provided with reference to FIG. 38 :

“a vector for the 4×(j−1)+1th column of the parity check matrix H is related to X 1 at time point j”;

“a vector for the 4×(j−1)+2th column of the parity check matrix H is related to X 2 at time point j”;

“a vector for the 4×(j−1)+3th column of the parity check matrix H is related to P 1 at time point j”; and

“a vector for the 4×(j−1)+4th column of the parity check matrix H is related to P 2 at time point j” (where j is an integer no smaller than one).

Based on the above, the following describes component H com [2×g−1][v] in row 2×g−1 (where g is an integer no smaller than one) and component H com [2×g][v] in row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

As already described above, a parity check polynomial satisfying zero of #((g−1)%2m); first expression can be used to generate a vector for row 2×g−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Further, a parity check polynomial satisfying zero of #((g−1)%2m); second expression can be used to generate a vector for row 2×g of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Accordingly, when g=2×f−1 (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f−1)−1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (131-1-1) or expression (131-1-2), can be used to generate a vector for row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Further, a parity check polynomial satisfying zero of #(((2×f−1)−1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (131-2-1) or expression (131-2-2), can be used to generate a vector for row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Further, when g=2×f (where f is an integer no smaller than one), a parity check polynomial satisfying zero of #(((2×f)−1)%2m); first expression, or that is, a parity check polynomial satisfying zero of either expression (132-1-1) or expression (132-1-2), can be used to generate a vector for row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Further, a parity check polynomial satisfying zero of #(((2×f)−1)%2m); second expression, or that is, a parity check polynomial satisfying zero of either expression (132-2-1) or expression (132-2-2), can be used to generate a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Accordingly, (1) when g=2×f−1 (where f is an integer no smaller than one), when a vector for row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-1-1), (2×f−1)−1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-1-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g−1][v]=H com [2×(2×f−1)−1][v] in row 2×g−1, or that is, row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, w=1.

[Math. 133]

H com [2×(2× f− 1)−1][4×((2× f− 1)−0−1)+ w ]=1  (133-1)

When y is an integer no smaller than one and no greater than R #(2c),w , and (2×f−1)−α #(2c),w,y −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−0−1)+ w ]=1  (133-2)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0, and u≠(2×f−1)−α #(2c),w,y } (where y is an integer no smaller than one and no greater than R #(2c),w );

H com [2×(2× f− 1)−1][4×( u− 1)+ w ]=0  (133-3)

The following holds true for X 2 . In the following, z=2, and y is an integer no smaller than R #(2c),z +1 and no greater than r #(2c),z .

[Math. 134]

When (2×f−1)−α #(2c),z,y −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−α #(2c),z,y −1)+ z ]  (134-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−α #(2c),z,y } (where y is an integer no smaller than R #(2c),z +1 and no smaller than r #(2c),z );

H com [2×(2× f− 1)−1][4×( u− 1)+ z ]=0  (134-2)

The following holds true for P 1 .

[Math. 135]

H com [2×(2× f− 1)−1][4×((2× f− 1)−0−1)+3]=1  (135-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0};

H com [2×(2× f− 1)−1][4×( u− 1)+3]=0  (135-2)

The following holds true for P 2 .

[Math. 136]

When (2×f−1)−β #(2c),0 −1≥0:

H com [2×(2× f− 1)−1][4×((2× f )−β #(2c),0 −1)+4]=1  (136-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−β #(2c),0 };

H com [2×(2× f− 1)−1][4×( u− 1)+4]=0  (136-2)

Further, (2) when g=2×f−1 (where f is an integer no smaller than one), when a vector for row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-1-2), ((2×f−1)−1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-1-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g−1][v]=H com [2×(2×f−1)−1][v] in row 2×g−1, or that is, row 2×(2×f−1)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, w=1.

[Math. 137]

H com [2×(2× f− 1)−1][4×((2× f− 1)−0−1)+ w ]=1  (137-1)

When y is an integer no smaller than one and no greater than R #(2c),w , and (2×f−1)−α #(2c),w,y −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−α #(2c),w,y −1)+ w ]=1  (137-2)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0 and u≠(2×f−1)−α #(2c),w,y } (where y is an integer no smaller than one and no greater than R #(2c),w );

H com [2×(2× f− 1)−1][4×( u− 1)+ w ]=0  (137-3)

The following holds true for X 2 . In the following, z=2, and y is an integer no smaller than R #(2c),z +1 and no greater than r #(2c),z .

[Math. 138]

When (2×f−1)−α #(2c),z,y −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−α #(2c),z,y −1)+ z ]=1  (138-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−α #(2c),z,y } (where y is an integer no smaller than R #(2c),z +1 and no greater than r #(2c),z );

H com [2×(2× f− 1)−1][4×( u− 1)+ z ]=0  (138-2)

The following holds true for P 1 .

[Math. 139]

H com [2×(2× f− 1)−1][4×((2× f− 1)−0−1)+3]=1  (139-1)

When (2×f−1)−β #(2c),1 −1≥0:

H com [2×(2× f− 1)−1][4×((2× f− 1)−β #(2c),1 −1)+3]=1  (139-2)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0 and u≠(2×f−1)−β #(2c),1 };

H com [2×(2× f− 1)−1][4×( u− 1)+3]=0  (139-3)

The following holds true for P 2 .

[Math. 140]

For all u being an integer no smaller than one;

H com [2×(2× f− 1)−1][4×( u− 1)+4]=0  (140)

Further, (3) when g=2×f−1 (where f is an integer no smaller than one), when a vector for row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-2-1), (2×f−1)−1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-2-1) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g][v]=H com [2×(2×f−1)][v] in row 2×g, or that is, row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, z=1, and y is an integer no smaller than R #(2c),z +1 and no greater than r #(2c),z .

[Math. 141]

When (2×f−1)−α #(2c),z,y −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),z,y −1)+ z ]=1  (141-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−α #(2c),z,y } (where y is an integer no smaller than R #(2c),z +1 and no greater than r #(2c),z ;

H com [2×(2× f− 1)][4×( u− 1)+ z ]=0  (141-2)

The following holds true for X 2 . In the following, w=2.

[Math. 142]

H com [2×(2× f− 1)][4×((2× f− 1)−0−1)+ w ]=1  (142-1)

When y is an integer no smaller than one and no greater than R #(2c),w , and (2×f−1)−α #(2c),w,y −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),w,y −1)+ w ]=1  (142-2)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0 and u≠(2×f−1)−α #(2c),w,y } (where y is an integer no smaller than one and no greater than R #(2c),w );

H com [2×(2× f− 1)][4×( u− 1)+ w ]=0  (142-3)

The following holds true for P 1 .

[Math. 143]

When (2×f−1)−β #(2c),2 −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−β #(2c),2 −1)+3]=1  (143-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−β #(2c),2 };

H com [2×(2× f− 1)][4×( u− 1)+3]=0  (143-2)

The following holds true for P 2 .

[Math. 144]

H com [2×(2× f− 1)][4×((2× f− 1)−0−1)+4]=1  (144-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0};

H com [2×(2× f− 1)][4×( u− 1)+4]=0  (144-2)

Further, (4) when g=2×f−1 (where f is an integer no smaller than one), when a vector for row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (131-2-2), (2×f−1)−1)%2m=2c holds true. Accordingly, a parity check polynomial satisfying zero of expression (131-2-2) where 2i=2c holds true (where c is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g][v]=H com [2×(2×f−1)][v] in row 2×g, or that is, row 2×(2×f−1) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, z=1, and y is an integer no smaller than R #(2c),z +1 and no greater than r #(2c),z .

[Math. 145]

When (2×f−1)−α #(2c),z,y −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),z,y −1)+ z ]=1  (145-1)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−α #(2c),z,y } (where y is an integer no smaller than R #(2c),z +1 and no greater than r #(2c),z );

H com [2×(2× f− 1)][4×( u− 1)+ z ]=0  (145-2)

The following holds true for X 2 . In the following, w=2.

[Math. 146]

H com [2×(2× f− 1)][4×((2× f− 1)−0−1)+ w ]=1  (146-1)

When y is an integer no smaller than one and no greater than R #(2c),w , and (2×f−1)−α #(2c),w,y −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−α #(2c),w,y −1)+ w ]=1  (146-2)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0} and u≠(2×f−1)−α #(2c),w,y } (where y is an integer no smaller than one and no greater than R #(2c),w );

H com [2×(2× f− 1)][4×( u− 1)+ w ]=0  (146-3)

The following holds true for P 1 .

[Math. 147]

For all u being an integer no smaller than one;

H com [2×(2× f− 1)][4×( u− 1)+3]=0  (147)

The following holds true for P 2 .

[Math. 114]

H com [2×(2× f− 1)][4×((2× f− 1)−0−1)+4]=1  (148-1)

When (2×f−1)−β #(2c),3 −1≥0:

H com [2×(2× f− 1)][4×((2× f− 1)−β #(2c),3 −1)+4]=1  (148-2)

For all u being an integer no smaller than one satisfying {u≠(2×f−1)−0 and u≠(2×f−1)−β #(2c),3 };

H com [2×(2× f− 1)][4×( u− 1)+4]=0  (148-3)

Further, (5) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-1-1), ((2×f)−1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-1-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g−1][v]=H 0 [2×(2×f)−1][v] in row 2×g−1, or that is, row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, z=1, and y is an integer no smaller than R #(2d+1),z +1 and no greater than r #(2d+1),z .

[Math. 149]

When (2×f)−α #(2d+1),z,y −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),z,y −1)+ z ]=1  (149-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−α #(2d+1),z,y } (where y is an integer no smaller than R #(2d+1),z +1 and no greater than r #(2d+1),z );

H com [2×(2× f )−1][4×( u− 1)+ z ]=0  (149-2)

The following holds true for X 2 . In the following, w=2.

[Math. 150]

H com [2×(2× f )−1][4×((2× f )−0−1)+ w ]=1  (150-1)

When y is an integer no smaller than one and no greater than R #(2d+1),w , and (2×f)−α #(2d+1),w,y −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),w,y −1)+ w ]=1  (150-2)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0} and {u≠(2×f)−α #(2d+1),w,y } (where y is an integer no smaller than one and no greater than R #(2d+1),w );

H com [2×(2× f )−1][4×( u− 1)+ w ]=0  (150-3)

The following holds true for P 1 .

[Math. 151]

H com [2×(2× f )−1][4×((2× f )−0−1)+3]=1  (151-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0};

H com [2×(2× f )−1][4×( u− 1)+3]=0  (151-2)

The following holds true for P 2 .

[Math. 152]

When (2×f)−β #(2d+1),0 −1≥0:

H com [2×(2× f )−1][4×((2× f )−β #(2d+1),0 −1)+4]=1  (152-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−β #(2d+1),0 };

H com [2×(2× f )−1][4×( u− 1)+4]=0  (152-2)

Further, (6) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-1-2), ((2×f)−1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-1-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g−1][v]=H 0 [2×(2×f)−1][v] in row 2×g−1, or that is, row 2×(2×f)−1 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, z=1, and y is an integer no smaller than R #(2d+1),z +1 and no greater than r #(2d+1),z .

[Math. 153]

When (2×f)−α #(2d+1),z,y −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),z,y −1)+ z ]=1  (153-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−α #(2d+1),z,y } (where y is an integer no smaller than R #(2d+1),z +1 and no greater than r #(2d+1),z );

H com [2×(2× f )−1][4×( u− 1)+ z ]=0  (153-2)

The following holds true for X 2 . In the following, w=2.

[Math. 154]

H com [2×(2× f )−1][4×((2× f )−0−1)+ w ]=1  (154-1)

When y is an integer no smaller than one and no greater than R #(2d+1),w , and (2×f)−α #(2d+1),w,y −1≥0:

H com [2×(2× f )−1][4×((2× f )−α #(2d+1),w,1 −1)+ w ]=1  (154-2)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0} and {u≠(2×f)−α #(2d+1),w,y } (where y is an integer no smaller than one and no greater than R #(2d+1),w );

H com [2×(2× f )−1][4×( u− 1)+ w ]=0  (154-3)

The following holds true for P 1 .

[Math. 155]

H com [2×(2× f )−1][4×((2× f )−0−1)+3]=1  (155-1)

When (2×f)−β #(2d+1),1 −1≥0:

H com [2×(2× f )−1][4×((2× f )−β #(2d+1),1 −1)+3]=1  (155-2)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0 and u≠(2×f)−β #(2d+1),1 };

H com [2×(2× f )−1][4×( u− 1)+3]=0  (155-3)

The following holds true for P 2 .

[Math. 156]

For all u being an integer no smaller than one;

H com [2×(2× f )−1][4×( u− 1)+4]=0  (156)

Further, (7) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×0 of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-2-1), ((2×f)−1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-2-1) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g][v]=H com [2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, w=1.

[Math. 157]

H com [2×(2× f )][4×((2× f )−0−1)+ w ]=1  (157-1)

When y is an integer no smaller than one and no greater than R #(2d+1),w , and (2×f)−α #(2d+1),w,y −1≥0:

H com [2×(2× f )][4×((2× f )−α #(2d+1),w,y −1)+ w ]=1  (157-2)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0} and {u≠(2×f)−α #(2d+1),w,y } (where y is an integer no smaller than one and no greater than R #(2d+1),w );

H com [2×(2× f )][4×( u− 1)+ w ]=0  (157-3)

The following holds true for X 2 . In the following, z=2, and y is an integer no smaller than R #(2d+1),z +1 and no greater than r #(2d+1),z .

[Math. 158]

When (2×f)−α #(2d+1),z,y −1≥0:

H com [2×(2× f )][4×((2× f )−α #(2d+1),z,y −1)+ z ]=1  (158-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−α #(2d+1),z,y } (where y is an integer no smaller than R #(2d+1),z +1 and no greater than r #(2d+1),z );

H com [2×(2× f )][4×( u− 1)+ z ]=0  (158-2)

The following holds true for P 1 .

[Math. 159]

When (2×f)−β #(2d+1),2 −1≥0;

H com [2×(2× f )][4×((2× f )−β #(2d+1),2 −1)+3]=1  (159-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−β #(2d+1),2 };

H com [2×(2× f )][4×( u− 1)+3]=0  (159-2)

The following holds true for P 2 .

[Math. 160]

H com [2×(2× f )][4×((2× f )−0−1)+4]=1  (160-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0};

H com [2×(2× f )][4×( u− 1)+4]=0  (160-2)

Further, (8) when g=2×f (where f is an integer no smaller than one), when a vector for row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix H definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, can be generated by using a parity check polynomial satisfying zero provided by expression (132-2-2), ((2×f)−1)%2m=2d+1 holds true. Accordingly, a parity check polynomial satisfying zero of expression (132-2-2) where 2i+1=2d+1 holds true (where d is an integer no smaller than zero and no greater than m−1).

Accordingly, component H com [2×g][v]=H com [2×(2×f)][v] in row 2×g, or that is, row 2×(2×f) of the parity check matrix H, which is for an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial, the parity check matrix definable by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, is expressed as follows.

The following holds true for X 1 . In the following, w=1.

[Math. 161]

H com [2×(2× f )][4×((2× f )−0−1)+ w ]=1  (161-1)

When y is an integer no smaller than one and no greater than R #(2d+1),w , and (2×f)−α #(2d+1),w,y −1≥0:

H com [2×(2× f )][4×((2× f )−α #(2d+1),w,y −1)+ w ]=1  (161-2)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0} and {u≠(2×f)−α #(2d+1),w,y } (where y is an integer no smaller than one and no greater than R #(2d+1),w );

H com [2×(2× f )][4×( u− 1)+ w ]=0  (161-3)

The following holds true for X 2 . In the following, z=2, and y is an integer no smaller than R #(2d+1),z +1 and no greater than r #(2d+1),z .

[Math. 162]

When (2×f)−α #(2d+1),z,y −1≥0:

H com [2×(2× f )][4×((2× f )−α #(2d+1),z,y −1)+ z ]=1  (162-1)

For all u being an integer no smaller than one satisfying {u≠(2×f)−α #(2d+1),z,y } (Where y is an integer no smaller than R #(2d+1),z +1 and no greater than r #(2d+1),z );

H com [2×(2× f )][4×( u− 1)+ z ]=0  (162-2)

The following holds true for P 1 .

[Math. 163]

For all u being an integer no smaller than one;

H com [2×(2× f )][4×( u− 1)+3]=0  (163)

The following holds true for P 2 .

[Math. 164]

H com [2×(2× f )][4×((2× f )−0−1)+4]=1  (164-1)

When (2×f)−β #(2d+1),3 −1≥0:

H com [2×(2× f )][4×((2× f )−β #(2d+1),3 −1)+4]=1  (164-2)

For all u being an integer no smaller than one satisfying {u≠(2×f)−0 and u≠(2×f)−β #(2d+1),3 };

H com [2×(2× f )][4×( u− 1)+4]=0  (164-3)

As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be generated by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression, and the code so generated achieves high error correction capability.

In the present embodiment, description is provided of a device that uses the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

As one example, description is provided of a case where the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, is applied to a communication device.

FIG. 22 illustrates the structures of a transmitting device 2200 and a receiving device 2210 in the communication device pertaining to the present embodiment.

An encoder 2201 receives information to be transmitted as input, and is capable of performing various types of encoding. In particular, when receiving a specification to perform encoding by using the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, the encoder 2201 performs encoding by using the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, to calculate parities P 1 and P 2 . Further, the encoder 2201 outputs the information to be transmitted and the parities P 1 and P 2 as a transmission sequence.

A modulator 2202 receives the transmission sequence, which includes the information to be transmitted and the parities P 1 and P 2 , performs mapping based on a predetermined modulation scheme (e.g., BPSK, QPSK, 16QAM, 64QAM), and outputs a baseband signal. Further, the modulator 2202 may also receive information other than the transmission sequence, which includes the information to be transmitted and the parities P 1 and P 2 , as input, perform mapping, and output a baseband signal. For example, the modulator 2202 may receive control information as input.

The transmitting device outputs a transmission signal after performing predetermined signal processing (e.g., signal processing for generation of an OFDM signal, frequency conversion, amplification) with respect to such signals (e.g., baseband signals, pilot signals). The transmitting device may transmit the transmission signal over a wireless transmission path utilizing electromagnetic waves, or over a wired transmission path utilizing a coaxial cable, a power line, an optical cable, or the like.

The transmission signal is received by the receiving device 2210 after travelling over the transmission path. A receiver 2211 receives a reception signal as input, performs predetermined signal processing (e.g., bandwidth limitation, frequency conversion, signal processing for OFDM, frequency offset estimation, signal detection, channel estimation), and outputs a baseband signal and a channel estimation signal.

A log-likelihood ratio generation section 2212 receives the baseband signal and the channel estimation signal as input (may receive other signals as input), and for example, calculates and outputs a log-likelihood ratio for each bit (may calculate and output a hard value (hard decision value)).

A decoder 2213 receives the log-likelihood ratio for each bit as input, performs belief propagation decoding (e.g., sum-product decoding, scheduled sum-product decoding (Layered BP (belief propagation) decoding), min-sum decoding, Normalized BP decoding, offset BP decoding), and outputs an estimation sequence. The decoder 2213 performs the belief propagation decoding based on the parity check matrix for the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

FIG. 40 illustrates one example of the structure of an encoder for the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2. Description on such an encoder has been provided with reference to the encoder 2201 in FIG. 22 .

In FIG. 40 , an X z computation section 4001 - z (where z is an integer no smaller than one and no greater than two) includes a plurality of shift registers that are connected in series and a calculator that performs XOR calculation on bits collected from some of the shift registers (refer to FIGS. 2 and 22 ).

The X z computation section 4001 - z receives an information bit X z,j at time point j as input, performs the XOR calculation, and outputs bits 4002 - z −1 and 4002 - z −2, which are acquired through the X z calculation.

A P 1 computation section 4004 - 1 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGS. 2 and 22 ).

The P 1 computation section 4004 - 1 receives a bit P 1,j of parity P 1 at time point j as input, performs the XOR calculation, and outputs bits 4005 - 1 - 1 and 4005 - 1 - 2 , which are acquired through the P 1 calculation.

A P 2 computation section 4004 - 2 includes a plurality of shift registers that are connected in series and a calculator that that performs XOR calculation on bits collected from some of the shift registers (refer to FIGS. 2 and 22 ).

The P 2 computation section 4004 - 2 receives a bit P 2,j of parity P 2 at time point j as input, performs the XOR calculation, and outputs bits 4005 - 2 - 1 and 4005 - 2 - 2 , which are acquired through the P 2 calculation.

An XOR (calculator) 4005 - 1 receives the bit 4002 - 1 - 1 acquired by X 1 calculation, the bit 4002 - 2 - 1 acquired by X 2 calculation, the bit 4005 - 1 - 1 acquired by P 1 calculation, and the bit 4005 - 2 - 1 acquired by the P 2 calculation as input, performs XOR calculation, and outputs a bit P 1,j of parity P 1 at time point j.

An XOR (calculator) 4005 - 2 receives the bit 4002 - 1 - 2 acquired by X 1 calculation, the bit 4002 - 2 - 2 acquired by X 2 calculation, the bit 4005 - 1 - 2 acquired by P 1 calculation, and the bit 4005 - 2 - 2 acquired by the P 2 calculation as input, performs XOR calculation, and outputs a bit P 2,j of parity P 2 at time point j.

It is preferable that initial values of the shift registers of the X z computation section 4001 - z , the P 1 computation section 4004 - 1 , and the P 2 computation section 4004 - 2 illustrated in FIG. 40 be set to “0” (zero). By making such a configuration, it becomes unnecessary to transmit to the receiving device parities P 1 and P 2 before the setting of initial values.

The following describes a method of information-zero termination.

Suppose that in FIG. 41 , information X 1 and information X 2 exist from time point 0, and information X 2 at time point s (where s is an integer no smaller than zero) is the last information bit. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information X 1,j and information X 2,j , being information X 1 and information X 2 at time point j, respectively, where j is an integer no smaller than zero and no greater than s.

In such a case, the transmitting device transmits information X 1 , information X 2 , parity P 1 , and parity P 2 from time point 0 to time point s, or that is, transmits X 1,j , P 1,j , P 2,j , where j is an integer no smaller than zero and no greater than s. (Note that P 1,j and P 2,j denote parity P 1 and parity P 2 at time point j, respectively.)

Further, suppose that information X 1 and information X 2 from time point s+1 to time point s+g (where g is an integer no smaller than one) is “0”, or that is, when denoting information X 1 and information X 2 at time point t as X 1,t , X 2,t , respectively, X 1,t =0 and X 2,t =0 hold true for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, by performing encoding, acquires parities P 1,t and P 2,t for t being an integer no smaller than s+1 and no greater than s+g. The transmitting device, in addition to the information and parities described above, transmits parities P 1,t and P 2,t for t being an integer no smaller than s+1 and no greater than s+g.

Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, and log-likelihood ratios corresponding to X 1,t =0 and X 2,t =0 for t being an integer no smaller than s+1 and no greater than s+g, and thereby acquires an estimation sequence of information.

FIG. 42 illustrates an example differing from that illustrated in FIG. 41 . Suppose that information X 1 and information X 2 exist from time point 0, and information X f for time point s (where s is an integer no smaller than zero) is the last information bit. Here, f equals one. In FIG. 41 , f equals 2. That is, suppose that the information to be transmitted from the transmitting device to the receiving device is information X i,s , where i is an integer no smaller than one and no greater than f, and information X 1,j and information X 2,j , being information X 1 and information X 2 at time point j, respectively, where j is an integer no smaller than zero and no greater than s−1.

In such a case, the transmitting device transmits information X 1 , information X 2 , parity P 1 , and parity P 2 from time point 0 to time point s−1, or that is, transmits X 1,j , X 2,j , P 1,j , P 2,j , where j is an integer no smaller than zero and no greater than s−1. (Note that P 1,j and P 2,j denote parity P 1 and parity P 2 at time point j, respectively.)

Further, suppose that at time point s, information X i,s , when i is an integer no smaller than one and no greater than f, is information that the transmitting device is to transmit, and suppose that X k,s , when k is an integer equaling f+1, equals “0” (zero).

Further, suppose that information X 1 and information X 2 from time point s+1 to time point s+g−1 (where g is an integer no smaller than two) is “0”, or that is, when denoting information X 1 and information X 2 at time point t as X 1,t , X 2,t , respectively, X 1,t =0 and X 2,t =0 hold true when t is an integer no smaller than s+1 and no greater than s+g−1. The transmitting device, by performing encoding from time point s to time point s+g−1, acquires parities P 1,u and P 2,u for u being an integer no smaller than s and no greater than s+g−1. The transmitting device, in addition to the information and parities described above, transmits X i,s for i being an integer no smaller than one and no greater than f, and parities P 1,u and P 2,u for u being an integer no smaller than s and no greater than s+g−1.

Meanwhile, the receiving device performs decoding by using log-likelihood ratios for the information and the parities transmitted by the transmitting device, log-likelihood ratios corresponding to X k,s =0 (where k is an integer equaling f+1) and log-likelihood ratios corresponding to X 1,t =0 and X 2,t =0 for t being an integer no smaller than s+1 and no greater than s+g−1, and thereby acquires an estimation sequence of information.

Although description is provided above taking an example where error correction coding is introduced to a communication device, the error correction coding described above is not limited to being introduced to a communication device, and for example, may be introduced to a storage medium (storage). When making such a modification, information that is to be stored to a storage medium (storage) is encoded by using the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, and resultant information and parities are stored to the storage medium (storage). When making such a modification, it is preferable that information-zero termination be introduced as described above and that a data sequence as described above corresponding to a data sequence (information and parities) transmitted by the transmitting device when information-zero termination is applied be stored to the storage medium (storage).

Further, the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2, is applicable to any device that requires error correction coding (e.g., a memory, a hard disk).

In the present embodiment, description is provided of a method of configuring an LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). The LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme described in the present embodiment is based on the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

Patent Literature 2 includes explanation regarding an LDPC-CC of coding rate (n−1)/n (where n is an integer no smaller than two) that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). However, Patent Literature 2 poses a problem for not disclosing an LDPC-CC of a coding rate not satisfying (n−1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

In the present embodiment, as one example of an LDPC-CC of a coding rate not satisfying (n−1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), description is provided of a method of configuring an LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

Although coding rate 2/4 equals coding rate 1/2, the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme pertaining to the present embodiment differs, in terms of generation method, from a conventional LDPC-CC of coding rate (n−1)/n or a conventional LDPC-CC of coding rate (n−1)/n that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

[Periodic Time-Varying LDPC-CC of Coding Rate 2/4 Using Improved Tail-Biting Scheme and Based on Parity Check Polynomial]

The following describes a periodic time-varying LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme and is based on a parity check polynomial, based on the configuration of the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

The following describes a method of configuring an LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial. Such method has already been described in embodiment 2.

First, the following parity check polynomials satisfying zero are prepared.

In expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), i is an integer no smaller than zero and no greater than m−1 (i=0, 1, . . . , m−2, m−1).

In expressions (165-1-1), (165-1-2), (165-2-1), (165-2-2), α #(2i),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r #(2i),p (where r #(2i),p is a natural number)) and β #(2i),0 is a natural number, β #(2i),1 is a natural number, β #(2i),2 is an integer no smaller than zero, and β #(2i),3 is a natural number.

Further, R #(2i),p is a natural number satisfying 1≤R #(2i),p <r #(2i),p .

Further, y is an integer no smaller than one and no greater than r #(2i),p,z is an integer no smaller than one and no greater than r #2i,p , and α #(2i),p,y ≠α #(2i),p,z holds true for ∀ (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r #(2i),p,z is an integer no smaller than one and no greater than r #2i,p , and α #(2i),p,y ≠α #(2i)p,z holds true for all y and all z satisfying y≠z.)

Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (165-1-1) or expression (165-1-2) is referred to as “#(2i); first expression” for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (165-2-1) or expression (165-2-2) is referred to as “#(2i); second expression” for realizing a time-varying period 2m.

Thus, for each i, as #(2i); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (165-1-1) or expression (165-1-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (165-1-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (165-1-2) where i=m−1 is prepared.

Similarly, for each i, as #(2i); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (165-2-1) or expression (165-2-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (165-2-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (165-2-2) where i=m−1 is prepared.

Similarly, the following parity check polynomials satisfying zero are provided.

In expression (166-1-1), (166-1-2), (166-2-1), (166-2-2), i is an integer no smaller than zero and no greater than m−1 (i=0, 1, . . . , m−2, m−1).

In expression (166-1-1), (166-1-2), (166-2-1), (166-2-2), α #(2i+1),p,q (where p is an integer no smaller than one and no greater than two, q is an integer no smaller than one and no greater than r #(2i+1)p (where r #(2i+1),p is a natural number)) and β #(2i+1),0 is a natural number, β #(2i+1),1 is a natural number, β #(2i+1),2 is an integer no smaller than zero, and β #(2i+1),3 is a natural number.

Further, R #(2i+1),p is a natural number satisfying 1≤R #(2i+1),p <r #(2i+1),p .

Further, y is an integer no smaller than one and no greater than r #(2i+1),p , z is an integer no smaller than one and no greater than r #(2i+1),p , and α #(2i+1),p,y ≠α #(2i+1),p,z holds true for ∀ (y, z) where y≠z. ∀ is a universal quantifier. (y is an integer no smaller than one and no greater than r #(2i+1),p ,z is an integer no smaller than one and no greater than r #(2i+1),p , and α #(2i+1),p,y ≠α #(2i+1),p,z holds true for all y and all z satisfying y≠z.)

Note that in the following, to simplify explanation, a parity check polynomial satisfying zero that is expressed by expression (166-1-1) or expression (166-1-2) is referred to as “#(2i+1); first expression” for realizing a time-varying period 2m, and a parity check polynomial satisfying zero that is expressed by expression (166-2-1) or expression (166-2-2) is referred to as “#(2i+1); second expression” for realizing a time-varying period 2m.

Thus, for each i, as #(2i+1); first expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (166-1-1) or expression (166-1-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=0, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=1, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=2, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=z, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (166-1-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (166-1-2) where i=m−1 is prepared.

Similarly, for each i, as #(2i+1); second expression for realizing a time-varying period 2m, a parity check polynomial satisfying zero expressed by either expression (166-2-1) or expression (166-2-2) is prepared.

That is, for i=0, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=0, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=0 is prepared.

Similarly:

for i=1, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=1, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=1 is prepared;

for i=2, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=2, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=2 is prepared;

for i=z, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=z, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=z is prepared (where z is an integer no smaller than zero and no greater than m−1); and

for i=m−1, a parity check polynomial satisfying zero provided by expression (166-2-1) where i=m−1, or a parity check polynomial satisfying zero provided by expression (166-2-2) where i=m−1 is prepared.

As such, an LDPC-CC of coding rate 2/4 and time-varying period 2×m that is based on a parity check polynomial can be defined by using a total of 4×m parity check polynomials satisfying zero, which include an m number of parity check polynomials satisfying zero of #(2i); first expression, an m number of parity check polynomials satisfying zero of #(2i); second expression, an m number of parity check polynomials satisfying zero of #(2i+1); first expression, and an m number of parity check polynomials satisfying zero of #(2i+1); second expression.

Here, m is an integer no smaller than one. Further, different parity check polynomials are to be prepared, so that the time varying period 2×m is formed by a 4×m number of parity check polynomials satisfying zero including parity check polynomials satisfying zero provided by expression (165-1-1) or expression (165-1-2), parity check polynomials satisfying zero provided by expression (165-2-1) or expression (165-2-2), parity check polynomials satisfying zero provided by expression (166-1-1) or expression (166-1-2), and parity check polynomials satisfying zero provided by expression (166-2-1) or expression (166-2-2).

For example, the time varying period 2×m is formed by preparing a 4×m number of different parity check polynomials satisfying zero.

Meanwhile, even if the 4×m number of parity check polynomials satisfying zero include a same parity check polynomial in plurality, the time-varying period 2×m can be formed by configuring the arrangement of the parity check polynomials.

The following describes the relationship between time point j and expression (165-1-1), (165-1-2), (165-2-1), (165-2-2), (166-1-1), (166-1-2), (166-2-1), and (166-2-2) (where j is an integer no smaller than zero).

The following presumes that 2k=j%2m holds true. In the following, % means a modulo, and for example, α%6 represents a remainder after dividing α by 6. (Accordingly, k is integer no smaller than zero and no greater than m−1).

Accordingly, at time point j, #(2k); first expression and #(2k); second expression, which are respectively acquired by setting i=k in #(2i); first expression and #(2i); second expression, hold true.

Further, when 2h+1=j%2m holds true (accordingly, h is an integer no smaller than zero and no greater than m−1), at time point j, #(2h+1); first expression and #(2h+1); second expression, which are respectively acquired by setting i=h in #(2i+1); first expression and #(2i+1); second expression, hold true.

Note that in the parity check polynomials satisfying zero of expression (165-1-1), (165-1-2), (165-2-1), (165-2-2), (166-1-1), (166-1-2), (166-2-1), and (166-2-2), a sum of the number of terms of P 1 (D) and the number of terms of P 2 (D) equals two. This realizes sequentially finding parities P 1 and P 2 when applying an improved tail-biting scheme, and thus, is a significant factor realizing a reduction in computation amount (circuit scale).

The following describes the relationship between the time-varying period of the parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2 and on which the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, and block size in the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) proposed in the present embodiment.

Regarding this point, in order to achieve error correction capability of even higher level, a configuration is preferable where a Tanner graph formed by the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2 and on which the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, resembles a Tanner graph of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). Thus, the following conditions are significant.

<Condition #N1>

The number of rows in a parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 4×m.

Accordingly, the number of columns in the parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is a multiple of 4×2×m. According to this condition, (for example) a log-likelihood ratio that is necessary in decoding is a log-likelihood ratio of the number of columns in the parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

Note that the relationship between the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2 and on which the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based, is described in detail later in the present disclosure.

Thus, when denoting the parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as H pro , the number of columns of H pro can be expressed as 4×2×m×z (where z is a natural number).

Accordingly, a transmission sequence (encoded sequence (codeword)) v s of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as v s =(X s,1,1 , X s,2,1 , P pro s,1,1 , P pro s,2,1 , X s,1,2 , X s,2,2 , P pro s,1,2 , P pro s,2,2 , . . . , X s,1,k , X s,2,1 , P pro s,1,k , P pro s,2,k , . . . , X s,1,2×m×z , X s,2,2×m×z , P pro s,1,2×m×z , P pro s,2,2×m×z ) T =(λ pro,s,1 , λ pro,s,2 , . . . , λ pro,s,2×m×z−1 , λ pro,s,2×m×z ) T (where k=1, 2, . . . , 2×m×z−1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and H pro v s =0 holds true (here, H pro v s =0 indicates that all elements of the vector H pro v s are zeroes).

X s,j,k (where j is an integer no smaller than one and no greater than two) is a bit of information X j , P pro s,1,k is a bit of parity P 1 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and P pro s,2,k is a bit of parity P 2 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

Further, λ s,2,k =(X s,1,k , X s,2,k , P pro s,1,k , P pro s,2,k ) holds true.

In addition, the number of rows in the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

It has been indicated above that the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is based on the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2. This is explained in the following.

First, consideration is made of a parity check matrix when configuring a periodic time-varying LDPC-CC using tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which has been provided in embodiments 1 and 2.

FIG. 43 illustrates a configuration of a parity check matrix H when configuring a periodic time-varying LDPC-CC using tail-biting by performing tail-biting by using only parity check polynomials satisfying zero for an LDPC-CC of coding rate 2/4 and time-varying period 2m.

Since Condition #N1 is satisfied in FIG. 43 , the number of rows of the parity check matrix is m×z and the number of columns of the parity check matrix is 4×2×m×z.

As illustrated in FIG. 43 :

“a vector for the first row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression”;

“a vector for the second row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression”;

“a vector for the third row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression”;

“a vector for the fourth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression”;

“a vector for the 2×(2m−1)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−2); first expression”;

“a vector for the 2×(2m−1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−2); second expression”;

“a vector for the 2×(2m)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−1); first expression”;

“a vector for the 2×(2m)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−1); second expression”;

“a vector for the 2×(2m+1)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; first expression”;

“a vector for the 2×(2m+1)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #0; second expression”;

“a vector for the 2×(2m+2)−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; first expression”;

“a vector for the 2×(2m+2)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #1; second expression”;

“a vector for the 2×i−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i−1)%2m); first expression”;

“a vector for the (2×i)th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #((i−1)%2m); second expression” (where i is an integer no smaller than one and no greater than 2×m×z);

“a vector for the 2×(2m−1)×z−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−2); first expression”;

“a vector for the 2×(2m−1)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−2); second expression”;

“a vector for the 2×(2m)×z−1th row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−1); first expression”; and

“a vector for the 2×(2m)×zth row of the parity check matrix H can be generated from a parity check polynomial satisfying zero of #(2m−1); second expression”.

To prepare for the explanation to be provided in the following, a mathematical expression is provided of the parity check matrix H in FIG. 43 , which is a parity check matrix when configuring a periodic time-varying LDPC-CC by performing tail-biting by using only parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 and time-varying period 2m that is based on a parity check polynomial, description of which is provided in embodiments 1 and 2. When denoting a vector having one row and 4×2×m×z columns in row k of the parity check matrix H as h k , the parity check matrix H in FIG. 43 is expressed as follows.

The following describes a parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

FIG. 44 illustrates one example of a configuration of a parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

The parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) satisfies Condition #N1.

When denoting a vector having one row and 4×2×m×z columns in row k of the parity check matrix H pro in FIG. 44 , which is for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), as g k , the parity check matrix H pro in FIG. 44 is expressed as follows.

A transmission sequence (encoded sequence (codeword)) v s of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as v s =(X s,1,1 , X s,2,1 , P pro s,1,1 , P pro s,2,1 , X s,1,2 , X s,2,2 , P pro s,1,2 , P pro s,2,2 , . . . , X s,1,k , X s,2,1 , P pro s,1,k , P pro s,2,k , . . . , X s,1,2×m×z , X s,2,2×m×z , P pro s,1,2×m×z , P pro s,2,2×m×z ) T =(λ pro,s,1 , λ pro,s,2 , . . . , λ pro,s,2×m×z−1 , λ pro,s,2×m×z ) T (where k=1, 2, . . . , 2×m×z−1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and H pro v s =0 holds true (here, H pro v s =0 indicates that all elements of the vector H pro v s are zeroes).

X s,j,k (where j is an integer no smaller than one and no greater than two) is a bit of information X j , P pro s,1,k is a bit of parity P 1 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and P pro s,2,k is a bit of parity P 2 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

In the parity check matrix H pro in FIG. 44 , which illustrates one example of a configuration of a parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), rows other than row one, or that is, rows between row two to row 2×(2×m)×z in the parity check matrix H pro in FIG. 44 , have the same configuration as rows between row two and row 2×(2×m)×z in the parity check matrix H in FIG. 43 (refer to FIGS. 43 and 44 ). Accordingly, FIG. 44 includes an indication of #0′; first expression at 4401 in the first row. (This point is explained later in the present disclosure.) Accordingly, the following relational expression holds true based on expression 167 and 168.

[Math. 169]

For all i no smaller than two and no greater than 2×(2×m)×z, the following holds true:

g i =h i   (169)

Further, the following holds true when i=1.

[Math. 170]

g 1 ≠h 1   (170)

Accordingly, the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as follows.

In expression 171, expression 170 holds true.

Next, explanation is provided of a method of configuring g 1 in expression 171 so that parities can be found sequentially and high error correction capability can be achieved.

One example of a method of configuring g 1 in expression 171, so that parities can be found sequentially and high error correction capability can be achieved, is using a parity check polynomial satisfying zero of #0; first expression of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), which serves as the basis.

Since g 1 is row one of the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), g 1 is generated from a parity check polynomial satisfying zero that is obtained by transforming a parity check polynomial satisfying zero of #0; first expression. As described above, a parity check polynomial satisfying zero of #0; first expression is expressed by either expression (172-1-1) or expression (172-1-2).

As one example of a parity check polynomial satisfying zero for generating vector g 1 in row one of the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), a parity check polynomial satisfying zero of #0; first expression is expressed as follows, for either expression (172-1-1) or expression (172-1-2).

Accordingly, vector g 1 is a vector having one row and 4×2×m×z columns that is obtained by performing tail-biting with respect to expression 173.

Note that in the following, a parity check polynomial that satisfies zero provided by expression 173 is referred to as #0′; first expression.

Accordingly, row one of the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be obtained by transforming #0′; first expression of expression 173 (that is, a vector g 1 corresponding to one row and 4×2×m×z columns can be obtained).

A transmission sequence (encoded sequence (codeword)) v s of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is v s =(X s,1,1 , X s,2,1 , P pro s,1,1 , P pro s,2,1 , X s,1,2 , X s,2,2 , P pro s,1,2 , P pro s,2,2 , . . . , X s,1,k , X s,2,1 , P pro s,1,k , P pro s,2,k , . . . , X s,1,2×m×z , X s,2,2×m×z , P pro s,1,2×m×z , P pro s,2,2×m×z ) T =(λ pro,s,1 , λ pro,s,2 , . . . , λ pro,s,2×m×z−1 , λ pro,s,2×m×z ) T , and the number of parity check polynomials satisfying zero necessary for obtaining this transmission sequence is 2×(2×m)×z.

Here, when arranging such 2×(2×m)×z number of parity check polynomials satisfying zero in order, a parity check polynomial satisfying zero appearing eth is referred to in the following as an “eth parity check polynomial satisfying zero” (where e is an integer no smaller than zero and no greater than 2×(2×m)×z−1).

As such, the parity check polynomials satisfying zero are arranged in the following order:

zeroth: zeroth parity check polynomial satisfying zero;

first: first parity check polynomial satisfying zero;

second: second parity check polynomial satisfying zero;

eth: eth parity check polynomial satisfying zero;

2×(2×m)×z−2th: 2×(2×m)×z−2th parity check polynomial satisfying zero; and

2×(2×m)×z−1th: 2×(2×m)×z−1th parity check polynomial satisfying zero.

Accordingly, the transmission sequence (encoded sequence (codeword)) v s of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is obtained. (As can be seen from description provided above, when expressing the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as provided in expression 168, a vector composed of row e+1 of the parity check matrix H pro corresponds to the eth parity check polynomial satisfying zero.)

Accordingly, in the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC):

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0′; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the second parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the third parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m−1)−2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m−2); first expression;

the 2×(2m−1)−1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m−2); second expression;

the 2×(2m)−2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m−1); first expression;

the 2×(2m)−1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m−1); second expression;

the 2×(2m+1)−2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; first expression;

the 2×(2m+1)−1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×(2m+2)−2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; first expression;

the 2×(2m+2)−1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #1; second expression;

the 2×(2m−1)×z−2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m−2); first expression;

the 2×(2m−1)×z−1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m−2); second expression;

the 2×(2m)×z−2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m−1); first expression; and

the 2×(2m)×z−1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #(2m−1); second expression.

That is,

the 0th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0′; first expression provided by expression 173;

the first parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #0; second expression;

the 2×i−2th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i−1)%2m); first expression; and

the 2×i−1th parity check polynomial satisfying zero is a parity check polynomial satisfying zero of #((i−1)%2m); second expression (where i is an integer no smaller than two and no greater than 2×m×z).

As description has been provided above, the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), at the same time as achieving high error correction capability, enables finding multiple parities sequentially, and therefore, achieves an advantageous effect of reducing circuit scale of an encoder.

In the following, explanation is provided of what is meant by “finding parities sequentially”.

In the example described above, since bits of information X 1 and information X 2 are pre-acquired, P pro s,1,1 can be calculated by using the 0th parity check polynomial satisfying zero of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), or that is, by using the parity check polynomial satisfying zero of #0′; first expression provided by expression 173.

Then, from the bits of information X 1 and information X 2 and P pro s,1,1 , another parity (denoted as P c=1 ) can be calculated by using another parity check polynomial satisfying zero.

Further, from the bits of information X 1 and information X 2 and P c=1 , another parity (denoted as P c=2 ) can be calculated by using another parity check polynomial satisfying zero.

By repeating such operation, from the bits of information X 1 and information X 2 and P c=h , another parity (denoted as P c=h+1 ) can be calculated by using a given parity check polynomial satisfying zero.

This is referred to as “finding parities sequentially”, and when parities can be found sequentially, multiple parities can be obtained without calculation of complex simultaneous equations, whereby an advantageous effect is achieved of reducing circuit scale (computation amount) of an encoder.

Next, explanation is provided of configurations and operations of an encoder and a decoder for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

In the following, one example case is considered where the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is used in a communication system. When applying the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) to a communication system, the encoder and the decoder for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) are characterized for each being configured and each operating based on the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship H pro v s =0.

The following provides explanation while referring to FIG. 25 , which is an overall diagram of a communication system. An encoder 2511 of a transmitting device 2501 receives an information sequence of block s (X s,1,1 , X s,2,1 , X s,1,2 , X s,2,2 , . . . , X s,1,k , X s,2,k , . . . , X s,1,2×m×z , X s,2,2×m×z ) as input. The encoder 2511 performs encoding based on the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) and based on the relationship H pro v s =0. The encoder 2511 generates a transmission sequence (encoded sequence (codeword)) v s of block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), denoted as v s =(X s,1,1 , X s,2,1 , P pro s,1,1 , P pro s,2,1 , X s,1,2 , X s,2,2 , P pro s,1,2 , P pro s,2,2 , . . . , X s,1,k , X s,2,1 , P pro s,1,k , P pro s,2,k , . . . , X s,1,2×m×z , X s,2,2×m×z , P pro s,1,2×m×z , P pro s,2,2×m×z ) T , and outputs the transmission sequence v s . As already described above, the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is characterized for enabling parities to be found sequentially.

A decoder 2523 of a receiving device 2520 in FIG. 25 receives, as input, a log-likelihood ratio of each bit of, for example, the transmission sequence v s =(X s,1,1 , X s,2,1 , P pro s,1,1 , P pro s,2,1 , X s,1,2 , X s,2,2 , P pro s,1,2 , P pro s,2,2 , . . . , X s,1,k , X s,2,1 , P pro s,1,k , P pro s,2,k , . . . , X s,1,2×m×z , X s,2,2×m×z , P pro s,1,2×m×z , P pro s,2,2×m×z ) T . The log-likelihood ratios are output from a log-likelihood ratio generator 2522 . The decoder 2523 performs decoding for an LDPC code according to the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC). For example, the decoding may be decoding disclosed in Non-Patent Literature 4, Non-Patent Literature 6, Non-Patent Literature 7, Non-Patent Literature 8, etc., i.e., simple BP decoding such as min-sum decoding, offset BP decoding, or Normalized BP decoding, or Belief Propagation (BP) decoding in which scheduling is performed with respect to the row operations (Horizontal operations) and the column operations (Vertical operations) such as Shuffled BP decoding or Layered BP decoding. The decoding may also be decoding such as bit-flipping decoding disclosed in Non-Patent Literature 17, for example. The decoder 2523 obtains an estimation transmission sequence (estimation encoded sequence) (reception sequence) of block s through the decoding, and outputs the estimation transmission sequence.

In the above, explanation is provided on operations of the encoder and the decoder in a communication system as one example. Alternatively, the encoder and the decoder may be used in technical fields related to storages, memories, etc.

The following describes a specific example of a configuration of a parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

When denoting the parity check matrix for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) as H pro as described above, the number of columns of H pro can be expressed as 4×2×m×z (where z is a natural number). (Note that m denotes a time-varying period of the LDPC-CC of coding rate 2/4 that is based on a parity check polynomial, which serves as the basis.)

Accordingly, as already described above, a transmission sequence (encoded sequence (codeword)) v s composed of a 4×2×m×z number of bits in block s of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) can be expressed as v s =(X s,1,1 , X s,2,1 , P pro s,1,1 , P pro s,2,1 , X s,1,2 , X s,2,2 , P pro s,1,2 , P pro s,2,2 , . . . , X s,1,k , X s,2,1 , P pro s,1,k , P pro s,2,k , . . . , X s,1,2×m×z , X s,2,2×m×z , P pro s,1,2×m×z , P pro s,2,2×m×z ) T =(λ pro,s,1 , λ pro,s,2 , . . . , λ pro,s,2×m×z−1 , λ pro,s,2×m×z ) T , (where k=1, 2, . . . , 2×m×z−1, 2×m×z (i.e., k is an integer no smaller than one and no greater than 2×m×z)), and H pro v s =0 holds true (here, H pro v s =0 indicates that all elements of the vector H pro v s are zeroes).

X s,j,k (where j is an integer no smaller than one and no greater than two) is a bit of information X j , P pro s,1,k is a bit of parity P 1 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC), and P pro s,2,k is a bit of parity P 2 of the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC).

Further, λ pro,s,k =(X s,1,k , X s,2,k , P pro s,1,k , P pro s,2,k ) holds true.

In addition, the number of rows in the parity check matrix H pro for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) is 4×m×z.

Note that the method of configuring parity check polynomials satisfying zero for the LDPC-CC of coding rate 2/4 that uses an improved tail-biting scheme (an LDPC block code using an LDPC-CC) has already been described above.

In the above, description has been provided of a parity check matrix H pro for the LDPC-CC of coding rate 2/4 that