Coupling circuits with capacitors

1. Field of the Invention

The present invention relates to a network filtering circuit, and more particularly to a preferable Electromagnetic Compatibility (EMC) and impedance matching circuit network.

2. Description of Related Arts

Chinese Patent No. CN204733134U issued on Dec. 25, 2013, discloses a network filtering circuit including a cable side, a physical side, and a plurality of differential pair transmission channels connected therebetween. Each of the transmission channels includes a CMC (Common Mode Choke) and two Y type capacitors. Each differential pair transmission channel includes a first transmission line and a second transmission line with the aforementioned two Y type capacitors respectively connected within the first transmission line and the second transmission line in series connection. The CMC includes a first coil and a second coil coupled with each other wherein the CMC is closer to the physical side while the two Y type capacitors are closer to the cable side and directly directed to the ground node. The Electro Magnetic Interference (EMI) is derived from the ground line which performs reference potential, If the ground line is improperly designed, the ground potential will be unstable that have the whole network circuits malfunction. The ground line is used for stabilizing the ground potential, thus eliminating the interference. The prior art shows the Y type capacitor is directly linked to the ground node, thus having the first transmission line and the second transmission line tend to receive the EMI from the ground node and affecting the signal transmission.

Accordingly, an object of the present invention is to provide network filtering circuit with preferable Electro Magnetic compatibility and impedance matching. The invention includes a cable side for connection with a network cable, a physical side for connection with a mother board, and a plurality of differential pair transmission channels connected between the cable side and the physical side. Each of the transmission channels includes a first transmission line, the second transmission line, two first capacitors linked between the first transmission line and the second transmission line in series connection with a middle line linked to a position of a connection line between these two first capacitors wherein a resistor has one end linked to the middle line and the other end eventually linked to a ground node.

Accordingly, another object of the present invention is to provide network filtering circuit with preferable Electro Magnetic compatibility and impedance matching. The invention includes a cable side for connection with a network cable, a physical side for connection with a mother board, and a plurality of differential pair transmission channels connected between the cable side and the physical side. Each of the transmission channels includes a first transmission line and a second transmission line with a CMC and two coupling capacitors connected thereto in series connection wherein the CMC includes a first coil and a second coil respectively connected to the first transmission line and the second transmission line, the CMC is closer to the physical side while and the two coupling capacitors are closer to the cable side. The network circuit further includes two filtering (Y type) capacitors linked between the first transmission line and the second transmission line, a middle line connected between the two filtering capacitors and having an extension line wherein in such an extension line there are a resistor and an optional adjusting capacitor to a ground node at the end in series connection.

Compared with the prior arts, the invention provides the middle line with an additional resistor before reaching the ground node so as to achieved an efficient grounding effect and the better EMC and corresponding impedance matching.

Other objects, advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

FIG. 1 is a network filtering circuit according to the invention.

Reference will now be made in detail to some preferred embodiments of the present invention.

Referring to FIG. 1 , a network filtering circuit 100 according to the invention. The network filtering circuit 100 includes a cable side 10 for connection with a network cable, a physical side 30 for connection with a mother board, and a plurality of transmission channels 20 connected between the cable side 10 and the physical side 30 .

Each of the transmission channels 60 includes a first (differential) transmission line 201 , the second (differential) transmission line 202 , and a CMC 40 and two filtering/first capacitors 60 linked, in series connection, between the first transmission line 201 and the second transmission line 202 . The CMC 40 includes a first coil 401 and a second coil 402 coupled with each other and respectively connected with the corresponding first transmission line 201 and the second transmission line 202 . Two coupling/second capacitors 50 are respectively connected with the corresponding first transmission line 201 and the second transmission line 202 and linked to the corresponding first coil 401 and second coil 402 in series connection. Notably, the CMC is closer to the physical side while the second capacitors 50 are closer to the cable side 10 .

A middle line 601 is between the two first capacitors 60 with an extension line (not labeled), and in such an extension line there are a resistor 70 and an adjusting/third capacitor 80 and a ground node 90 at the end in series connection sequentially wherein the resistor 70 is connected between the middle line 601 and the third capacitor 80 .

Notably, the second capacitors 50 are located between the CMC and the first capacitors 40 . Each of the first transmission line 201 and the second transmission line 202 further includes a fourth capacitor 95 located between the CMC and the corresponding second capacitor 50 , and is further directly connected to another ground node 90 . Under this arrangement, the first capacitor 60 and the fourth capacitor 95 are respectively linked to two opposite ends of the corresponding second capacitor 50 . In this design, the resistor 70 is of 75Ω, the third capacitor 80 is of 1000 pF.

Compared with the prior arts, the invention provides the middle line 601 with an additional resistor 70 and an optional third capacitor 80 before reaching the ground node 90 so as to achieve an efficient grounding effect and the better EMC and corresponding impedance matching.

It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.