Electronic device, electronic device fabrication method, and electronic apparatus

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-253364, filed on Dec. 25, 2015, the entire contents of which are incorporated herein by reference.

The embodiments discussed herein are related to an electronic device, an electronic device fabrication method, and an electronic apparatus.

The technique of stacking a plurality of semiconductor chips is known. In respect to this technique, for example, the following method is known. A lower-layer semiconductor chip is sucked and held on a suction stage and a group of bumps formed over an under surface of an upper-layer semiconductor chip sucked and held by a bonding tool are bonded to a group of bumps formed over an upper surface of the lower-layer semiconductor chip by thermocompression bonding or the like.

Japanese Laid-open Patent Publication No. 2012-089579

There may be a concavity in a surface of a semiconductor chip opposite to a surface over which a group of bumps are formed because of, for example, variation in the thickness of semiconductor substrates which occurs in a manufacturing process. When this semiconductor chip is bonded to another semiconductor chip, the surface in which the concavity is formed is sucked and held. At this time the concavity is sucked. As a result, the semiconductor chip deforms. This may lead to variation in height in the group of bumps formed over the opposite surface. If such variation in height occurs in a group of bumps of one of two semiconductor chips to be bonded together, a bonding failure may occur. For example, part of terminals or a group of terminals of the one semiconductor chip may not be bonded to corresponding terminals or a corresponding group of terminals of the other semiconductor chip.

Such a bonding failure caused by sucking and holding a surface in which a concavity is formed may occur not only in bonding groups of bumps of semiconductor chips together but also in bonding groups of terminals of various substrates, such as electronic parts and wafers, together.

According to an aspect, there is provided an electronic device including a first substrate having a group of first terminals over a first surface and having a concavity in a second surface opposite to the first surface, a filler placed in the concavity, a flat plate placed over the second surface with the filler therebetween, and a second substrate disposed on a first surface side of the first substrate and having a group of second terminals bonded to the group of first terminals over a third surface opposite the first surface.

The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.

FIGS. 1A and 1B illustrate an example of bonding terminal groups together;

FIGS. 2A through 2C illustrate another example of bonding terminal groups together;

FIGS. 3A through 3C illustrate an example of bonding in the case of there being height variation in a terminal group;

FIG. 4 illustrates an example of an electronic device according to a first embodiment;

FIGS. 5A through 5C illustrate an example of a method for forming an electronic part according to the first embodiment;

FIGS. 6A and 6B illustrate an example of a terminal group bonding method according to the first embodiment;

FIGS. 7A through 7C illustrate a first modification;

FIGS. 8A and 8B illustrate a second modification;

FIGS. 9A and 9B illustrate a third modification;

FIG. 10 illustrates a fourth modification;

FIGS. 11A through 11C illustrate an example of an electronic part formation method according to a second embodiment;

FIGS. 12A through 12C illustrate an example of a terminal group bonding method according to the second embodiment;

FIGS. 13A and 13B illustrate an example of an electronic device according to a third embodiment;

FIG. 14 illustrates an example of an electronic device according to a fourth embodiment;

FIG. 15 illustrates another example of the electronic device according to the fourth embodiment;

FIGS. 16A through 16C illustrate an example of an electronic part formation method according to a fifth embodiment;

FIGS. 17A through 17C illustrate an example of a terminal group bonding method according to the fifth embodiment;

FIG. 18 illustrates another example of an electronic device according to the fifth embodiment;

FIGS. 19A through 19C illustrate another example of the electronic part formation method according to the fifth embodiment and still another example of the electronic device according to the fifth embodiment;

FIG. 20 illustrates an example of an electronic device; and

FIG. 21 illustrates an example of an electronic apparatus.

First a form of bonding terminal groups together will be described.

FIGS. 1A and 1B illustrate an example of bonding terminal groups together.

FIGS. 1A and 1B illustrate an example of bonding together a group of terminals 110 formed over a substrate 100 and a group of terminals 210 formed over a substrate 200 . FIG. 1A illustrates an example of the state before bonding of the group of terminals 110 formed over the substrate 100 and the group of terminals 210 formed over the substrate 200 . FIG. 1B illustrates an example of the state after bonding of the group of terminals 110 formed over the substrate 100 and the group of terminals 210 formed over the substrate 200 .

The substrate 100 and the substrate 200 are, for example, semiconductor chips (semiconductor elements), wafers before dicing for obtaining individual semiconductor chips, or circuit boards such as interposers or printed circuit boards. The substrate 100 and the substrate 200 may be a combination of semiconductor chips, a combination of wafers, a combination of a semiconductor chip and a wafer, a combination of a semiconductor chip and a circuit board, or the like.

In this example, each terminal 110 formed over the substrate 100 includes a post (pillar) 111 formed so as to protrude from a surface (front surface) 100 a of the substrate 100 and a solder 112 placed at the tip of the post 111 . The post 111 is electrically connected to a conductor portion (not illustrated), such as an electrode, a wiring, or a via, or a circuit element (not illustrated), such as a transistor, formed in the substrate 100 . The group of terminals 110 of the substrate 100 are formed at positions corresponding to the group of terminals 210 of the substrate 200 .

The same applies to each terminal 210 formed over the substrate 200 . In this example, each terminal 210 includes a post 211 formed so as to protrude from a surface (front surface) 200 a of the substrate 200 and a solder 212 placed at the tip of the post 211 . The post 211 is electrically connected to a conductor portion (not illustrated) or a circuit element (not illustrated) formed in the substrate 200 . The group of terminals 210 of the substrate 200 are formed at positions corresponding to the group of terminals 110 of the substrate 100 .

The substrate 100 having the above group of terminals 110 and the substrate 200 having the above group of terminals 210 are bonded together, for example, in the following way.

First, as illustrated in FIG. 1A , the front surface 100 a of the upper substrate 100 over which the group of terminals 110 are formed and the front surface 200 a of the lower substrate 200 over which the group of terminals 210 are formed are disposed opposite each other. At that time the lower substrate 200 is placed on, for example, a suction stage 400 having a hole 410 with a surface (back surface) 200 b opposite to the front surface 200 a over which the group of terminals 210 are formed toward the suction stage 400 , is sucked through the hole 410 , and is held. With the upper substrate 100 , for example, a bonding tool 300 having a hole 310 is used. A surface (back surface) 100 b of the upper substrate 100 opposite to the front surface 100 a over which the group of terminals 110 are formed is sucked through the hole 310 and is held. The substrate 100 sucked and held by the bonding tool 300 is disposed over the substrate 200 sucked and held on the suction stage 400 . Alignment between the group of terminals 110 and the group of terminals 210 is performed to dispose the group of terminals 110 opposite the group of terminals 210 .

In this state, at the same time that the substrate 100 sucked and held by the bonding tool 300 is being heated by, for example, a heating mechanism included in the bonding tool 300 , the substrate 100 is pressed to the substrate 200 side sucked and held on the suction stage 400 . By doing so, the solders 112 of the terminals 110 of the substrate 100 and the corresponding solders 212 of the terminals 210 of the substrate 200 are melted and integrated. As a result, as illustrated in FIG. 1B , the posts 111 and the posts 211 are bonded together by solder bonding portions 500 .

By performing this bonding, an electronic device 1000 in which the substrate 100 and the substrate 200 are connected electrically and mechanically by the posts 111 , the solder bonding portions 500 , and the posts 211 is obtained.

However, the back surface 100 b of the substrate 100 sucked and held by, for example, the bonding tool 300 may have irregularities because of variation in the thickness of substrates which occurs in the process of manufacturing the substrate 100 . The presence of the irregularities may make it impossible to successfully bond the group of terminals 110 of the substrate 100 to the group of terminals 210 of the substrate 200 . This problem will be described by reference to FIGS. 2A through 2C .

FIGS. 2A through 2C illustrate another example of bonding terminal groups together.

FIGS. 2A through 2C are views for describing bonding together a group of terminals 110 of a substrate 100 A having a concavity 120 in a back surface 100 b and a group of terminals 210 of a substrate 200 . FIG. 2A illustrates an example of the substrate 100 A having the concavity 120 in the back surface 100 b . FIG. 2B illustrates an example of the state before bonding of the group of terminals 110 of the substrate 100 A and the group of terminals 210 of the substrate 200 . FIG. 2C illustrates an example of the state after bonding of the group of terminals 110 of the substrate 100 A and the group of terminals 210 of the substrate 200 . With the exception that the substrate 100 A has the concavity 120 in the back surface 100 b , the substrate 100 A is equal in structure to the above substrate 100 .

The concavity 120 illustrated in FIG. 2A may be formed in the process of manufacturing the substrate 100 A. For example, if a semiconductor substrate of a semiconductor chip on which circuit elements, such as transistors, are formed or a semiconductor substrate (wafer) before dicing for obtaining individual semiconductor chips is polished by chemical mechanical polishing (CMP) or is back-ground to reduce the thickness, then the above concavity 120 may be formed. The depth of the concavity 120 , that is to say, variation in the thickness (difference in thickness between the deepest portion and the shallowest portion) in the substrate 100 A depends on the size of the substrate 100 A and is greater than, for example, 10 μm.

When the group of terminals 110 formed over a front surface 100 a of the substrate 100 A having the above concavity 120 in the back surface 100 b are bonded to the group of terminals 210 formed over a front surface 200 a of the substrate 200 , the back surface 100 b of the substrate 100 A is sucked and held by a bonding tool 300 . However, if the back surface 100 b of the substrate 100 A in which the concavity 120 is formed is sucked in this way by the bonding tool 300 , the following may occur. That is to say, when gas between the back surface 100 b and a front surface (sucking surface) 300 a of the bonding tool 300 is evacuated through a hole 310 , the inside of the concavity 120 is sucked on the sucking surface 300 a as illustrated in FIG. 2B . As a result, the substrate 100 A changes in shape and has a concavity 121 in the front surface 100 a (over which the group of terminals 110 are formed).

As a result of sucking and holding the back surface 100 b having the concavity 120 , the concavity 121 is formed in the front surface 100 a of the substrate 100 A opposite to the back surface 100 b . Accordingly, even if the group of terminals 110 in which height variation is controlled are formed in advance over the front surface 100 a , comparatively large height variation occurs in the group of terminals 110 . As a result, as illustrated in FIG. 2C , when the group of terminals 110 of the substrate 100 A are bonded to the group of terminals 210 of the substrate 200 sucked and held on a suction stage 400 , part of the terminals 110 (part of the group of terminals 110 ) may not be bonded to part of the terminals 210 (part of the group of terminals 210 ) because of variation in the distance between the group of terminals 110 and the group of terminals 210 .

Such a bonding failure depends on the shape of the substrate 100 A. Accordingly, as long as the back surface 100 b is sucked on the sucking surface 300 a (flat surface) of the bonding tool 300 , an increase in load does not eliminate the variation in the distance between the group of terminals 110 and the group of terminals 210 . As a result, (posts 111 of) the terminals 110 (group of terminals 110 ) and (posts 211 of) the terminals 210 (group of terminals 210 ) bonded together at the beginning are apart and all the group of terminals 110 and all the group of terminals 210 may not be bonded together.

If there is comparatively large height variation from the beginning before bonding in the group of terminals 110 of the substrate 100 A or the group of terminals 210 of the substrate 200 , then the above bonding failure may be more apt to occur.

FIGS. 3A through 3C illustrate an example of bonding in the case of there being height variation in a terminal group.

FIG. 3A illustrates an example of a substrate 100 B having a concavity 120 in a back surface 100 b and having over a front surface 100 a a group of terminals 110 in which there is height variation. FIG. 3B illustrates an example of the state before bonding of the group of terminals 110 of the substrate 100 B and a group of terminals 210 of a substrate 200 . FIG. 3C illustrates an example of the state after bonding of the group of terminals 110 of the substrate 100 B and the group of terminals 210 of the substrate 200 . With the exception that the substrate 100 B has the concavity 120 in the back surface 100 b and has over the front surface 100 a the group of terminals 110 in which there is height variation, the substrate 100 B is equal in structure to the above substrate 100 .

As illustrated in FIG. 3A , in the group of terminals 110 formed over the front surface 100 a opposite to the back surface 100 b in which the concavity 120 is formed, there may be variation in the height from the front surface 100 a to a vertex portion of each terminal 110 (tip of each solder 112 ). For example, there may be a height variation of about 3 μm in the group of terminals 110 . The substrate 100 B of FIG. 3A in which the height from the front surface 100 a of a terminal 110 corresponding to a comparatively deep portion of the concavity 120 is lower than the height from the front surface 100 a of a terminal 110 corresponding to a comparatively shallow portion of the concavity 120 is taken as an example.

As illustrated in FIG. 3B , when the back surface 100 b of the substrate 100 B is sucked and held by a bonding tool 300 , the concavity 120 in the back surface 100 b is sucked and the substrate 100 B changes in shape. That is to say, a concavity 121 is formed in the front surface 100 a opposite to the back surface 100 b . This is the same with the above substrate 100 A. As a result, as illustrated in FIG. 3C , when the group of terminals 110 of the substrate 100 B are bonded to the group of terminals 210 of the substrate 200 sucked and held on a suction stage 400 , the distance between a terminal 110 corresponding to a comparatively deep portion of the concavity 120 whose height from the front surface 100 a is comparatively low and a corresponding terminal 210 increases. Therefore, with the substrate 100 B of FIGS. 3A through 3C having the concavity 120 and the group of terminals 110 in which there is height variation, a bonding failure is more apt to occur. For example, part of the terminals 110 (part of the group of terminals 110 ) may not be bonded to part of the terminals 210 (part of the group of terminals 210 ).

As has been described in the foregoing, with the substrate 100 A or the substrate 100 B having the concavity 120 in the back surface 100 b sucked by the bonding tool 300 , a bonding failure may occur at the time of bonding the group of terminals 110 to the corresponding group of terminals 210 of the substrate 200 .

A case where the concavity 120 is in the back surface 100 b of the substrate 100 A or the substrate 100 B sucked and held by the bonding tool 300 is taken as an example. Furthermore, if a concavity is in the back surface 200 b of the substrate 200 sucked and held on the suction stage 400 or if both of the substrate 100 A or the substrate 100 B and the substrate 200 have concavities, the same bonding failure may occur.

In view of the above problems, techniques described in the following as embodiments are used for preventing a bonding failure which may occur at the time of bonding groups of terminals of substrates together.

A first embodiment will be described first.

FIG. 4 illustrates an example of an electronic device according to a first embodiment.

FIG. 4 is a fragmentary schematic sectional view of an electronic device 1 . The electronic device 1 includes a substrate 10 and a substrate 20 . The substrate and the substrate 20 are, for example, semiconductor chips, wafers before dicing for obtaining individual semiconductor chips, or circuit boards such as interposers or printed circuit boards. The substrate 10 and the substrate 20 may be a combination of semiconductor chips, a combination of wafers, a combination of a semiconductor chip and a wafer, a combination of a semiconductor chip and a circuit board, or the like.

The substrate 10 has a group of terminals 11 over one surface (front surface) 10 a and has a concavity 12 in a surface (back surface) 10 b opposite to the front surface 10 a . In this example, a terminal 11 including a post 11 a formed so as to protrude from the front surface 10 a of the substrate 10 is illustrated. The post 11 a is formed by the use of a material such as copper (Cu), nickel (Ni), or gold (Au). The post 11 a is electrically connected to a conductor portion (not illustrated), such as an electrode, a wiring, or a via, or a circuit element (not illustrated), such as a transistor, formed in the substrate 10 . Furthermore, in this example, a central portion of the concavity 12 is deeper than an end portion of the concavity 12 in section. For example, the concavity 12 is formed in the process of manufacturing the substrate 10 . If a semiconductor substrate of a semiconductor chip on which circuit elements, such as transistors, are formed or a semiconductor substrate (wafer) before dicing for obtaining individual semiconductor chips is polished by the CMP or is back-ground to reduce the thickness, then the above concavity 12 may be formed.

A filler 13 is placed in the concavity 12 in the back surface 10 b of the substrate 10 . A material having a certain heat conduction property is used as the filler 13 . For example, a material whose heat conduction property is higher than or equal to that of the substrate 10 is used as the filler 13 . A resin composition containing resin containing particles of a material having a certain heat conduction property as a filler may be used as the filler 13 . A material, such as silver (Ag), Cu, Au, aluminum (Al), silicon carbide (SiC), or aluminum nitride (AlN), is used as a filler. A material, such as epoxy resin or silicone resin, is used as resin.

A flat plate 14 is placed over the back surface 10 b of the substrate 10 with the filler 13 placed in the concavity 12 therebetween. A material having a certain heat conduction property is used as the flat plate 14 . For example, a material whose heat conduction property is higher than or equal to that of the substrate 10 is used as the flat plate 14 . A material having not only a certain heat conduction property but also certain rigidity is used as the flat plate 14 . For example, a material whose rigidity is higher than or equal to that of the substrate 10 is used as the flat plate 14 . A material, such as Cu, Al, SiC, or AlN, or silicon (Si), having a certain heat conduction property and certain rigidity is used as the flat plate 14 .

A structure including the substrate 10 , the group of terminals 11 , the concavity 12 , the filler 13 , and the flat plate 14 corresponds to an upper electronic part 2 in the electronic device 1 .

The substrate 20 bonded to the electronic part 2 including the substrate 10 has a group of terminals 21 over a surface (front surface) 20 a opposite the front surface 10 a of the substrate 10 (over which the group of terminals 11 are formed). The group of terminals 21 of the substrate 20 are formed at positions corresponding to the group of terminals 11 of the substrate 10 . In this example, a terminal 21 including a post 21 a formed so as to protrude from the front surface 20 a of the substrate 20 is illustrated. The post 21 a is formed by the use of a material such as Cu, Ni, or Au. The post 21 a is electrically connected to a conductor portion (not illustrated), such as an electrode, a wiring, or a via, or a circuit element (not illustrated), such as a transistor, formed in the substrate 20 .

As illustrated in FIG. 4 , the substrate 20 may have a group of terminals 22 in a surface (back surface) 20 b opposite to the front surface 20 a over which the group of terminals 21 are formed. In this example, pads are illustrated as the group of terminals 22 formed in the back surface 20 b . A terminal 21 formed over the front surface 20 a and a terminal 22 formed in the back surface 20 b are electrically connected via a conductor 23 formed by the use of a through silicon via (TSV) formation technique, a through hole formation technique, or the like according to, for example, the form of the substrate 20 .

A terminal 11 (post 11 a ) of the substrate 10 (electronic part 2 ) and a terminal 21 (post 21 a ) of the substrate 20 are bonded together by a solder bonding portion 50 . A solder containing tin (Sn) is used for forming the solder bonding portion 50 . For example, a Sn solder, a Sn—Ag solder containing Sn and Ag, a Sn—Ag—Cu solder containing Sn, Ag, and Cu, a Sn—In solder containing Sn and indium (In), or a Sn—Bi solder containing Sn and bismuth (Bi) is used as a solder contained in the solder bonding portion 50 . The substrate 10 and the substrate 20 are connected electrically and mechanically by posts 11 a , solder bonding portions 50 , and posts 21 a.

As illustrated in FIG. 4 , a resin layer 60 which covers the posts 11 a , the solder bonding portions 50 , and the posts 21 a may be formed between the substrate 10 and the substrate 20 bonded together. Various insulating resin materials, such as epoxy resin, may be used for forming the resin layer 60 . The resin layer 60 may contain an insulating filler. Bonding strength between the substrate and the substrate 20 bonded together via the solder bonding portions 50 is improved by the resin layer 60 .

An example of a method for forming the electronic device 1 having the above structure will now be described with reference to FIGS. 5A through 5C and FIGS. 6A and 6B .

FIGS. 5A through 5C illustrate an example of a method for forming the electronic part according to the first embodiment.

FIG. 5A is a fragmentary schematic sectional view of a process for sucking a substrate 10 . FIG. 5B is a fragmentary schematic sectional view of a process for placing a filler 13 . FIG. 5C is a fragmentary schematic sectional view of a process for placing a flat plate 14 . The formation of the electronic part 2 will now be described in order with reference to FIGS. 5A through 5C .

First the substrate 10 illustrated in FIG. 5A is prepared. The substrate 10 has a group of terminals 11 over a front surface 10 a and has a concavity 12 in a back surface 10 b . A terminal 11 includes a post 11 a and a solder 11 b placed at the tip of the post 11 a . A Sn solder, a Sn—Ag solder, a Sn—Ag—Cu solder, a Sn—In solder, a Sn—Bi solder or the like is used as the solder 11 b . As stated above, the concavity 12 is formed by, for example, the CMP or back grind performed in the process of manufacturing the substrate 10 .

As illustrated in FIG. 5A , for example, a resin layer 60 a is formed over the front surface 10 a of the substrate 10 over which the group of terminals 11 are formed. The resin layer 60 a becomes the above resin layer 60 illustrated in FIG. 4 . A paste resin material, such as a non-conductive paste (NCP), or a film-shaped resin material, such as a non-conductive film (NCF), is used for forming the resin layer 60 a over the front surface 10 a of the substrate 10 . The thickness of the resin layer 60 a formed in advance over the front surface 10 a of the substrate 10 before bonding the substrate 10 to a substrate 20 is set on the basis of a gap between the substrate 10 and the substrate 20 after bonding so as to cover a post 11 a and a solder 11 b of each terminal 11 .

As illustrated in FIG. 5A , the substrate 10 over whose front surface 10 a the resin layer 60 a is formed is placed on a sucking surface 40 a of a suction stage 40 having a hole 41 with the front surface 10 a over which the resin layer 60 a is formed toward the suction stage 40 , is sucked through the hole 41 , and is held. When the front surface 10 a side of the substrate 10 (resin layer 60 a formed over the front surface 10 a , in this example) is sucked on the suction stage 40 , a state in which height variation in the group of terminals 11 is minimized is maintained or arises. The concavity 12 remains in the back surface 10 b of the substrate 10 .

As illustrated in FIG. 5B , in a state in which the substrate 10 over whose front surface 10 a the resin layer 60 a is formed is sucked and held in this way on the suction stage 40 , a filler 13 a is placed in the concavity 12 in the back surface 10 b of the substrate 10 . The filler 13 a becomes the above filler 13 illustrated in FIG. 4 . For example, a supply apparatus 80 , such as a dispenser, is used for applying the liquid filler 13 a to the back surface 10 b of the substrate 10 in which the concavity 12 is formed. A film-shaped filler 13 a may be placed on the back surface 10 b of the substrate 10 in which the concavity 12 is formed. In this case, the concavity 12 does not need to be filled in with the film-shaped filler 13 a at the stage at which the film-shaped filler 13 a is placed on the back surface 10 b of the substrate 10 .

As illustrated in FIG. 5C , after the filler 13 a is placed on the back surface 10 b of the substrate 10 in which the concavity 12 is formed, the flat plate 14 is placed over the back surface 10 b of the substrate 10 . As illustrated in FIG. 20 , for example, the flat plate 14 is equal in size to the back surface 10 b of the substrate 10 in planar view. The flat plate 14 is placed over the substrate 10 which is sucked and held on the suction stage 40 and in whose back surface 10 b the filler 13 a is placed in the concavity 12 . If thermosetting resin, for example, is used as the filler 13 a , then heating and pressurization are performed. By doing so, the filler 13 a in the concavity 12 in the back surface 10 b is cured (above filler 13 illustrated in FIG. 4 is formed) and the flat plate 14 is fixed onto the back surface 10 b.

If the film-shaped filler 13 a is used, the concavity 12 is filled in with the filler 13 a which softens or melts, the filler 13 a is cured (above filler 13 illustrated in FIG. 4 is formed), and the flat plate 14 is fixed onto the back surface 10 b , at the time of heating and pressurization.

The filler 13 a may be cured by directing light such as ultraviolet rays, depending on the form of resin (component, such as a hardener, contained) used as the filler 13 a . In the processes of FIGS. 5A and 5B , for example, photo-curing resin used as the filler 13 a is placed in the concavity 12 in the back surface 10 b of the substrate 10 sucked and held on the suction stage 40 . In the process of FIG. 5C , the flat plate 14 is pressed to the substrate 10 side and light is directed. By doing so, the filler 13 a in the concavity 12 is cured (above filler 13 illustrated in FIG. 4 is formed) and the flat plate 14 is fixed onto the back surface 10 b.

By the processes illustrated in FIGS. 5A through 5C , the flat plate 14 is placed over the back surface 10 b of the substrate 10 with the filler 13 a with which the concavity 12 is filled in therebetween, and the electronic part 2 is formed. The formed electronic part 2 is removed from the suction stage 40 . As illustrated in FIGS. 6A and 6B , the group of terminals 11 of the electronic part 2 are bonded to a group of terminals 21 of the substrate 20 .

FIGS. 6A and 6B illustrate an example of a terminal group bonding method according to the first embodiment.

FIG. 6A illustrates an example of the state before bonding of the group of terminals 11 of the electronic part 2 (substrate 10 ) and the group of terminals 21 of the substrate 20 . FIG. 6B illustrates an example of the state after bonding of the group of terminals 11 of the electronic part 2 (substrate 10 ) and the group of terminals 21 of the substrate 20 .

The substrate 20 illustrated in FIG. 6A is prepared. The substrate 20 has the group of terminals 21 over a front surface 20 a and has a group of terminals (pads) 22 in a back surface 20 b . A terminal 21 formed over the front surface 20 a includes a post 21 a and a solder 21 b placed at the tip of the post 21 a . A Sn solder, a Sn—Ag solder, a Sn—Ag—Cu solder, a Sn—In solder, a Sn—Bi solder or the like is used as the solder 21 b . The substrate 20 is placed on a suction stage 40 having a hole 41 with the back surface 20 b in which the group of terminals 22 are formed toward the suction stage 40 , is sucked through the hole 41 , and is held.

As illustrated in FIG. 6A , with the electronic part 2 a bonding tool 30 having a hole 31 is used. The flat plate 14 placed over the back surface 10 b of the substrate 10 with the filler 13 a therebetween is sucked through the hole 31 and held by the bonding tool 30 . The electronic part 2 sucked and held by the bonding tool 30 is disposed over the substrate 20 on the suction stage 40 . Alignment between the group of terminals 11 and the group of terminals 21 is performed to dispose the group of terminals 11 opposite the group of terminals 21 .

In the process illustrated in FIG. 6A , in the electronic part 2 sucked and held by the bonding tool 30 , the concavity 12 in the back surface 10 b is filled in with the filler 13 and the flat plate 14 is placed on the sucking surface 30 a side of the bonding tool 30 . By doing so, flattening is performed. Accordingly, a situation such as deformation of the electronic part 2 at the time of being sucked by the bonding tool 30 , that is to say, a situation, such as deformation of the substrate 100 which is illustrated in FIG. 2B or FIG. 3B and which occurs for the reason that the concavity 120 is sucked, is effectively reduced.

The flat plate 14 has certain rigidity and functions as a stiffener. That is to say, when the electronic part 2 is sucked by the bonding tool 30 , the flat plate 14 minimizes deformation of the electronic part 2 or keeps the shape of the electronic part 2 . Deformation of the electronic part 2 is minimized in this way at the time of being sucked by the bonding tool 30 . As a result, height variation in the group of terminals 11 formed over the front surface 10 a is minimized. A material for and the thickness of the flat plate 14 are set so as to minimize deformation of the electronic part 2 which occurs at the time of being sucked by the bonding tool 30 .

As illustrated in FIG. 6A , the electronic part 2 is sucked and held by the bonding tool 30 . Next, as illustrated in FIG. 6B , at the same time that the electronic part 2 is being heated by, for example, a heating mechanism included in the bonding tool 30 , the electronic part 2 is pressed to the substrate 20 side sucked and held on the suction stage 40 . At this time the group of terminals 11 on the electronic part 2 side crash through the resin layer 60 a due to pressing. As a result, a solder 11 b of each terminal 11 touches a solder 21 b of a corresponding terminal 21 on the substrate 20 side. The solder 11 b and the solder 21 b are melted and integrated by heating. By doing so, a solder bonding portion 50 is formed. Furthermore, the resin layer 60 a is cured (above resin layer 60 illustrated in FIG. 4 is formed) by heating at the time of the formation of the solder bonding portions 50 or by a curing process (heating, light irradiation, or the like) after the formation of the solder bonding portions 50 .

As a result, the electronic part 2 and the substrate 20 are connected electrically and mechanically by the posts 11 a , the solder bonding portions 50 , and the posts 21 a . In addition, the resin layer 60 is formed between the electronic part 2 and the substrate 20 . Accordingly, bonding strength between the electronic part 2 and the substrate 20 is improved.

The solders 21 b do not need to be placed on the posts 21 a of the terminals 21 of the substrate 20 . By bonding the solders 11 b placed on the posts 11 a of the terminals 11 of the substrate 10 to the posts 21 a of the substrate 20 , the solder bonding portions 50 may be formed.

In the process illustrated in FIG. 6B , deformation of the electronic part 2 is minimized by the filler 13 and the flat plate 14 at the time of being sucked by the bonding tool 30 . As a result, height variation in the group of terminals 11 is minimized. Accordingly, variation in the distance between the group of terminals 11 on the electronic part 2 side and the group of terminals 21 on the substrate 20 side is minimized. A bonding failure is effectively reduced. For example, a bonding failure in which part of the terminals 11 (part of the group of terminals 11 ) are not bonded to part of the terminals 21 (part of the group of terminals 21 ), that is to say, a bonding failure illustrated in FIG. 2C or FIG. 3C is effectively reduced.

The electronic part 2 and the substrate 20 bonded together are removed from the bonding tool 30 and the suction stage 40 respectively. As a result, the electronic device 1 illustrated in FIG. 4 is obtained.

As stated above, in the electronic device 1 a bonding failure which occurs between the group of terminals 11 and the group of terminals 21 is effectively reduced by the filler 13 with which the concavity 12 in the back surface 10 b of the substrate 10 is filled in and the flat plate 14 placed over the back surface 10 b with the filler 13 therebetween.

In addition, by using a material having a good heat conduction property for the filler 13 and the flat plate 14 in the electronic device 1 , the heat transfer characteristic is improved. For example, a semiconductor chip or the like which generates heat at operation time may be used as the substrate 10 included in the electronic part 2 or the substrate 20 bonded to the substrate 10 . In this case, if the filler 13 and the flat plate 14 each having a good heat conduction property are used in the electronic device 1 , heat generated by the substrate 10 or transferred to the substrate 10 is efficiently transferred to the flat plate 14 through the filler 13 and is efficiently radiated from the flat plate 14 to the outside of the electronic device 1 . That is to say, the filler 13 functions as a thermal interface material (TIM) between the substrate 10 and the flat plate 14 and the flat plate 14 functions as a heat spreader or a radiation plate. This reduces the occurrence of overheat of the substrate 10 and the substrate 20 at operation time. Accordingly, deterioration in the performance of or damage to the substrate 10 and the substrate 20 caused by overheat is effectively minimized and a high performance and high-quality electronic device 1 is realized.

Furthermore, there are cases where a semiconductor chip which emits electromagnetic waves at operation time, a semiconductor chip whose operation may be influenced by electromagnetic waves from the outside, or the like is used as the substrate 10 included in the electronic part 2 of the electronic device 1 . In these cases, the flat plate 14 in the electronic device 1 may also function as an electromagnetic wave shielding member for reducing electromagnetic wave emission from the substrate 10 or electromagnetic wave incidence to the substrate 10 , depending on a material used as the flat plate 14 or the frequency of electromagnetic waves.

The electronic device 1 may be electrically connected to another electronic part or electronic device by the use of a terminal 22 of the substrate 20 . For example, the electronic device 1 is electrically connected to a semiconductor chip, a semiconductor chip laminate, a circuit board, a semiconductor chip (group) mounted over a circuit board, or the like by the use of a terminal 22 .

Furthermore, in the above description a single concavity 12 having a shape in which a central portion is deeper than an end portion is cited as the concavity 12 in the back surface 10 b of the substrate 10 . However, the shape of the concavity 12 in the back surface 10 b of the substrate 10 is not limited to the above shape.

FIGS. 7A through 7C illustrate a first modification.

FIG. 7A is a fragmentary schematic sectional view of another example of the substrate 10 . FIG. 7B is a fragmentary schematic sectional view of another example of the electronic part 2 . FIG. 7C is a fragmentary schematic sectional view of another example of the electronic device 1 .

A substrate 10 illustrated in FIG. 7A has concavities 12 in plural portions (two portions in section, for example) of a back surface 10 b . As stated above, the CMP or the back grind may be performed on the back surface 10 b in the process of manufacturing the substrate 10 . At this time the positions or number of concavities 12 formed may change according to the disposition (density) of a group of terminals 11 formed over a front surface 10 a or the disposition (density) of conductor portions in the substrate 10 to which the group of terminals 11 are connected. As illustrated in FIG. 7A , for example, a comparatively large load is apt to be applied at the time of the CMP or the back grind to areas of the back surface 10 b corresponding to areas of the front surface 10 a over which the density of terminals 11 is comparatively high. As a result, the concavities 12 may be formed.

Even if the substrate 10 has the concavities 12 in the plural portions of the back surface 10 b , the concavities 12 in the plural portions of the back surface 10 b are filled in with a filler 13 and a flat plate 14 is placed over the back surface 10 b , as illustrated in FIG. 7B . By doing so, an electronic part 2 is obtained. This is the same with the above case. Furthermore, as illustrated in FIG. 7C , the electronic part 2 (group of terminals 11 of the substrate 10 ) are bonded to a substrate 20 (group of terminals 21 ) to obtain an electronic device 1 . This is the same with the above case.

Furthermore, in the above description a case where the group of terminals 11 each having a post 11 a and the group of terminals 21 each having a post 21 a are bonded together is taken as an example. However, a combination of a terminal 11 and a terminal 21 to be bonded together is not limited to this example.

FIGS. 8A and 8B illustrate a second modification.

FIG. 8A is a fragmentary schematic sectional view of another example of the substrate 20 . FIG. 8B is a fragmentary schematic sectional view of still another example of the electronic device 1 .

A substrate 20 illustrated in FIG. 8A has pads as terminals 21 (does not have the above posts 21 a ). The substrate 20 illustrated in FIG. 8A is used. As illustrated in FIG. 8B , a group of posts 11 a of terminals 11 of an electronic part 2 (substrate 10 ) are bonded to a group of terminals 21 of the substrate 20 , which are pads, by solder bonding portions 50 . The solder bonding portions 50 are formed by melting solders placed before bonding on the posts 11 a at the time of bonding the substrate 10 and the substrate 20 together. Alternatively, the solder bonding portions 50 are formed by melting and integrating solders placed before bonding on the posts 11 a and solders placed before bonding on the terminals 21 (pads) at the time of bonding the substrate 10 and the substrate 20 together. A Sn solder, a Sn—Ag solder, a Sn—Ag—Cu solder, a Sn—In solder, a Sn—Bi solder or the like is used as the solders on the posts 11 a or the solders on the terminals 21 .

As has been described, an electronic device 1 in which the group of terminals 11 each having a post 11 a and the group of terminals 21 , which are pads, are bonded together is also obtained. A filler 13 and a flat plate 14 is placed over a back surface 10 b of the substrate 10 to minimize deformation of the substrate 10 at the time of the electronic part 2 being sucked and held. This minimizes variation in the distance between the group of terminals 11 of the substrate 10 and the group of pads of the substrate 20 and the occurrence of a bonding failure caused by this variation.

Furthermore, in the above description the substrate 10 having the posts 11 a as the terminals 11 is taken as an example. However, there is no limit to the form of the terminals 11 .

FIGS. 9A and 9B illustrate a third modification.

FIG. 9A is a fragmentary schematic sectional view of still another example of the electronic part 2 . FIG. 9B is a fragmentary schematic sectional view of still another example of the electronic device 1 .

A substrate 10 of an electronic part 2 illustrated in FIGS. 9A and 9B has solder ball bumps as terminals 11 . The electronic part 2 including the substrate 10 illustrated in FIG. 9A is used. As illustrated in FIG. 9B , a group of solder ball bumps of the electronic part 2 (substrate 10 ), which are the terminals 11 , are bonded to, for example, a group of pads of a substrate 20 , which are terminals 21 . Solder bonding portions 50 are formed by melting the solder ball bumps formed before bonding at the time of bonding the substrate 10 and the substrate 20 together. Alternatively, the solder bonding portions 50 are formed by melting and integrating the solder ball bumps formed before bonding and solders placed before bonding on the terminals 21 (pads) at the time of bonding the substrate 10 and the substrate 20 together. A Sn solder, a Sn—Ag solder, a Sn—Ag—Cu solder, a Sn—In solder, a Sn—Bi solder or the like is used as the solder ball bumps or the solders on the terminals 21 .

As has been described, an electronic device 1 in which the group of terminals 11 , which are solder ball bumps, are bonded to the group of terminals 21 , which are pads, is also obtained. Even if the substrate 10 having solder ball bumps as the group of terminals 11 is used, a filler 13 and a flat plate 14 is placed over a back surface 10 b of the substrate 10 to minimize deformation of the substrate 10 at the time of the electronic part 2 being sucked and held. This minimizes variation in the distance between the group of solder ball bumps of the substrate 10 and the group of pads of the substrate 20 and the occurrence of a bonding failure caused by this variation. In this example, the group of terminals 11 , which are solder ball bumps, are bonded to the group of terminals 21 , which are pads. However, the group of terminals 21 may be posts or solder ball bumps. In such a case, the same effect is also obtained.

Furthermore, in the above description a case where the concavity 12 in the back surface 10 b of the substrate 10 is filled in with the filler 13 , where the flat plate 14 is placed over the back surface 10 b , and where the substrate 10 is bonded to the substrate 20 is taken as an example. However, the substrate 10 may be bonded to the following substrate. This substrate has a concavity in a surface. The concavity is filled in with a filler. A flat plate is placed over the surface. This is the same with the substrate 10 .

FIG. 10 illustrates a fourth modification.

FIG. 10 is a fragmentary schematic sectional view of an electronic device 1 a . The electronic device 1 a illustrated in FIG. 10 includes an upper electronic part 2 including a substrate 10 , a filler 13 , and a flat plate 14 and a lower electronic part 2 a including a substrate 70 , a filler 73 , and a flat plate 74 .

The substrate 70 of the lower electronic part 2 a has a group of terminals 71 over a surface (front surface) 70 a and has a concavity 72 in a surface (back surface) 70 b opposite to the front surface 70 a . A terminal 71 including a post 71 a formed so as to protrude from the front surface 70 a of the substrate 70 is taken as an example. The post 71 a is formed by the use of a material such as Cu, Ni, or Au. The post 71 a is electrically connected to a conductor portion (not illustrated), such as an electrode, a wiring, or a via, or a circuit element (not illustrated), such as a transistor, formed in the substrate 70 . Furthermore, the concavity 72 in which a central portion is deeper than an end portion in section is taken as an example. The concavity 72 is formed by, for example, the CMP or the back grind performed in the process of manufacturing the substrate 70 .

The filler 73 is placed in the concavity 72 in the back surface 70 b of the substrate 70 . The same material that is used as the above filler 13 is used as the filler 73 . The flat plate 74 is placed over the back surface 70 b of the substrate 70 with the filler 73 in the concavity 72 therebetween. The same material that is used as the above flat plate 14 is used as the flat plate 74 .

A structure including the substrate 70 , the group of terminals 71 , the concavity 72 , the filler 73 , and the flat plate 74 corresponds to the lower electronic part 2 a of the electronic device 1 a.

Terminals 11 (posts 11 a ) of the substrate 10 (electronic part 2 ) and the terminals 71 (posts 71 a ) of the substrate 70 are bonded together by solder bonding portions 50 . The solder bonding portions 50 are formed by melting and integrating, for example, solders placed before bonding on the posts 11 a of the substrate 10 and solders placed before bonding on the posts 71 a of the substrate 70 at bonding time. A Sn solder, a Sn—Ag solder, a Sn—Ag—Cu solder, a Sn—In solder, a Sn—Bi solder or the like is used as the solders placed on the posts 11 a of the substrate 10 or the solders placed on the posts 71 a of the substrate 70 . The substrate 10 and the substrate 70 are connected electrically and mechanically by the posts 11 a , the solder bonding portions 50 , and the posts 71 a . In addition, bonding strength between the substrate 10 and the substrate 70 is improved by a resin layer 60 formed between the substrate 10 and the substrate 70 bonded together with the solder bonding portions 50 therebetween.

It is assumed that the substrate 70 has the concavity 72 in the back surface 70 b , that the filler 73 is not placed in the concavity 72 , and that the flat plate 74 is not placed over the back surface 70 b . When the substrate 70 is sucked and held on a suction stage with the back surface 70 b toward the suction stage in order to bond the substrate 70 to the electronic part 2 , the concavity 72 is sucked on a sucking surface of the suction stage and deformation of the substrate 70 may occur. If such deformation of the substrate 70 occurs, height variation occurs in the group of terminals 71 . As a result, variation in the distance between the group of terminals 11 of the substrate 10 and the group of terminals 71 occurs. Accordingly, a bonding failure may occur. For example, a bonding failure in which part of the terminals 11 (part of the group of terminals 11 ) are not bonded to part of the terminals 71 (part of the group of terminals 71 ) may occur.

As stated above, however, if the filler 73 is placed in the concavity 72 in the back surface 70 b of the substrate 70 and the flat plate 74 is placed over the back surface 70 b , deformation of the substrate 70 (electronic part 2 a ) is minimized even at the time of being sucked and held on the suction stage. As a result, when the group of terminals 11 and the group of terminals 71 are bonded together, a bonding failure does not occur. Accordingly, a high performance and high-quality electronic device 1 a is realized.

With the electronic device 1 a each of the concavity 12 and the concavity 72 may be formed in plural portions. This is the same with FIGS. 7A through 7C . Furthermore, each terminal 71 of the substrate 70 in the electronic device 1 a is not limited to a terminal including a post 71 a . Each terminal 71 of the substrate 70 in the electronic device 1 a may be a pad as in the examples of FIGS. 8A and 8B . In addition, each terminal 11 of the substrate 10 in the electronic device 1 a is not limited to a terminal including a post 11 a . Each terminal 11 of the substrate 10 in the electronic device 1 a may be a solder ball bump as in the examples of FIGS. 9A and 9B .

More concrete examples of an electronic device and an electronic device formation method will now be described as second through fifth embodiments.

First the second embodiment will be described.

An example of a case where semiconductor chips are used as the substrate 10 and the substrate 20 described in the above first embodiment will now be described as the second embodiment.

FIGS. 11A through 11C illustrate an example of an electronic part formation method according to the second embodiment.

FIG. 11A is a fragmentary schematic sectional view of a process for sucking a semiconductor chip 10 A. FIG. 11B is a fragmentary schematic sectional view of a process for placing a filler 13 A. FIG. 11C is a fragmentary schematic sectional view of a process for placing a flat plate 14 A.

The semiconductor chip 10 A illustrated in FIG. 11A includes a semiconductor substrate 15 A and a wiring layer 16 A formed over the semiconductor substrate 15 A.

Circuit elements, such as transistors, resistors, and capacitors, are formed in a front surface of the semiconductor substrate 15 A. In this example, a transistor 15 Aa formed in an element region demarcated by an isolation region 15 Ab is illustrated as a circuit element formed in the semiconductor substrate 15 A.

The wiring layer 16 A includes conductor portions, such as wirings 16 Aa, vias 16 Ab, and electrodes 16 Ac, formed in an insulating portion 16 Ad. The insulating portion 16 Ad is formed by the use of an organic or inorganic insulating material. The conductor portions, such as the wirings 16 Aa, the vias 16 Ab, and the electrodes 16 Ac, are formed by the use of a conductor material such as Cu or Al.

A group of terminals 11 A are formed over the electrodes 16 Ac in the wiring layer 16 A. Each terminal 11 A includes a post 11 Aa protruding from a front surface 10 Aa of the semiconductor chip 10 A and a solder 11 Ab placed at the tip of the post 11 Aa. The post 11 Aa is formed by the use of a material such as Cu, Ni, or Au. A solder, such as a Sn—Ag solder, containing Sn is used as the solder 11 Ab. The circuit elements, such as the transistor 15 Aa, formed in the semiconductor substrate 15 A are electrically connected to the group of terminals 11 A formed over the front surface 10 Aa via the conductor portions, such as the wirings 16 Aa, the vias 16 Ab, and the electrodes 16 Ac, in the wiring layer 16 A.

As illustrated in FIG. 11A , there is a concavity 12 A in a back surface 10 Ab of the semiconductor chip 10 A formed as a result of, for example, the CMP or the back grind performed on the semiconductor substrate 15 A. A resin layer 60 Aa is formed over the front surface 10 Aa of the semiconductor chip 10 A having the concavity 12 A in the back surface 10 Ab. The resin layer 60 Aa side of the semiconductor chip 10 A is sucked on a suction stage 40 .

As illustrated in FIG. 11B , a filler 13 Aa is then placed in the concavity 12 A in the back surface 10 Ab of the semiconductor chip 10 A sucked on the suction stage 40 . Furthermore, as illustrated in FIG. 11C , the flat plate 14 A is placed over the back surface 10 Ab and the filler 13 Aa is cured (filler 13 A is formed). The same material that is used as the above filler 13 a and filler 13 may be used as the filler 13 Aa and the filler 13 A. The same material that is used as the above flat plate 14 may be used as the flat plate 14 A.

An electronic part 2 A including the semiconductor chip 10 A, the filler 13 A with which the concavity 12 A in the back surface 10 Ab of the semiconductor chip 10 A is filled in, and the flat plate 14 A placed over the back surface 10 Ab with the filler 13 A therebetween is formed by the processes illustrated in FIGS. 11A through 11C .

FIGS. 12A through 12C illustrate an example of a terminal group bonding method according to the second embodiment.

FIG. 12A illustrates an example of the state before bonding of the group of terminals 11 A of the electronic part 2 A (semiconductor chip 10 A) and a group of terminals 21 A of a semiconductor chip 20 A. FIG. 12B illustrates an example of the state at bonding time of the group of terminals 11 A of the electronic part 2 A (semiconductor chip 10 A) and the group of terminals 21 A of the semiconductor chip 20 A. FIG. 12C illustrates an example of the state after bonding of the group of terminals 11 A of the electronic part 2 A (semiconductor chip 10 A) and the group of terminals 21 A of the semiconductor chip 20 A.

The electronic part 2 A including the semiconductor chip 10 A, the filler 13 A, and the flat plate 14 A is removed from the suction stage 40 and the group of terminals 11 A of the electronic part 2 A are bonded to the group of terminals 21 A of the semiconductor chip 20 A other than the semiconductor chip 10 A.

As illustrated in FIG. 12A , the semiconductor chip 20 A has the group of terminals 21 A. Each terminal 21 A includes a post 21 Aa protruding from a front surface 20 Aa of the semiconductor chip 20 A and a solder 21 Ab placed at the tip of the post 21 Aa. The post 21 Aa is formed by the use of a material such as Cu, Ni, or Au. A solder, such as a Sn—Ag solder, containing Sn is used as the solder 21 Ab. The group of terminals 21 A are formed at positions corresponding to the group of terminals 11 A of the semiconductor chip 10 A. The post 21 Aa is electrically connected to a conductor portion (not illustrated), such as an electrode, a wiring, or a via, or a circuit element (not illustrated), such as a transistor, formed in the semiconductor chip 20 A. Furthermore, the semiconductor chip 20 A has a group of terminals 22 A in a back surface 20 Ab. In this example, pads are illustrated as the group of terminals 22 A. A terminal 21 A formed over the front surface 20 Aa and a terminal 22 A formed in the back surface 20 Ab are electrically connected via a conductor 23 A formed by the use of the TSV formation technique. The terminal 22 A and the conductor 23 A are formed by the use of a material such as Cu or Al.

As illustrated in FIG. 12A , the semiconductor chip 20 A is held on a suction stage 40 which sucks the side of the back surface 20 Ab in which the group of terminals 22 A are formed. As illustrated in FIG. 12A , the electronic part 2 A including the semiconductor chip 10 A is held by a bonding tool 30 which sucks the flat plate 14 A side and is disposed over the semiconductor chip 20 A on the suction stage 40 . Alignment between the group of terminals 11 A and the group of terminals 21 A is performed to dispose the group of terminals 11 A opposite the group of terminals 21 A.

As illustrated in FIG. 12B , at the same time that the electronic part 2 A is being heated by, for example, the bonding tool 30 , the electronic part 2 A is pressed to the semiconductor chip 20 A side. By doing so, the electronic part 2 A is bonded to the semiconductor chip 20 A. At that time a solder 11 Ab of each terminal 11 A which crashes through the resin layer 60 Aa due to pressing touches a solder 21 Ab of a corresponding terminal 21 A on the semiconductor chip 20 A side. The solder 11 Ab and the solder 21 Ab are melted and integrated by heating. By doing so, a solder bonding portion 50 A is formed. As a result, the semiconductor chip 10 A and the semiconductor chip 20 A are connected electrically and mechanically by the posts 11 Aa, the solder bonding portions 50 A, and the posts 21 Aa. Furthermore, a cured resin layer 60 A is formed by heating at the time of the formation of the solder bonding portions 50 A or by a curing process (heating, light irradiation, or the like) after the formation of the solder bonding portions 50 A. Accordingly, bonding strength between the semiconductor chip 10 A and the semiconductor chip 20 A is improved.

As a result, an electronic device 1 A illustrated in FIG. 12C is formed. The group of terminals 11 A of the electronic part 2 A including the semiconductor chip 10 A and the group of terminals 21 A of the semiconductor chip 20 A are bonded together in the electronic device 1 A.

With the electronic device 1 A variation in the distance between the group of terminals 11 A and the group of terminals 21 A at bonding time is effectively minimized by the filler 13 A and the flat plate 14 A. As a result, the occurrence of a bonding failure caused by this variation is effectively reduced. Accordingly, a high performance and high-quality electronic device 1 A is realized.

With the electronic device 1 A the concavity 12 A may be formed in plural portions of the back surface 10 Ab of the semiconductor chip 10 A. This is the same with FIGS. 7A through 7C . Furthermore, each terminal 21 A of the semiconductor chip 20 A in the electronic device 1 A is not limited to a terminal including a post 21 Aa. Each terminal 21 A of the semiconductor chip 20 A in the electronic device 1 A may be a pad as in the examples of FIGS. 8A and 8B . In addition, each terminal 11 A of the semiconductor chip 10 A in the electronic device 1 A is not limited to a terminal including a post 11 Aa. Each terminal 11 A of the semiconductor chip 10 A in the electronic device 1 A may be a solder ball bump as in the examples of FIGS. 9A and 9B . Moreover, the following chip may be used as the semiconductor chip 20 A as in the example of FIG. 10 . This semiconductor chip has a concavity in a surface opposite to a side on which the electronic part 2 A is bonded. A determined filler is placed in the concavity and a determined flat plate is placed over the filler.

Next, the third embodiment will be described.

An example of a case where a semiconductor chip and a circuit board are used as the substrate 10 and the substrate 20 , respectively, described in the above first embodiment will now be described as the third embodiment.

FIGS. 13A and 13B illustrate an example of an electronic device according to the third embodiment.

FIG. 13A is a fragmentary schematic sectional view of a first example of the structure of an electronic device 1 B. The electronic device 1 B illustrated in FIG. 13A includes an electronic part 2 A including a semiconductor chip 10 A, a filler 13 A, and a flat plate 14 A and formed by processes like those illustrated in FIGS. 11A through 11C and an interposer 20 B.

The interposer 20 B includes a substrate 25 B and conductor portions such as wirings 26 Ba and vias 26 Bb. A material, such as Si or glass, is used as the substrate 25 B. The conductor portions are formed by the use of a conductor material such as Cu. A group of terminals 21 B are formed over parts (electrodes) of the wirings 26 Ba in a front surface 20 Ba of the interposer 20 B. Each terminal 21 B includes a post 21 Ba protruding from a front surface 20 Ba. The post 21 Ba is formed by the use of a material such as Cu, Ni, or Au. Wirings 26 Ba in the front surface 20 Ba and a back surface 20 Bb of the interposer 20 B are electrically connected via a via 26 Bb.

In the electronic device 1 B, the group of terminals 21 B of the interposer 20 B and a group of terminals 11 A of the electronic part 2 A (semiconductor chip 10 A) are bonded together by solder bonding portions 50 B. The solder bonding portions 50 B are formed by melting and integrating, for example, solders (solders containing Sn) placed before bonding on the posts 21 Ba and solders (above solders 11 Ab) placed before bonding on posts 11 Aa at the time of bonding together the interposer 20 B and the electronic part 2 A. A resin layer 60 B (obtained by curing the resin layer 60 Aa illustrated in FIG. 12A , for example) is formed between the interposer 20 B and the electronic part 2 A in the electronic device 1 B.

With the electronic device 1 B in which the electronic part 2 A is bonded in this way to a circuit board such as the interposer 20 B, variation in the distance between the group of terminals 11 A and the group of terminals 21 B at bonding time is also minimized effectively by the filler 13 A and the flat plate 14 A. As a result, the occurrence of a bonding failure caused by this variation is effectively reduced. Accordingly, a high performance and high-quality electronic device 1 B is realized.

With the electronic device 1 B a concavity 12 A may be formed in plural portions of a back surface 10 Ab of the semiconductor chip 10 A. This is the same with FIGS. 7A through 7 C. Furthermore, each terminal 21 B of the interposer 20 B in the electronic device 1 B is not limited to a terminal including a post 21 Ba. Each terminal 21 B of the interposer 20 B in the electronic device 1 B may be a wiring 26 Ba (pad) in the front surface 20 Ba as in the examples of FIGS. 8A and 8B . In addition, each terminal 11 A of the semiconductor chip 10 A in the electronic device 1 B is not limited to a terminal including a post 11 Aa. Each terminal 11 A of the semiconductor chip 10 A in the electronic device 1 B may be a solder ball bump as in the examples of FIGS. 9A and 9B .

In addition, FIG. 13B is a fragmentary schematic sectional view of a second example of the structure of an electronic device 1 C. The electronic device 1 C illustrated in FIG. 13B includes an electronic part 2 A including a semiconductor chip 10 A, a filler 13 A, and a flat plate 14 A and formed by processes like those illustrated in FIGS. 11A through 11C and a printed circuit board 20 C.

The printed circuit board 20 C includes conductor portions, such as wirings 26 Ca, vias 26 Cb, and electrodes 26 Cc, formed in an insulating portion 26 Cd. In this example, the printed circuit board 20 C having a multilayer wiring structure is illustrated. However, the number of layers formed by the wirings 26 Ca is not limited to this example. The insulating portion 26 Cd is formed by the use of an organic or inorganic insulating material. The conductor portions are formed by the use of a conductor material such as Cu or Al. A group of terminals 21 C are formed over the electrodes 26 Cc in a front surface 20 Ca of the printed circuit board 20 C. Each terminal 21 C includes a post 21 Ca protruding from the front surface 20 Ca. The post 21 Ca is formed by the use of a material such as Cu, Ni, or Au. Electrodes 26 Cc in the front surface 20 Ca and a back surface 20 Cb of the printed circuit board 20 C are electrically connected via a wiring 26 Ca and a via 26 Cb.

In the electronic device 1 C, the group of terminals 21 C of the printed circuit board 20 C and a group of terminals 11 A of the electronic part 2 A (semiconductor chip 10 A) are bonded together by solder bonding portions 50 C. The solder bonding portions 50 C are formed by melting and integrating, for example, solders (solders containing Sn) placed before bonding on the posts 21 Ca and solders (above solders 11 Ab) placed before bonding on posts 11 Aa at the time of bonding together the printed circuit board 20 C and the electronic part 2 A. A resin layer 60 C (obtained by curing the resin layer 60 Aa illustrated in FIG. 12A , for example) is formed between the printed circuit board 20 C and the electronic part 2 A in the electronic device 1 C.

With the electronic device 1 C in which the electronic part 2 A is bonded in this way to a circuit board such as the printed circuit board 20 C, variation in the distance between the group of terminals 11 A and the group of terminals 21 C at bonding time is also minimized effectively by the filler 13 A and the flat plate 14 A. As a result, the occurrence of a bonding failure caused by this variation is effectively reduced. Accordingly, a high performance and high-quality electronic device 1 C is realized.

With the electronic device 1 C a concavity 12 A may be formed in plural portions of a back surface 10 Ab of the semiconductor chip 10 A. This is the same with FIGS. 7A through 7C . Furthermore, each terminal 21 C of the printed circuit board 20 C in the electronic device 1 C is not limited to a terminal including a post 21 Ca. Each terminal 21 C of the printed circuit board 20 C in the electronic device 1 C may be an electrode 26 Cc (pad) in the front surface 20 Ca as in the examples of FIGS. 8A and 8B . In addition, each terminal 11 A of the semiconductor chip 10 A in the electronic device 1 C is not limited to a terminal including a post 11 Aa. Each terminal 11 A of the semiconductor chip 10 A in the electronic device 1 C may be a solder ball bump as in the examples of FIGS. 9A and 9B .

Next, the fourth embodiment will be described.

An example of a case where a semiconductor chip and a wafer are used as the substrate 10 and the substrate 20 , respectively, described in the above first embodiment will now be described as the fourth embodiment.

FIG. 14 illustrates an example of an electronic device according to the fourth embodiment.

FIG. 14 is a fragmentary schematic sectional view of an electronic device 1 D. The electronic device 1 D illustrated in FIG. 14 includes a group of electronic parts 2 A each including a semiconductor chip 10 A, a filler 13 A, and a flat plate 14 A and formed by processes like those illustrated in FIGS. 11A through 11C and a wafer 20 D over which the group of electronic parts 2 A are mounted. In FIG. 14 (and FIG. 15 ), the details of the internal structure of the semiconductor chips 10 A included in the electronic parts 2 A are not illustrated.

The wafer 20 D is a wafer before dicing for obtaining individual semiconductor chips. The wafer 20 D has plural dicing lines (scribe lines) 27 D and regions enclosed by the dicing lines 27 D are regions (semiconductor chip formation regions) 28 D in which semiconductor chips before dicing are to be formed. By dicing along the dicing lines 27 D the wafer 20 D in which determined structures corresponding to the semiconductor chips are formed, the individual semiconductor chips (semiconductor chip 20 A illustrated in FIG. 12A , for example) each having the determined structure are obtained. A group of terminals 21 D (group of terminals 21 A illustrated in FIG. 12A , for example) are formed over a front surface 20 Da of each semiconductor chip formation region 28 D in the wafer 20 D. Each terminal 21 D includes a post 21 Da protruding from the front surface 20 Da. The post 21 Da is formed by the use of a material such as Cu, Ni, or Au.

In the electronic device 1 D, the groups of terminals 21 D over the semiconductor chip formation regions 28 D of the wafer 20 D and groups of terminals 11 A of the electronic parts 2 A (semiconductor chips 10 A) are bonded together by solder bonding portions 50 D. The solder bonding portions 50 D are formed by melting and integrating, for example, solders (solders containing Sn) placed before bonding on the posts 21 Da and solders (above solders 11 Ab) placed before bonding on posts 11 Aa at the time of bonding together the wafer 20 D and the electronic parts 2 A. A resin layer 60 D (obtained by curing the resin layer 60 Aa illustrated in FIG. 12A , for example) is formed between the wafer 20 D and the electronic parts 2 A in the electronic device 1 D.

With the electronic device 1 D in which the electronic parts 2 A are bonded in this way to the wafer 20 D, variation in the distance between the groups of terminals 11 A and the groups of terminals 21 D at bonding time is also minimized effectively by the fillers 13 A and the flat plates 14 A. As a result, the occurrence of a bonding failure caused by this variation is effectively reduced. Accordingly, a high performance and high-quality electronic device 1 D is realized.

FIG. 15 illustrates another example of the electronic device according to the fourth embodiment.

FIG. 15 is a fragmentary schematic sectional view of electronic devices 1 Da obtained from the electronic device 1 D illustrated in FIG. 14 . The electronic device 1 D illustrated in FIG. 14 is diced along the dicing lines 27 D of the wafer 20 D and the semiconductor chip formation regions 28 D to which the electronic parts 2 A are bonded are separated. As a result, as illustrated in FIG. 15 , each electronic device 1 Da (electronic device 1 A illustrated in FIG. 12C , for example) in which an electronic part 2 A is bonded to a semiconductor chip 28 Da having the determined structure and formed in a semiconductor chip formation region 28 D is obtained.

With the electronic device 1 D or the electronic device 1 Da a concavity 12 A may be formed in plural portions of a back surface 10 Ab of the semiconductor chip 10 A. This is the same with FIGS. 7A through 7C . Furthermore, each terminal 21 D of the wafer 20 D or the semiconductor chip 28 Da in the electronic device 1 D or the electronic device 1 Da is not limited to a terminal including a post 21 Da. Each terminal 21 D of the wafer 20 D or the semiconductor chip 28 Da in the electronic device 1 D or the electronic device 1 Da may be a pad as in the examples of FIGS. 8A and 8B . In addition, each terminal 11 A of the semiconductor chip 10 A in the electronic device 1 D or the electronic device 1 Da is not limited to a terminal including a post 11 Aa. Each terminal 11 A of the semiconductor chip 10 A in the electronic device 1 D or the electronic device 1 Da may be a solder ball bump as in the examples of FIGS. 9A and 9B . Moreover, the following wafer may be used as a wafer to which the electronic parts 2 A are bonded, as in the example of FIG. 10 . This wafer has a concavity in a surface opposite to a side on which the electronic parts 2 A are bonded. A determined filler is placed in the concavity and a determined flat plate is placed over the filler.

Next, the fifth embodiment will be described.

An example of a case where wafers are used as the substrate 10 and the substrate 20 described in the above first embodiment will now be described as the fifth embodiment.

FIGS. 16A through 16C illustrate an example of an electronic part formation method according to the fifth embodiment.

FIG. 16A is a fragmentary schematic sectional view of a process for sucking a wafer 10 B. FIG. 16B is a fragmentary schematic sectional view of a process for placing a filler 13 B. FIG. 16C is a fragmentary schematic sectional view of a process for placing a flat plate 14 B.

The wafer 10 B illustrated in FIG. 16A is a wafer before dicing for obtaining individual semiconductor chips. Regions enclosed by dicing lines 17 B are semiconductor chip formation regions 18 B. By dicing the wafer 10 B along the dicing lines 17 B, the individual semiconductor chips (semiconductor chip 10 A illustrated in FIG. 12A , for example) each having a determined structure are obtained. A group of terminals 11 B (group of terminals 11 A illustrated in FIG. 12A , for example) are formed over a front surface 10 Ba of each semiconductor chip formation region 18 B in the wafer 10 B. Each terminal 11 B includes a post 11 Ba protruding from the front surface 10 Ba and a solder 11 Bb placed at the tip of the post 11 Ba. The post 11 Ba is formed by the use of a material such as Cu, Ni, or Au. A solder, such as a Sn—Ag solder, containing Sn is used as the solder 11 Bb.

There is a concavity 12 B in a back surface 10 Bb of the wafer 10 B formed by, for example, the CMP or the back grind performed in a manufacturing process. The shape or number of concavities 12 B is not limited to that of the concavity 12 B illustrated in FIG. 16A . As illustrated in FIG. 16A , a resin layer 60 Ba is formed over the front surface 10 Ba of the wafer 10 B having the concavity 12 B, and the resin layer 60 Ba side is sucked on a suction stage 40 .

As illustrated in FIG. 16B , a filler 13 Ba is then placed in the concavity 12 B in the back surface 10 Bb of the wafer 10 B sucked on the suction stage 40 . Furthermore, as illustrated in FIG. 16C , a flat plate 14 B is placed over the back surface 10 Bb and the filler 13 Ba is cured (filler 13 B is formed). The same material that is used as the above filler 13 a and filler 13 may be used as the filler 13 Ba and the filler 13 B. The same material that is used as the above flat plate 14 may be used as the flat plate 14 B.

An electronic part 2 B including the wafer 10 B, the filler 13 B with which the concavity 12 B in the back surface 10 Bb of the wafer 10 B is filled in, and the flat plate 14 B placed over the back surface 10 Bb with the filler 13 B therebetween is formed by the processes illustrated in FIGS. 16A through 16C .

FIGS. 17A through 17C illustrate an example of a terminal group bonding method according to the fifth embodiment.

FIG. 17A illustrates an example of the state before bonding of the group of terminals 11 B of the electronic part 2 B (wafer 10 B) and a group of terminals 21 D of a wafer 20 D. FIG. 17B illustrates an example of the state at bonding time of the group of terminals 11 B of the electronic part 2 B (wafer 10 B) and the group of terminals 21 D of the wafer 20 D. FIG. 17C illustrates an example of the state after bonding of the group of terminals 11 B of the electronic part 2 B (wafer 10 B) and the group of terminals 21 D of the wafer 20 D.

The electronic part 2 B including the wafer 10 B, the filler 13 B, and the flat plate 14 B is removed from the suction stage 40 and the group of terminals 11 B of the electronic part 2 B are bonded to the group of terminals 21 D of the wafer 20 D other than the wafer 10 B.

As illustrated in FIG. 17A , the wafer 20 D is held on a suction stage 40 which sucks the back surface 20 Db side. As illustrated in FIG. 17A , the electronic part 2 B including the wafer 10 B is held by a bonding tool 30 which sucks the flat plate 14 B side and is disposed over the wafer 20 D on the suction stage 40 . Alignment between the group of terminals 11 B and the group of terminals 21 D is performed to dispose the group of terminals 11 B opposite the group of terminals 21 D.

As illustrated in FIG. 17B , at the same time that the electronic part 2 B is being heated by, for example, the bonding tool 30 , the electronic part 2 B is pressed to the wafer 20 D side. By doing so, the electronic part 2 B is bonded to the wafer 20 D. At that time a solder 11 Bb of each terminal 11 B which crashes through the resin layer 60 Ba due to pressing touches a solder 21 Db of a corresponding terminal 21 D on the wafer 20 D side. The solder 11 Bb and the solder 21 Db are melted and integrated by heating. By doing so, a solder bonding portion 50 E is formed. As a result, the electronic part 2 B including the wafer 10 B and the wafer 20 D are connected electrically and mechanically by the posts 11 Ba, the solder bonding portions 50 E, and posts 21 Da. Furthermore, a cured resin layer 60 E is formed by heating at the time of the formation of the solder bonding portions 50 E or by a curing process (heating, light irradiation, or the like) after the formation of the solder bonding portions 50 E. Accordingly, bonding strength between the electronic part 2 B including the wafer 10 B and the wafer 20 D is improved.

As a result, an electronic device 1 E illustrated in FIG. 17C is formed. The group of terminals 11 B of the electronic part 2 B including the wafer 10 B and the group of terminals 21 D of the wafer 20 D are bonded together in the electronic device 1 E.

With the electronic device 1 E in which the electronic part 2 B including the wafer 10 B is bonded in this way to the wafer 20 D, variation in the distance between the group of terminals 11 B and the group of terminals 21 D at bonding time is also minimized effectively by the filler 13 B and the flat plate 14 B. As a result, the occurrence of a bonding failure caused by this variation is effectively reduced. Accordingly, a high performance and high-quality electronic device 1 E is realized.

FIG. 18 illustrates another example of the electronic device according to the fifth embodiment.

FIG. 18 is a fragmentary schematic sectional view of electronic devices 1 Ea obtained from the electronic device 1 E illustrated in FIG. 17C . With the electronic device 1 E illustrated in FIG. 17C , for example, dicing lines 17 B of the wafer 10 B included in the electronic part 2 B and dicing lines 27 D of the wafer 20 D are formed in advance in corresponding positions. The electronic device 1 E is diced along the dicing lines 17 B of the wafer 10 B and the dicing lines 27 D of the wafer 20 D into individual semiconductor chip formation regions 18 B and semiconductor chip formation regions 28 D. As a result, as illustrated in FIG. 18 , each electronic device 1 Ea (electronic device 1 A illustrated in FIG. 12C , for example) in which a semiconductor chip 18 Ba formed in a semiconductor chip formation region 18 B and a semiconductor chip 28 Da formed in a semiconductor chip formation region 28 D are bonded together is obtained.

With the electronic device 1 E or the electronic device 1 Ea a concavity 12 B may be formed in plural portions of a back surface 10 Bb of the wafer 10 B or a semiconductor chip 18 Ba. This is the same with FIGS. 7A through 7C . Furthermore, each terminal 21 D of the wafer 20 D or the semiconductor chip 28 Da in the electronic device 1 E or the electronic device 1 Ea is not limited to a terminal including a post 21 Da. Each terminal 21 D of the wafer 20 D or the semiconductor chip 28 Da in the electronic device 1 E or the electronic device 1 Ea may be a pad as in the examples of FIGS. 8A and 8B . In addition, each terminal 11 B of the wafer 10 B in the electronic device 1 E or the electronic device 1 Ea is not limited to a terminal including a post 11 Ba. Each terminal 11 B of the wafer 10 B in the electronic device 1 E or the electronic device 1 Ea may be a solder ball bump as in the examples of FIGS. 9A and 9B . Moreover, the following wafer may be used as a wafer to which the electronic part 2 B is bonded, as in the example of FIG. 10 . This wafer has a concavity in a surface opposite to a side on which the electronic part 2 B is bonded. A determined filler is placed in the concavity and a determined flat plate is placed over the filler.

Furthermore, a case where dicing is performed after boding the wafer 10 B and the wafer 20 D together to obtain the electronic device 1 Ea is taken as an example. However, the wafer 10 B may be diced before boding the wafer 10 B and the wafer 20 D together.

FIGS. 19A through 19C illustrate another example of the electronic part formation method according to the fifth embodiment and still another example of the electronic device according to the fifth embodiment.

FIG. 19A is a fragmentary schematic sectional view of a process for dicing a wafer 10 B. FIG. 19B is a fragmentary schematic sectional view of a process for bonding individual electronic parts 2 C. FIG. 19C is a fragmentary schematic sectional view of a process for dicing a wafer 20 D.

In this example, as illustrated in FIGS. 16A through 16C , a filler 13 B with which a concavity 12 B in a back surface of the wafer 10 B is filled in is placed and a flat plate 14 B which covers the filler 13 B is placed. After that, dicing is performed along dicing lines 17 B. As a result, the individual electronic parts 2 C illustrated in FIG. 19A are obtained. Each electronic part 2 C includes a semiconductor chip 18 Ba, the filler 13 B with which the concavity 12 B is filled in, and the flat plate 14 B which covers the filler 13 B.

As illustrated in FIG. 19B , a group of terminals 11 B of each electronic part 2 C obtained in this way are bonded to a group of terminals 21 D of the wafer 20 D by solder bonding portions 50 E as in the example of FIG. 14 described in the above fourth embodiment. After that, as illustrated in FIG. 19C , the wafer 20 D is diced along dicing lines 27 D as in the example of FIG. 15 . As a result, each electronic device 1 Ea in which a semiconductor chip 18 Ba and a semiconductor chip 28 Da are bonded together is obtained. Each electronic device 1 Ea is the same as each electronic device 1 Ea illustrated in the example of FIG. 18 .

The electronic device 1 Ea is also obtained by the method illustrated in FIGS. 19A through 19C .

In addition, an example of an electronic device is illustrated in FIG. 20 with regard to the above first through fifth embodiments. FIG. 20 is a schematic perspective view of an example of an electronic device. As illustrated in FIG. 20 , for example, the flat plate 14 described in the above first embodiment is equal or approximately equal in size to the back surface 10 b of the substrate 10 in planar view. This minimizes an increase in the size (plane size) of the substrate 10 and the electronic part 2 caused by placing the filler 13 and the flat plate 14 for reducing a bonding failure.

If the semiconductor chip 10 A is used as the substrate 10 (second to fourth embodiments), the flat plate 14 A is equal or approximately equal in size to the back surface 10 Ab of the semiconductor chip 10 A in planar view. If the wafer 10 B is used as the substrate 10 (fifth embodiment), the flat plate 14 B is equal or approximately equal in size to the back surface 10 Bb of the wafer 10 B in planar view. In these cases, an increase in the size of the semiconductor chip 10 A and the electronic part 2 A or the wafer 10 B and the electronic part 2 B is also minimized.

The electronic devices 1 , 1 a , 1 A, 1 B, 1 C, 1 Da, 1 Ea, and the like described in the above first through fifth embodiments are used in various electronic apparatuses, such as computers (personal computers, supercomputers, servers, and the like), smartphones, portable telephones, tablet terminals, sensors, cameras, audio devices, measuring devices, inspection devices, and manufacturing devices.

FIG. 21 illustrates an example of an electronic apparatus. FIG. 21 is a schematic view of an example of an electronic apparatus. As illustrated in FIG. 21 , for example, the electronic device 1 illustrated in FIG. 4 is mounted (contained) in an aforementioned electronic apparatus 90 as an example. In this example, the electronic device 1 is connected electrically and mechanically to another electronic part 91 (semiconductor chip, a circuit board, or the like) via the terminals 22 and solder bonding portions 92 .

With the electronic device 1 , the concavity 12 in the back surface 10 b of the substrate 10 is filled in with the filler 13 and the flat plate 14 is placed over the back surface 10 b with the filler 13 therebetween. As a result, deformation of the substrate 10 sucked and held at the time of being bonded to the substrate 20 is minimized and a failure in bonding the group of terminals 11 and the group of terminals 21 together is reduced. Accordingly, a high performance and high-quality electronic device 1 is realized and a high performance and high-quality electronic apparatus 90 in which such an electronic device 1 is mounted is realized.

Electronic apparatuses in which the other electronic devices 1 a , 1 A, 1 B, 1 C, 1 Da, 1 Ea, and the like are mounted are also realized in the same way.

According to the disclosed techniques, a high performance and high-quality electronic device in which a failure in bonding together groups of terminals of substrates to be bonded together is reduced is realized. Furthermore, a high performance and high-quality electronic apparatus including such an electronic device is realized.

All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.