Interface board, a multichip package (MCP) test system including the interface board, and an MCP test method using the MCP test system

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0159922, filed on Nov. 13, 2015, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The inventive concept relates to an interface board, a multichip package (MCP) test system comprising the interface board, and an MCP test method using the MCP test system.

A multichip package (MCP) product including two or more types of semiconductor chips that are not connected to each other undergoes various tests. A final test may be performed on a first type semiconductor chip of the two or more types of semiconductor chips. At this time, a second type semiconductor chip of the two or more types of semiconductor chips may have already passed a different test. However, the second type semiconductor chip may have been subsequently cracked in a transfer process or in a process of preparing the first type semiconductor chip for testing.

According to an exemplary embodiment of the inventive concept, there is provided an interface board for testing a multichip package, wherein the multichip package includes a first type semiconductor chip and a second type semiconductor chip, the interface board includes a first surface facing the multichip package and a second surface facing a test apparatus, the first surface includes upper terminals that are configured to be electrically connected to terminals of the multichip package, the second surface includes lower terminals that are configured to be electrically connected to the test apparatus, and the upper terminals include a first upper terminal group for testing the first type semiconductor chip and a second upper terminal group for testing whether a crack defect exists in the second type semiconductor chip.

According to an exemplary embodiment of the inventive concept, there is provided a method of testing a multichip package including a first type semiconductor chip and a second type semiconductor chip, the method includes disposing an interface board between the multichip package and a test apparatus, applying a first signal to the multichip package to test the first type semiconductor chip, applying a second signal to the multichip package to test whether a crack defect exists in the second type semiconductor chip, and determining the multichip package to be non-defective when a current flowing in the second type semiconductor chip in response to the second signal is less than about 10 mA.

According to an exemplary embodiment of the inventive concept, there is provided a multichip package test system including a plurality of test apparatuses sequentially arranged in a test order, a plurality of chamber units for connecting semiconductor devices contained in a test tray to the plurality of test apparatuses, a transfer portion for carrying the test tray between the plurality of chamber units, and a controller for controlling the plurality of chamber units, wherein a multichip package includes a first type semiconductor chip and a second type semiconductor chip, a final test apparatus of the plurality of test apparatuses further includes an interface board for testing the multichip package, the interface board includes a first surface facing the multichip package and a second surface facing test terminals, the first surface includes upper terminals that are configured to be electrically connected to terminals of the multichip package, the second surface includes lower terminals that are configured to be electrically connected to the test terminals, and the upper terminals include a first upper terminal group for testing the first type semiconductor chip and a second upper terminal group for testing whether a crack defect exists in the second type semiconductor chip.

According to an exemplary embodiment of the inventive concept, there is provided an interface board having a first surface facing a multichip package to be tested and a second surface facing a test apparatus, wherein the first surface includes a first upper terminal group for testing a first type semiconductor chip of the multichip package and a second upper terminal group for testing whether a crack defect exists in a second type semiconductor chip of the multichip package, the second surface includes a first lower terminal group for connecting the first upper terminal group to the test apparatus and a second lower terminal for connecting the second upper terminal group to the test apparatus, and terminals of the second upper terminal group are electrically connected to one another in the interface board.

According to an exemplary embodiment of the inventive concept, there is provided an interface board comprising: a first terminal group and a second terminal group disposed on a first side of the interface board, wherein the first terminal group is configured to receive signals from a first type semiconductor device and the second terminal group is configured to receive signals from a second type semiconductor device; and a third terminal group and a fourth terminal disposed on a second side of the interface board, wherein the third terminal group corresponds to the first terminal group and the fourth terminal corresponds to the second terminal group, and wherein the fourth terminal is electrically connectable to a channel terminal of a test apparatus.

The above and other features of the inventive concept will become more clearly understood by describing in detail exemplary embodiments thereof with reference to the accompanying drawings in which:

FIG. 1 is a schematic plan view of a test handler unit;

FIG. 2 is a view of a test handler system according to an exemplary embodiment of the inventive concept;

FIG. 3 is a side view illustrating a method of testing semiconductor devices using an interface board in test equipment according to an exemplary embodiment of the inventive concept;

FIG. 4 is a side view illustrating an interface board according to an exemplary embodiment of the inventive concept, which is interposed between a test apparatus and a multichip package (MCP);

FIG. 5 is a flowchart for describing an MCP test method according to an exemplary embodiment of the inventive concept;

FIG. 6 is a side view illustrating a use state of an interface board according to an exemplary embodiment of the inventive concept;

FIG. 7 is a flowchart for describing a method of determining a crack defect of a second type semiconductor chip, according to an exemplary embodiment of the inventive concept;

FIGS. 8A and 8B are side views illustrating a test method using the same test apparatus and only replacing the interface boards according to an exemplary embodiment of the inventive concept;

FIGS. 9 and 10 are side views illustrating use states of interface boards according to exemplary embodiments of the inventive concept; and

FIG. 11 is a side view illustrating a user state of an interface board according to an exemplary embodiment of the inventive concept.

FIG. 1 is a schematic plan view of a test handler unit 1 .

Referring to FIG. 1 , the test handler unit 1 may include a loading unit H 1100 for loading semiconductor devices contained in a customer tray, into a test tray H 200 , a test unit H 1200 for connecting the semiconductor devices loaded in the test tray H 200 to test equipment H 400 , and an unloading unit H 1300 for classifying the tested semiconductor devices by grades according to a test result and loading the classified semiconductor devices into the customer tray.

The loading unit H 1100 performs a process of loading semiconductor devices to be tested into the test tray H 200 . The loading unit H 1100 may include a loading stacker H 1110 for storing a customer tray containing the semiconductor devices to be tested and a loading picker H 1120 for transferring the semiconductor devices to be tested from the customer tray to the test tray H 200 . After the semiconductor devices to be tested are loaded in the test tray H 200 , the test tray H 200 is transferred to the test unit H 1200 .

The test unit H 1200 performs a process of electrically connecting the semiconductor devices loaded in the test tray H 200 to the test equipment H 400 . Accordingly, as the semiconductor devices loaded in the test tray H 200 are electrically connected to the test equipment H 400 , the test equipment H 400 tests the semiconductor devices loaded in the test tray H 200 . When the testing of the semiconductor devices is completed, the test tray H 200 is transferred to the unloading unit H 1300 .

The unloading unit H 1300 performs an unloading process in which the tested semiconductor devices are removed from the test tray H 200 . The unloading unit H 1300 may include an unloading stacker H 1310 for storing the customer trays containing the tested semiconductor devices and an unloading picker H 1320 for transferring the tested semiconductor devices from the test tray H 200 to the customer tray. As the tested semiconductor devices are transferred to the customer tray, the test tray H 200 is empted, and then, the empty test tray H 200 is transferred back to the loading unit H 1100 .

As described above, the test handler unit 1 sequentially performs the loading process, the test process, and the unloading process while circularly transferring the test tray H 200 in one apparatus.

FIG. 2 is a view of a test handler system 2 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 2 , the test system 2 according to the present embodiment may include a conveyer unit S 2 for carrying a test tray S 100 , a plurality of chamber units S 3 for performing a test process of electrically connecting semiconductor devices contained in the test tray S 100 to test equipment S 300 , a controller S 4 for controlling each of the chamber units S 3 , and a sorting unit S 5 separate from the chamber units S 3 .

The sorting unit S 5 performs a process of loading semiconductor devices to be tested into the test tray S 100 and a process of unloading tested semiconductor devices from the test tray S 100 .

The conveyer unit S 2 carries the test tray S 100 between the chamber units S 3 and the sorting unit S 5 , which are separated from each other, such that the test process may be independently performed with respect to the performance of the loading process and the unloading process.

FIG. 3 is a side view illustrating a method of testing semiconductor devices using an interface board in the test equipment according to an exemplary embodiment of the inventive concept.

Referring to FIG. 3 , a tray 110 where a plurality of semiconductor devices D to be tested are disposed may be arranged above an interface board 120 on a test apparatus T. In this state, to enhance a close contact between the tray 110 , the interface board 120 , and the test apparatus T, a match plate 50 for applying a certain pressure from the above may be further provided.

The test apparatus T is configured to test particular properties of the semiconductor devices D. For example, only one or two or more of the properties may be tested.

As illustrated in FIG. 3 , a pressurization apparatus 60 applies pressure to the match plate 50 , and the pressure is transferred to the tray 110 so that the tray 110 may be made to closely contact the interface board 120 . Furthermore, the interface board 120 may be made to closely contact the test apparatus T due to the pressure.

When the pressure is released after the test ends, the interface board 120 and the test apparatus T may be detached from each other by an elastic force applied by the interface board 120 or the test apparatus T. Furthermore, the tray 110 may be configured to be detached from the interface board 120 .

FIG. 4 is a side view illustrating the interface board 120 according to an exemplary embodiment of the inventive concept, which is interposed between the test apparatus T and a multichip package (MCP) 130 .

Referring to FIG. 4 , the MCP 130 may include a first type semiconductor chip 130 D 1 and a second type semiconductor chip 130 D 2 . In an exemplary embodiment of the inventive concept, the first type semiconductor chip 130 D 1 may include a plurality of semiconductor chips. In an exemplary embodiment of the inventive concept, the second type semiconductor chip 130 D 2 may include a plurality of semiconductor chips.

Furthermore, the first type semiconductor chip 130 D 1 and the second type semiconductor chip 130 D 2 may not be electrically connected to each other in an MCP state. In other words, the first type semiconductor chip 130 D 1 may be connected to a first terminal group 130 _ 1 through its own unique connection, and the first terminal group 130 _ 1 may not be electrically connected to the second type semiconductor chip 130 D 2 . Likewise, the second type semiconductor chip 130 D 2 may be connected to a second terminal group 130 _ 2 through its own unique connection, and the second terminal group 130 _ 2 may not be electrically connected to the first type semiconductor chip 130 D 1 .

Accordingly, when any one of the first and second terminal groups 130 _ 1 and 130 _ 2 of the MCP 130 is designated, a semiconductor chip connected to the designated terminal group may be either the first type semiconductor chip 130 D 1 or the second type semiconductor chip 130 D 2 . Furthermore, the designated terminal group may be connected to only one of the first type semiconductor chip 130 D 1 and the second type semiconductor chip 130 D 2 .

Although FIG. 4 exemplarily illustrates a package in which the MCP 130 has a shape of a ball grid array (BGA), the present inventive concept is not limited thereto.

The first type semiconductor chip 130 D 1 and the second type semiconductor chip 130 D 2 may each be a volatile memory device or a non-volatile memory device. In an exemplary embodiment of the inventive concept, the first type semiconductor chip 130 D 1 and the second type semiconductor chip 130 D 2 may each be a dynamic random access memory (DRAM) device, a flash memory device, or a memory controller.

Furthermore, the first type semiconductor chip 130 D 1 and the second type semiconductor chip 130 D 2 may be different types of semiconductor devices.

For example, the first type semiconductor chip 130 D 1 may be a DRAM device and the second type semiconductor chip 130 D 2 may be a flash memory device. In an exemplary embodiment of the inventive concept, the first type semiconductor chip 130 D 1 may be a DRAM device and the second type semiconductor chip 130 D 2 may be a stack structure of a flash memory device and a controller chip. In an exemplary embodiment of the inventive concept, the first type semiconductor chip 130 D 1 may be a flash memory device and the second type semiconductor chip 130 D 2 may be a DRAM device. In an exemplary embodiment of the inventive concept, the first type semiconductor chip 130 D 1 may be a stack structure of a flash memory device and a controller chip and the second type semiconductor chip 130 D 2 may be a DRAM device.

In an exemplary embodiment of the inventive concept, the first terminal group 130 _ 1 may include a plurality of terminals. For example, the first terminal group 130 _ 1 may include power terminals 130 _ 1 _VCC and 130 _ 1 _VCCQ. Power may be applied to the power terminals 130 _ 1 _VCC and 130 _ 1 _VCCQ. Furthermore, the first terminal group 130 _ 1 may include channel terminals 130 _ 1 _CMD, 130 _ 1 _DAT, 130 _ 1 _CLK, and 130 _ 1 _ETC. Channel signals may be applied to the channel terminals 130 _ 1 _CMD, 130 _ 1 _DAT, 130 _ 1 _CLK, and 130 _ 1 _ETC. The channel signals may be applied at a voltage lower than the power voltage.

In an exemplary embodiment of the inventive concept, the second terminal group 130 _ 2 may include a plurality of terminals. For example, the second terminal group 130 _ 2 may include power terminals 130 _ 2 _VDD 1 , 130 _ 2 _VDD 2 , 130 _ 2 _VDDCA, and 130 _ 2 _VDDQ. In a general operation, power is applied to the power terminals 130 _ 2 _VDD 1 , 130 _ 2 _VDD 2 , 130 _ 2 _VDDCA, and 130 _ 2 _VDDQ, however, in a test, channel signals may be applied to the power terminals 130 _ 2 _VDD 1 , 130 _ 2 _VDD 2 , 130 _ 2 _VDDCA, and 130 _ 2 _VDDQ. Furthermore, the second terminal group 130 _ 2 may include channel terminals 130 _ 2 _CLK and 130 _ 2 _ETC. In the general operation, channel signals may be applied to the channel terminals 130 _ 2 _CLK and 130 _ 2 _ETC, however, the channel terminals 130 _ 2 _CLK and 130 _ 2 _ETC may be grounded during the test.

Although FIG. 4 illustrates an example in which the first terminal group 130 _ 1 and the second terminal group 130 _ 2 are solder balls, connectors having different shapes such as a land or a pin may be used in accordance with an exemplary embodiment of the inventive concept.

The first terminal group 130 _ 1 may correspond to a first upper terminal group 120 _U 1 provided on an upper surface of the interface board 120 . The first upper terminal group 120 _U 1 may include terminals 120 _U 11 , 120 _U 12 , 120 _U 13 , 120 _U 14 , 120 _U 15 , and 120 _U 16 corresponding to the terminals of the first terminal group 130 _ 1 .

The second terminal group 130 _ 2 may correspond to a second upper terminal group 120 _U 2 provided on the upper surface of the interface board 120 . The second upper terminal group 120 _U 2 may include terminals 120 _U 21 , 120 _U 22 , 120 _U 23 , 120 _U 24 , 120 _U 25 , and 120 _U 26 corresponding to the terminals of the second terminal group 130 _ 2 . The second upper terminal group 120 _U 2 may be provided to test only whether a crack defect exists in the second type semiconductor chip 130 D 2 .

Terminals of the first upper terminal group 120 _U 1 may correspond to terminals of a first lower terminal group 120 _L 1 provided on a lower surface of the interface board 120 . In other words, the terminals 120 _U 11 , 120 _U 12 , 120 _U 13 , 120 _U 14 , 120 _U 15 , and 120 _U 16 may correspond to terminals 120 _L 11 , 120 _L 12 , 120 _L 13 , 120 _L 14 , 120 _L 15 , and 120 _L 16 . The terminals 120 _U 11 , 120 _U 12 , 120 _U 13 , 120 _U 14 , 120 _U 15 , and 120 _U 16 of the first upper terminal group 120 _U 1 may be electrically connected to the terminals 120 _L 11 , 120 _L 12 , 120 _L 13 , 120 _L 14 , 120 _L 15 , and 120 _L 16 of the first lower terminal group 120 _L 1 , respectively, via a first internal line 120 _IC 1 .

Terminals of the second upper terminal group 120 _U 2 may correspond to terminals of a second lower terminal group 120 _L 2 provided on the lower surface of the interface board 120 .

Among the terminals of the second upper terminal group 120 _U 2 , the terminals 120 _U 21 , 120 _U 22 , 120 _U 23 , and 120 _U 24 corresponding to the power terminals 130 _ 2 _VDD 1 , 130 _ 2 _VDD 2 , 130 _ 2 _VDDCA, and 130 _ 2 _VDDQ of the second terminal group 130 _ 2 may be electrically connected to an identical single terminal 120 _L 22 . The terminals 120 _U 21 , 120 _U 22 , 120 _U 23 , and 120 _U 24 may be electrically connected to one another through a wiring inside the interface board 120 . Furthermore, the terminals 120 _U 21 , 120 _U 22 , 120 _U 23 , and 120 _U 24 may be electrically connected to the terminal 120 _L 22 via the wiring inside the interface board 120 , in other words, a second internal line 120 _IC 2 .

Among the terminals of the second upper terminal group 120 _U 2 , the terminals 120 _U 25 and 120 _U 26 corresponding to the channel terminals 130 _ 2 _CLK and 130 _ 2 _ETC of the second terminal group 130 _ 2 may be electrically connected to an identical single terminal 120 _L 21 . The terminals 120 _U 25 and 120 _U 26 may be electrically connected to each other via a wiring inside the interface board 120 . Furthermore, the terminals 120 _U 25 and 120 _U 26 may be electrically connected to the terminal 120 _L 21 via the wiring inside the interface board 120 .

The first lower terminal group 120 _L 1 of the interface board 120 may correspond to a first test terminal group TP_ 1 for testing the first type semiconductor chip 130 D 1 , among the terminals TP_ 1 and TP_ 2 of the test apparatus T. In other words, the terminals 120 _L 11 , 120 _L 12 , 120 _L 13 , 120 _L 14 , 120 _L 15 , and 120 _L 16 may correspond to the terminals TP_ 11 , TP_ 12 , TP_ 13 , TP_ 14 , TP_ 15 , and TP_ 16 . The terminals TP_ 11 , TP_ 12 , TP_ 13 , TP_ 14 , TP_ 15 , and TP_ 16 may apply various signals to test the first type semiconductor chip 130 D 1 .

The second lower terminal group 120 _L 2 of the interface board 120 may correspond to the second test terminal group TP_ 2 for testing whether a crack defect exists in the second type semiconductor chip 130 D 2 , among the terminals TP_ 1 and TP_ 2 of the test apparatus T. In other words, the terminals 120 _L 21 and 120 _L 22 may correspond to terminals TP_ 21 and TP_ 22 .

A channel signal to test whether a crack defect exists in the second type semiconductor chip 130 D 2 may be input to the channel terminal TP_ 22 . In an exemplary embodiment of the inventive concept, the terminal TP_ 21 may be grounded while the channel signal to test whether a crack defect exists in the second type semiconductor chip 130 D 2 is input to the channel terminal TP_ 22 .

Furthermore, while the channel signal to test whether a crack defect exists in the second type semiconductor chip 130 D 2 is input to the terminal TP_ 22 , the terminals TP_ 11 , TP_ 12 , TP_ 13 , TP_ 14 , TP_ 15 , and TP_ 16 of the first test terminal group TP_ 1 may be grounded.

The channel signal input to the terminal TP_ 22 to test whether a crack defect exists in the second type semiconductor chip 130 D 2 may have a voltage of about 0.3 V or more. If the second type semiconductor chip 130 D 2 does not have a crack defect, when a channel signal of about 0.3 V or more is applied to the terminal TP_ 22 and the terminals TP_ 11 , TP_ 12 , TP_ 13 , TP_ 14 , TP_ 15 , and TP_ 16 are grounded, substantially no current flows between any one of the terminals TP_ 11 , TP_ 12 , TP_ 13 , TP_ 14 , TP_ 15 , and TP_ 16 and the terminal TP_ 22 . However, if the second type semiconductor chip 130 D 2 has a crack defect, when a channel signal of about 0.3 V or more is applied to the terminal TP_ 22 and the terminals TP_ 11 , TP_ 12 , TP_ 13 , TP_ 14 , TP_ 15 , and TP_ 16 are grounded, a current of about 10 mA or more may flow therebetween. This is due to a short circuit that is generated between the terminal of the second type semiconductor chip 130 D 2 and the grounded terminals due to the crack.

Although the current flowing when a short circuit is generated may vary depending on the amount of applied power, the current may still be about 10 mA or more.

FIG. 5 is a flowchart for describing an MCP test method according to an exemplary embodiment of the inventive concept.

Referring to FIG. 5 , a plurality of tests, in other words, a test A 1 to a test A N , may be performed on the MCP 130 . The test A 1 to the test A N may include a test on the first type semiconductor chip 130 D 1 and a test on the second type semiconductor chip 130 D 2 in the MCP 130 .

Previously, when the first type semiconductor chip 130 D 1 undergoes a test A N+1 , which is the last test of all of the tests, and the first type semiconductor chip 130 D 1 has passed all of the tests, the first type semiconductor chip 130 D 1 is released as a passed product. However, even though the second type semiconductor chip 130 D 2 has passed all of the tests from the test A 1 to the test A N , the second type semiconductor chip may acquire a defect, such as a chip crack, when the test A N+1 is performed on the first type semiconductor chip 130 D 1 . Even when a process of testing the second type semiconductor chip 130 D 2 is inserted just before the test A N+1 of the first type semiconductor chip 130 D 1 , a crack defect may still be generated in the second type semiconductor chip 130 D 2 when performing the test A N+1 on the first type semiconductor chip 130 D 1 . Furthermore, even when the process of testing the second type semiconductor chip 130 D 2 is inserted just after the test A N+1 of the first type semiconductor chip 130 D 1 , the first type semiconductor chip 130 D 1 itself may acquire a crack defect while testing the second type semiconductor chip 130 D 2 .

In an exemplary embodiment of the inventive concept, after the test A N+1 is performed on the first type semiconductor chip (P 110 ), in the same test apparatus, without moving a tray, a channel signal of a relatively low voltage is applied to determine only the existence of a leakage current (P 120 ). If there is a leakage current, it may be determined that a crack defect exists in the second type semiconductor chip 130 D 2 . The MCP 130 may be directly released without a further test just after passing the above test method (P 100 ).

Furthermore, since in the operation P 100 only the existence of a crack defect is tested with respect to the second type semiconductor chip 130 D 2 , all other tests for the second type semiconductor chip 130 D 2 may have already been performed by other test apparatuses prior to the operation P 100 . In other words, the test A 1 to the test A N may have already been performed on the second type semiconductor chip 130 D 2 upstream before the test A N+1 .

The interface board 120 described above with reference to FIG. 4 may be used in the operation P 100 of FIG. 5 .

FIG. 6 is a side view illustrating a use state of an interface board 120 A according to an exemplary embodiment of the inventive concept.

Referring to FIG. 6 , an MCP 130 is arranged above the test apparatus T with an interface board 120 A interposed therebetween. The MCP 130 may include the first type semiconductor chip 130 D 1 and the second type semiconductor chip 130 D 2 . In addition, the MCP 130 may include the first terminal group 130 _ 1 and the second terminal group 130 _ 2 on a lower surface thereof. Since a connection relationship therebetween is described above with reference to FIG. 4 , redundant descriptions thereof are omitted herein.

The first upper terminal group 120 _U 1 corresponding to the first terminal group 130 _ 1 is provided on an upper surface of the interface board 120 A. In addition, the second upper terminal group 120 _U 2 corresponding to the second terminal group 130 _ 2 is provided on the upper surface of the interface board 120 A.

The first lower terminal group 120 _L 1 corresponding to the first upper terminal group 120 _U 1 is provided on the lower surface of the interface board 120 A. In addition, the second lower terminal 120 _L 21 corresponding to the second upper terminal group 120 _U 2 is provided on the lower surface of the interface board 120 A.

Unlike the embodiment of FIG. 4 , in the embodiment of FIG. 6 , the terminals of the second upper terminal group 120 _U 2 are all connected to the second lower terminal 120 _L 21 , in other words an identical single terminal, regardless of whether the second lower terminal 120 _L 21 is a power terminal or not. The terminals of the second upper terminal group 120 _U 2 may be electrically connected to one another inside the interface board 120 A.

The first lower terminal group 120 _L 1 may correspond to the terminals TP_ 1 of the test apparatus T. The second lower terminal 120 _L 21 may correspond to the terminal TP_ 21 of the test apparatus T. The second upper terminal group 120 _U 2 may be electrically connected to an identical single terminal via the second lower terminal 120 _L 21 .

The terminal TP_ 21 of the test apparatus T may be a channel terminal. Accordingly, a channel signal may be input to the second type semiconductor chip 130 D 2 via the terminal TP_ 21 and the second lower terminal 120 _L 21 . As described above, the channel signal may have a voltage of about 0.3 V or more.

After the test for the first type semiconductor chip 130 D 1 is completed, the terminal TP_ 1 is grounded so that the first lower terminal group 120 _L 1 and the first upper terminal group 120 _U 1 may be grounded and consequently the first terminal group 130 _ 1 may be grounded. In this state, a channel signal may be applied to the terminal TP_ 21 .

When the second type semiconductor chip 130 D 2 does not have a crack, a current of the second type semiconductor chip 130 D 2 detected by an ammeter Amp connected to the terminal TP_ 21 is within several milliamperes (mA). When the current detected by the ammeter Amp is substantially within about 10 mA, the second type semiconductor chip 130 D 2 may be determined to be a non-defective product.

When the second type semiconductor chip 130 D 2 has a crack, a leakage current is generated at a grounded point from the terminal TP_ 21 of the second type semiconductor chip 130 D 2 , and thus, a slight current flow may be detected by the ammeter Amp. In other words, the ammeter Amp may detect a current of about 10 mA or more. In this case, the second type semiconductor chip 130 D 2 is determined to have a crack.

FIG. 7 is a flowchart for describing a method of determining a crack defect of the second type semiconductor chip 130 D 2 , according to an exemplary embodiment of the inventive concept. The operations of FIG. 7 may correspond to the operation P 100 of FIG. 5 .

Referring to FIGS. 4, 5, and 7 , the MCP 130 may be arranged above the test apparatus T by interposing the interface board 120 for an MCP test therebetween (P 210 ).

The test apparatus T is a final test apparatus of a plurality of test apparatuses that the MCP 130 undergoes. The interface board 120 is an interface board customized for the test apparatus T.

The test apparatus T is configured to test a particular one of the properties of the first type semiconductor chip 130 D 1 with respect to the MCP 130 . Furthermore, the test apparatus T may be an apparatus previously used to test the particular properties of the first type semiconductor chip 130 D 1 .

FIGS. 8A and 8B are side views illustrating a test method using the same test apparatus T and only replacing interface boards 120 conv and 120 ex according to an exemplary embodiment of the inventive concept.

Referring to FIG. 8A , the MCP 130 may include a first terminal group 130 _ 1 A corresponding to the first type semiconductor chip 130 D 1 and a second terminal group 130 _ 2 A corresponding to the second type semiconductor chip 130 D 2 .

The interface board 120 conv may include a first upper terminal group 120 _U 1 A, and a second upper terminal group 120 _U 2 A, on an upper surface thereof, respectively corresponding to the first terminal group 130 _ 1 A and the second terminal group 130 _ 2 A.

The interface board 120 conv has a first lower terminal group 120 _L 1 A corresponding to the first upper terminal group 120 _U 1 A, and the first lower terminal group 120 _L 1 A corresponds to terminals TP of the test apparatus T.

The second upper terminal group 120 _U 2 A on the upper surface of the interface board 120 conv may be grounded.

Of the terminals TP that are electrically connected to the first type semiconductor chip 130 D 1 via the interface board 120 conv , there is a channel terminal TP_minor that is not important or is unnecessary for the test performed by a final test apparatus. When the channel terminal TP_minor is used for the test performed by the final test apparatus, as illustrated in FIG. 8A , the channel terminal TP_minor is connected to terminals of the interface board 120 conv . However, this may not be the case if a test using the channel terminal TP_minor was performed in a test apparatus preceding the final test by the final test apparatus.

It is assumed in FIG. 8B that a test using the channel terminal TP_minor is performed by a preceding test apparatus, and thus, the channel terminal TP_minor is not needed for the test performed by the final test apparatus. In this case, in a modified interface board 120 ex , the second upper terminal group 120 _U 2 A may be connected to the second lower terminal 120 _L 21 . The second lower terminal 120 _L 21 may be a terminal corresponding to the channel terminal TP_minor among the terminals belonging to the first lower terminal group 120 _L 1 A according to the embodiment described above with reference to FIG. 8A .

As illustrated in FIG. 8B , the second upper terminal group 120 _U 2 A is electrically connected to the second lower terminal 120 _L 21 that is a common single terminal in the interface board 120 ex . Furthermore, the second lower terminal 120 _L 21 may be electrically connected to the terminal TP_ 21 that is the channel terminal TP_minor of the test apparatus T. The channel terminal TP_ 21 is a terminal for inputting a signal having a voltage lower than power.

As illustrated in FIG. 8B , the channel terminal TP_ 21 (TP_minor) is used for testing the second type semiconductor chip 130 D 2 after the change of the interface board. In other words, the channel terminal TP_ 21 may be electrically connected to the second type semiconductor chip 130 D 2 via the second lower terminal 120 _L 21 and the second upper terminal group 120 _U 2 A.

Referring back to FIGS. 4, 5 , and. 7 , a first signal to test the first type semiconductor chip 130 D 1 may be applied to the MCP 130 (P 220 ). The test of the first type semiconductor chip 130 D 1 may be, for example, a functional test, a direct current (DC) test, or an alternating current (AC) test, but the present inventive concept is not limited thereto.

The functional test may be a test to verify whether a semiconductor device operates corresponding to an intended logic function. The DC test may be a current (IDD) test, an electrostatic discharge (ESD) test, or an electrical overstress (EOS) test, but the present inventive concept is not limited thereto. The AC test may be a test related to a timing item, but the present inventive concept is not limited thereto.

When the first type semiconductor chip 130 D 1 passes the present test after applying the first signal to the first type semiconductor chip 130 D 1 , a second signal is applied to the MCP 130 to test whether a crack defect exists in the second type semiconductor chip 130 D 2 (P 230 ).

To accomplish this, the second signal may be applied to the channel terminal TP_ 21 (see FIG. 8B ). The second signal may have a voltage lower than a generally supplied power, for example, a voltage of about 0.3 V or more. The second signal is sequentially transmitted to the second lower terminal 120 _L 21 and the second upper terminal group 120 _U 2 A via the channel terminal TP_ 21 , and then, to the second type semiconductor chip 130 D 2 via a power terminal of the second terminal group 130 _ 2 A. The second signal may be input to the second type semiconductor chip 130 D 2 via the power terminal of the second type semiconductor chip 130 D 2 .

In this state, the first terminal group 130 _ 1 A and/or the first lower terminal group 120 _L 1 A related to the first type semiconductor chip 130 D 1 may be all grounded.

As described above, when the second type semiconductor chip 130 D 2 has no crack defect, a current flows as low as within several milliamperes in response to the second signal. In other words, when the current of the second terminal group 130 _ 2 A, which is the power terminal of the second type semiconductor chip 130 D 2 , is as low as within several milliamperes (P 240 ), the MCP 130 may be determined to be a non-defective product (P 250 ). In this state, the current flowing as low as within several milliamperes means a current less than about 10 mA, where a difference of about 0.5 mA to 8 mA exists according to the type of device.

When a current of about 10 mA or more flows in the second type semiconductor chip 130 D 2 in response to the second signal (P 240 ), the MCP 130 may be determined to be defective (P 260 ).

FIG. 9 is a side view illustrating a use state of an interface board 120 B according to an exemplary embodiment of the inventive concept.

Referring to FIG. 9 , an MCP 130 A may include the first type semiconductor chip 130 D 1 , the second type semiconductor chip 130 D 2 , and a third type semiconductor chip 130 D 3 . In an exemplary embodiment of the inventive concept, the first type semiconductor chip 130 D 1 may include a plurality of semiconductor chips. In an exemplary embodiment of the inventive concept, the second type semiconductor chip 130 D 2 may include a plurality of semiconductor chips. In an exemplary embodiment of the inventive concept, the third type semiconductor chip 130 D 3 may include a plurality of semiconductor chips.

Furthermore, the first type semiconductor chip 130 D 1 , the second type semiconductor chip 130 D 2 , and the third type semiconductor chip 130 D 3 in the MCP 130 A may not be electrically connected to one another. In other words, the first type semiconductor chip 130 D 1 may be connected to a first terminal group 130 _ 1 B through its own unique connection, and the first terminal group 130 _ 1 B may not be electrically connected to the second type semiconductor chip 130 D 2 and the third type semiconductor chip 130 D 3 . Likewise, the second type semiconductor chip 130 D 2 is connected to a second terminal group 130 _ 2 B through its own unique connection. The second terminal group 130 _ 2 B may not be electrically connected to the first type semiconductor chip 130 D 1 and the third type semiconductor chip 130 D 3 . Furthermore, the third type semiconductor chip 130 D 3 is connected to a third terminal group 130 _ 3 B through its own unique connection, and the third terminal group 130 _ 3 B may not be electrically connected to the first type semiconductor chip 130 D 1 and the second type semiconductor chip 130 D 2 .

Accordingly, when any one of the terminals of the first to third terminal groups 130 _ 1 B, 130 _ 2 B, and 130 _ 3 B provided under the MCP 130 A is designated, the semiconductor chip connected to the designated terminal may be any one of the first type semiconductor chip 130 D 1 , the second type semiconductor chip 130 D 2 , and the third type semiconductor chip 130 D 3 . Furthermore, the designated terminal may be connected to only one of the first type semiconductor chip 130 D 1 , the second type semiconductor chip 130 D 2 , and the third type semiconductor chip 130 D 3 .

The first type semiconductor chip 130 D 1 , the second type semiconductor chip 130 D 2 , and the third type semiconductor chip 130 D 3 may each be volatile memory devices or non-volatile memory devices. In an exemplary embodiment of the inventive concept, the first type semiconductor chip 130 D 1 , the second type semiconductor chip 130 D 2 , and the third type semiconductor chip 130 D 3 may each be DRAM devices, flash memory devices, or memory controllers. Furthermore, the first type semiconductor chip 130 D 1 , the second type semiconductor chip 130 D 2 , and the third type semiconductor chip 130 D 3 may be different types of semiconductor devices.

For example, the first type semiconductor chip 130 D 1 may be a DRAM device, the second type semiconductor chip 130 D 2 may be a flash memory device, and the third type semiconductor chip 130 D 3 may be a controller chip. In an exemplary embodiment of the inventive concept, the first type semiconductor chip 130 D 1 may be a DRAM device, the second type semiconductor chip 130 D 2 may be a controller chip, and the third type semiconductor chip 130 D 3 may be a flash memory device.

The first terminal group 130 _ 1 B may correspond to a first upper terminal group 120 _U 1 B provided on an upper surface of the interface board 120 B. The second terminal group 130 _ 2 B may correspond to a second upper terminal group 120 _U 2 B provided on the upper surface of the interface board 120 B. The third terminal group 130 _ 3 B may correspond to a third upper terminal group 120 _U 3 B provided on the upper surface of the interface board 120 B.

The second upper terminal group 120 _U 2 B may be used to test only whether the second type semiconductor chip 130 D 2 has a crack defect. The third upper terminal group 120 _U 3 B may be used to test only whether a crack defect exists in the third type semiconductor chip 130 D 3 .

Terminals of the first upper terminal group 120 _U 1 B may respectively correspond to terminals of a first lower terminal group 120 _L 1 B provided on a lower surface of the interface board 120 B. Terminals of the second upper terminal group 120 _U 2 B may respectively correspond to the second lower terminal 120 _L 21 provided on the lower surface of the interface board 120 B. Terminals of the third upper terminal group 120 _U 3 B may respectively correspond to a third lower terminal 120 _L 31 provided on the lower surface of the interface board 120 B.

The first lower terminal group 120 _L 1 B of the interface board 120 B may correspond to the first test terminal group TP_ 1 for testing the first type semiconductor chip 130 D 1 , among the terminals TP of the test apparatus T.

The second lower terminal 120 _L 21 and the third lower terminal 120 _L 31 of the interface board 120 B may respectively correspond to the channel terminal TP_ 21 and a channel terminal TP_ 31 among the terminals TP of the test apparatus T.

A second signal that is a channel signal to test whether a crack defect exists in the second type semiconductor chip 130 D 2 may be input to the channel terminal TP_ 21 . A third signal that is a channel signal to test whether a crack defect exists in the third type semiconductor chip 130 D 3 may be input to the channel terminal TP_ 31 . The first lower terminal group 120 _L 1 B may be entirely grounded.

FIG. 10 is a side view illustrating a use state of an interface board 120 C according to an exemplary embodiment of the inventive concept.

Referring to FIG. 10 , both of a second upper terminal group 120 _U 2 C and a third upper terminal group 120 _U 3 C are connected to the second lower terminal 120 _L 21 . Unlike the embodiment of FIG. 9 , the third lower terminal 120 _L 31 is not provided.

The first terminal group 130 _ 1 B may correspond to a first upper terminal group 120 _U 1 C provided on an upper surface of an interface board 120 C. The second terminal group 130 _ 2 B may correspond to the second upper terminal group 120 _U 2 C provided on the upper surface of the interface board 120 C. The third terminal group 130 _ 3 B may correspond to the third upper terminal group 120 _U 3 C provided on the upper surface of the interface board 120 C.

The second upper terminal group 120 _U 2 C may be used to test only whether a crack defect exists in the second type semiconductor chip 130 D 2 . The third upper terminal group 120 _U 3 C may be used to test only whether a crack defect exists in the third type semiconductor chip 130 D 3 .

Terminals of the first upper terminal group 120 _L 1 C may respectively correspond to terminals of a first lower terminal group 120 _L 1 C provided on a lower surface of the interface board 120 C. Both of the second upper terminal group 120 _U 2 C and the third upper terminal group 120 _U 3 C may be connected to the second lower terminal 120 _L 21 . The second upper terminal group 120 _U 2 C and the third upper terminal group 120 _U 3 C may be electrically connected to each other inside the interface board 120 C.

The first lower terminal group 120 _L 1 C of the interface board 120 C may correspond to the first test terminal group TP_ 1 for testing the first type semiconductor chip 130 D 1 , among the terminals TP of the test apparatus T. The second lower terminal 120 _L 21 of the interface board 120 C may correspond to the channel terminal TP_ 21 among the terminals TP of the test apparatus T.

A second signal that is a channel signal to test whether a crack defect exists in the second type semiconductor chip 130 D 2 and the third type semiconductor chip 130 D 3 may be input to the channel terminal TP_ 21 .

Since both of the second upper terminal group 120 _U 2 C and the third upper terminal group 120 _U 3 C are connected to the second lower terminal 120 _L 21 in the interface board 120 C, the interface board 120 C may be manufactured in a simpler structure and at a lower cost, compared to the interface board 120 B of FIG. 9 .

FIG. 11 is a side view illustrating a user state of an interface board 120 D according to an exemplary embodiment of the inventive concept.

Referring to FIG. 11 , a second upper terminal group 120 _U 2 D and a power terminal 120 _U 1 D of a first upper terminal group 120 _U 1 D are connected to the second lower terminal 120 _L 21 using a switch device 120 D_SW, which is different from the embodiment of FIG. 9 .

The first terminal group 130 _ 1 D may correspond to the first upper terminal group 120 _U 1 D provided on an upper surface of the interface board 120 D. The second terminal group 130 _ 2 D may correspond to the second upper terminal group 120 _U 2 D provided on the upper surface of the interface board 120 D. Among the first terminal group 130 _ 1 D, a power terminal 130 _ 1 'D may correspond to the power terminal 120 _U 1 'D of the first upper terminal group 120 _U 1 D provided on the interface board 120 D. The second upper terminal group 120 _U 2 D and the power terminal 120 _U 1 'D of the first upper terminal group 120 _U 1 D correspond to the second lower terminal 120 _L 21 via the switch device 120 D_SW.

The second upper terminal group 120 _U 2 D may be provided to test only whether a crack defect exists in the second type semiconductor chip 130 D 2 .

Terminals of the first upper terminal group 120 _U 1 D may respectively correspond to terminals of a first lower terminal group 120 _L 1 D provided on a lower surface of the interface board 120 D. The second upper terminal group 120 _U 2 D and the power terminal 120 _U 1 'D of the first upper terminal group 120 _U 1 D may be connected to the second lower terminal 120 _L 21 by the switch device 120 D_SW.

The first lower terminal group 120 _L 1 D of the interface board 120 D may correspond to the first test terminal group TP_ 1 to test the first type semiconductor chip 130 D 1 among the terminals TP of the test apparatus T. The power terminal 120 _U 1 'D of the first upper terminal group 120 _U 1 D may connect to the second lower terminal 120 _L 21 by the switch device 120 D_SW. The second lower terminal 120 _L 21 of the interface board 120 D may correspond to a power terminal TP_ 21 of the terminals TP of the test apparatus T.

The second upper terminal group 120 _U 2 D to test whether a crack defect exists in the second type semiconductor chip 130 D 2 may correspond to the power terminal TP_ 21 among the terminals TP of the test apparatus T as the switch device 120 D_SW is connected thereto.

In the interface board 120 D, the second upper terminal group 120 _U 2 D and the power terminal 120 _U 1 'D of the first upper terminal group 120 _U 1 D are selectively connected to the second lower terminal 120 _L 21 by the switch device 120 D_SW.

According to the above-described embodiments, whether a crack defect exists in a semiconductor chip may be easily determined by just a simple leak current test without having to transfer the semiconductor chip. Accordingly, an efficiency of an individual test is maintained in the final operation of an existing test method.

Furthermore, according to the above-described embodiments, the test cost may be reduced because the existing test equipment may be used as is by replacing just the interface board.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.