Fractional frequency clock divider with direct division

Many communications and processing devices include circuitry that operates according to different required clock input signals. A viable choice would be a clock tree generating all the required clock frequencies from one single input reference clock. Typically this can be realized by feeding the reference clock to a PLL to create and intermediate high frequency clock signal followed by one or more frequency dividers dividing the high frequency clock to generate lower frequency clock signals for use by the individual circuits. Some frequency divider applications require an integer relationship between the input frequency and the output frequency, where the frequency divider circuit is a counter providing a divider ratio of 1/K, where K is an integer. However, new applications often require one or more output frequencies that do not have an integer relationship to the input clock frequency. Certain fractional divider architectures provide integer fraction output frequencies, such as ⅔, or generally J/K where J and K are small integers to allow for practical intermediate frequencies. Many applications, moreover, require clock tree solutions where several output clocks are generated from one single reference clock, with no restriction on the frequency of the output clock signals. For instance, certain applications involve different data interfaces residing in a single device, each requiring a different clock frequency. In addition, many clock divider applications require output clock signals of high quality with very low level of phase noise, low time domain jitter and control of unwanted spurs, in addition to low power consumption and complexity in terms of occupied area.

Single and multichannel fraction frequency dividers are presented using direct division to facilitate low time domain integrated jitter and controlled noise, without excessive power consumption or large circuit area. Disclosed examples include fractional frequency divider circuits, including a counter or dynamic divider circuit to provide phase shifted pulse output signals in response to counting of an adjustable integer number N K cycles of an input clock signal, an output circuit to provide an output clock signal having an edge with digitally adjustable phase/delay with respect to its input reference phase provided by the dynamic frequency divider (counter), as well as a delta-sigma modulator (DSM), clocked by the dynamic divider output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the dynamic divider, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals. In one example, the phase adjustment value is used as an index into a lookup table or other code mapper or correction mapper circuit to drive first and second digital to analog converters (DACs) to provide analog output signals to a phase interpolator to control the position of the first edge of the output signal between the first edges of the pulse output signals. In certain examples, the phase interpolator circuit includes a slope adjustment circuit to generate sloped signals according to the edges of the pulse output signals, and the phase interpolator circuit generates the output clock signal edges according to the second sloped signals. The output circuit in certain examples includes divider divide by 2 frequency divider circuit to provide a second output clock signal at a second output frequency to facilitate uniform output clock duty cycle.

FIG. 1 shows a PLL-based multichannel frequency divider circuit using a single PLL.

FIG. 2 shows a multichannel fractional frequency divider integrated circuit.

FIG. 3 shows a fractional frequency divider circuit.

FIG. 4 is a signal diagram showing signal waveforms in the fractional frequency divider circuit of FIG. 3 .

FIG. 5 shows further details of an example phase accumulator in the fractional frequency divider circuit of FIG. 3 .

In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are intended to be inclusive in a manner similar to the term “comprising”, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections.

FIG. 1 shows a PLL-based multichannel frequency divider circuit 100 with a crystal 102 providing a clock signal to an input 104 of a single high frequency PLL 106 that provides a high frequency input 108 to multiple fractional frequency generators (FFGs) 110 - 1 , 110 - 2 , . . . , 110 -J. The FFGs 110 have corresponding outputs 112 - 1 , 112 - 2 . . . , 112 -J respectively providing output signals K 1 F 1 , K 1 F 2 , . . . , KJFJ with frequencies at or near the input clock frequency but slightly shifted up or down in frequency. Integer divider circuits 114 - 1 , 114 - 2 , . . . , 114 -J divide the corresponding FFG output signals K 1 F 1 , K 1 F 2 , . . . , KJFJ by corresponding integers K- 1 , K 2 , . . . , KJ and provide output signals at divider outputs 116 - 1 , 116 - 2 , . . . , 116 -J at corresponding frequencies F 1 , F 2 , . . . FJ. In this manner, the divider circuit 100 uses integer frequency division to obtain the final output frequencies. The drawback of this approach is that the final divider circuits 114 fold a large portion of the PPG phase noise and its undesired spurs back to the band of frequency offsets that are required to be clean to meet many application specifications. In addition, the FFG circuits 110 and the integer divider circuits 114 in FIG. 1 all operate off the high frequency input clock, and thus are subject to poor power efficiency for high input clock frequencies. Moreover, high-speed circuit components are required for the FFG and the divider circuits 110 and 114 .

Referring now to FIGS. 2-4 , FIG. 2 shows an efficient and simple frequency divider system 200 using a direct fractional frequency divider (DFFD) approach. A high frequency crystal clock source 202 , for example 2.5-5.0 GHz, provides a clock signal CLK to an input 204 of a PLL 206 . The PLL 206 has an output 208 providing an input clock signal CLKIN to one or more fractional frequency divider (FFD) circuits 210 - 1 , 210 - 2 , . . . , 210 -J having outputs 212 - 1 , 212 - 2 , . . . , 212 -J. The outputs 212 individually provide a corresponding output signal CLKOUT- 1 , CLKOUT- 2 , . . . , CLKOUT-J at corresponding output frequencies FOUT 1 , FOUT 2 , . . . , FOUTJ. The circuit 200 advantageously avoids the use of output dividers as was the case in FIG. 1 . The divider circuit 200 mitigates or avoids phase noise and spur folding associated with the integer dividers 114 in FIG. 1 by eliminating redundantly generated high quality clock edges by output divider circuitry. The circuit 200 and FIG. 2 also provides fractional frequency generation without requiring complex circuitry as was done in the past. In addition the proposed solution is capable of supporting maximum output frequency compared to the traditional approach of FIG. 1 , due to relaxing the speed requirement on a majority of the components within each fractional frequency divider block.

In some examples, the divider circuit 200 is fabricated in an integrated circuit (IC) 201 , and may include one or more FFD circuits 210 . In one example, the PLL circuit 206 is included in the IC 201 , and a terminal (e.g., IC pad or pin) 203 provides connectivity to receive the clock signal CLK from an external circuit (e.g., a crystal as shown, a voltage-controlled oscillator (VCO), or other clock source), and the PLL 206 provides the input clock signal CLKIN to one or more FFD circuits 210 . In another example, the PLL 206 is external to the IC 201 , and the input pad 203 provides the input clock signal CLKIN to the inputs of the FFD circuit or circuits 210 . In certain implementations, output terminals are provided to deliver the output clock signals CLKOUT to external circuitry (not shown).

FIG. 3 shows further details of an example FFD circuit 210 which includes a dynamic divider circuit 302 , an output circuit 310 , a delta sigma modulator (DSM) 320 , and a phase accumulator circuit 326 . FIG. 4 shows a signal diagram 400 including signal waveforms in the PFD circuit 210 of FIG. 3 . The dynamic divider 302 provides the dynamic divider circuit 302 includes an input 304 to receive the input clock signal CLKIN having an input frequency FIN. The dynamic divider circuit 302 in one example provides phase shifted first and second the pulse output signals P 1 and P 2 at outputs 306 and 308 , respectively, in response to counting of an adjustable integer number N K cycles of an input clock signal CLKIN. The dynamic divider circuit 302 includes a first output 306 that provides the first pulse output signal P 1 . FIG. 4 shows the first pulse output signal P 1 at 402 , including a first (e.g., rising) edge 404 a and a second (e.g., falling) edge 404 b . The dynamic divider circuit 302 in one example is a counter circuit that implements a divide by “N K ” edge counter function and generates first edge 404 a of the signal P 1 following or in response to the N K th rising edge of the input clock signal CLKIN. In one example, a second output 308 of the dynamic divider circuit 302 provides the second pulse output signal P 2 , shown as signal 404 in FIG. 4 . The signal P 2 includes a first (e.g., rising) edge 406 a and a second (e.g., falling) edge 406 b . The rising first edge 406 a of the signal P 2 follows a first rising edge of the N K th falling edge of the input clock signal CLKIN. The dynamic divider circuit 302 also includes a control input to receive a divisor input signal N K representing the adjustable integer number N K .

The dynamic divider 302 in certain examples acts as an edge counter, which counts only rising edges of the input clock. In other examples, the dynamic divider circuits counts only the falling edges of the input clock. In other examples, the dynamic divider circuit 302 counts all the edges (including rising/falling edges). Any mode of operation of the dynamic divider can be used. The dynamic divider circuit 302 can also include duty cycle control circuitry in order to provide the pulse signals P 1 and P 2 with a consistent duty cycles. In the illustrated example, the dynamic divider circuit 302 provides the pulse output signals P 1 and P 2 having pulse widths greater than a full cycle of the input clock signal CLKIN (signal 402 in FIG. 4 ). In other possible implementations, the dynamic divider circuit 302 provides the first and second pulse output signals P 1 and P 2 with falling first edges 406 a and 406 a , along with rising second edges 406 b and 406 b . In other possible implementations, the dynamic divider circuit 302 provides only the first pulse P 1 as input to the phase interpolator 340 , and the output circuit 310 uses this input to create its output pulse with a digitally adjustable delay/phase. In such an example, the second pulse P 2 can be used as a clock signal as depicted in FIG. 3 . In certain implementations, the dynamic divider circuit provides extra timing control signals (not shown) to the output circuit for clocking, setting, and resetting its constituent circuit components.

The output circuit 310 includes a first output 312 that provides a first output clock signal CLKOUT, illustrated as signal 408 in FIG. 4 . The first output clock signal CLKOUT has a first output frequency FOUT less than FIN the input frequency, and CLKOUT includes first and second (e.g., rising and falling) edges 408 a and 408 b . In addition, the CLKOUT signal output circuit 310 provides the first edge 408 a of the CLKOUT signal between the first edges 404 a and 406 a of the pulse output signals P 1 and P 2 . In some examples, the output circuit 310 includes a duty cycle restoration circuit 315 that provides the CLKOUT signal according to the output of the phase interpolator circuit 340 . In this example, the rising edge 408 a is accurately created by the phase interpolator circuit 340 according to jitter and spur requirements of the targeted applications, while the falling edge 408 b can created less accurately by duty cycle restoration block only satisfying the duty cycle requirements of the targeted application. In certain examples, the output circuit 310 avoids using duty cycle restoration 315 , and instead incorporates an integer divider circuit 314 , such as a divide by 2 circuit in one example to produce output CLKOUTa instead of CLKOUT. The integer divider circuit 314 receives the output from the phase interpolator circuit 340 and includes a second output 312 a that provides a second output clock signal CLKOUTa at a second output frequency less than the first output frequency FOUT (e.g., FOUT/2). in other examples different integer dividers 314 , for example, divide by 4, divide by 8, etc. is also possible. FIG. 4 illustrates the CLKOUTa signal 410 including a first (e.g., rising) edge 410 a and a second (e.g., falling) edge 410 b.

The DSM circuit 320 includes a clock input to receive the second pulse output signal P 2 , and thus operates at a lower frequency than the input frequency FIN. The DSM 320 includes an output 322 that provides a DSM output value m K , and a second input to receive a first predetermined value α. The FFD circuit 210 also implements a summation function 324 , for example, and adder circuit or programming instructions, to provide a input value SI representing the sum of the DSM output value m K and the second predetermined value M P . The first predetermined value α can be programmable or configurable in certain implementations. For example, the IC 201 in FIG. 2 includes terminals 211 as one or more configuration input to receive configuration signals or values (illustrated as “CONFIG” in FIG. 2 ) allowing a user to set or configure the first predetermined value α as well as a second predetermined value M P and a third predetermined value M C as discussed further below. These values, in turn, set the fractional divider ratio of the FFD circuit 210 .

The phase accumulator 326 includes an input to receive the step input value SI, as well as a first output 328 a coupled to the control input of the divider circuit 302 to provide the divisor input signal N K to set the adjustable integer counter value used to count the edges (rising or fallings edges or both) of the input clock signal CLKIN. In addition, the phase accumulator 326 includes a second output 328 b which provides a multibit digital phase adjustment value b K to the output circuit 310 to control the position of the first edge 408 a of the output clock signal CLKOUT between the first edges 404 a and 406 a of the pulse output signals P 1 and P 2 . In general, the phase accumulator 326 provides an output having B bits, where B=10 in one example.

The output circuit 310 uses the phase adjustment value b K in order to perform phase interpolation to generate the edges of the first output clock signal CLKOUT at an interpolated temporal location or point between the edges 404 a and 406 a of the P 1 and P 2 signals. In this manner, the FFD circuit 210 provides a wide range of possible fractional divisor or divider ratios to provide an output clock at any desired frequency. In the example of FIG. 3 , the first output clock signal frequency FOUT=FIN/(M C +(M P +α)2 −B ) and the second output clock frequency is FOUT/2. As seen in FIG. 3 , one example of the output circuit 310 includes a code mapping circuit or correction mapper circuit 330 (labelled “CODE MAPPER” in the drawing), for example, a lookup table (LUT) that provides one or more multi-bit output values 332 (shown as a single value in FIG. 3 ) according to the phase adjustment value b K , as well as one or more analog to digital converters (DACs, not shown) that provide analog signals to a phase interpolator circuit 340 . In practice, the phase interpolator circuit 340 may suffer from nonlinearities. The code mapping circuit 330 and the DAC(s) provide a calibration mechanism to compensate for such phase interpolator nonlinearity. In one example for a 10-bit phase interpolator 326 , 13-bit DACs can be used, and an example look up table implementation includes 1024 rows, where each row is a 13-bit code to be used by one of the two DACs. The code mapping circuit 330 can be programmed with suitable values to calibrate the circuit 210 for any nonlinearities of the phase interpolator 340 and/or the DACs. In another example the code mapping may use much small memory size than a direct LUT approach would use. This form of mapping can be done by reading a correction sequence from a smaller memory and modifying the input code by using the correction sequence to create the final output code. The phase interpolator circuit 340 is coupled to the dynamic divider circuit 302 to receive the first and second pulse output signals P 1 and P 2 , and includes an output used to generate the first output clock signal CLKOUT. In operation, the phase interpolator circuit 340 controls the position of the first edge 408 a of the output signal CLKOUT between the first edges 404 a , 406 a of the pulse output signals P 1 and P 2 according to analog output signals from first and second DACs. In certain examples, the code mapping circuit 330 provides the multibit outputs having a longer bit blanks than the phase adjustment value b K . For example, the code mapping circuit 330 in FIG. 3 provides 13-bit outputs 332 to the DACs based on a 10-bit phase adjustment value b K from the phase accumulator circuit 326 .

In operation, the phase accumulator circuit 326 provides the phase adjustment value b K to the output circuit 310 , which adjusts the location of the output clock edge 408 a within a phase interpolation (PI) range 412 between the first edges 404 a and 406 a of the P 1 and P 2 signals. In the example of FIG. 4 , the divisor input signal N K initially has a value of 13 clock steps, where the clock step is a half cycle of the input clock CLKIN 402 , with the corresponding first edge 408 a of the output clock signal CLKOUT 408 initially around 30% between the first edges 404 a and 404 b . In the next output clock cycle, the phase accumulator 326 adjusts the phase adjustment value b K to cause the phase interpolator 342 locate the rising output clock edge closer to the first edge 406 a of the second pulse output signal P 2 . In this example, moreover, the phase accumulator 326 provides the output to set the integer divisor signal N K to represent 14 clock steps for the subsequent output clock cycle. In the next output clock cycle in FIG. 4 , the phase accumulator circuit 326 provides an updated phase adjustment value b K to relocate the rising edge of the CLKOUT signal 408 closer to the first edge 404 a of the P 1 pulse output signal 404 .

Referring also to FIG. 5 , the phase accumulator circuit 326 in one example is implemented using a step accumulator circuit 500 . The step accumulator circuit 500 includes a clock input to receive the second pulse output signal P 2 , as well as an input to receive the step input value SI. The step accumulator circuit 500 also includes a first step accumulator output 502 to provide a carry forward value QK, and a second step accumulator output 328 b provides the phase adjustment value b K to the output circuit 310 to control the temporal position of the first edge 408 a of the first clock output signal CLKOUT between the edges 404 a and 404 b of the P 1 and P 2 signals. A summation or addition circuit or function 504 adds the carry forward value QK from the first step accumulator output 502 with a third predetermined value M C . The first output 328 b of the phase accumulator circuit 326 in this example provides the divisor input signal N K to the control input of the dynamic divider circuit 302 according to the sum of the values QK and M C .

As seen in FIGS. 3 and 5 , the output circuitry 310 as well as the DSM 320 , the phase accumulator 326 and the code mapping circuit 330 are clocked by the P 2 signal, and thus operate at a low frequency compared with the input frequency FIN of the input clock signal CLKIN. In some implementations, the dynamic divider circuit 302 may provide another timing signal to be used as clock instead of pulse P 2 . This timing signal needs to have the same rate as pulses P 1 and P 2 , but a different delay or pulse duration. This design therefore provides advantages compared to conventional approaches, since high-speed digital circuit components are not required for the component circuits 310 , 320 and 326 of the FFD circuit 210 , and these circuits consume less power than circuitry operating off of the input clock CLKIN. The example FFD circuit 210 in FIG. 3 uses both falling and rising edges of the input clock signal CLKIN to generate edges of the output clock signal CLKOUT. In this case, the dynamic divider circuit 302 performs an edge counting on input CLKIN. In the illustrated example depicted in FIG. 4 the dynamic divider circuit 302 provides a first pulse output signal P 1 with a rising edge corresponding to a falling edge of the input clock signal CLKIN as well as a second pulse output signal P 2 with a rising edge corresponding to a subsequent rising edge of the input clock signal CLKIN. In this example, the first and second pulse output signals P 1 and P 2 provide pulses having a duration longer than the clock cycle of the input signal CLKIN. As further shown in FIG. 4 , moreover, the FFD circuit 210 provides a set up time 414 to allow adjustment of the outputs of the phase interpolator circuit 340 (for example settling the DACs utilized within this circuit) beginning with the second or falling edge 406 b of the second pulse output signal P 2 before the next first or rising edge of the P 1 pulse output signal. The circuit 210 operates based on a clock step equal to one half of the period TIN of the input clock signal CLKIN (TIN=1/FIN) for a clock step of TIN/2, and the output clock signal CLKOUT has a period TOUT of 1/FOUT, with FOUT=2FIN/(M C +(M P +α)2 −B ) as shown in FIG. 4 .

The output signals P 1 and P 2 are provided from the first and second dynamic divider circuit outputs 306 and 308 , respectively, as inputs to the phase interpolator circuit 340 . The phase interpolator circuit 340 provides phase interpolation to generate rising edges of the output clock signal CLKOUT provided at the output 312 in between rising edges of the P 1 and P 2 pulse output signals. The dynamic divider circuit 302 operates according to an adjustable comp value N K received from a first output 328 a of the phase accumulator circuit 326 . In operation, the phase interpolator circuit 340 adjusts the edge location between the respective rising edges of P 1 and P 2 according to the code mapper output 332 . The phase interpolator operates according to a value from the code mapping circuit 330 that operates according to (e.g., clocked by) the falling edges of P 2 . The time between consecutive pulses in the P 1 signal, as well as the time between consecutive pulses in the P 2 signal, is controlled according to an adjustable integer divisor value N K provided by the phase accumulator circuit 326 .

The combination of the phase interpolation via the circuit 340 to generate the output clock edges, as well as the adjustment of the divider circuit divisor value N K provides fractional frequency division by the FFD circuit 210 without requiring additional multipliers and dividers and/or extra PLL circuitry associated with conventional fractional frequency divider approaches. The dynamic divider circuit 302 in one example includes high-speed digital circuitry to provide clean edges to the pulse output signals P 1 and P 2 . The remainder of the circuitry in the FFD 210 does not need to include high-speed digital circuit components, as these are operated at the lower (e.g., divided) output frequency FOUT, e.g., clocked by P 2 in the example of FIG. 3 . Moreover, operation of the remaining FFD components at the lower output frequency FOUT facilitates low power operation of the FFD circuit 210 . The parameters α, M P and M C define the effective fractional divide ratio of the FFD circuit 210 , and can be user-defined such as by programming an IC implementation of a single FFD circuit 210 or a multi-channel divider system 201 as shown in FIG. 2 , with the IC 201 including suitable pins or pads allowing configuration or programming of the parameters α, M P and M C . In the illustrated implementation, M C is an integer value defining large or big steps for advancing the value N K , and the parameter M P is an integer defining small steps for adjusting the input to the step accumulator circuit 500 in FIG. 5 . The parameter α in one example is a programmable value representing a real value between 0 and 1. In practice the parameter α is represented by fixed point. The fixed point accuracy in representing this parameter will define the final output frequency resolution in terms of ppm (parts per million) or ppb (parts per billion) and so on. In practice, the fractional divide ratio of the FFD circuit 210 is set by configuration of the parameters α, M P and M C through user input, or these values can be preset in certain examples.

The phase interpolator 340 generates the output clock signal CLKOUT according to the P 1 and P 2 pulse output signals. In one example, the phase interpolator circuit 340 can be a quadrature phase interpolator. Two DAC circuits are deployed inside the phase interpolator circuit 340 , with the first and second DAC circuits receive multibit outputs for the respective signals P 1 and P 2 and individually provide analog output signals to the phase interpolator circuit 340 to control the position of the first edges 410 a of the output signal CLKOUT between the first edges 404 a and 406 a of the pulse output signals P 1 and P 2 . In practice, the phase interpolator circuit 340 and its constituent DACs may add some level of nonlinearity, and the code mapping circuit 330 has first and second 13-bit outputs that provide 13-bit output values to the respective DACs to facilitate calibration of such phase interpolator nonlinearity. In one example, the DACs provide a current signal to circuitry within the phase interpolator in order to provide a calibrated amount of offset current according to the corresponding code mapping circuit value to accommodate phase nonlinearity of the phase interpolator circuit 340 . The DAC codes provided by the code mapping circuit 330 control the analog signals provided to the phase interpolator circuit 340 to adjust the position of the output clock edge between the corresponding edges of the P 1 and P 2 signals. The code mapping circuit 330 in one example receives a 10-bit input value bx from the second output 328 b of the phase accumulator circuit 326 . In general, the phase accumulator 326 provides a digital output signal b K of length “B”, where B=10 bits in the illustrated example. The code mapping circuit 330 provides the DAC code outputs at a higher bit resolution e.g., 13 bits). This allows finer control of the time-domain distance between the output clock edge and the edges of the corresponding P 1 and P 2 signals. After the falling edge of the corresponding P 2 pulse signal, the circuit 210 as a set up time 414 FIG. 4 ) to allow the updated code mapping circuit value to change operation of the DACs for a subsequent phase interpolation.

The input clock signal CLKIN defines a time grid with a granularity of half a clock cycle (TIN/2) that defines a clock step for operation of the circuit 210 . For input clocks that have some level of duty cycle distortion, the full clock cycle (TIN) can alternatively in other implementations used as a clock step. The edge counter circuit 302 effectively counts a given number N K clock edges or clock steps, and outputs a duty cycled pulse P 1 having a rising edge N K clock steps from its previous rising edge. As previously noted, the parameter N K is not fixed and can be updated by the phase accumulator circuit 326 . The second output pulse signal P 2 is phase shifted from P 1 by one clock step. The ideal edges of the final output clock will be somewhere between the two rising edges of P 1 and P 2 in order to accommodate potentially complex fractional divisor ratios for the FFD circuit 210 .

The phase interpolator 340 in one example is a linear phase interpolator controlled by the two DACs that establish a high resolution time grid between the two rising edges 404 a and 406 a of P 1 and P 2 . The time grid of the 13-bit DACs have a granularity (e.g., a phase interpolator step or PI step) of the clock step divided by 2 B , where B is the effective resolution of the phase interpolator (e.g., B=10 in the above example). The output clock edges are generated by the phase interpolator 340 using the edge counter 302 and the phase interpolation the output clock edges 408 a are generated with the resolution of the PI step. For example, a 5 GHz input clock with reliable 50% duty cycle will establish 100 ps clock step that, combined with 10-bit (B=10) PI step, provides a final temporal adjustment granularity of less than 100 fs. Because the FFD circuit 210 can be used for potentially any divisor ratio and input clock frequency FIN, ideally there is no restriction on the output frequency FOUT. In practice, the desired output clock will not necessarily stay on this high resolution time grid, and some level of quantization noise may be present on the produced output edges 408 a and 408 b of the output clock signal CLKOUT.

The DSM 320 facilitates achieving the desired output frequency FOUT and also helps push a large portion of the quantization noise power out of the desired frequency offset band (e.g., 10 KHz to 10 MHz). In operation the DSM 320 performs dithering at the level of PI steps and provides proper level of noise shaping according to its adopted order and architecture and provides a dithering sequence with time average equal to the predetermined value α. The phase accumulator circuit 326 controls the dynamic divider parameter N K , and also generates the proper phase adjustment values for the phase interpolator 340 through the phase adjustment value bx and the code mapping circuit 330 . In operation, the phase accumulator circuit 326 moves M C clock steps and M P +m K PI steps forward, where m K is the delta-sigma modulator output at the Kth edge. Over time, the average value of the m K sequence converges to the input value of α. In one implementation, α is a multibit value between 0 and 1 representing a residual fractional portion of the PI step, and M P and M C are small and large step sizes for the clock and PI steps, respectively. The phase accumulator clock step in the illustrated example is TIN/2, and the PI step is the clock step/2 B . In each output clock cycle TOUT, the circuit 326 advances M P +m K phase steps and M C clock steps forward. The current content of the accumulator is incremented by the step input SI=M P +m K . The phase adjustment value b K =MOD (b K-1 +M P +m K , 2 B ), where b K-1 is the value of b K from the previous cycle. In this example, the carry forward value Q K =|(b K-1 +M P +m K )/2 B |. The circuit 210 moves forward N K =M C +Q K clock steps that for the Kth output edge. The phase interpolator circuit 340 in one example provides accurate generation of rising edges. As discussed previously, the integer divider circuit 314 can be used to ensure small or no duty cycle distortion on the generated output frequency FOUT/2. In other examples, the first output clock signal CLKOUT is provided to the recipient circuit, and the output circuit 310 can include suitable circuitry to ensure that the falling edges are within a prescribed acceptable duty cycle range.

The phase interpolator circuit 340 in one example includes a slope adjustment circuit (not shown) to generate a first sloped signal according to the edge 404 a of the first pulse output signal P 1 , and a second sloped signal according to the edge 406 a of the second pulse output signal P 2 . In this example, the phase interpolator circuit 340 generates the first edge 408 a of the first output clock signal CLKOUT according to the sloped signals. The phase interpolator 340 may include conventional phase interpolator circuits that operate with sine waves or 50% duty-cycled waveforms. In such an approach, the phase interpolator circuit 340 directly uses the multiple phases of the input clock (for example quadrant signals) and the dynamic divider circuit 302 provides an edge selection pulse with similar shape to the pulse signal P 1 . The edge selection signal is applied to the interpolated waveform through an AND gate (not shown) to let the desired edges of the waveform to go through. In other examples, absent this condition, a slope adjustment circuit can be used to facilitate phase interpolation for non 50% duty cycled waveforms P 1 and P 2 . In one example, such a slope adjustment circuit can include RC circuits or other suitable circuitry to generate the sloped signals with enough level of slope at the edges of P 1 and P 2 to facilitate proper phase interpolation in the circuit 340 . Amplitude interpolation of the sloped signals provides a phase/time interpolation functionality. The edges in one example are created by a switching transistor circuit charging a capacitor using a fixed current source (not shown). During the on time of the pulses P 1 and P 2 , the corresponding slope adjustment circuits are charged, and during the P 1 and P 2 off time, the slope adjustment circuits are discharged to provide the sloped signals. Another example only uses the P 1 pulse as input to the phase interpolator circuit 340 and the starting level of the sloped signal is adjusted using a voltage DAC (not shown). Using this approach, the DAC value is controlled by the output of the code mapping circuit 330 , and different DAC levels result in different level crossing times of the generated sloped signal. In such an approach, the phase interpolator circuit 340 is performing as a digital-to-phase convertor as it is only using one input and thus no interpolation is actually performed. For large enough RC time constant values of the charging circuit, such a slope circuit creates a desired linear slope. The bandwidth of the phase interpolator circuit 340 and its constituent components is designed to be large enough to ensure output settling between the falling edge 406 b of the signal P 2 to the next rising edge of P 1 . The resulting P 1 and P 2 duty cycle relaxes the speed requirement of the phase interpolator circuit 340 .

As previously mentioned, the disclosed examples provide ICs 201 , divider systems 200 and FFD circuits 210 that use direct fractional frequency division and avoid using output dividers. This, in turn, facilitates low power compact designs that are robust and provide a wide range of divisor values by use of the edge counter 302 applied to the high speed input clock before any processing. In contrast to frequency dividers with fixed count modules, the edge counter parameter N K in the circuits 210 is not fixed and can change from one output edge to the next. Moreover, quadrature interpolation is not required, and rather than creating several phases (e.g., 4 to 8) for phase interpolation as in some conventional approaches, only two phases P 1 and P 2 are generated and used for phase interpolation in the circuits 210 . Two-phase duty-cycled operation avoids the requirement for phase Multiplexing or switching used in other multi-phase approaches. Accordingly, overall operation is largely glitch free and this has two-fold effect in complexity reduction as there is no need for phase mux/switching and the operation is glitch free and does not require glitch removal circuitry.

Moreover, low power consumption is achieved and, apart from the edge counter 302 , the rest of the constituent circuits 310 , 320 and 326 do not need to work with the high speed input clock (instead these are clocked by P 2 which is at the rate 1× or 2× of the output clock frequency in some examples shown above). In addition, the use of duty-cycled pulse output signals P 1 and P 2 can provide large enough transition time to relax speed requirements of the constituent DAC components employed within the phase interpolator circuit 340 . Furthermore, removal of output integer dividers as utilized in FIG. 1 but removed in FIG. 2 avoids the associated phase noise and spur folding effects. The disclosed examples can therefore fully benefit from noise shaping capability of the delta-sigma modulator 320 without any restriction on its order except its complexity. In operation, the disclosed examples provide a low power, low-complexity solution while achieving at the same time high performance in terms of phase noise and spur level for fully fractional clock division to facilitate high accuracy with resolution on the order of 0.01 parts per billion (PPB) and less compared to the input clock, as well as integrated time domain jitter of less than 130 fs RMS over a band of 10 KHz to 20 MHz, and spur level of −100 dBC relative to the main clock carrier power.

The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.