Constant on-time switching converter with reference voltage adjusting circuit and controller thereof

This application claims the benefit of CN application 201510562550.7 filed on Sep. 7, 2015, and incorporated herein by reference.

The present invention generally relates to electronic circuits, and more particularly but not exclusively to constant on-time switching converters and controllers thereof.

COT (constant on-time) control method is widely used in power supply area due to its simple structure and excellent transient response. Nevertheless, for switching converters with COT control, there may be a sub-harmonic oscillation at the output voltage because of the insufficient ESR (equivalent series resistance) of the output capacitor.

To avoid this sub-harmonic oscillation, a compensation signal in phase with the inductor current is often employed. FIG. 1 illustrates a schematic of a prior COT switching converter 100 , wherein a ramp compensation generator consisting of a resistor Rramp and a capacitor Cramp is coupled to the inductor L in parallel. The compensation signal RAMP generated by the ramp compensation generator is added to a feedback signal FB to avoid this sub-harmonic oscillation.

However, the compensation signal may affect the average value of the feedback signal FB and results in poor load and line regulation. Also, the resistor Rramp coupled between the switching node SW and the feedback signal FB affects the load transient quite much. When the switching converter works in CCM mode, the ringing and noise from the switching node SW may be conducted to feedback signal FB through the ramp compensation generator when the switches M 1 and M 2 are turned OFF, and may cause the double pulse problem. In addition, the parameters of the ramp compensation generator shown in FIG. 1 are difficult to determine under the different input voltages, output voltages and switching frequencies.

Embodiments of the present invention are directed to a constant on-time controller used in a switching converter, the switching converter includes a switching circuit having a main switch. The controller comprises: an on-time control circuit configured to generate an on-time control signal which is used to control the on-time of the main switch; a comparing circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to receive a feedback signal indicative of the output voltage of the switching circuit, the second input terminal is coupled to receive a reference voltage, wherein the comparing circuit compares the reference voltage and the feedback signal and generates a comparison signal at the output terminal; a logic circuit coupled to the on-time control circuit and the comparing circuit, wherein based on the on-time control signal and the comparison signal, the logic circuit generates a control signal to control the main switch; and a reference voltage adjusting circuit coupled to the logic circuit, wherein based on a basic reference voltage and the control signal, the reference voltage adjusting circuit generates the reference voltage, wherein in each switching cycle of the switching converter, the reference voltage is pulled down when the main switch is turned ON and increases with a slew rate until the main switch is turned ON again in the next switching cycle or the reference voltage increases to a maximum value.

The present invention can be further understood with reference to the following detailed description and the appended drawings, wherein like elements are provided with like reference numerals.

FIG. 1 illustrates a schematic of a prior COT switching converter 100 .

FIG. 2 illustrates a block diagram of a switching converter 200 in accordance with an embodiment of the present invention.

FIG. 3A illustrates working waveforms of the prior switching converter 100 shown in FIG. 1 during stable state.

FIG. 3B illustrates working waveforms of the switching converter 200 shown in FIG. 2 during stable state.

FIG. 4A illustrates working waveforms of the prior switching converter 100 shown in FIG. 1 during load transient change.

FIG. 4B illustrates working waveforms of the switching converter 200 shown in FIG. 2 during load transient change.

FIG. 5 illustrates the reference voltage adjusting circuit 204 A in accordance with an embodiment of the present invention.

FIG. 6 illustrates the reference voltage adjusting circuit 204 B in accordance with another embodiment of the present invention.

FIG. 7 illustrates the reference voltage adjusting circuit 204 C in accordance with still another embodiment of the present invention.

FIG. 8 illustrates the reference voltage adjusting circuit 204 D in accordance with yet another embodiment of the present invention.

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

It is to be understood that “substantially” is a term of art, and is meant to convey the principle that relationship such simultaneity or perfect synchronization cannot be met with exactness, but only within the tolerances of the technology available to a practitioner of the art under discussion.

FIG. 2 illustrates a block diagram of a switching converter 200 in accordance with an embodiment of the present invention. The switching converter 200 comprises a controller, a switching circuit and a feedback circuit 205 . The switching circuit is applied in synchronous buck converter and comprises switches M 1 , M 2 , an inductor L, an output capacitor Cout. The switching circuit is configured to convert an input voltage Vin into an output voltage Vout via turning ON and OFF of switches M 1 and M 2 . The switch M 1 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to receive the input voltage Vin. The switch M 2 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the switch M 1 to form the switching node SW, the second terminal is coupled to ground. The inductor L has a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the switch M 1 and the first terminal of the switch M 2 . The output capacitor Cout is coupled between the second terminal of the inductor L and ground, the voltage across the output capacitor Cout is the output voltage Vout. Even though in the embodiment shown in FIG. 2 , the switches M 1 , M 2 , the inductor L and the output capacitor Cout constitute a synchronous BUCK converter. However, it is apparent to those skilled in the art that the switch M 2 may be replaced by a diode to form a non-synchronous BUCK converter. Moreover, the present invention is also applicable to other suitable topologies, such as synchronous or asynchronous buck converter, flyback converter or forward converter and so on. The switches in the switching circuit may be any controllable semiconductor devices, such as MOSFET (metal oxide semiconductor field effect transistor), IGBT (isolated gate bipolar transistor) and so on.

The feedback circuit 205 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the switching circuit to receive the output voltage Vout, the feedback circuit 205 generates a feedback signal FB indicative of the output voltage at the output terminal. The feedback circuit 205 may consist of a resistor divider, or even just a wire where the feedback signal FB is equal to the output voltage Vout.

The controller comprises an on-time control circuit 201 , a comparing circuit 202 , a logic circuit 203 and a reference voltage adjusting circuit 204 . The on-time control circuit 201 is configured to generate an on-time control signal COT to control the on-time of the switch M 1 . The on-time of the switch M 1 may be a constant value or a variable value related to the input voltage Vin or the output voltage Vout. The comparing circuit 202 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the feedback circuit 205 to receive the feedback signal FB, the second input terminal is coupled to receive a reference voltage REF, wherein the comparing circuit 202 compares the reference voltage REF and the feedback signal FB and generates a comparison signal SET at the output terminal.

The logic circuit 203 is coupled to the on-time control circuit 201 and the comparing circuit 202 , wherein based on the on-time control signal COT and the comparison signal SET, the logic circuit 203 generates control signals HS and LS to respectively control switches M 1 and M 2 . Generally, when the on-time of the switch M 1 reaches the on-time set by the on-time control circuit 201 , the switch M 1 is turned OFF, and the switch M 2 is turned ON. Normally, to prevent cross conduction of switches M 1 and M 2 , a dead time is set between control signals HS and LS. Moreover, the controller further comprises a minimum off-time control circuit to prevent the comparing circuit 202 from being affected by the system noise. The comparison signal SET is disabled by the minimum off-time control circuit during a minimum off-time TOFF MIN . The minimum off-time control circuit is well-known to the person skilled in the art and will not be described in detail

The reference voltage adjusting circuit 204 is coupled to the logic circuit 203 , based on a basic reference voltage Vref and the control signal HS, the reference voltage adjusting circuit 204 generates the reference voltage REF, wherein in each switching cycle of the switching converter, the reference voltage REF is pulled down when the switch M 1 is turned ON, and then increases with a slew rate until the reference voltage REF increases to a maximum value. The maximum value may equal to the basic reference voltage Vref. In another embodiment, the maximum value substantially equals to the basic reference voltage Vref, for example, the difference between the maximum value and the basic reference voltage Vref may be from 20 mV to 40 mV.

FIG. 3A illustrates working waveforms of the prior switching converter 100 shown in FIG. 1 during stable state. FIG. 3B illustrates working waveforms of the switching converter 200 shown in FIG. 2 during stable state. FIG. 4A illustrates working waveforms of the prior switching converter 100 shown in FIG. 1 during load transient change. FIG. 4B illustrates working waveforms of the switching converter 200 shown in FIG. 2 during load transient change. As shown in FIGS. 3A-4B , wherein IL represents a current flowing through the inductor L, Vsw represents the voltage at the switching node SW and Iout represents an output current of the switching circuit. It can be seen from FIG. 3B , the ramp compensation of FIG. 2 is added to the basic reference voltage Vref instead of the feedback signal FB, so the feedback signal FB is no longer affected by the ramp compensation like in the prior art, and therefore the load and line regulation of the switching converter is effectively improved. This can avoid the ringing and noise issue from the switching node SW during DCM mode. Moreover, owing to the feedback signal FB only reflects the output voltage Vout at any time, which can effectively improve the transient response. Referring now to FIGS. 4A and 4B , compared with the prior example shown in FIG. 1 , the embodiment shown in FIG. 2 can provide a much faster ramp rate of the current IL average caused by the load increase, additionally, the off-time of the switch M 1 is shorter over the prior art.

FIG. 5 illustrates the reference voltage adjusting circuit 204 A in accordance with an embodiment of the present invention. The reference voltage adjusting circuit 204 A comprises resistors R 1 , R 2 , a diode D 1 , a current source IS 1 , a capacitor C 1 , a transistor S 1 , a one-shot circuit 241 and a voltage-to-current converter 242 . The current source IS 1 has a first terminal and a second terminal, wherein the first terminal is coupled to a power supply Vcc. The capacitor C 1 a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the current source IS 1 , and the second terminal is coupled to ground. The one-shot circuit 241 has an input terminal and an output terminal, wherein the input terminal is coupled to receive the control signal HS. The transistor S 1 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the capacitor C 1 , the second terminal is coupled to ground, the control terminal is coupled to the output terminal of the one-shot circuit 241 . The diode D 1 has an anode and a cathode, wherein the anode is coupled to the first terminal of the capacitor C 1 , the cathode is coupled to the basic reference voltage Vref. The voltage-to-current converter 242 has an input terminal and an output terminal, wherein the input terminal is coupled to the first terminal of the capacitor C 1 , based on the voltage Vc 1 across the capacitor C 1 , the voltage-to-current converter 242 generates a current I 1 at the output terminal. The resistor R 1 has a first terminal and a second terminal, wherein the first terminal is coupled to the basic reference voltage Vref. The resistor R 2 has a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the resistor R 1 and the output terminal of the voltage-to-current converter 242 and is configured to provide the reference voltage REF, the second terminal is coupled to ground.

According to the embodiment shown in FIG. 5 , the reference voltage REF can be expressed as:

REF = R ⁢ ⁢ 2 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 * Vref + R ⁢ ⁢ 1 * R ⁢ ⁢ 2 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 * I ⁢ ⁢ 1 = R ⁢ ⁢ 2 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 * Vref + R ⁢ ⁢ 1 * R ⁢ ⁢ 2 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 * K ⁢ ⁢ 1 * Vc ⁢ ⁢ 1 ( 1 )

K1 is conversion factor of the voltage-to-current converter 242 .

In each switching cycle of the switching converter, when the switch M 1 is turned ON, the one-shot circuit 241 outputs a short pulse to turn ON the transistor S 1 , the voltage Vc 1 across the capacitor C 1 is discharged to zero. After that, the transistor S 1 is turned OFF, the current source IS 1 charges the capacitor C 1 , the voltage Vc 1 across the capacitor C 1 increases until the switch M 1 is turned ON again in the next switching cycle or the voltage Vc 1 increases to the basic reference voltage Vref. It can be seen from the above analysis and equation (1), the reference voltage REF is pulled down to

R ⁢ ⁢ 2 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 * Vref

when the switch M 1 is turned ON and then increases with a constant slew rate until the switch M 1 is turned ON again in the next switching cycle or the reference voltage REF increases to

In some applications, the ESR of the output capacitor Cout may cause a DC error at the output voltage Vout. To solve this problem, the controller further includes an error compensation circuit. FIG. 6 illustrates the reference voltage adjusting circuit 204 B in accordance with another embodiment of the present invention. Compared with the embodiment of FIG. 5 , the reference voltage adjusting circuit 204 B further comprises a buffer circuit 243 , an error compensation circuit 244 and a resistor R 3 . The error compensation circuit 244 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to receive the feedback signal FB, the second input terminal is coupled to receive the basic reference voltage Vref, based on the feedback signal FB and the basic reference voltage Vref, the error compensation circuit 244 generates a current I 2 at the output terminal. The buffer circuit 243 has an input terminal and an output terminal, wherein the input terminal is coupled to the first terminal of the resistor R 2 and the output terminal of the voltage-to-current converter 242 . The resistor R 3 has a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal of the buffer circuit 243 , the second terminal is coupled to the output terminal of the error compensation circuit 244 and is configured to provide the reference voltage REF.

According to the embodiment shown in FIG. 6 , the reference voltage REF can be expressed as:

It can be seen from equation (2), in each switching cycle of the switching converter, the reference voltage REF is pulled down to

R ⁢ ⁢ 2 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 * Vref + I ⁢ ⁢ 2 * R ⁢ ⁢ 3

when the switch M 1 is turned ON, and then the reference voltage REF increases with a constant slew rate until the switch M 1 is turned ON again in the next switching cycle or the reference voltage REF increases to

In one embodiment, the error compensation circuit 244 may comprises an error amplifier 2441 , a low-pass filter 2442 and a voltage-to-current converter 2443 . The error amplifier 2441 has a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the inverting input terminal is coupled to receive the feedback signal FB, the non-inverting input terminal is coupled to receive the basic reference voltage Vref. The low-pass filter 2442 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the error amplifier 2441 . The voltage-to-current converter 2443 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the low-pass filter 2442 , the voltage-to-current converter 2443 provides the current I 2 at the output terminal. Based on the feedback signal FB and the basic reference voltage Vref, the error compensation circuit 244 adjusts the current I 2 and the reference voltage REF, this influences the frequency of the switching converter as a result of the change of the reference voltage REF, and thus avoids DC error at the output voltage Vout.

FIG. 7 illustrates the reference voltage adjusting circuit 204 C in accordance with still another embodiment of the present invention. In the embodiment of the reference voltage adjusting circuit 204 C, the output terminal of the voltage-to-current converter 242 is coupled to different means when compared with the circuit 204 B shown in FIG. 6 . As shown in FIG. 7 , the output terminal of the voltage-to-current converter 242 is coupled to the second terminal of the resistor R 3 instead of the input terminal of the buffer circuit 243 .

According to the embodiment shown in FIG. 7 , the reference voltage REF can be expressed as:

It can be seen from equation (3), in each switching cycle of the switching converter, the reference voltage REF is pulled down to

R ⁢ ⁢ 2 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 * Vref + I ⁢ ⁢ 2 * R ⁢ ⁢ 3

when the switch M 1 is turned ON, and then the reference voltage REF increases with a constant slew rate until the switch M 1 is turned ON again in the next switching cycle or the reference voltage REF increases to

FIG. 8 illustrates the reference voltage adjusting circuit 204 D in accordance with yet another embodiment of the present invention. When compared the reference voltage adjusting circuit 204 D with the circuit 204 C shown in FIG. 7 , the output terminal of the error compensation circuit 244 is coupled to the first terminal of the resistor R 2 and the input terminal of the buffer circuit 243 instead of the second terminal of the resistor R 3 .

According to the embodiment shown in FIG. 8 , the reference voltage REF can be expressed as:

It can be seen from equation (4), in each switching cycle of the switching converter, the reference voltage REF is pulled down to

R ⁢ ⁢ 2 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 * Vref + R ⁢ ⁢ 1 * R ⁢ ⁢ 2 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 * I ⁢ ⁢ 2

when the switch M 1 is turned ON, and then the reference voltage REF increases in a constant slew rate until the switch M 1 is turned ON again in the next switching cycle or the reference voltage REF increases to

Throughout the specification, the terms “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. Moreover, the drawings are only for illustration purpose. Usually, these drawings are not necessarily drawn to scale. Persons of ordinary skill in the art will appreciate that the terms “coupled” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements.

Obviously many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.