Layout method of mask pattern, manufacturing method of a semiconductor device and exposure mask

This application is based upon and claims the benefit of priority from U.S. Provisional Application No. 62/335,279, filed on May 12, 2016; the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a layout method of mask pattern, a manufacturing method of a semiconductor device, and an exposure mask.

In a lithography process, variations in the cross section shape of a resist pattern may deteriorate uniformity of dimensions of a processing film.

FIG. 1A is a schematic block diagram of a pattern layout supporting device according to a first embodiment and its peripheral devices, FIG. 1B is a schematic cross-sectional view of an exposure device in which the pattern layout supporting device illustrated in FIG. 1A is used, FIG. 1C is a cross-sectional view of a step after formation of a resist pattern, and FIG. 1D is a cross-sectional view of a step after formation of a processed pattern;

FIG. 2A is a plane view of a configuration example of a mask pattern before division according to the first embodiment, FIG. 2B is a diagram illustrating the relationship between X position of the mask pattern illustrated in FIG. 2A and the amount of attenuation, FIG. 2C is a plane view illustrating a configuration example of the mask pattern after division according to the first embodiment, and FIG. 2D is a diagram illustrating the relationship between X position of the mask pattern illustrated in FIG. 2C and the amount of attenuation;

FIG. 3A is a plane view of a shape of a resist pattern using an exposure mask illustrated in FIG. 2A , FIGS. 3B to 3D are cross-sectional views of shapes of divided regions of the resist pattern illustrated in FIG. 3A , FIG. 3E is a plane view of a shape of a processed pattern using the resist pattern illustrated in FIG. 3A , and FIGS. 3F to 3H are cross-sectional views of shapes of divided regions of the processed pattern illustrated in FIG. 3E ;

FIG. 4A is a plane view of a shape of a resist pattern using an exposure mask illustrated in FIG. 2C , FIGS. 4B to 4D are cross-sectional views of shapes of divided regions of the resist pattern illustrated in FIG. 4A , FIG. 4E is a plane view of a shape of a processed pattern using the resist pattern illustrated in FIG. 4A , and FIGS. 4F to 4H are cross-sectional views of shapes of divided regions of the processed pattern illustrated in FIG. 4E ;

FIG. 5 is a plane view illustrating parameters for sub patterns for use in the mask pattern after division according to the first embodiment;

FIG. 6 is a flowchart of a layout method of mask pattern according to the first embodiment;

FIG. 7 is a plane view of a configuration example of a mask pattern according to a second embodiment; and

FIGS. 8A to 8F are cross-sectional views of a manufacturing method of a semiconductor device according to a third embodiment.

In general, according to one embodiment, a layout method of mask pattern includes dividing a layout region of a mask pattern into N (N is an integer of 2 or larger) units, arranging a main pattern resolved by exposure light and arranging sub patterns not resolved by the exposure light outside the main pattern such that distributions of attenuation amount of the exposure light in the divided layout regions are different.

Exemplary embodiments of a layout method of mask pattern and a manufacturing method of a semiconductor device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

(First Embodiment)

FIG. 1A is a schematic block diagram of a pattern layout supporting device according to a first embodiment and its peripheral devices, FIG. 1B is a schematic cross-sectional view of an exposure device in which the pattern layout supporting device illustrated in FIG. 1A is used, FIG. 1C is a cross-sectional view of a step after formation of a resist pattern, and FIG. 1D is a cross-sectional view of a step after formation of a processed pattern.

Referring to FIG. 1A , a pattern layout supporting device 11 is provided with a pattern division unit 11 a and a pattern setting unit 11 b . Peripheral devices of the pattern layout supporting device 11 include a CAD system 12 and a mask data creation unit 13 . Referring to FIG. 1B , an exposure device 14 includes a light source G, a diaphragm S, an exposure mask M 1 , and a lens L.

The pattern division unit 11 a divides a layout region of a mask pattern of the exposure mask M 1 into N units. The pattern setting unit 11 b sets arrangement positions of a main pattern H resolved by exposure light EL and sub patterns HS not resolved by the exposure light EL. The sub patterns HS may be sub resolution assist features (SRAF). The sub patterns HS can be different in distribution of attenuation amount of the exposure light EL among the divided layout regions. The sub patterns HS can have lines and spaces alternately and repeatedly arranged on both sides of the main pattern H, for example.

The resolution with a wavelength of the exposure light EL of 365 nm (i line) and a numerical aperture NA of 0.65 is 350 nm. The wavelength with a wavelength of the exposure light EL of 248 nm (KrF) and a numerical aperture NA of 0.66 is 90 nm. The resolution with a wavelength of the exposure light EL of 193 nm (ArE) and a numerical aperture NA of 0.93 is 65 nm. The resolution with a wavelength of the exposure light EL of 193 nm (ArE) and a numerical aperture NA of 1.35 is 38 nm.

The CAD system 12 creates design layout data for a semiconductor integrated circuit. The pattern division unit 11 a divides the layout region of the mask pattern into N units. Further, the pattern setting unit 11 b sets arrangement positions of the main pattern H and the sub patterns HS in the respective divided layout regions, and sends the setting data to the mask data creation unit 13 .

Then, the mask data creation unit 13 creates mask data corresponding to the main pattern H and the sub patterns HS set for the individual divided layout regions. The main pattern H and the sub patterns HS specified by the mask data created by the mask data creation unit 13 are formed from light-shielding films on the exposure mask M 1 .

Meanwhile, as illustrated in FIG. 1B , a processing film TB 1 is formed on a foundation layer K 1 , and a resist film RB 1 is applied to the processing film TB 1 . The foundation layer K 1 and the processing film TB 1 may be semiconductor substrates, insulation films such as silicon oxide films or silicon nitride films, semiconductor films of amorphous silicon or polycrystalline silicon, or metallic films of Al, Cu, or the like. The processing film TB 1 may be a stacked body in which a plurality of layers is stacked.

The light source G emits the exposure light EL. The exposure light EL is narrowed down by the diaphragm S and enters the resist film RB 1 through the exposure mask M 1 and the lens L to expose the resist film RB 1 to the light.

Next, as illustrated in FIG. 1C , after the light exposure of the resist film RB 1 , the resist film RB 1 is developed to form a resist pattern R 1 on the processing film TB 1 . The sub patterns HS can define the cross-sectional shape of the resist pattern R 1 . For example, arranging the sub patterns HS on both sides of the main pattern H can define a taper angle θ of end portions of the resist pattern R 1 . The taper angle θ can be adjusted by adjusting the width, pitch, and number of the sub patterns HS.

Next, as illustrated in FIG. 1D , the processing film TB 1 is etched with the resist pattern R 1 as a mask to form a processed pattern T 1 . At this time, the processed pattern T 1 has a process conversion difference B. The process conversion difference B is the difference between the edge position of the resist pattern R 1 and the edge position of the processed pattern T 1 . The process conversion difference B can be adjusted by adjusting the taper angle θ.

A division method of the layout region of the mask pattern and a layout method of the sub patterns HS in the individual divided layout regions will be explained below specifically. In the first embodiment, the layout region of the mask pattern is divided into three as an example.

FIG. 2A is a plane view of a configuration example of the mask pattern before division according to the first embodiment, FIG. 2B is a diagram illustrating the relationship between X position of the mask pattern illustrated in FIG. 2A and the amount of attenuation, FIG. 2C is a plane view illustrating a configuration example of the mask pattern after division according to the first embodiment, and FIG. 2D is a diagram illustrating the relationship between X position of the mask pattern illustrated in FIG. 2C and the amount of attenuation.

Referring to FIG. 2A , an exposure mask M 0 before the division of the layout region has a mask pattern H 0 formed thereon. The mask pattern H 0 can be a solid pattern to be resolved by the exposure light EL. As illustrated in FIG. 2R , in a distribution L 0 of attenuation amount of the exposure mask M 0 , the amount of attenuation of the exposure light EL rises steeply at the edge position in the mask pattern H 0 .

FIG. 3A is a plane view of a shape of a resist pattern using the exposure mask illustrated in FIG. 2A , FIGS. 3B to 3D are cross-sectional views of shapes of individual divided regions of the resist pattern illustrated in FIG. 3A , FIG. 3E is a plane view of a shape of a processed pattern using the resist pattern illustrated in FIG. 3A , and FIGS. 3F to 3H are cross-sectional views of shapes of individual divided regions of the processed pattern illustrated in FIG. 3E . FIGS. 3F to 3H correspond to the positions of FIGS. 3B to 3D .

Referring to FIG. 3A , lithography is performed with the use of the exposure mask M 0 illustrated in FIG. 2A to form a resist pattern R 0 on the processing film TB 1 . At this time, an inclined surface SA 1 with a taper angle θA 1 is formed at the edge of the resist pattern R 0 in a region DA 1 , an inclined surface SA 2 with a taper angle θA 2 is formed at the edge of the resist pattern R 0 in a region DA 2 , and an inclined surface SA 3 with a taper angle θA 3 is formed at the edge of the resist pattern R 0 in a region DA 3 . In this case, the relationship θA 2 >θA 1 =θA 3 can hold.

Next, as illustrated in FIGS. 3E to 3H , the processing film TB 1 is etched via the resist pattern R 0 to form a processed pattern T 0 . At this time, the processed pattern T 0 has a process conversion difference A 1 corresponding to the inclined surface SA 1 of the resist pattern R 0 , a process conversion difference A 2 corresponding to the inclined surface SA 2 of the resist pattern R 0 , and a process conversion difference A 3 corresponding to the inclined surface SA 3 of the resist pattern R 0 . When θA 2 >θA 1 =θA 3 , A 2 <A 1 =A 3 . Accordingly, when lithography is performed with the use of the exposure mask M 0 illustrated in FIG. 2A , the process conversion differences A 1 to A 3 generated in the processed pattern T 0 vary between the region DA 2 and the regions DA 1 and DA 3 .

Therefore, the resist pattern R 0 is divided into the regions DAT to DA 3 according to the process conversion differences A 1 to A 3 and the layout region of the mask pattern is divided in correspondence with the dividing positions in the resist pattern R 0 . Then, the sub patterns are arranged in the individual divided respective layout regions such that the process conversion differences are equal among the regions DA 1 to DA 3 .

Specifically, referring to FIG. 2C , the layout region of the mask pattern on the exposure mask M 1 is divided into the regions D 1 to D 3 . The regions D 1 to D 3 of the exposure mask M 1 can correspond to the regions DA 1 to DA 3 of the resist pattern R 0 , respectively. A main pattern H 1 is arranged in the region D 1 , and sub patterns HS 1 are arranged on the both sides of the main pattern H 1 . The sub patterns HS 1 can be symmetrically arranged with respect to the main pattern H 1 .

A main pattern H 2 is arranged in the region D 2 , and sub patterns HS 2 are arranged on the both sides of the main pattern H 2 . The sub patterns HS 2 can be symmetrically arranged with respect to the main pattern H 2 . A main pattern H 3 is arranged in the region D 3 , and sub patterns HS 3 are arranged on the both sides of the main pattern H 3 . The sub patterns HS 3 can be symmetrically arranged with respect to the main pattern H 3 .

The main patterns H 1 to H 3 can solid patterns to be resolved by the exposure light EL. The arrangement densities of the sub patterns HS 1 to HS 3 in the regions D 1 to D 3 can be lower with decreasing proximity to the edges of the main patterns H 1 to H 3 . The number of the sub patterns HS 2 arranged in the region D 2 can be larger than the numbers of the sub patterns HS 1 and HS 3 in the regions D 1 and D 3 . The regions D 1 and D 3 can be symmetrically arranged with respect to the region D 2 .

As illustrated in FIG. 2D , in the distributions L 1 to L 3 of attenuation in the exposure mask M 1 , the amount of attenuation of the exposure light EL rises with an inclination at the edge position of the mask pattern. The inclination of the rise in the distributions L 1 and L 3 of attenuation in the regions D 1 and D 3 is larger than that in the distribution L 2 of attenuation in the region D 2 .

FIG. 4A is a plane view of a shape of a resist pattern using the exposure mask illustrated in FIG. 20 , FIGS. 48 to 4D are cross-sectional views of shapes of individual divided regions of the resist pattern illustrated in FIG. 4A , FIG. 48 is a plane view of a shape of a processed pattern using the resist pattern illustrated in FIG. 4A , and FIGS. 4F to 4H are cross-sectional views of shapes of individual divided regions of the processed pattern illustrated in FIG. 48 . FIGS. 4F to 48 correspond to the positions of FIGS. 48 to 40 , respectively.

Referring to FIG. 4A , lithography is performed with the use of the exposure mask M 1 illustrated in FIG. 20 to form a resist pattern R 1 on the processing film TB 1 . At this time, an inclined surface SB 1 with a taper angle θB 1 is formed at the edge of the resist pattern R 1 corresponding to the region D 1 of the exposure mask M 1 , an inclined surface SB 2 with a taper angle θB 2 is formed at the edge of the resist pattern R 1 corresponding to the region D 2 of the exposure mask M 1 , and an inclined surface SB 3 with a taper angle θB 3 is formed at the edge of the resist pattern R 1 corresponding to the region D 3 of the exposure mask M 1 . In this example, the relationship θB 1 =θB 2 =θB 3 can hold.

Next, as illustrated in FIGS. 4E to 4H , the processing film TB 1 is etched via the resist pattern R 1 to form a processed pattern T 1 . The processed pattern T 1 has a process conversion difference B 1 corresponding to the inclined surface SB 1 of the resist pattern R 1 , a process conversion difference B 2 corresponding to the inclined surface SB 2 of the resist pattern R 1 , and a process conversion difference B 3 corresponding to the inclined surface SB 3 of the resist pattern R 1 . When θB 1 =θB 2 =θB 3 , A 1 =A 2 =A 3 . Accordingly, when lithography is performed with the use of the exposure mask M 1 illustrated in FIG. 2C , the process conversion differences generated in the processed pattern T 1 can be equal among the regions DA 1 to DA 3 .

FIG. 5 is a plane view illustrating parameters for sub patterns for use in the mask pattern after division according to the first embodiment.

Referring to FIG. 5 , when the sub patterns HS are arranged on the both sides of the main pattern H, a distance LG from the edge position of the main pattern H and width W and pitch P of the sub patterns HS can be adjusted. The width W and pitch P of the sub patterns HS can be set such that the sub patterns HS are not resolved. The width W of the sub patterns HS can be smaller with decreasing proximity to the edge position of the main pattern H.

By adjusting the distance LG from the edge position of the main pattern H, the width W and pitch P of the sub patterns HS, the taper angle θ of the edge position of the resist pattern R 1 and the process conversion difference B can be adjusted.

FIG. 6 is a flowchart of a layout method of masks pattern according to the first embodiment.

Referring to FIG. 6 , lithography is performed with the use of an exposure mask before the division of a layout region to form a resist pattern on a processing film (S 1 ).

Next, the processing film is etched via the resist pattern to form a processed pattern on a wafer (S 2 ).

Next, the resist pattern is divided into several regions depending on the process conversion differences or cross-sectional shapes of the resist pattern at the individual edge positions (S 3 ).

Next, process conversion differences with a change in the taper angle of the resist cross section are acquired (S 4 ). The process conversion differences with a change in the taper angle of the resist cross section may be determined by simulation or may be measured under different experimental conditions such that the taper angle of the resist cross section changes.

Next, the relationship between the taper angle of the resist cross section and the arrangement method of the sub patterns is acquired (S 5 ). The relationship between the taper angle of the resist cross section and the arrangement method of the sub patterns may be determined by simulation or may be actually measured with changes in the arrangement method of the sub patterns. At this time, as illustrated in FIG. 5 , the taper angle of the edge position of the resist pattern can be adjusted by adjusting the distance LG from the edge position of the main pattern H and the width N and pitch P of the sub patterns HS.

Next, the layout region of the mask pattern is divided in correspondence with the dividing positions in the resist pattern. Then, the sub patterns with a resolution equal to or less than the resolution limit to produce the desired process conversion differences are arranged in the individual divided layout regions (S 6 ). At this time, a maximum value Δm of the process conversion differences in the individual regions obtained by dividing the resist pattern at S 3 is used as a reference.

Then, the sub patterns can be arranged in the regions with the process conversion differences Δx other than the region with the maximum value Δm to compensate for the difference Δm−Δx between the maximum value Δm and the process conversion differences Δx in the regions. The maximum value Δm of the process conversion difference is used as a reference because the sub patterns can be arranged to increase the process conversion differences but the sub patterns cannot be arranged to decrease the process conversion differences.

Accordingly, it is possible to reduce variations in the process conversion differences at the edge positions of the processed pattern without changing the dimensions of the resist pattern.

(Second Embodiment)

FIG. 7 is a plane view of a configuration example of a mask pattern according to a second embodiment. In the second embodiment, the layout region of the mask pattern is divided into five as an example.

Referring to FIG. 7 , in an exposure mask M 2 , the layout region of the mask pattern is divided into regions D 11 to D 15 . The exposure mask M 2 includes four sides E 1 to E 4 . The regions D 12 to D 14 have the two sides E 1 and E 2 at end portions, the region D 11 has the three sides E 1 to E 3 at the end portions, and the region D 15 has the three sides E 1 , E 2 , and E 4 at the end portions.

A main pattern H 11 is arranged in the region D 11 and sub patterns HS 11 are arranged on both sides of the main pattern H 11 . The sub patterns HS 11 can be symmetrically arranged with respect to the main pattern H 11 . In addition, sub patterns HS 16 are arranged on the side E 3 of the region D 11 . A main pattern H 12 is arranged in the region D 12 and sub patterns HS 12 are arranged on both sides of the main pattern H 12 . The sub patterns HS 12 can be symmetrically arranged with respect to the main pattern H 12 .

A main pattern H 13 is arranged in the region D 13 and sub patterns HS 13 are arranged on both sides of the main pattern H 13 . The sub patterns HS 13 can be symmetrically arranged with respect to the main pattern H 13 . A main pattern H 14 is arranged in the region D 14 and sub patterns HS 14 are arranged on both sides of the main pattern H 14 . The sub patterns HS 14 can be symmetrically arranged with respect to the main pattern H 14 . A main pattern H 15 is arranged in the region D 15 and sub patterns HS 15 are arranged on both sides of the main pattern H 15 . The sub patterns HS 15 can be symmetrically arranged with respect to the main pattern H 15 . In addition, sub patterns HS 17 are arranged on the side of E 4 of the region D 15 .

The main patterns H 11 to H 15 can be solid patterns to be resolved by the exposure light EL. The arrangement density of the sub patterns HS 11 to HS 15 in the regions D 11 to D 15 can be lower with decreasing proximity to the edges of the main patterns H 11 to H 15 . The numbers of the sub patterns HS 12 and HS 14 arranged in the regions D 12 and D 14 can be larger than the numbers of the sub patterns HS 11 and HS 15 arranged in the regions D 11 and D 15 .

The number of the sub patterns HS 13 arranged in the region U 13 can be larger than the numbers of the sub patterns HS 12 and HS 14 arranged in the regions D 12 and D 14 . The numbers of the sub patterns HS 16 and HS 17 arranged in the regions D 11 and D 15 can be smaller than the numbers of the sub patterns HS 11 and HS 15 . The regions D 11 and D 15 can be symmetrically arranged with respect to the regions D 12 to D 14 . The regions D 12 and D 14 can be symmetrically arranged with respect to the region D 13 .

By making the numbers of the sub patterns HS 16 and HS 17 arranged in the regions D 11 and D 15 smaller than the numbers of the sub patterns HS 11 and HS 15 , the inclination angle of the edge positions of the resist pattern on the sides E 3 and E 4 can be smaller than the inclination angle of the edge positions of the resist pattern on the sides E 1 and E 2 . Accordingly, the process conversion difference on the sides E 3 and E 4 can be smaller than that on the sides E 1 and E 2 , thereby decreasing the amount of recession of the processed pattern on the sides E 3 and E 4 as compared to that on the sides E 1 and E 2 .

(Third Embodiment)

FIGS. 8A to 8F are cross-sectional views of a manufacturing method of a semiconductor device according to a third embodiment. FIGS. 8A, 8C, and 8E are cross-sectional views corresponding to line A-A′ of FIG. 7 , and FIGS. 8B, 6D, and 8F are cross-sectional views corresponding to line B-B′ of FIG. 7 .

Referring to FIGS. 8A and 8B , a stacked body TA is formed on a foundation layer K 2 . The stacked body TA has inter-layer insulation films 21 and conductive films 22 alternately stacked. For example, the material for the inter-layer insulation films 21 can be SiO 2 , and the material for the conductive films 22 can be a metal such as W or a polycrystalline silicon, or the like.

Lithography is performed with the use of the exposure mask M 2 illustrated in FIG. 7 to form a resist pattern R 2 on the stacked body TA. At this time, an inclined surface SC 1 with a taper angle θC 1 is formed at the edge of the resist pattern R 2 on the side E 1 of the exposure mask M 2 , and an inclined surface 3 C 2 with a taper angle θC 2 can be formed at the edge of the resist pattern R 2 on the side E 3 of the exposure mask M 2 . In this case, the relationship θC 2 >θC 1 can hold.

Next, as illustrated in FIGS. 8C and 8D , each time one each of the inter-layer insulation films 21 and the conductive films 22 is etched, the resist pattern R 2 is repeatedly slimmed to form steps DA and DB in the stacked body TA. At this time, the upper inter-layer insulation films 21 and conductive films 22 are receded relative to the lower inter-layer insulation films 21 and conductive films 22 to expose the lower conductive films 22 from the upper inter-layer insulation films 21 and conductive films 22 . By establishing the relationship θC 2 >θC 1 , a terrace size C 2 of the steps DB can be smaller than a terrace size C 1 of the steps DA.

Next, as illustrated in FIGS. 8E and 8F , an insulation film 23 is embedded in the steps DA and DB to flatten the steps DA and DB.

Next, an insulation film 24 is formed on the insulation film 23 and the stacked body TA by a method such as CVD. Then, contact plugs 25 are embedded into the insulation films 23 and 24 so as to be in contact with the individual conductive films 22 . Then, wires 26 connected to the contact plugs 25 are formed on the insulation film 24 .

By making the terrace size C 2 of the steps DB smaller than the terrace size C 1 of the steps DA, it is possible to reduce the chip size while maintaining the contact region.

In addition, by dividing the layout region of the mask pattern into the regions D 11 to D 15 and arranging the sub patterns HS 11 to HS 15 in the region D 11 to D 15 , respectively, the inclination angles at the edge positions of the resist pattern R 2 on the sides E 1 and E 2 can be equal. Accordingly, even when the stacked body TA is etched while the resist pattern R 2 is repeatedly slimmed, it is possible to reduce variations in the process conversion differences at the edge positions of the individual layers in the stacked body TA.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.