Image sensor supporting various operating modes and operating method thereof

A claim for priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 10-2015-0171656 filed Dec. 3, 2015, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

Inventive concepts described herein relate to an image sensor, and more particularly, relate to an image sensor supporting various operating modes that make it possible to improve the performance of an analog-to-digital converter (ADC).

The use of a mobile device such as a smartphone, a tablet personal computer (PC), a digital camera, an MP3 player, or an e-book reader continues to increase. To photograph an image, at least one image sensor is mounted on most mobile devices. Image sensors may be implemented, for example, as a charge coupled device (CCD) image sensor or a complementary metal-oxide semiconductor (CMOS) image sensor, for example.

Compared with a CMOS image sensor, a CCD image sensor has a low noise and an excellent image quality. However, a CMOS image sensor provides for simple and varied scanning and operation. Additionally, a signal processing circuit may be integrated in a single chip with a CMOS image sensor, thereby enabling miniaturization of a product. And, because a CMOS image sensor is compatible with CMOS process technology, the unit cost of production is reduced. Because of low power consumption, a CMOS image sensor is easily applied to a mobile device.

As the resolution of pixels constituting an image sensor increases and as an image sensor is miniaturized, a shared type of pixel array in which a plurality of transmission transistors share the same floating diffusion (FD) area is widely used. In the case of an image sensor using the shared type of pixel array, one analog digital converter generally processes a sense voltage outputted from pixels connected to one column. However, due to a structural feature that a floating diffusion area is shared therewith, all analog digital converters are not used while processing an image and this reduces the operating speed of an image sensor. Accordingly, it is important to improve the operating speed of an image sensor using a shared type of pixel array in which a plurality of transmission transistors shares the same floating diffusion area.

Example embodiments in accordance with principles of inventive concepts provide a method of reducing the operating speed of an analog digital converter while the operating speed of an image sensor is maintained by effectively arranging pixels included in an image sensor and column line connected to the pixels.

According example embodiments in accordance with principles of inventive concepts, an image sensor includes an active pixel sensor array including first to fourth pixel units sequentially arranged in a column direction, and each of the first to fourth pixel units includes a plurality of pixels, and a first pixel group including the first and second pixel units is connected to a first column line, and a second pixel group including the third and fourth pixel units is connected to a second column line and a correlated double sampling circuit including first and second correlated double samplers and configured to convert a first sense voltage sensed from a selected pixel of the first pixel group and a second sense voltage sensed from a selected pixel of the second pixel group into a first correlated double sampling signal and a second correlated double sampling signal, respectively. The first sense voltage is converted into the first correlated double sampling signal by one of the first and second correlated double samplers, and the second sense voltage is converted into the second correlated double sampling signal by the other of the first and second correlated double samplers.

According to another example embodiment in accordance with principles of inventive concepts, an image sensor includes an active pixel sensor array including first to tenth pixel units sequentially arranged in a column direction, each of the first to tenth pixel units includes a plurality of pixels, a first pixel group including the first, second, and seventh to tenth pixel units is connected to a first column line, and a second pixel group including the third to sixth pixel units is connected to a second column line, a row decoder configured to select a row of the active pixel sensor array under control of a timing controller, a correlated double sampling circuit including first and second correlated double samplers and configured to convert a first sense voltage sensed from a selected pixel of the first pixel group and a second sense voltage sensed from a selected pixel of the second pixel group into a first correlated double sampling signal and a second correlated double sampling signal, respectively, and a multiplexer configured to connect the first column line to one of the first and second correlated double samplers and to connect the second column line to the other of the first and second correlated double samplers under control of the timing controller. The first sense voltage is converted into the first correlated double sampling signal by one of the first and second correlated double samplers, and the second sense voltage is converted into the second correlated double sampling signal by the other of the first and second correlated double samplers.

According to still another example embodiment of the inventive concept, an image sensor includes an active pixel sensor array including first to fourth pixel units sequentially arranged in a column direction and fifth to eighth pixel units sequentially arranged in a column, which is adjacent to the first to fourth pixel units, in a column direction, and each of the first to eighth pixel units includes a plurality of pixels, and a first pixel group including the first and second pixel units is connected to a first column line, and a second pixel group including the third and fourth pixel units is connected to a second column line, and a third pixel group including the fifth and sixth pixel units is connected to a third column line, and a fourth pixel group including the seventh and eighth pixel units is connected to a fourth column line and a correlated double sampling circuit including first and fourth correlated double samplers and configured to convert a first sense voltage sensed from a selected pixel of the first pixel group and a second sense voltage sensed from a selected pixel of the second pixel group into a first correlated double sampling signal and a second correlated double sampling signal, respectively and to convert a third sense voltage sensed from a selected pixel of the third pixel group and a fourth sense voltage sensed from a selected pixel of the fourth pixel group into a third correlated double sampling signal and a fourth correlated double sampling signal, respectively. The first sense voltage is converted into the first correlated double sampling signal by one of the first and second correlated double samplers. The second sense voltage is converted into the second correlated double sampling signal by the other of the first and second correlated double samplers. The third sense voltage is converted into the third correlated double sampling signal by one of the third and fourth correlated double samplers. The fourth sense voltage is converted into the fourth correlated double sampling signal by the other of the third and fourth correlated double samplers.

In an example embodiment an image sensor includes an array of pixel units arranged in columns and rows, each pixel unit including a plurality of pixels sharing a floating diffusion region, and each pixel associated with a characteristic light range sensitivity; a plurality of correlated double-sampling circuits configured to perform correlated double sampling on photo signals generated by the pixels, wherein the correlated double samplers are configured to perform correlated double sampling in parallel on signals from a plurality of pixels of the same characteristic light range sensitivity from different pixel units within a column of pixel units; and a plurality of analog-to-digital converters configured to convert correlated double-sampled signals from different pixel units within a column of pixel units in parallel.

The above and other objects and features will become apparent from the following description with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified, and wherein

FIG. 1 is a block diagram illustrating an image sensor according to an embodiment of the inventive concept;

FIG. 2 is a block diagram illustrating an active pixel sensor array illustrated in FIG. 1 ;

FIG. 3 is a circuit diagram illustrating a pixel unit illustrated in FIG. 2 ;

FIG. 4 is a conceptual diagram illustrating an operating method of an image sensor according to an embodiment of the inventive concept;

FIGS. 5 to 12 are block diagrams illustrating embodiments illustrated in FIG. 4 by H-time;

FIG. 13 is a block diagram illustrating an operating method of an image sensor according to an embodiment of the inventive concept;

FIGS. 14 to 17 are block diagrams illustrating embodiments illustrated in FIG. 13 by H-time;

FIG. 18 is a conceptual diagram illustrating an active pixel sensor array driven according to an embodiment described through FIGS. 13 to 17 ;

FIG. 19 is a conceptual diagram illustrating an operating method of an image sensor according to an embodiment of the inventive concept;

FIG. 20 is a conceptual diagram illustrating an active pixel sensor array driven according to an embodiment described in FIG. 19 ;

FIG. 21 is a block diagram illustrating an operating method of an image sensor according to an embodiment of the inventive concept;

FIG. 22 is a conceptual diagram illustrating an active pixel sensor array driven according to an embodiment described in FIG. 20 ;

FIG. 23 is a block diagram illustrating an operating method of an image sensor according to an embodiment of the inventive concept;

FIG. 24 is a conceptual diagram illustrating an active pixel sensor array driven according to an embodiment described in FIG. 23 ;

FIG. 25 is a block diagram illustrating a configuration of a correlated double sampling circuit illustrated in FIG. 2 ;

FIG. 26 is a block diagram illustrating a configuration of a correlated double sampling circuit during a binning mode;

FIG. 27 is a conceptual diagram illustrating an active pixel sensor array driven according to a sub-sampling mode described in FIGS. 23 and 24 and a binning mode described in FIG. 26 ; and

FIG. 28 is a block diagram illustrating a mobile device to which the inventive concept is applied.

Below, example embodiments of inventive concepts will now be described more fully so that those skilled in the art can easily comprehend the inventive concepts.

FIG. 1 is a block diagram illustrating an example embodiment of an image sensor 100 in accordance with principles of inventive concepts. Referring to FIG. 1 , the image sensor 100 may include an active pixel sensor (APS) array 110 , a row decoder 120 , a multiplexing circuit 130 , a correlated double sampling circuit 140 , an analog-to-digital converting circuit 150 , an output buffer 160 , a column decoder 170 , and a timing controller 180 .

The active pixel sensor array 110 may include a plurality of pixels arranged in rows and columns. The active pixel sensor array 110 may include pixel units each of which shares the same floating diffusion (FD) area as one another. That is, pixels in a pixel unit may share a floating diffusion area, or region. In an example embodiment, one pixel unit is composed of four pixels all of which share the same floating diffusion area, but inventive concepts are not limited thereto. In other example embodiments different numbers of pixels may be included in a pixel unit, all of which share a floating diffusion area; one pixel unit may include eight pixels, all of which share the same floating diffusion area, for example. According to an embodiment of the inventive concept, pixel units connected to one multiplexer may be divided into two groups so as to be connected to two column lines different from each other. The detailed structure of the active pixel sensor array 110 will be described in the discussion related to FIG. 2 .

Each of the pixels constituting the active pixel sensor array 110 may convert a light signal into an electrical signal. Pixels connected to a row selected by a selection signal SEL may be driven by a reset signal RS and transmission signals TGs. In example embodiments the transmission signals TGs may include a plurality of transmission signals (e.g., TG 1 to TG 4 ), each for driving a plurality of pixels constituting a pixel unit (PXU). As a result, the electrical signal sensed at each pixel connected to the selected row may be transmitted to the correlated double sampling circuit 140 through a plurality of column lines CL 1 to CL 2 n.

The row decoder 120 may select any row of the active pixel sensor array 110 under control of the timing controller 180 . To select a, the row decoder 120 may generate the selection signal SEL. The row decoder 120 may transmit the reset signal RS and the transmission signals TGs to pixels corresponding to the selected row. In response, analog reference and an image signals generated from active pixel sensors of the selected row may be transmitted to the correlated double sampler 140 .

The multiplexing circuit 130 may select a plurality of column line CL 1 to CL 2 n . For example, the multiplexing circuit 130 may include a plurality of multiplexers, and two column lines may be connected to one multiplexer and a plurality of pixel units may be connected to each column line. The multiplexing circuit 130 may control the two column lines so as to be respectively connected to different correlated double samplers from each other based on a control signal C_SW received from the timing controller 180 . However, according to another embodiment of the inventive concept, the multiplexing circuit 130 may be omitted. In this case, inputs Vout 1 and Vout 2 may be directly and simultaneously input to correlated double samplers CDS 1 and CDS 2 , respectively. As a result, a sampling operation may be simultaneously performed with respect to pixels of two groups connected to one multiplexer, thereby improving the operating speed of an image sensor. The description thereof will be described in greater detail in the discussion related to FIG. 4 .

The correlated double sampling circuit 140 may sequentially sample and hold a set of reference signal (REF) and an image signal (IMG) provided from the active pixel sensor array 110 to each of a plurality of column lines CL 1 to CL 2 n . That is, the correlated double sampling circuit 130 may sample and hold the level of the reference signal REF and the image signal IMG corresponding to each column. The correlated double sampling circuit 130 may transmit, to the analog-to-digital converting circuit 150 , the set of the reference signal (REF) and/or the image signal (IMG) of each of the columns sampled according to control of the timing controller 180 by a plurality of column units. The correlated double sampling circuit 140 may include a plurality of correlated double samplers. In example embodiments, two correlated double samplers may be connected to one multiplexer.

The analog-to-digital converting circuit 150 may convert a correlated double sampling signal (e.g., the reference signal (REF) and/or the image signal (IMG)), which is outputted from the correlated double sampling circuit 130 , related to each column into a digital signal and may output the digital signal.

The output buffer 160 may latch and output image data from each column unit, which is provided from the analog-to-digital converting circuit 150 . The output buffer 160 may temporarily store image data outputted from the analog-to-digital converting circuit 150 under control of the timing controller 180 and may output the image data sequentially latched by the column decoder 170 .

The column decoder 170 may select the column of the output buffer 160 under control of the timing controller 180 . The output buffer 160 may sequentially output image data stored by a column unit based on the selection of the column decoder 160 .

Above, a configuration of the image sensor 100 according to an example embodiment in accordance with principles of inventive concepts is briefly described. In particular, two column lines and two correlated double samplers may be connected to each multiplexer constituting the multiplexing circuit 1300 , and pixels of two groups may be respectively connected to two column lines. Moreover, the timing controller 180 may control a multiplexer such that pixels of two different groups are respectively connected to two different correlated double samplers. As a result, two analog digital converters respectively connected to two correlated double samplers may simultaneously perform a converting operation in parallel, thereby improving the operating speed of the image sensor 100 .

FIG. 2 is a block diagram illustrating in greater detail an example embodiment of an active pixel sensor array 110 in accordance with principles of inventive concepts. Referring to FIG. 2 , the active pixel sensor array 110 may include a plurality of pixels arranged in a plurality of rows and a plurality of columns. Each pixel unit (PXU) may include four pixels and may be defined as a group of pixels sharing the same floating diffusion area (FD) with one another. A pixel unit (PXU) may be connected to two column lines (e.g., CL 1 and CL 2 ) and one row line (i.e., one of RL 1 to RLm). For example, the reset signal RS, the transmission signals TGs, and the selection signal SEL may be inputted through a row line RL 1 connected to the pixel unit (PXU). The detailed structure of an example embodiment of the pixel unit PXU will be described in the discussion related to FIG. 3 .

A pixel unit (PXU) may include a pixel R including a red filter, pixels Gr and Gb, each of which includes a green filter, and a pixel B including a blue filter. The pixel Gr may be a pixel that is adjacent to the pixel R in a row direction, and the pixel Gb may be a pixel that is adjacent to the pixel B in a row direction. The red filter may allow light of a red wavelength bandwidth to pass, the green filter may pass light of a green wavelength bandwidth, and the blue filter may pass light of a blue wavelength bandwidth. Each pixel may include a plurality of transistors and a photoelectric conversion device. Each pixel may detect a light using a photoelectric conversion device, may convert the light into an electrical signal, and may output the electrical signal through column lines CL 1 to CL 2 n.

When the reset signal RS and the transmission signals TGs are inputted to a row selected in response to the selection signal SEL, sense voltages Vout 1 to Vout 2 n corresponding to the reset signal RS and the transmission signals TGs may be outputted to each of the column lines CL 1 to CL 2 n of the selected row.

According to an embodiment of the inventive concept, pixel units (PXUs) arranged between two columns adjacent to each other may be connected to two different column lines. For example, referring to FIG. 2 , pixel units PXU 1 , PXU 2 , PXU 7 , etc. among pixel units PXU 1 to PXUm that are arranged on the leftmost side may be connected to the first column line CL 1 . Pixel units PXU 3 to PXU 6 , etc. may be connected to the second column line CL 2 . That is, the pixel units PXU 1 and PXU 2 respectively connected to the first and second row lines RL 1 and RL 2 may be connected to the first column line CL 1 and pixel units PXU 3 to PXUm may be alternately connected to the second column line CL 2 and the first column line CL 1 by four pixel units connected to four row lines. Even though the pixel unit PXUm is illustrated as being connected to the first column line CL 1 in FIG. 2 , the pixel unit PXUm may be connected to the second column line CL 2 based on the number of rows (e.g., m).

The multiplexing circuit 130 may include a plurality of multiplexers, MUX 1 to MUXn. As illustrated in FIG. 2 , two column lines may be connected to each multiplexer. The multiplexer may allow sense voltages (e.g., Vout 1 and Vout 2 ) outputted from each column line to be respectively connected to different correlated double samplers (e.g., CDS 1 and CDS 2 ) based on a control signal C_MUX from the timing controller 180 (refer to FIG. 1 ). As a result, the sense voltages (e.g., Vout 1 and Vout 2 ) outputted from the different column lines (e.g., CL 1 and CL 2 ) may be simultaneously processed.

The correlated double sampling circuit 140 may include a plurality of correlated double samplers CDS 1 to CDS 2 n . As illustrated in FIG. 2 , two correlated double samplers may be connected to a column line by one multiplexer. Each correlated double sampler may sample the sense voltages Vout 1 to Vout 2 n provided from a multiplexer as each of the reference signal REF and the image signal IMG.

The analog-to-digital converting circuit 150 may include a plurality of analog-to-digital converters ADC 1 to ADC 2 n . The plurality of analog-to-digital converters ADC 1 to ADC 2 n may respectively correspond to the plurality of correlated double samplers, and the analog-to-digital converters ADC 1 to ADC 2 n may respectively convert analog signals AS 1 to AS 2 n , each of which is received from a corresponding correlated double sampler, into digital signals DS 1 to DS 2 n.

FIG. 3 is a circuit diagram illustrating an example embodiment of a pixel unit PXU 1 in accordance with principles of inventive concepts. Referring to FIG. 3 , a pixel unit PXU 1 may include four photoelectric conversion devices (PCDs), four transmission transistors T 1 to T 4 , a reset transistor RT, a drive transistor DT, and a select transistor ST. The transmission transistor T 1 , the reset transistor RT, the drive transistor DT, and the select transistor ST may constitute the pixel Gr of FIG. 2 , the transmission transistor T 2 , the reset transistor RT, the drive transistor DT, and the select transistor ST may constitute the pixel B of FIG. 2 , the transmission transistor T 3 , the reset transistor RT, the drive transistor DT, and the select transistor ST may constitute the pixel R of FIG. 2 , and, the transmission transistor T 4 , the reset transistor RT, the drive transistor DT, and the select transistor ST may constitute the pixel Gb of FIG. 2 , for example.

Each photoelectric conversion device PCD may be a light sensing device for generating and accumulating a charge based on an amount, or intensity, of incident light. The photoelectric conversion device PCD may be implemented with a photo diode, a photo transistor, a photo gate, a pinned photo diode (PPD), and the like.

The transmission transistors T 1 to T 4 may transmit a charge accumulated by the photoelectric conversion devices PCDs onto the floating diffusion area FD. As illustrated in FIG. 3 , the transmission transistors T 1 to T 4 may share the floating diffusion area FD. That is, the output of each of the transmission transistors T 1 to T 4 may be connected to one node. Each of the transmission transistors T 1 to T 4 may be turned on or off in response to each of the transmission signals TG 1 to TG 4 provided from the row decoder 120 (refer to FIG. 1 ).

The floating diffusion area FD may function to detect a charge corresponding to an amount of incident light. A charge provided from a photoelectric conversion device PCD may be accumulated in the floating diffusion area FD during a time when each of the transmission signals TG 1 to TG 4 is activated. For example, each of the transmission signals TG 1 to TG 4 may be sequentially activated, and thus the transmission transistors T 1 to T 4 may be sequentially turned on, and charge sequentially accumulated and read out for each PCD. The floating diffusion area FD may be connected to the gate terminal of the drive transistor DT, operating as a source follower amplifier to read out charge accumulated in the floating diffusion area FD. The floating diffusion area FD may receive a power supply voltage Vdd by the reset transistor RT.

The reset transistor RT may reset the floating diffusion area FD in response to a reset signal RS 1 . The source terminal of the reset transistor RT may be connected to the floating diffusion area FD, and the drain terminal thereof may be connected to a power supply voltage Vdd terminal. When the reset transistor RT is turned-on in response to the reset signal RS 1 , the power supply voltage Vdd connected with the drain terminal of the reset transistor RT may be transmitted to the floating diffusion area FD and the charge accumulated at the floating diffusion area FD may move to the power supply voltage Vdd terminal, and the voltage of the floating diffusion area FD may sequentially provide a reset and photo-signal

The drive transistor DT may be turned-on/off according to an electrical potential of the floating diffusion area FD. For example, if the reset transistor RT is turned-on by the reset signal RS 1 , the drive transistor DT is turned-off, and floating diffusion area FD is reset as Vdd. That is, a first analogue signal corresponding to the reset signal RS 1 is outputted through column line CL 1 . On the other hand, if the reset transistor RT is turned-off by the reset signal RS 1 and the first transmission transistor T 1 is turned-on by the first transmission signal TG 1 , a charge provided from the photoelectric conversion device PCD may be accumulated in the floating diffusion area FD. As a result, the drive transistor DT is turned-on and a second analogue signal corresponding to the charge is outputted through column line CL 1 . The pixel unit PXU 1 is illustrated as being connected to the first column line CL 1 ; other pixel units (e.g., PXU 3 to PXU 6 , etc.) may be connected to the second column line CL 2 in this example embodiment, as previously described.

The select transistor ST may select a pixel to be read by a row unit. The select transistor ST may be driven in response to the selection signal SEL 1 provided by a row unit. When the select transistor ST is turned on, the potential of the floating diffusion area FD may be amplified and transmitted to the drain terminal of the select transistor ST through the drive transistor DT.

According to the described example embodiment, one pixel unit is described as including four photoelectric conversion devices (i.e., four pixels). However, embodiments of inventive concepts may not be limited thereto. For example, one pixel unit may include eight pixels. In such embodiments, because the structure is the same except that eight transmission transistors share one floating diffusion area, a detailed description thereof will not be repeated here.

FIG. 4 is a conceptual diagram for illustrating an operating method of an image sensor according to an example embodiment in accordance with principles of inventive concepts. In FIG. 4 , a full mode of operation will be described below. The full mode may refer to performing a sampling and holding operation and an analog-to-digital converting operation with respect to a voltage sensed by all pixels constituting the active pixel sensor array 110 (refer to FIG. 2 ). For example, the pixel units PXU 1 to PXUm connected to the multiplexer MUX 1 of FIG. 2 is described below.

In an example embodiment, the first pixel unit PXU 1 connected to the first row line and the second pixel unit PXU 2 connected to the second row line may be connected to the first column line CL 1 . Subsequent pixel units PXU 3 to PXUm may be alternately connected to different column lines (alternating CL 1 and CL 2 , for example) by four-pixel units. That is, for example, the third pixel unit PXU 3 connected to the third row line, the fourth pixel unit PXU 4 connected to the fourth row line, the fifth pixel unit PXU 5 connected to the fifth row line, and the sixth pixel unit PXU 6 connected to the sixth row line may be connected to the second column line CL 2 ; the seventh pixel unit PXU 7 connected to the seventh row line, the eighth pixel unit PXU 8 connected to the eighth row line, the ninth pixel unit PXU 9 connected to the ninth row line, and the tenth pixel unit PXU 10 connected to the tenth row line may be connected to the first column line CL 1 , and so on.

In operation, from 1 Horizontal time (H-time) to 8 H-time, sensing operations by the first and second pixel unit PXU 1 and PXU 2 connected to the first column line CL 1 and sensing operations by the third and fourth pixel unit PXU 3 and PXU 4 connected to the second column line CL 2 may be performed at the same timing. That is, for example, a sensing operation at the pixel Gr of the first pixel unit PXU 1 and a sensing operation at the pixel Gr of the third pixel unit PXU 3 may occur simultaneously in a first horizontal time period; sensing of the pixel B of the first pixel unit PXU 1 and of the pixel B of the third pixel unit PXU 3 may occur simultaneously during a second horizontal time period; sensing of the pixel Gr of the second pixel unit PXU 2 and of the pixel Gr of the fourth pixel unit PXU 4 , may occur simultaneously during a third horizontal time period; sensing of the pixel B of the second pixel unit PXU 2 and of the pixel B of the fourth pixel unit PXU 4 , may occur simultaneously during a fourth horizontal time period; sensing of the pixel R of the first pixel unit PXU 1 and of the pixel R of the third pixel unit PXU 3 , may occur simultaneously during a fifth horizontal time period; and so on.

In more detail, when the selection signal SEL 1 is applied to select the first pixel unit PXU 1 , a selection signal S_SEL 3 for selecting the third pixel unit PXU 3 may be applied simultaneously. When the reset signal RS 1 is applied to drive the reset transistor RT (refer to FIG. 2 ) of the first pixel unit PXU 1 , a reset signal S_RS 3 may be applied to simultaneously drive the reset transistor of the third pixel unit PXU 3 . When the transmission signals TGs for driving the transmission transistors T 1 to T 4 of the first pixel unit PXU 1 are applied, the transmission signals TGs for driving the transmission transistors T 1 to T 4 of the third pixel unit PXU 3 may be applied simultaneously. An “S”, which is illustrated in FIG. 4 , attached in front of names of signals applied to the third pixel unit PXU 3 may be to give a meaning of “being performed at the same time” (or, simultaneously) as the corresponding signals applied to first pixel unit PXU 1 .

When sensing operations by the first to fourth pixel units PXU 1 to PXU 4 are completed according to the simultaneous read operation, sensing operations by the fifth to eighth pixel units PXU 5 to PXU 8 may be performed from 9 H-time to 16 H-time in a manner corresponding to that just described in relation to pixel units PXU 1 through PXU 4 . During each H-time, or period, specific control signals inputted to pixels are illustrated in, and will be described in greater detail in the discussion related to FIGS. 5 to 12 .

Referring to FIG. 5 , the selection signal SEL 1 , the reset signal RS 1 and the first transmission signal TG 1 may be applied to the first pixel unit PXU 1 during 1 H-time (also referred to herein as a first horizontal time period). The first transmission signal TG 1 may be a signal for driving the pixel Gr (e.g., the first transmission transistor T 1 of FIG. 2 ) constituting the first pixel unit PXU 1 . At the same time, the selection signal S_SEL 3 , the reset signal S_RS 3 , and a first transmission signal S_TG 1 may be applied to the third pixel unit PXU 3 . The first transmission signal S_TG 1 may be a signal for driving the pixel Gr (e.g., the first transmission transistor T 1 of FIG. 2 ) constituting the third pixel unit PXU 3 . The voltage Vout 1 sensed by the pixel Gr of the first pixel unit PXU 1 may be outputted through the first column line CL 1 , and the voltage Vout 2 sensed by the pixel Gr of the third pixel unit PXU 3 may be outputted through the second column line CL 2 . Because the sense voltages Vout 1 and Vout 2 are simultaneously outputted by the pixel units PXU 1 and PXU 2 respectively connected to the column lines CL 1 and CL 2 , the sense voltages Vout 1 and Vout 2 may be simultaneously processed by the correlated double samplers CDS 1 and CDS 2 (refer to FIG. 2 ), respectively.

Referring to FIG. 6 , the selection signal SEL 1 , the reset signal RS 1 and the second transmission signal T 2 may be applied to the first pixel unit PXU 1 during 2 H-time (also referred to herein as the second horizontal time period). The second transmission signal TG 2 may be a signal for driving the pixel B (e.g., the second transmission transistor T 2 of FIG. 2 ) constituting the first pixel unit PXU 1 . At the same time, the selection signal S_SEL 3 , the reset signal S_RS 3 , and a second transmission signal S_TG 2 may be applied to the third pixel unit PXU 3 . The second transmission signal S_TG 2 may be a signal for driving the pixel B (e.g., the second transmission transistor T 2 of FIG. 2 ) constituting the third pixel unit PXU 3 .

The voltage Vout 1 sensed by the pixel B of the first pixel unit PXU 1 may be outputted through the first column line CL 1 , and the voltage Vout 2 sensed by the pixel B of the third pixel unit PXU 3 may be outputted through the second column line CL 2 .

Referring to FIG. 7 , a selection signal SEL 2 , a reset signal RS 2 , and the first transmission signal TG 1 may be applied to the second pixel unit PXU 2 during 3 H-time (also referred to herein as the third horizontal time period). The first transmission signal TG 1 may be a signal for driving the pixel Gr (e.g., the first transmission transistor T 1 of FIG. 2 ) constituting the second pixel unit PXU 2 . At the same time, a selection signal S_SEL 4 , a reset signal S_RS 4 , and the first transmission signal S_TG 1 may be applied to the fourth pixel unit PXU 4 . The first transmission signal S_TG 1 may be a signal for driving the pixel Gr (e.g., the first transmission transistor T 1 of FIG. 2 ) constituting the fourth pixel unit PXU 4 .

The voltage Vout 1 sensed by the pixel Gr of the second pixel unit PXU 2 may be outputted through the first column line CL 1 , and the voltage Vout 2 sensed by the pixel Gr of the fourth pixel unit PXU 4 may be outputted through the second column line CL 2 .

Referring to FIG. 8 , the selection signal SEL 2 , the reset signal RS 2 and the second transmission signal TG 2 may be applied to the second pixel unit PXU 2 during 4 H-time (also referred to herein as the fourth horizontal time period). The second transmission signal TG 2 may be a signal for driving the pixel B (e.g., the second transmission transistor T 2 of FIG. 2 ) constituting the second pixel unit PXU 2 . At the same time, the selection signal S_SEL 4 , the reset signal S_RS 4 , and the second transmission signal S_TG 2 may be applied to the fourth pixel unit PXU 4 . The second transmission signal S_TG 2 may be a signal for driving the pixel B (e.g., the second transmission transistor T 2 of FIG. 2 ) constituting the fourth pixel unit PXU 4 .

The voltage Vout 1 sensed by the pixel B of the second pixel unit PXU 2 may be outputted through the first column line CL 1 , and the voltage Vout 2 sensed by the pixel B of the fourth pixel unit PXU 4 may be outputted through the second column line CL 2 .

Referring to FIG. 9 , the selection signal SEL 1 , the reset signal RS 1 and the third transmission signal TG 3 may be applied to the first pixel unit PXU 1 during 5 H-time (also referred to herein as the fifth horizontal time period). The third transmission signal TG 3 may be a signal for driving the pixel R (e.g., the third transmission transistor T 3 of FIG. 2 ) constituting the first pixel unit PXU 1 . At the same time, the selection signal S_SEL 4 , the reset signal S_RS 4 , and a third transmission signal S_TG 3 may be applied to the fourth pixel unit PXU 4 . The third transmission signal S_TG 3 may be a signal for driving the pixel R (e.g., the third transmission transistor T 3 of FIG. 2 ) constituting the third pixel unit PXU 3 .

The voltage Vout 1 sensed by the pixel R of the first pixel unit PXU 1 may be outputted through the first column line CL 1 , and the voltage Vout 2 sensed by the pixel R of the third pixel unit PXU 3 may be outputted through the second column line CL 2 .

Referring to FIG. 10 , the selection signal SEL 1 , the reset signal RS 1 , and the fourth transmission signal TG 4 may be applied to the first pixel unit PXU 1 during 6 H-time (also referred to herein as the sixth horizontal time period) The fourth transmission signal TG 4 may be a signal for driving the pixel Gb (e.g., the fourth transmission transistor T 4 of FIG. 2 ) constituting the first pixel unit PXU 1 . At the same time, the selection signal S_SEL 4 , the reset signal S_RS 4 , and a fourth transmission signal S_TG 4 may be applied to the third pixel unit PXU 3 . The fourth transmission signal S_TG 4 may be a signal for driving the pixel Gb (e.g., the fourth transmission transistor T 4 of FIG. 2 ) constituting the third pixel unit PXU 3 .

The voltage Vout 1 sensed by the pixel Gb of the first pixel unit PXU 1 may be outputted through the first column line CL 1 , and the voltage Vout 2 sensed by the pixel Gb of the third pixel unit PXU 3 may be outputted through the second column line CL 2 .

Referring to FIG. 11 , the selection signal SEL 2 , the reset signal RS 2 , and the third transmission signal TG 3 may be applied to the second pixel unit PXU 2 during 7 H-time (also referred to herein as the seventh horizontal time period). The third transmission signal TG 3 may be a signal for driving the pixel R (e.g., the third transmission transistor T 3 of FIG. 2 ) constituting the second pixel unit PXU 2 . At the same time, the selection signal S_SEL 4 , the reset signal S_RS 4 , and the third transmission signal S_TG 3 may be applied to the fourth pixel unit PXU 4 . The third transmission signal S_TG 3 may be a signal for driving the pixel R (e.g., the third transmission transistor T 3 of FIG. 2 ) constituting the fourth pixel unit PXU 4 .

The voltage Vout 1 sensed by the pixel R of the second pixel unit PXU 2 may be outputted through the first column line CL 1 , and the voltage Vout 2 sensed by the pixel R of the fourth pixel unit PXU 4 may be outputted through the second column line CL 2 .

Finally, referring to FIG. 12 , the selection signal SEL 2 , the reset signal RS 2 , and the fourth transmission signal TG 4 may be applied to the second pixel unit PXU 2 during 8 H-time (also referred to herein as the eighth horizontal time period). The fourth transmission signal TG 4 may be a signal for driving the pixel Gb (e.g., the fourth transmission transistor T 4 of FIG. 2 ) constituting the second pixel unit PXU 2 . At the same time, the selection signal S_SEL 4 , the reset signal S_RS 4 , and the fourth transmission signal S_TG 4 may be applied to the fourth pixel unit PXU 4 . The fourth transmission signal S_TG 4 may be a signal for driving the pixel Gb (e.g., the fourth transmission transistor T 4 of FIG. 2 ) constituting the fourth pixel unit PXU 4 .

The voltage Vout 1 sensed by the pixel Gb of the second pixel unit PXU 2 may be outputted through the first column line CL 1 , and the voltage Vout 2 sensed by the pixel Gb of the fourth pixel unit PXU 4 may be outputted through the second column line CL 2 .

As described in FIGS. 5 to 12 , a sensing operation may be simultaneously performed with respect to the pixel units (PXUs) respectively connected to different column lines, thereby reducing processing time by the correlated double sampling circuit 140 (refer to FIG. 2 ), and the analog digital converting circuit 150 . Moreover, during the procedure, the multiplexing circuit 130 (refer to FIG. 2 ) may allow the sense voltages Vou 1 to Vout 2 n to be respectively processed by different correlated double samplers (and different analog digital converters).

FIG. 13 is a block diagram illustrating an operating method of an image sensor according to another example embodiment in accordance with principles of inventive concepts in which a different pattern of simultaneous readouts are employed. FIGS. 14 to 17 are block diagrams illustrating embodiments illustrated in FIG. 13 by H-time, or horizontal time period.

In an example embodiment, a binning mode will be described below. Unlike the above-described full mode, associated with FIGS. 4-12 , the binning mode may refer to a mode in which a value (or mean value) obtained by summing output values of the same type of pixels is outputted as a sense voltage. According to an embodiment of the inventive concept, 2-binning mode in which a value (or mean value) obtained by summing outputs of the same type of two pixels is outputted as a sense voltage will be described. For example, the pixel units PXU 1 to PXUm connected to the multiplexer MUX 1 of FIG. 2 is described below. The transmission signals TGs illustrated in FIG. 13 may include the transmission signals TG 1 to TG 4 for driving four pixels included in one pixel unit (PXU).

Referring to FIGS. 13 and 14 , during 1 H-time, a sensing operation by the pixels Gr of the first to fourth pixel units PXU 1 to PXU 4 may be performed.

To perform a sensing operation by the pixel Gr of the first pixel unit PXU 1 , the reset signal RS 1 , the selection signal SEL 1 and the transmission signal TG 1 may be inputted to the first pixel unit PXU 1 . At the same time, to perform a sensing operation by the pixel Gr of the first pixel unit PXU 1 , a reset signal B_RS 2 , a selection signal B_SEL 2 and a transmission signal B_TG 1 may be inputted to the second pixel unit PXU 2 . The voltage Vout 1 sensed by the first and second pixel units PXU 1 and PXU 2 may be simultaneously outputted to the first column line CL 1 .

Moreover, to perform a sensing operation by the pixel Gr of the third pixel unit PXU 3 , the reset signal S_RS 3 , the selection signal S_SEL 3 , and the transmission signal S_TG 1 may be inputted to the third pixel unit PXU 3 . At the same time, to perform a sensing operation by the pixel Gr of the fourth pixel unit PXU 4 , the reset signal S_RS 3 , the selection signal S_SEL 3 , and the transmission signal S_TG 1 may be inputted to the fourth pixel unit PXU 4 . The voltage Vout 2 sensed by the third and fourth pixel units PXU 3 and PXU 4 may be simultaneously outputted to the second column line CL 2 .

That is, a binning operation in which a value (or mean value) obtained by summing voltages sensed by the first and second pixel units PXU 1 and PXU 2 is outputted may be performed, and a binning operation in which a value (or mean value) obtained by summing voltages sensed by the third and fourth pixel units PXU 3 and PXU 4 is outputted may be performed. Of course, in order to obtain a mean value by perform binning operation, meaning circuit or averaging circuit (not shown), configured to receive sense voltages Vout 1 and Vout 2 and to calculate the mean value, may be further provided. Moreover, sensing operations may be simultaneously performed by the first and second pixel units PXU 1 and PXU 2 and the third and fourth pixel units PXU 3 and PXU 4 .

Afterwards, from 2 H-time to 4 H-time (also referred to herein as from horizontal time period 2H though horizontal time period 4H), a sensing operation similar to the sensing operation of the pixel Gr may be performed with respect to other pixels B, R, and Gb of each of the first to fourth pixel units PXU 1 to PXU 4 . An operation from 2 H-time to 4 H-time is described in FIGS. 15 to 17 in detail. This is similar to the above-described sensing operation during 1 H-time, and, as a result, the detailed description thereof will not be repeated here.

According to an example embodiment, sensing operations may be simultaneously performed by pixel groups connected to two different column lines. As a result, the processing time span of the correlated double sampling circuit 140 (refer to FIG. 2 ) and the analog digital converting circuit 150 may be reduced by more reducing idle times. Additionally, a summation value (or mean value) of voltages sensed by a plurality of pixels through the binning operation may be outputted, and thus the number of occurrence of processing a sense voltage by a correlated double sampler and an analog digital converter may be reduced. As a result, the power-consumption of an image sensor may be reduced.

FIG. 18 is a conceptual diagram illustrating an active pixel sensor array driven according to an example embodiment described in the discussion related to FIGS. 13 to 17 . Pixels attached to one another in units of four may constitute one pixel unit (PXU). Moreover, a digit indicated at the center of a pixel unit may be the number of a column line to which a voltage sensed by a pixel is outputted.

In operation, during 1 H-time (also referred to herein as a first horizontal time period), a sensing operation by pixels Gr of pixel units respectively connected to rows R 1 to R 10 may be performed. For example, a sensing operation by the pixels connected to the row R 2 and a sensing operation by the pixels connected to the row R 4 may simultaneously be performed. As illustrated in FIG. 18 , a voltage sensed by the pixel Gr connected to the row R 2 and the column C 1 may be outputted through the first column line {circle around ( 1 )} and a voltage sensed by the pixel Gr connected to the row R 4 and the column C 1 may be outputted through the second column line {circle around ( 2 )}. Sense voltages outputted through the first and second column lines {circle around ( 1 )} and {circle around ( 2 )} may be respectively processed by two different correlated double samplers and two different analog-to-digital converters.

In example embodiments, a binning operation (i.e., vertical binning) may be performed with respect to the pixels connected to two rows (e.g., R 1 and R 2 ) that are adjacent to each other. This is indicated by the shaded areas and arrows in FIG. 18 . For example, a value (or a mean value) obtained by summing voltages sensed by the pixel Gr connected to the row R 1 and the column C 1 and the pixel Gr connected to the row R 2 and the column C 1 may be outputted through the first column line CL 1 (refer to FIG. 2 ).

From 2 H-time to 4 H-time (also referred to herein as from horizontal time period 2H through horizontal time period 4H), operations similar to the operations during 1 H-time may be performed. That is, a voltage sensed by the pixel unit connected to the row R 2 and a voltage sensed by the pixel unit connected to the row R 4 may be respectively outputted through the first column line {circle around ( 1 )} and the second column line {circle around ( 2 )}. Operations similar thereto may be performed with respect to the pixel units connected to the column C 3 to C 8 . Sensing operations may be simultaneously performed by the pixel groups connected to two different column lines based on the operating method, thereby improving the operating speed of an image sensor. By operating in parallel in this fashion a system and method in accordance with principles of inventive concepts may accelerate the operation of an image sensor in accordance with principles of inventive concepts.

FIG. 19 is a conceptual diagram illustrating an operating method of an image sensor according to an example embodiment in accordance with principles of inventive concepts. In this example embodiment, a sub-sampling mode will be described. The sub-sampling mode may refer to performing a sensing operation through only a subset of all the pixels of an active pixel sensor array.

Referring to FIG. 19 , a method in which the column lines CL 1 and CL 2 are connected to the pixel units PXU 1 to PXUm may be the same as described above. That is, the pixel units PXU 1 and PXU 2 may be connected to the first column line CL 1 , and the pixel units PXU 3 to PXUm may be alternately connected to different column lines by four pixel units. A hatched area in FIG. 19 may indicate a pixel unit upon which a sensing operation is not performed. The transmission signals TGs inputted to the pixel unit (PXU) may include the transmission signals TG 1 to TG 4 (refer to FIG. 3 ) for driving each of pixels constituting the pixel unit (PXU).

During 1 H-time (also referred to herein as a first horizontal time period 1H), a sensing operation may be performed by the pixel Gr of the second pixel unit PXU 2 . A sensing operation may be performed according to the selection signal SEL 2 , the reset signal RS 2 , and the transmission signal TG 1 received from the row decoder 120 (refer to FIG. 1 ). The voltage Vout 1 sensed by the pixel Gr of the second pixel unit PXU 2 may be outputted through the first column line CL 1 .

At the same time, a sensing operation may be performed by the pixel Gr of the fifth pixel unit PXU 5 . A sensing operation may be performed according to the selection signal SEL 5 , the reset signal RS 5 , and the transmission signal TG 1 received from the row decoder 120 . The voltage Vout 2 sensed by the pixel Gr of the fifth pixel unit PXU 5 may be outputted through the second column line CL 2 .

Afterwards, from 2 H-time to 4 H-time and from 5 H-time to 8 H-time (also referred to herein as from a second 2H through fourth 4H and from a fifth 5H through eighth 8H horizontal time period), the operation similar thereto may be performed. The sensing operations are simultaneously performed by two pixel units respectively connected to different column lines from each other may be similar to above-described embodiments. A sub-sampling mode in accordance with principles of inventive concepts may be used in an environment in which a rapid sensing speed or reduced power consumption is required.

FIG. 20 is a conceptual diagram illustrating an active pixel sensor array driven according to an example embodiment such as that described in relation to FIG. 19 . Pixels attached to one another in units of four may constitute one pixel unit. In this example embodiment a digit displayed at the center of a pixel unit may be the number of a column line to which a voltage sensed by a pixel is outputted. A hatched area (i.e., skip) in FIG. 20 may indicate a pixel unit upon which a sensing operation is not performed.

During 1 H-time, a first horizontal time period 1H, sensing operations by pixels Gr of pixel units respectively connected to the rows R 2 and R 5 may be performed. A sensing operation by the pixels connected to the row R 2 and a sensing operation by the pixels connected to the row R 5 may be simultaneously performed in accordance with principles of inventive concepts. As illustrated in FIG. 20 , a voltage sensed by the pixel Gr connected to the row R 2 and the column C 1 may be outputted through the first column line {circle around ( 1 )}, and a voltage sensed by the pixel Gr connected to the row R 5 and the column C 1 may be outputted through the second column line {circle around ( 2 )}. Sense voltages outputted through the first and second column lines {circle around ( 1 )} and {circle around ( 2 )} may be respectively processed by two different correlated double samplers and two different analog-to-digital converters.

From 2 H-time to 4 H-time, from a second 2H through a fourth 4H horizontal time period, an operation similar to the operation during 1 H-time, a first horizontal time period 1H, may be performed. That is, a voltage sensed by the pixel unit connected to the row R 2 and a voltage sensed by the pixel unit connected to the row R 5 may be respectively outputted through the first column line {circle around ( 1 )} and the second column line {circle around ( 2 )}. Operations similar thereto may be performed with respect to the pixel units connected to the column C 3 to C 8 . Sensing operations may be simultaneously performed by the pixel groups connected to two different column lines, thereby improving the operating speed of an image sensor.

FIG. 21 is a block diagram illustrating an example embodiment of an operating method of an image sensor in accordance with principles of inventive concepts. According to an example embodiment, 4-binning mode in which a value (or mean value) obtained by summing outputs of the same type of four pixels is outputted as a sense voltage will be described. For example, the pixel units PXU 1 to PXUm connected to the multiplexer MUX 1 of FIG. 2 is described below. The transmission signals TGs illustrated in FIG. 21 may include the transmission signals TG 1 to TG 4 for driving four pixels included in one pixel unit (PXU).

During 1 H-time, a first horizontal time period 1H, sensing operations may be performed by the pixels Gr of the third to tenth pixel units PXU 3 to PXU 10 . Sensing operations by the pixels Gr of the third to sixth pixel units PXU 3 to PXU 6 may be performed according to selection signals SEL 3 , B_SEL 4 , B_SEL 5 , and B_SEL 6 , reset signals RS 3 , B_RS 4 , B_RS 5 , and B_RS 6 , and the transmission signal TG 1 received from the row decoder 120 (refer to FIG. 1 ). The voltage Vout 1 sensed by the third to sixth pixel units PXU 3 to PXU 6 may be outputted through the first column line CL 1 .

At the same time, sensing operations by the pixels Gr of the seventh to tenth pixel units PXU 7 to PXU 10 may be performed according to selection signals S_SEL 7 , SB_SEL 8 , SB_SEL 9 , and SB_SEL 10 , reset signals S_RS 7 , SB_RS 8 , SB_RS 9 , and SB_RS 10 , and the transmission signal TG 1 received from the row decoder 120 . The voltage Vout 2 sensed by the seventh to tenth pixel units PXU 7 to PXU 10 may be outputted through the second column line CL 2 .

An operation performed from 2 H-time to 4 H-time, from a second horizontal time period 2H through a fourth horizontal time period 4H, is similar to the operation performed during 1 H-time, the first horizontal time period 1H, and thus the detailed description thereof will not be repeated here.

According to an example embodiment in accordance with principles of inventive concepts, a binning operation is performed with respect to four pixels, unlike the example embodiment described in in the discussion related to FIG. 13 . The example 4-binning mode may be used in an environment in which rapid sensing or reduced power consumption is required of an image sensor.

FIG. 22 is a conceptual diagram illustrating an active pixel sensor array driven according to an example embodiment described in the discussion related to FIG. 20 . Pixels attached to one another in units of four may constitute one pixel unit. A digit displayed at the center of a pixel unit may be the number of a column line to which a voltage sensed by a pixel is outputted. A hatched area (i.e., skip) in FIG. 22 may indicate a pixel unit upon which a sensing operation is not performed. An area illustrated with the shade and an arrow in FIG. 22 may indicate that a binning operation (i.e., vertical binning) is performed with respect to pixels connected to four rows (e.g., rows R 3 to R 6 ) adjacent to one another.

During 1 H-time, first horizontal time period 1H, sensing operations by pixels Gr of pixel units respectively connected to the rows R 3 to R 10 may be performed. The voltage Vout 2 sensed by the pixel Gr of each of a pixel unit connected to the row R 3 and the column C 1 , a pixel unit connected to the row R 4 and the column C 1 , a pixel unit connected to the row R 5 and the column C 1 , and a pixel unit connected to the row R 6 and the column C 1 may be outputted through the second column line {circle around ( 2 )}. The voltage Vout 1 sensed by the pixel Gr of each of a pixel unit connected to the row R 7 and the column C 1 , a pixel unit connected to the row R 8 and the column C 1 , a pixel unit connected to the row R 9 and the column C 1 , and a pixel unit connected to the row R 10 and the column C 1 may be outputted through the second column line {circle around ( 1 )}. The sense voltages Vout 1 and Vout 2 simultaneously outputted may be respectively processed by two different correlated double samplers and two different analog-to-digital converters.

From 2 H-time to 4 H-time, from the second horizontal time period through the fourth horizontal time period, an operation similar to the operation during 1 H-time, the first horizontal time period, may be performed. That is, voltages sensed by the pixel units connected to the rows R 3 to R 6 and voltages sensed by the pixel units connected to the rows R 7 to R 10 may be respectively outputted through the first column line {circle around ( 1 )} and the second column line {circle around ( 2 )}. Operations similar thereto may be performed with respect to the pixel units connected to the column C 3 to C 8 . Sensing operations may be simultaneously performed by the pixel groups connected to two different column lines, thereby improving the operating speed of an image sensor in accordance with principles of inventive concepts.

FIG. 23 is a block diagram illustrating an operating method of an image sensor according to an example embodiment in accordance with principles of inventive concepts. In an example embodiment, a sub-sampling mode will be described. However, unlike the sub-sampling mode described in FIG. 19 , 6-sub-sampling mode in which sensing operations by two pixel units are performed per 6 pixel units and in which a binning operation (in which a summation value of a sense result is simultaneously outputted) is performed will be described. A hatched area in FIG. 23 may indicate a pixel unit within which a sensing operation is not performed.

During 1 H-time, first horizontal period 1H, a sensing operation may be performed by the pixel Gr of the third pixel unit PXU 3 . A sensing operation may be performed according to the selection signal SEL 3 , the reset signal RS 3 , and the transmission signal TG 1 received from the row decoder 120 (refer to FIG. 1 ). A sensing operation may be performed by the pixel Gr of the fourth pixel unit PXU 4 . A sensing operation may be performed according to the selection signal SEL 4 , the reset signal RS 4 , and the transmission signal TG 1 received from the row decoder 120 . The voltage Vout 2 sensed by the pixel Gr of the third pixel unit PXU 3 and the pixel Gr of the fourth pixel unit PXU 4 may be outputted through the second column line CL 2 .

At the same time, a sensing operation may be performed by the pixel Gr of the ninth pixel unit PXU 9 . A sensing operation may be performed according to the selection signal SEL 9 , the reset signal RS 9 , and the transmission signal TG 1 received from the row decoder 120 . A sensing operation may be performed by the pixel Gr of the tenth pixel unit PXU 10 . A sensing operation may be performed according to the selection signal SEL 10 , the reset signal RS 10 , and the transmission signal TG 1 received from the row decoder 120 . The voltage Vout 1 sensed by the pixel Gr of the ninth pixel unit PXU 9 and the pixel Gr of the tenth pixel unit PXU 10 may be outputted through the first column line CL 1 .

Afterwards, from 2 H-time to 4 H-time, second horizontal period 2H through fourth horizontal period 4H, the operation similar to the operation during 1 H-time, first horizontal period 1H, may be performed. That sensing operations are simultaneously performed by two pixel units of two groups respectively connected to different column lines from each other may be similar to above-described embodiments in FIG. 19 . However, in an example embodiment in accordance with principles of inventive concepts, a binning operation as well as a sub-sampling may be performed. In such example embodiments a binning operation may be used in an environment in which rapid sensing speed or reduced power consumption by an image sensor is required, for example.

FIG. 24 is a conceptual diagram illustrating an active pixel sensor array driven according to an example embodiment described in the discussion related to FIG. 23 . Pixels attached to one another in units of four may constitute one pixel unit. A digit displayed at the center of a pixel unit may be the number of a column line to which a voltage sensed by a pixel is outputted. A hatched area (i.e., skip) in FIG. 24 may indicate a pixel unit within which a sensing operation is not performed. An area illustrated with the shade and an arrow in FIG. 24 may indicate that a binning operation (i.e., vertical binning) is performed with respect to pixels connected to two rows (e.g., rows R 3 and R 4 ) adjacent to one another.

During 1 H-time, a first horizontal period 1H, sensing operations by pixels Gr of pixel units respectively connected to the rows R 3 and R 4 may be performed. The voltage Vout 2 sensed by the pixel Gr connected to the row R 3 and the column C 1 and the pixel Gr connected to the row R 4 and the column C 1 may be simultaneously outputted through the second column line {circle around ( 2 )}. That is, a binning operation may be performed with respect to pixel units connected to the row R 3 and pixel units connected to the row R 4 .

At the same time, sensing operations by pixels Gr of pixel units respectively connected to the rows R 9 and R 10 may be performed. The voltage Vout 1 sensed by the pixel Gr connected to the row R 9 and the column C 1 and the pixel Gr connected to the row R 10 and the column C 1 may be simultaneously outputted through the first column line {circle around ( 1 )}. That is, a binning operation may be performed with respect to pixel units connected to the row R 9 and pixel units connected to the row R 10 .

The sense voltages Vout 1 and Vout 2 outputted through the first and second column lines {circle around ( 1 )} and {circle around ( 2 )} may be respectively processed by two different correlated double samplers and two different analog-to-digital converters. Afterwards, from 2 H-time to 4 H-time, from the second horizontal period 2H through the fourth horizontal period 4H, an operation similar to the operation during 1 H-time, first horizontal period 1H, may be performed. As such, a sensing operation and a binning operation may be simultaneously performed by the pixel groups connected to two different, thereby improving the operating speed of an image sensor in accordance with principles of inventive concepts.

FIG. 25 is a block diagram illustrating a configuration of an example embodiment of a correlated double sampling circuit, such as correlated double sampling circuit 140 illustrated in FIG. 2 . Unlike the above-described vertical binning (in a column direction), the configuration of FIG. 25 will be used to illustrate horizontal binning (in a row direction) in accordance with principles of inventive concepts.

Referring to FIG. 25 , the correlated double sampling circuit 140 may include a plurality of correlated double samplers 140 _ 1 to 140 _ 2 n . The correlated double samplers 140 _ 1 to 140 _ 2 n may include amplifiers 142 _ 1 to 142 _ 2 n , respectively. Each correlated double sampler may be connected to another correlated double sampler through a switch. For example, the first correlated double sampler 140 _ 1 may be connected with to third correlated double sampler 140 _ 3 through switch SW 1 . The switches SW 1 , SW 2 , SW 3 , . . . , etc. may be switched on in the binning mode or switched off in the full mode according to the control signal C_SW received from the timing controller 180 (refer to FIG. 1 ).

In example embodiments in accordance with principles of inventive concepts correlated double samplers may be connected (for example, using switches SW 1 , SW 2 , SW 3 , etc.,) to perform a binning operation with respect to two pixel units adjacent to each other in a row direction. Accordingly, when performing a binning operation with respect to four pixel units adjacent to one another in a row direction, the first correlated double sampler 140 _ 1 may not be connected with the third correlated double sampler 140 _ 3 .

In the full mode of operation described in the discussion related to FIG. 4 , switches SW 1 , SW 2 , SW 3 , . . . , etc. may be switched off (that is, open). As a result, the sense voltages Vout 1 to Vout 2 n outputted through each of the column lines CL 1 to CL 2 n (refer to FIG. 2 ) may be respectively inputted to the correlated double samplers 140 _ 1 to 140 _ 2 n through the multiplexing circuit 130 and the correlated double samplers 140 _ 1 to 140 _ 2 n may output the analog signals AS 1 to AS 2 n , respectively.

FIG. 26 is a block diagram illustrating a configuration of a correlated double sampling circuit 140 during a binning mode (H-binning, or horizontal binning). When the switch SW 1 is switched on according to the control signal C_SW from the timing controller 180 (refer to FIG. 2 ), a sense voltage inputted from the first multiplexer MUX 1 to the first correlated double sampler 140 _ 1 and a sense voltage inputted from the second multiplexer MUX 2 to the first correlated double sampler 140 _ 1 may be sequentially inputted through the amplifier 142 _ 1 . That is, an analog signal B_AS 1 outputted from the amplifier 142 _ 1 may be a signal outputted through a binning operation. At this time, other amplifiers may be turned off except the amplifiers 142 _ 1 and 142 _ 3 .

The outputted analog signal B_AS 1 may be inputted to the first converter ADC 1 (refer to FIG. 2 ) and may be converted into a digital signal. Through such a binning operation, the operating speed of an image sensor may be improved, and power consumption may be reduced.

FIG. 27 is a conceptual diagram illustrating an active pixel sensor array driven according to a sub-sampling mode in accordance with principles of inventive concepts, such as that described in the discussion related to FIGS. 23 and 24 and a binning mode described in the discussion related to FIG. 26 . Pixels attached, or adjacent, to one another in units of four may constitute one pixel unit. Moreover, a digit displayed at the center of a pixel unit may be the number of a column line to which a voltage sensed by a pixel is outputted. A hatched area (i.e., skip) in FIG. 27 may indicate a pixel unit within which a sensing operation is not performed. An area illustrated with shade and an arrow in FIG. 27 may mean that a binning operation (i.e., vertical binning and horizontal binning) is performed with respect to pixel units adjacent to one another.

An operating method of FIG. 27 may be similar to that of FIG. 24 , and a duplicated description will not be presented here. In an example embodiment in accordance with principles of inventive concepts, a binning operation (i.e., H-binning, or horizontal binning) in a row direction may be performed. As described in the discussion related to FIG. 26 , when the switch SW 1 is switched on (that is, closed) according to the control signal C_SW from the timing controller 180 (refer to FIG. 2 ), voltages sensed from pixel units connected to the rows C 3 and C 4 may be inputted to the first correlated double sampler 140 _ 1 . The first correlated double sampler 140 _ 1 (refer to FIG. 26 ) may perform a sampling and holding operation with respect to a voltage sensed from pixel units connected to the rows C 3 and C 4 as well as a voltage sensed from pixel units connected to the rows C 1 and C 2 . Additionally, the analog signal B_AS 1 (refer to FIG. 26 ) processed by the first correlated double sampler 140 _ 1 may be converted into a digital signal by the first analog digital converter ADC 1 .

In example embodiments in accordance with principles of inventive concepts, sensing operations may be simultaneously performed by pixel units of two different groups respectively connected to two different column lines. Voltages sensed by pixel units of two different groups may be processed by different correlated double samplers (and different analog digital converters). As a result, the operating speed of an image sensor may be improved. Additionally, the power consumption of an image sensor may be reduced according to various operating modes described herein.

FIG. 28 is a block diagram illustrating a mobile device in which inventive concepts are applied. Referring to FIG. 28 , a mobile device 1000 may be implemented to support a mobile industry processor interface (MIPI) standard or an embedded DisplayPort (eDP) standard. The mobile device 1000 may include an application processor 1100 , a display unit 1200 , an image processing unit 1300 , data storage 1400 , a wireless transceiver unit 1500 , and a user interface 1600 .

The application processor 1100 may control an overall operation of the mobile device 1000 . The application processor 1100 may include a DSI host interfacing with the display unit 1200 and a CSI host interfacing with the image processing unit 1300 .

The display unit 1200 may include the display panel 1210 and a display serial interface (DSI) peripheral circuit 1220 . The display panel 1210 may display image data. A display serial interface (DSI) host mounted on the application processor 1100 may perform a serial communication with the display panel 1210 through a DSI. The DSI peripheral circuit 1220 may include a timing controller, a source driver, and the like which are required to drive the display panel 1210 .

The image processing unit 1300 may include a camera module 1310 and a camera serial interface (CSI) peripheral circuit 1320 . The camera module 1310 and the CSI peripheral circuit 1320 may include a lens, and an image sensor. Image data generated from the camera module 1310 may be processed at the image processor 1100 , and the processed image may be transmitted to the application processor 5100 through a CSI. The image sensor may support one or more operating modes in accordance with principles of inventive concepts. In example embodiments, a sensing operation may be simultaneously performed by two pixel groups respectively connected to different column lines, thereby improving an operating speed.

The data storage 1400 may include embedded universal flash storage (UFS) storage 1410 and a removable UFS card 1420 . The embedded UFS storage 1410 and the removable UFS card 1420 may communicate with the application processor 1100 through M-PHY layer. A host (i.e., application processor 1100 ) may include a bridge to communicate with the removable UFS card 1420 based on another protocol different from a UFS protocol. The application processor 1100 and the removable UFS card 1420 may communicate with each other through various card protocols (e.g., a universal serial bus (USB) flash drive (UFD), a multimedia card (MMC), an embedded multimedia card (eMMC), a secure digital (SD), a mini SD, a Micro SD) The embedded UFS storage 1410 and the removable UFS card 1420 may be implemented with a three-dimensional nonvolatile memory device in which a cell string to which a memory cell is connected is formed to be perpendicular to a substrate, for example.

A wireless transceiver unit 1500 may include an antenna 1510 , a radio frequency (RF) unit 1520 , and a modulator/demodulator (MODEM) 1530 . An embodiment of the inventive concept is exemplified as the modem 1530 communicates with the application processor 1100 through M-PHY layer. However, the scope and spirit of inventive concepts are not limited thereto. For example, the modem 1530 may be included in the application processor 1100 .

Although detailed embodiments of inventive concepts have been described, it should be understood that numerous other modifications, changes, variations, and substitutions can be devised by those skilled in the art. Moreover, it should be understood that the inventive concepts cover various techniques which can be readily modified and embodied based on the above-described embodiments.