Low power clock buffer circuit for integrated circuit with multi-voltage design

This application claims the benefit of U.S. Provisional Application No. 62/208,910, filed on Aug. 24, 2015, the contents of which are incorporated herein by reference.

The invention relates to a clock buffer circuit, and, more particularly, to a power-mode-aware clock buffer circuit for an integrated circuit with multi-voltage design.

In order to reduce power consumption, an integrated circuit with multi power modes is provided to provide different operation voltages for function modules. For example, the function module required to operate at full speed is provided with the maximum operation voltage. For an integrated circuit, the clock latency of one function module operating at one power mode is different from the clock latency of another function module operating at another power mode. Moreover, even though two function modules operate at the same power mode, the clock latency occurring in the two function modules is different due to characteristics of the element, the data transmission path, and so on. This difference in the clock latency may cause clock skew between the two function modules, which degrades system performance. Thus, a power-mode aware clock buffer circuit is required to eliminate clock skew.

An exemplary embodiment of a clock buffer circuit is provided. The clock buffer circuit receives an input clock signal and generates a delay clock signal. The clock buffer circuit comprises an input circuit, an output circuit, a first delay path, and a second delay path. The input circuit receives the input clock signal and generates an output clock signal according to the input clock signal. The output circuit generates the delay clock signal derived from the output clock signal. The first delay path is coupled between the input circuit and the output circuit. The second delay path is coupled between the input circuit and the output circuit. The input circuit selectively provides the output clock signal to a first specific delay path among the first and second delay paths according to a control signal. The output circuit receives the output clock signal which passes through the first specific delay path and outputs the delay clock signal.

An exemplary embodiment of an integrated circuit is provided. The integrated circuit comprises a control circuit, a first function circuit, a first determination circuit, and a first controllable delay circuit. The control circuit generates a first operation voltage. The first function circuit is supplied by the first operation voltage and operates based on a first delay clock signal. The first determination circuit receives the first operation voltage and generates a first control signal according to the first operation voltage. The first controllable delay circuit receives an input clock signal to generate the first delay clock signal with a first variable delay time according to the first control signal.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows one exemplary embodiment of an integrated circuit with multi-voltage design;

FIG. 2 shows one exemplary embodiment of clock buffer circuits;

FIGS. 3A-3D are schematic diagrams illustrating operations of clock buffer circuits of FIG. 2 ;

FIG. 4 shows another exemplary embodiment of clock buffer circuits;

FIG. 5 shows another exemplary embodiment of clock buffer circuits;

FIGS. 6A-6D are schematic diagrams illustrating operations of clock buffer circuits of FIG. 5 ;

FIG. 7 shows one exemplary embodiment of an integrated circuit with multi-voltage design;

FIG. 8 shows another exemplary embodiment of clock buffer circuits; and

FIG. 9 shows another exemplary embodiment of an integrated circuit with multi-voltage design.

The following description is of the contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 is an integrated circuit with multi-voltage design. As shown in FIG. 1 , the integrated circuit 1 comprises a power mode control circuit 10 , a plurality of determination circuits 11 , a plurality of clock buffer circuits 12 , and a plurality of function circuits 13 . The power mode control circuit 10 generates and provides voltages to the function circuits 13 to serve as their operation voltages. In the embodiment, one function circuit 13 corresponds to one determination circuit 11 and one clock buffer circuit 12 . In other words, each of the number of determination circuits 11 and the number of clock buffer circuits 12 is equal to the number of function circuits 13 . In the embodiment, two determination circuits 11 A and 11 B, two clock buffer circuits 12 A and 12 B, and two function circuits 13 A and 13 B are taken as an example for illustration. The power mode control circuit 10 generates two voltages VDDA and VDDB to the function modules 13 A and 13 B to serve as the operation voltages of the function modules 13 A and 13 B, respectively. There is data transmission between the function modules 13 A and 13 B.

For each clock buffer circuit, there are at least two delay paths for a clock signal CKIN. The delay paths in each clock buffer circuit have different delay times. For example, the clock buffer circuit 12 A comprises two delay paths P 120 A and P 121 A. By arranging different numbers of buffers 120 A coupled in series, the delay time of the delay path P 120 A is different from the delay time of the delay path P 121 A. In the embodiment, the delay time of the delay path P 121 A with more buffers 120 A is longer than the delay time of the delay path P 120 A with fewer buffers 120 A. In FIG. 1 , the delay path P 120 A comprises two buffers 120 A, while the delay path P 121 A comprises four buffers 120 A. The delay time of the delay path P 121 B is also longer than the delay time of the delay path P 120 B. In the embodiment, the number of buffers 120 B of the delay path P 120 B may be equal to or different from the number of buffers 120 A of the delay path P 120 A, while the number of buffers 120 B of the delay path P 121 B may be equal to or different from the number of buffers 120 A of the delay path P 121 A. In the embodiment of FIG. 1 , the delay path P 120 B comprises one buffer 120 B, while the delay path P 121 B comprises three buffers 120 B. In the embodiment, for each of the clock buffer circuits 12 A and 12 B, since there are at least two delay paths, the clock buffer circuit has a variable delay time for generating a corresponding delay clock signal.

In the following description, the clock buffer circuit 12 A is given as an example. Both of the delay paths P 120 A and P 121 A are coupled between an input circuit 121 A and an output circuit 122 A. The input circuit 121 A receives the input clock signal CKIN and generates an output clock signal CKOUTA according to the input clock signal CKIN. In the embodiment, the input circuit 121 A may directly output the input clock signal CKIN to serve as the output clock signal CKOUTA or generate the output clock signal CKOUTA whose timing is synchronized with the timing of the input clock signal CKIN. Each of the input circuit 121 A and the output circuit 122 A is controlled by a control signal S 11 A. The determination circuit 11 A receives the voltage VDDA from the power mode control circuit 10 and generates the control signal S 11 A according to the voltage VDDA. The input circuit 121 A is controlled by the control signal S 11 A to selectively provide the output clock signal CKOUTA to one specific delay path among the delay paths P 120 A and P 121 A, such as the delay path P 121 A, as indicated by the left dot-line arrow. Accordingly, the output circuit 122 A receives the output clock signal CKOUTA passing through the specific delay path (delay path P 120 A) and outputs the clock signal delayed by the specific delay path (referred to as “delay clock signal CKDLYA”) to the function circuit 13 A. The function circuit 13 A operates based on the delay clock signal CKDLYA. At this time, according to the control signal S 11 A, the input circuit 121 A blocks the input clock signal CKIN or any clock signal derived from the input clock signal CKIN (such as the output clock signal CKOUTA) from being provided to another specific delay path among the delay paths P 120 A and P 121 A, which is different from the above specific delay path through which the output clock signal CKOUTA passes, that is the other delay path P 121 A. In this embodiment, the determination circuit 11 B and the clock buffer circuit 12 B may perform similar operations.

According to the embodiment above, for each clock buffer circuit, the delay path which is configured to delay the output clock signal is determined or selected according to the voltage supplied to the corresponding function circuit. During the operation of each buffer circuit, one delay path receives the output clock signal and operates to delay the output clock signal. The other delay path(s) does not receive any clock signal and furthermore does not perform the clock delay. Thus, the power consumed by each buffer circuit during the operation can be reduced.

In the following description, details of the operation of the integrated circuit 1 will be described by taking as an example of the set of the determination circuit 11 A, the clock buffer circuit 12 A, and the function circuit 13 A, as shown in FIG. 2 .

Referring to FIG. 2 , the input circuit 121 A comprises a demultiplexer 20 A. The demultiplexer 20 A has an input terminal T 20 A receiving the input clock signal CKIN and two output terminals T 21 A and T 22 A respectively coupled to the delay paths P 120 A and P 121 A. The demultiplexer 20 A also has a control terminal T 23 A receiving the control signal S 11 A. The output circuit 122 A comprises a multiplexer 21 A. The multiplexer 21 A has two input terminals T 24 A and T 25 A respectively coupled to the delay paths P 120 A and P 121 A and an output terminal T 26 A coupled to the function circuit 13 A. The multiplexer 21 A also has a control terminal T 27 A receiving the control signal S 11 A. Each of the delay paths P 120 A and P 121 A is formed by at least one buffer coupled in series. With more buffers, the delay time of the corresponding delay path is longer. In the embodiment, the number of buffers 120 A of the delay path P 121 A is greater than the number of buffers 120 A of the delay path P 120 A. Thus, the delay time of the delay path P 121 A is longer than the delay time of the delay path P 120 A.

The determination circuit 11 A receives the voltage VDDA from the power mode control circuit 10 and generates a control signal S 11 A according to the voltage VDDA. In the embodiment, the determination circuit 11 A may detect the value of the voltage VDDA and generate the control signal S 11 A with a digital form according to the detection result. The control signal S 11 A is used to indicate that the voltage VDDA is at a relatively high level or a relatively low level. When the voltage VDDA is at a relatively high level, the determination circuit 20 generates the control signal S 11 A with the logic value “1”. The demultiplexer 20 A is controlled by the control signal S 11 A to transmit the input clock signal CKIN from the input terminal T 20 A to the output terminal T 22 A to serve as the output clock signal CKOUTA. The output clock signal CKOUTA is delayed by the delay path P 121 A and then transmitted to the input terminal T 25 A of the multiplexer 21 A. At this time, the demultiplexer 20 A does not transmit the input clock signal CKIN or any clock signal derived from the input clock signal CKIN to the delay path P 120 A through the output terminal T 21 A. The multiplexer 21 A is controlled by the control signal S 11 A to transmit the output clock signal CKOUTA, which passes through the delay path P 121 A, from the input terminal T 25 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. Accordingly, the function circuit 13 A receives the delay clock signal CKDLYA and operates based on the delay clock signal CKDLYA.

For example, when the voltage VDDA is at a relatively low level, determination circuit 20 generates the control signal S 11 A with the logic value “0”. The demultiplexer 20 A is controlled by the control signal S 11 A to transmit the input clock signal CKIN from the input terminal T 20 A to the output terminal T 21 A to serve as the output clock signal CKOUTA. The output clock signal CKOUTA is delayed by the delay path P 120 A and then transmitted to the input terminal T 24 A of the multiplexer 21 A. At this time, the demultiplexer 20 A does not transmit the input clock signal CKIN or any clock signal derived from the input clock signal CKIN to the delay path P 121 A through the output terminal T 22 A. The multiplexer 21 A is controlled by the control signal S 11 A to transmit the output clock signal CKOUTA, which passes through the delay path P 120 A, from the input terminal T 24 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. Accordingly, the function circuit 13 A receives the delay clock signal CKDLYA and operates based on the delay clock signal CKDLYA.

The clock buffer circuit 12 B has a similar structure as the clock buffer circuit 12 A. The determination circuit 11 B and the clock buffer circuit 12 B perform a similar operation as the determination circuit 11 A and the clock buffer circuit 12 A. Thus, the detailed description is omitted here.

According to the operations of the determination circuits 11 A and 11 B and the clock buffer circuits 12 A and 12 B, the timing variation in the data transmission between the function circuits 13 A and 13 B with different operation voltages can be decreased. In the first case, the power mode control circuit 10 may generate a voltage with a relatively high level to the function circuit 13 A and a voltage with a relatively low level to the function circuit 13 B. The function circuit 13 A may operate at a high speed with less clock latency, while the function circuit 13 B may operate at a low speed with greater clock latency. At this time, according to the operation of the demultiplexer 20 A controlled by the control signal S 11 A with the logic value “1”, the demultiplexer 20 A transmits the input clock signal CKIN to the delay path P 121 A to serve as the output clock signal CKOUTA, and the output clock signal CKOUTA is delayed by the delay path P 121 A with the longer delay time. According to the operation of the demultiplexer 20 B controlled by the control signal S 11 B with the logic value “0”, while the demultiplexer 20 B transmits the input clock signal CKIN to the delay path P 120 B to serve as the output clock signal CKOUTB and the output clock signal CKOUTB is delayed by the delay path P 120 B with the shorter delay time, as shown FIG. 3A . The multiplexer 21 A is controlled by the control signal S 11 A to transmit the output clock signal CKOUTA, which is delayed by the delay path P 121 A, from the input terminal T 25 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. The multiplexer 21 B is controlled by the control signal S 11 B to transmit the output clock signal CKOUTB, which is delayed by the delay path P 120 B, from the input terminal T 24 B to the output terminal T 26 B to serve as the delay clock signal CKDLYB.

In second case, the power mode control circuit 10 may generate a voltage with a relatively low level to the function circuit 13 A and a voltage with a relatively high level to the function circuit 13 B. The function circuit 13 A may operate at a low speed with greater clock latency, while the function circuit 13 B may operate at a high speed with less clock latency. At this time, according to the operation of the demultiplexer 20 A controlled by the control signal S 11 A with the logic value “0”, the demultiplexer 20 A transmits the input clock signal CKIN to the delay path P 120 A to serve as the output clock signal CKOUTA, and the output clock signal CKOUTA is delayed by the delay path P 120 A with the shorter delay time. According to the operation of the demultiplexer 20 B controlled by the control signal S 11 B with the logic value “1”, the demultiplexer 20 B transmits the input clock signal CKIN to the delay path P 121 B to serve as the output clock signal CKOUTB, and the output clock signal CKOUTB is delayed by the delay path P 121 B with the longer delay time, as shown FIG. 3B . The multiplexer 21 A is controlled by the control signal S 11 A to transmit the output clock signal CKOUTA, which is delayed by the delay path P 120 A, from the input terminal T 24 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. The multiplexer 21 B is controlled by the control signal S 11 B to transmit the output clock signal CKOUTB, which is delayed by the delay path P 121 B, from the input terminal T 25 B to the output terminal T 26 B to serve as the delay clock signal CKDLYB.

In the third case, the power mode control circuit 10 may generate a voltage with a relatively high level to the function circuit 13 A and a voltage with a relatively high level to the function circuit 13 B. The function circuit 13 A may operate at a high speed with less clock latency, while the function circuit 13 B may operate at a high speed with less clock latency. At this time, according to the operation of the demultiplexer 20 A controlled by the control signal S 11 A with the logic value “1”, the demultiplexer 20 A transmits the input clock signal CKIN to the delay path P 121 A to serve as the output clock signal CKOUTA, and the output clock signal CKOUTA is delayed by the delay path P 121 A with the longer delay time. According to the operation of the demultiplexer 20 B controlled by the control signal S 11 B with the logic value “1”, while the demultiplexer 20 B transmits the input clock signal CKIN to the delay path P 121 B to serve as the output clock signal CKOUTB, and the output clock signal CKOUTB is delayed by the delay path P 121 B with the longer delay time, as shown FIG. 3C . The multiplexer 21 A is controlled by the control signal S 11 A to transmit the output clock signal CKOUTA, which is delayed by the delay path P 121 A, from the input terminal T 25 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. The multiplexer 21 B is controlled by the control signal S 11 B to transmit the output clock signal CKOUTB, which is delayed by the delay path P 121 B, from the input terminal T 25 B to the output terminal T 26 B to serve as the delay clock signal CKDLYB.

In fourth case, the power mode control circuit 10 may generate a voltage with a relatively low level to the function circuit 13 A and a voltage with a relatively low level to the function circuit 13 B. The function circuit 13 A may operate at a low speed with greater clock latency, while the function circuit 13 B may operate at a low speed with greater clock latency. At this time, according to the operation of the demultiplexer 20 A controlled by the control signal S 11 A with the logic value “0”, the demultiplexer 20 A transmits the input clock signal CKIN to the delay path P 120 A to serve as the output clock signal CKOUTA, and the output clock signal CKOUTA is delayed by the delay path P 120 A with the shorter delay time. According to the operation of the demultiplexer 20 B controlled by the control signal S 11 B with the logic value “0”, the demultiplexer 20 B transmits the input clock signal CKIN to the delay path P 120 B to serve as the output clock signal CKOUTB, and the output clock signal CKOUTB is delayed by the delay path P 120 B with the shorter delay time, as shown FIG. 3D . The multiplexer 21 A is controlled by the control signal S 11 A to transmit the output clock signal CKOUTA, which is delayed by the delay path P 120 A, from the input terminal T 24 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. The multiplexer 21 B is controlled by the control signal S 11 B to transmit the output clock signal CKOUTB, which is delayed by the delay path P 120 B, from the input terminal T 24 B to the output terminal T 26 B to serve as the delay clock signal CKDLYB.

According to the above embodiments, through the respective delay paths in the clock buffer circuits 12 A and 12 B, the clock latency of the function circuits 13 A and 13 B is compensated for. The clock skew between the function circuits 13 A and 13 B is lessened or eliminated. Moreover, during the operation of each buffer circuit, one delay path receives the output clock signal and operates to delay the received output clock signal. The other delay path(s) does not receive any clock signal for clock delay. Thus, the power consumed by each buffer circuit during the operation can be reduced.

In another embodiment, each of the input circuits 121 A and 121 B may comprise clock gating cells. Each of the control signals S 11 A and S 11 B is a digital signal with bits. The number of clock gating cells is equal to the number of delay paths. In the following description, the input circuit 121 A is given as an example for illustration. Referring to FIG. 4 , the input circuit 121 A comprises two clock gating cells 40 A and 41 A. Each of the clock gating cells 40 A and 41 A receives the input clock signal CKIN and the control signal S 11 A. When the voltage VDDA is at a relatively high level, the determination circuit 20 generates the control signal S 11 A to enable the clock gating cell 41 A to generate the output clock signal CKOUTA whose timing is synchronized with the timing of the input clock signal CKIN. The output clock signal CKOUTA is delayed by the delay path P 121 A and then transmitted to the input terminal T 25 A of the multiplexer 21 A. At this time, the clock gating cell 40 A is disabled according to the control signal S 11 A. That is, the clock gating cell 40 A does not generate the output clock signal CKOUTA or any clock signal derived from the input clock signal CKIN to the delay path P 120 A. The multiplexer 21 A is controlled by the control signal S 11 A to transmit the output clock signal CKOUTA, which passes through the delay path P 121 A, from the input terminal T 25 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. When the voltage VDDA is at a relatively low level, determination circuit 20 generates the control signal S 11 A to enable the clock gating cell 40 A to generate the output clock signal CKOUTA whose timing is synchronized with the timing of the input clock signal CKIN. The output clock signal CKOUTA is delayed by the delay path P 120 A and then transmitted to the input terminal T 24 A of the multiplexer 21 A. At this time, the clock gating cell 41 A is disabled according to the control signal S 11 A. That is, the clock gating cell 41 A does not generate the output clock signal CKOUTA or any clock signal derived from the input clock signal CKIN to the delay path P 121 A. The multiplexer 21 A is controlled by the control signal S 11 A to transmit the output clock signal CKOUTA, which passes through the delay path P 120 A, from the input terminal T 24 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. The input circuit 121 B has a similar structure as the input circuit 121 A. The input circuit 121 B performs a similar operation as the input circuit 121 A. Thus, the detailed description is omitted here.

In another embodiment, each of the control signals S 11 A and S 11 B is a digital signal with bits. In the embodiment of FIG. 4 , each control signal is a digital signal with 3 bits “B 0 B 1 B 2 ”. The clock gating cells 40 A and 41 A are controlled by the two bits (such as B 0 and B 1 ) of the control signal S 11 A respectively. The multiplexer 21 A is controlled by the bit B 2 of the control signal S 11 A. As shown in FIG. 5 , each of the clock gating cells 40 A and 40 B comprises an AND gate. The AND gate 50 A receives the input clock signal CKIN and the bit B 0 of the control signal S 11 A, while the AND gate 51 A receives the input clock signal CKIN and the bit B 1 of the control signal S 11 A. When one AND gate receives a bit with “1”, the AND gate generates the output clock signal CKOUTA. That is, the corresponding clock gating cell is enabled. When one AND gate receives a bit with “0”, the corresponding clock gating cell is disabled.

According to the operations of the clock gating cells and the clock buffer circuits corresponding to the function circuits 13 A and 13 B, the timing variation in the data transmission between the function circuits 13 A and 13 B can be decreased. In the first case, the power mode control circuit 10 may generate a voltage with a relatively high level to the function circuit 13 A and a voltage with a relatively low level to the function circuit 13 B. The function circuit 13 A may operate at a high speed with less clock latency, while the function circuit 13 B may operate at a low speed with greater clock latency. Referring to FIG. 6A , at this time, the determination circuit 11 A generates the control signal S 11 A with “011” (B 0 =0, B 1 =1, B 2 =1), while the determination circuit 11 B generates the control signal S 11 B with “100” (B 0 =1, B 1 =0, B 2 =0). According to the operations of the clock gating cells 40 A and 41 A, the AND gate 51 A generates the output clock signal CKOUTA to the delay path P 121 A (that is the clock gating cell 41 A is enabled by the bit B 1 of the control signal S 11 A) and the output clock signal CKOUTA is delayed by the delay path P 121 A with the longer delay time, while the AND gate 50 A does not generate the output clock signal CKOUTA or any clock signal derived from the input clock signal CKIN (that is the clock gating cell 40 A is disabled by the bit B 0 of the control signal S 11 A), as shown in FIG. 6A . According to the operations of the clock gating cells 40 B and 41 B, the AND gate 50 B generates the output clock signal CKOUTB to the delay path P 120 B (that is the clock gating cell 40 B is enabled by the bit B 0 of the control signal S 11 B) and the output clock signal CKOUTB is delayed by the delay path P 120 B with the shorter delay time, while the AND gate 51 B does not generate the output clock signal CKOUTB or any clock signal derived from the input clock signal CKIN (that is the clock gating cell 41 B is disabled by the bit B 1 of the control signal S 11 B), as shown FIG. 6A . The multiplexer 21 A is controlled by the bit B 2 (B 2 =1) of the control signal S 11 A to transmit the output clock signal CKOUTA, which is delayed by the delay path P 121 A, from the input terminal T 25 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. The multiplexer 21 B is controlled by the bit B 2 (B 2 =0) of the control signal S 11 B to transmit the output clock signal CKOUTB, which is delayed by the delay path P 120 B, from the input terminal T 24 B to the output terminal T 26 B to serve as the delay clock signal CKDLYB.

In second case, the power mode control circuit 10 may generate a voltage with a relatively low level to the function circuit 13 A and a voltage with a relatively high level to the function circuit 13 B. The function circuit 13 A may operate at a low speed with greater clock latency, while the function circuit 13 B may operate at a high speed with less clock latency. Referring to FIG. 6B , at this time, the determination circuit 11 A generates the control signal S 11 A with “100” (B 0 =1, B 1 =0, B 2 =0), while the determination circuit 11 B generates the control signal S 11 B with “011” (B 0 =0, B 1 =1, B 2 =1). According to the operations of the clock gating cells 40 A and 41 A, the AND gate 50 A generates the output clock signal CKOUTA to the delay path P 120 A (that is the clock gating cell 40 A is enabled by the bit B 0 of the control signal S 11 A) and the output clock signal CKOUTA is delayed by the delay path P 120 A with the shorter delay time, while the AND gate 51 A does not generate the output clock signal CKOUTA or any clock signal derived from the input clock signal CKIN (that is the clock gating cell 41 A is disabled by the bit B 1 of the control signal S 11 A), as shown in FIG. 6B . According to the operations of the clock gating cells 40 B and 41 B, the AND gate 51 B generates the output clock signal CKOUTB to the delay path P 121 B (i.e. the clock gating cell 41 B is enabled by the bit B 1 of the control signal S 11 B) and the output clock signal CKOUTB is delayed by the delay path P 121 B with the longer delay time, while the AND gate 50 B does not generate the output clock signal CKOUTB or any clock signal derived from the input clock signal CKIN (i.e. the clock gating cell 40 B is disabled by the bit B 0 of the control signal S 11 B), as shown in FIG. 6B . The multiplexer 21 A is controlled by the bit B 2 (B 2 =0) of the control signal S 11 A to transmit the output clock signal CKOUTA, which is delayed by the delay path P 120 A, from the input terminal T 24 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. The multiplexer 21 B is controlled by the bit B 2 (B 2 =1) of the control signal S 11 B to transmit the output clock signal CKOUTB, which is delayed by the delay path P 121 B, from the input terminal T 25 B to the output terminal T 26 B to serve as the delay clock signal CKDLYB.

In third case, the power mode control circuit 10 may generate a voltage with a relatively high level to the function circuit 13 A and a voltage with a relatively high level to the function circuit 13 B. The function circuit 13 A may operate at a high speed with less clock latency, while the function circuit 13 B may operate at a high speed with less clock latency. Referring to FIG. 6C , at this time, the determination circuit 11 A generates the control signal S 11 A with “011” (B 0 =0, B 1 =1, B 2 =1), and the determination circuit 11 B generates the control signal S 11 B with “011” (B 0 =0, B 1 =1, B 2 =1). According to the operations of the clock gating cells 40 A and 41 A, the AND gate 51 A generates the output clock signal CKOUTA to the delay path P 121 A (that is the clock gating cell 41 A is enabled by the bit B 1 of the control signal S 11 A) and the output clock signal CKOUTA is delayed by the delay path P 121 A with the longer delay time, while the AND gate 50 A does not generate the output clock signal CKOUTA or any clock signal derived from the input clock signal CKIN (that is the clock gating cell 40 A is disabled by the bit B 0 of the control signal S 11 A), as shown in FIG. 6C . According to the operations of the clock gating cells 40 B and 41 B, the AND gate 51 B generates the output clock signal CKOUTB to the delay path P 121 B (that is the clock gating cell 41 B is enabled by the bit B 1 of the control signal S 11 B) and the output clock signal CKOUTB is delayed by the delay path P 121 B with the longer delay time, while the AND gate 50 B does not generate the output clock signal CKOUTB or any clock signal derived from the input clock signal CKIN (that is the clock gating cell 40 B is disabled by the bit B 0 of the control signal S 11 B), as shown in FIG. 6C . The multiplexer 21 A is controlled by the bit B 2 (B 2 =1) of the control signal S 11 A to transmit the output clock signal CKOUTA, which is delayed by the delay path P 121 A, from the input terminal T 25 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. The multiplexer 21 B is controlled by the bit B 2 (B 2 =1) of the control signal S 11 B to transmit the output clock signal CKOUTB, which is delayed by the delay path P 121 B, from the input terminal T 25 B to the output terminal T 26 B to serve as the delay clock signal CKDLYB.

In fourth case, the power mode control circuit 10 may generate a voltage with a relatively low level to the function circuit 13 A and a voltage with a relatively low level to the function circuit 13 B. The function circuit 13 A may operate at a low speed with greater clock latency, while the function circuit 13 B may operate at a low speed with greater clock latency. Referring to FIG. 6D , at this time, the determination circuit 11 A generates the control signal S 11 A with “100” (B 0 =1, B 1 =0, B 2 =0), while the determination circuit 11 B generates the control signal S 11 B with “100” (B 0 =1, B 1 =0, B 2 =0). According to the operations of the clock gating cells 40 A and 41 A, the AND gate 50 A generates the output clock signal CKOUTA to the delay path P 120 A (that is the clock gating cell 40 A is enabled by the bit B 0 of the control signal S 11 A) and the output clock signal CKOUTA is delayed by the delay path P 120 A with the shorter delay time, while the AND gate 51 A does not generate the output clock signal CKOUTA or any clock signal derived from the input clock signal CKIN (that is the clock gating cell 41 A is disabled by the bit B 1 of the control signal S 11 A), as shown in FIG. 6D . According to the operations of the clock gating cells 40 B and 41 B, the AND gate 50 B generates the output clock signal CKOUTB to the delay path P 120 B (that is the clock gating cell 40 B is enabled by the bit B 0 of the control signal S 11 B) and the output clock signal CKOUTB is delayed by the delay path P 120 B with the shorter delay time, while the AND gate 51 B does not generate the output clock signal CKOUTB or any clock signal derived from the input clock signal CKIN (that is the clock gating cell 41 B is disabled by the bit B 1 of the control signal S 11 B), as shown FIG. 6D . The multiplexer 21 A is controlled by the bit B 2 (B 2 =0) of the control signal S 11 A to transmit the output clock signal CKOUTA, which is delayed by the delay path P 120 A, from the input terminal T 24 A to the output terminal T 26 A to serve as the delay clock signal CKDLYA. The multiplexer 21 B is controlled by the bit B 2 (B 2 =0) of the control signal S 11 B to transmit the output clock signal CKOUTB, which is delayed by the delay path P 120 B, from the input terminal T 24 B to the output terminal T 26 B to serve as the delay clock signal CKDLYB.

In the above embodiments, two delay paths in one clock buffer circuit are given as an example. In other embodiments, for minimizing the timing variation in the data transmission between the function circuits 13 A and 13 B, at least one clock buffer circuit may comprise more than two delay paths, such as three delay paths. As shown in FIG. 7 , the clock buffer circuit 12 A comprises three delay paths 70 A, 71 A, and 72 A, and the clock buffer circuit 12 B comprises three delay paths 70 B, 71 B, and 72 B. For example, the input circuit 121 A is controlled by the corresponding determination circuit 11 A to generate the output clock signal CKOUTA to one of the three delay paths 70 A, 71 A, and 72 A and block the input clock signal CKIN or any clock signal derived from the input clock signal CKIN (such as the output clock signal CKOUTA) from being provided to the other two delay paths. Accordingly, the power consumption of the clock buffer circuits 120 A and 120 B can be decreased. The integrated circuit shown in FIG. 7 operates based on the principle, operations, and circuit structures described in the above embodiment. Thus, the related description is omitted.

In another embodiment, there is a least one buffer shared by the delay paths of one clock buffer circuit. As shown in FIG. 1 , the delay path P 120 A comprises two buffers 120 A, and the delay path P 121 A comprises four buffers 120 A. Thus, the delay paths P 120 A and P 121 A may share one buffer. As shown in FIG. 8 , there is an additional delay path P 80 . The delay path P 80 receives the input clock signal CKIN and delays the input clock signal CKIN. The delayed input clock signal CKIN is transmitted to the input circuit 121 A for the further delay operation. Accordingly, the number of buffers in the clock buffer circuit 12 A can be decreased. For example, compared with the clock buffer circuit 12 A in FIGS. 1-6D , the number of buffers in the clock buffer circuit 12 A in FIG. 8 is decreased from 6 to 5.

In the above embodiments, the number of buffers of the delay path P 80 , the number of buffers of the delay path P 120 A, and the number of buffers of the delay path P 121 A are examples for illustration without limitations. These can be determined according to the system requirement and circuit design.

FIG. 9 shows yet another embodiment of the clock buffer circuits. In the embodiment, controlled delay circuits 90 A and 90 B generate delay clock signals to the function circuit 13 A and 13 B respectively. Each of the controlled delay circuits 90 A and 90 B has a variable delay time which is determined by the corresponding control signal from the determination circuit. For example, the variable delay time of the controlled delay circuit 90 A is determined by the control signal S 11 A, so that the controlled delay circuit 90 A generates the delay clock signal CKDLYA according to the determined delay time. Similarly, the variable delay time of the controlled delay circuit 90 B is determined by the control signal S 11 B, so that the controlled delay circuit 90 B generates the delay clock signal CKDLYB according to the determined delay time.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.