Method of monitoring clock and oscillator module thereof

Embodiments of the present disclosure are related to an oscillator module, and more particularly to the oscillator module monitoring a clock signal in low power and method of calibration thereof.

The electronic device can include a “working-usually” device and a “standby-often” device. For examples, a mobile device is a working-usually device and an Internet of Things (IoT) device is a standby-often device. The IoT may include a smart gate lock, window security device and health care device, a smart watch, a smart ring and so on. If the IoT device needs to change battery every one or two weeks, that does not make sense. The major concern of the electronic device is about the power consumption and the battery life thereof. The power management can improve the chip's power efficiency so as to prolong the battery life and the operating time.

An electronic device requires an oscillator to provide with a clock to maintain its function, even if the electronic device is in an idle state, it still needs clock to let the entire system of the electronic device be monitored. Temperature, process variation of different lot of wafer, and capacitor loading may affect a workable clock of the oscillator, so the clock needs to be calibrated.

Although the electronic device is designed to have low power consumption, it still needs power to support a standby mode in order that it wakes up to function normally, therefore the calibration of the clock powered by a power source in the idle mode plays an important role for saving power. Please refer to FIG. 1 , which shows power consumption in the different applications in the prior art. The horizontal axis represents time and the vertical axis represents a power consumption. The illustration in Application I shows a timing diagram regarding to the power consumption in the mobile device, and the illustration in Application II shows a timing diagram regarding to the power consumption in the IoT device. In FIG. 1 , the mobile device and the IoT device respectively have periods t_prid 1 and t_prid 2 which can be the same, the active time t_act of the IoT device is relatively shorter than that of the mobile device, typically about a time level from milli-seconds to a few seconds, and there is lower power consumption to be made because the duration of the active time t_act is relatively short. However, the sleep time t_sleep of the IoT device is relatively longer than that of the mobile device, typically about a time level of days, therefore a power source reduction of driving the clock can contribute a lot for power saving and prolong the battery life further. For example, it may reach to a goal of ten-year battery life of the IoT device.

Please refer to FIG. 2 , which shows a conventional clock calibration circuit 10 . The conventional clock calibration circuit 10 includes a power source 101 , an inverting amplifier 102 , a crystal resonator 104 , load capacitors C 1 and C 2 , and an analog amplitude calibration circuit 103 . The analog amplitude calibration circuit 10 includes a peak detector 1031 , a capacitor C 3 and a comparator 1032 . The power source 101 provides enough current to the inverting amplifier 102 , and the amplifier 102 , in response to the current provided from the power source 101 , inverts a phase of a clock CK 1 signal generating from the crystal resonator 104 , and outputs a clock signal CK 2 to the peak detector 1031 . The peak detector 1031 can be implemented by a differential amplifier or alike.

Please refer to FIG. 3 , which shows the peak detector 1031 implemented 1033 in the prior art. The peak detector 1033 may include two transistors M 1 , M 2 , which are coupled in parallel, and coupled to the capacitor C 3 and a resistor R 0 . The differential amplifier 1033 receives complementary signals Vin+ and Vin− to output an envelope signal Senv. For example, clock signals CK 1 and CK 2 are inputted into gate terminals of the two transistors M 1 and M 2 respectively. The envelope signal Senv of the peak detector 1031 is shown in FIG. 4 . The voltage waveform way of the envelope signal Senv is tooth-like. Capacitor C 3 is charged when either Vin+ or Vin− approach their maximum peak value while it is discharged via R 0 when Vin+ and Vin− close to their average value. This continuous charging and discharging on C 3 creates an average voltage Vavg on C 3 which is directly proportional to the input amplitude of Vin+ or Vin−. The comparator 1032 compares the average voltage Vavg with a reference voltage Vref to output a feedback signal Sfb to adjust the power source 101 . The reference voltage Vref needs to be set to assure that the power source 101 provides enough current to the inverting amplifier 102 in order to support the clock signals CK 1 and CK 2 to work normally. In order to let the clock signals CK 1 and CK 2 work normally, the amplitude of which is about 200˜300 mV typically.

Please refer back to FIG. 2 , while the analog amplitude calibration circuit 103 is powered, a quiescent current flowing therein makes power consumption; and the IoT device often include at least one of a conventional clock calibration circuit 10 , so that the total power consumption is relatively large. The quiescent current in the analog amplitude calibration circuit 103 consumes 1˜5 uA of the quiescent current typically, and it will consume a large amount of power as long as the idle mode keeps a long period, therefore the structure in the analog amplitude calibration circuit 103 is not suitable for the IoT device at a low power condition. In addition, if the frequency of the clock signal CK 1 , CK 2 is relative low, for example typical 32 kHz, then a time constant of capacitor C 3 will be large, which causes a large-capacity on-chip capacitor C 3 to occupy large chip area. In addition, in order to generate the reference voltage Vref, there is a need to add other peripheral circuit, which results in relative large power consumption.

On the other hand, some factors can affect the clock signals CK 1 , CK 2 of the crystal resonator 104 . They include temperature, humidity, voltage/current sparks, process variation, capacitor loading, so the clock signals CK 1 , CK 2 need to be calibrated for accuracy demanding applications.

Furthermore, saving the chip area and saving the power consumption are also expected. Accordingly, there is a need for a method and a module to reduce the power consumption, simultaneously calibrate the clock signal to run in an economical power and keep it in a relatively stable state, and have an economical chip area.

In addition, it is expected that the clock signal is always monitored and can be optimized to save power and be calibrated automatically whenever it is abnormal.

In accordance with one embodiment of the present disclosure, an oscillator module is provided. The oscillator module used with a plurality of power sources, comprising an oscillator unit, a clock monitor unit (CMU), a software module and a digital calibration circuit. The oscillator unit generates a clock signal. The CMU is coupled to the oscillator unit, determines whether an amplitude of the clock signal exceeds a predetermined threshold, and outputs an alarm signal if the amplitude of the clock signal is lower than the predetermined threshold. The software module is coupled to the CMU, and receives the alarm signal to output a calibration signal. The digital calibration circuit is coupled to the oscillator and the software module, outputs a control signal in response to the clock signal and the calibration signal, adjusts the plurality of power sources to modify the clock signal.

In accordance with a further embodiment of the present disclosure, the present invention provides an oscillator module. The oscillator module comprises an oscillator unit and a digitized circuit. The oscillator unit generates a clock signal. The digitized circuit is coupled to the oscillator unit and digitally detects whether the clock signal is normal, wherein if the clock signal is normal, the digitized circuit idles itself; and if not, the digitized circuit is activated digitally.

In accordance with one embodiment of the present disclosure, an oscillator module is provided. The oscillator module comprises an oscillator unit and a digitized circuit. The oscillator unit generates a clock signal. The digitized circuit digitally detecting whether the clock signal is normal, wherein if the clock signal is normal, the digitized circuit idles itself and the oscillator module monitors whether the clock signal remains normal.

The above embodiments and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed descriptions and accompanying drawings.

FIG. 1 shows power consumption in the different applications in the prior art;

FIG. 2 shows a conventional clock calibration circuit;

FIG. 3 shows a peak detector implemented by a differential amplifier in the prior art;

FIG. 4 shows an envelope signal of the peak detector in the prior art;

FIG. 5 shows a clock calibration module according to a first preferred embodiment of the present disclosure;

FIG. 6 shows a finite state machine (FSM) state diagram of an FSM unit according to the first preferred embodiment of the present disclosure;

FIG. 7( a ) shows the digital amplitude calibration module;

FIG. 7( b ) shows a timing diagram of input and output signals of the FSM unit according to the first preferred embodiment of the present disclosure;

FIG. 8 shows a plurality of power sources according to the first preferred embodiment of the present disclosure;

FIG. 9 shows an implementation circuit of a CED in detail according to the second preferred embodiment of the present disclosure;

FIG. 10 shows an implementation circuit of the CED in detail according to the third preferred embodiment of the present disclosure;

FIG. 11 shows a kick signal boosting the clock signal of a clock calibration module according to the preferred embodiment of the present disclosure;

FIG. 12 shows a driving circuit according to the preferred embodiment of the present disclosure;

FIG. 13 shows waveforms of the clock signal when it is initialized;

FIG. 14 shows a timing diagram of decreased power controlled by the FSM unit according to the preferred embodiment of the present disclosure;

FIG. 15 shows an FSM state diagram of decreased power controlled by the FSM unit according to the preferred embodiment of the present disclosure;

FIG. 16( a ) shows an oscillator module with a monitor circuit according to the preferred embodiment of the present disclosure;

FIG. 16( b ) shows an inverting amplifier according to a preferred embodiment of the present disclosure;

FIG. 17 shows a power control circuit according to the preferred embodiment of the present disclosure;

FIG. 18 shows a detail of the set of OR gates;

FIG. 19 shows the CMU in detail according to the preferred embodiment of the present disclosure;

FIG. 20 shows characteristic waveform of the schmitt trigger unit according to the preferred embodiment of the present disclosure;

FIG. 21 shows an oscillator module according to the preferred embodiment of the present disclosure; and

FIG. 22 shows a method of initializing an oscillator module generating a clock signal to be used with a plurality of power sources coupled to a plurality of amplifiers respectively.

Please refer to FIG. 5 , which shows a clock calibration module 20 according to a first preferred embodiment of the present disclosure. In FIG. 5 , the clock calibration module 20 includes a plurality of power sources 201 , an inverting amplifier 202 , a resonator 204 , load capacitors C 3 and C 4 , and a digital amplitude calibration module 203 . The digital amplitude calibration module 203 includes a clock existence detector (CED) 2031 and a finite state machine (FSM) unit 2032 . The plurality of control signals AMP_CTRL <2:0> together with decoder (not shown) controls the plurality of power sources 201 to provide the inverting amplifier 202 with a suitable current, the inverting amplifier 202 drives the resonator 204 to output a clock signal CK 3 to the CED 2031 , and the CED 2031 detects whether the clock signal CK 3 is normal or is acceptable. The plurality of control signals AMP_CTRL <2:0> can be a single control signal depending on the number of power source applied. When the clock signal CK 3 is normal, the CED 2031 outputs a data signal Sd 1 indicating a message CKO_ALIVE which shows the clock signal CK 3 is alive. The finite state machine 2032 takes some proper measurements accordingly in response to receiving the data signal Sd 1 . The plurality of control signals AMP_CTRL <2:0> together with decoder indicates that eight power sources can be controlled, and the number of the control signal depends on the demand that the resonator 204 can start up the clock signal CK 3 normally. The manual calibration signal CSR_MAN_CAL can trigger the FSM unit 2032 to start a calibration process. The FSM unit 2032 can be constructed by a circuit synthesized by electronic design automation (EDA) tools, such as the synopsis and the like, a circuit designer can use a hardware description language (HDL) to build the circuit, such as the verilog HDL, the VHDL, or the like.

Please refer to FIG. 6 , which shows the FSM state diagram of the FSM unit 2032 according to the first preferred embodiment of the present disclosure. The FSM state diagram includes a calibration state S 10 and an idle state S 12 . In some embodiments, when the manual calibration signal CSR_MAN_CAL is in a low level state, the FSM unit 2032 enters into the idle state S 12 , and once the manual calibration signal CSR_MAN_CAL becomes in a high level state, the FSM unit 2032 enters into the calibration state S 10 . For some reasons whenever the clock signal CK 3 is abnormal, the manual calibration signal CSR_MAN_CAL can be operated by a user or by a software, even by an alarm triggered due to a detection of attenuation of the clock signal CK 3 .

Please refer to FIG. 7( a ) , which shows the digital amplitude calibration module 203 , and please refer to FIG. 7( b ) , which shows a timing diagram of input and output signals of the FSM unit 2032 according to the first preferred embodiment of the present disclosure. Please refer to FIGS. 6, 7 ( a ) and 7 ( b ). In FIG. 6 , in the state S 101 , the calibration process starts up, and the plurality of control signals AMP_CTRL <2:0> are set to zero for all bits, it shows zero power in FIG. 7( b ) during a first cycle time t_adj 1 , which is a predetermined period of time and depends on the CED 2031 . The power can be provided in the form of a plurality of current sources or a plurality of voltage sources. When the manual calibration signal CSR_MAN_CAL is in a high level state, the calibration signal MAN_CAL is changed from a low level state to a high level state after one period 1 T 1 , the calibration complete signal MAN_CAL_DONE is changed from a high level state to a low level state, and the FSM unit 2032 outputs a kick signal kick_bar to the resonator 204 , then the FSM unit 2032 starts to monitor the message CKO_ALIVE. The kick signal kick_bar can give the resonator 204 an instant clock boost to help the clock signal CK 3 swing further. In FIG. 6 , in the state S 102 , the CED 2031 monitors the message CKO_ALIVE and the clock signal CK 3 is checked by using the message CKO_ALIVE. In the state S 103 it is decided whether the message CKO_ALIVE indicating the status of the clock signal CK 3 is high. If the message CKO_ALIVE shows a low level state, it indicates the clock signal CK 3 is not normal, and additional power is necessary to drive, so the calibration process is configured to have a state S 104 . In FIGS. 6 7 ( a ) and 7 ( b ), in the state S 104 , the plurality of control signals AMP_CTRL <2:0> digitally adjust the plurality of power source 201 by elevating one step, i.e., from three binary bits “000” to “001”, it shows one additional step power is accumulated as in FIG. 7( b ) during a second cycle time t_adj 2 being equal to the first cycle time t_adj 1 , and the FSM unit 2032 outputs the kick signal kick_bar to the resonator 204 . If the message CKO_ALIVE shows a high level state, the FSM unit 2032 outputs a reset signal (not shown) to let the CED 2031 output the message CKO_ALIVE showing a low level state again, and the calibration process is configured to have a state S 105 . In the state S 105 , the same way as performed in the state S 104 adjusts power by elevating one step. This is because some factors including temperature, process variation, humidity can affect the frequency or the amplitude of the clock signal CK 3 , therefore in order to guarantee the clock signal CK 3 can swing and function normally within the variety of condition, it is reasonable to elevate power by one step. In some embodiments, because the message CKO_ALIVE has shown a high level state, it indicates that the clock signal CK 3 swings sufficiently to work normally, so the FSM unit 2032 keeps the plurality of control signals AMP_CTRL <2:0>, and don't need to digitally adjusts the plurality of power source 201 by elevating one step, in other words, the state S 105 can be omitted.

Please refer to FIGS. 6, 7 ( a ) and 7 ( b ), when the message CKO_ALIVE shows a low level state again, the calibration signal MAN_CAL provided from the FSM unit 2032 to the CED 2031 is changed to be in a low level state, which idles all the operations of detecting the clock signal CK 3 regardless it is normal or abnormal. Meanwhile, the calibration complete signal MAN_CAL_DONE provided from the FSM unit 2032 goes to be in a high level state again, and indicates that the calibration process is done and the FSM unit 2032 enters the idle state S 12 .

When the FSM unit 2032 enters the idle state S 12 , it also disables the CED 2031 . In addition, the CED 2031 and the FSM unit 2032 are all digital devices, so there is almost no power to waste during the idle state S 12 . The digital amplitude calibration module 203 has the advantage of saving power because it is only active during the calibration process and otherwise is idle, thus the whole digital structure of the digital amplitude calibration module 203 consumes very low power which almost can be neglected. Unlike the analog amplitude calibration circuit 103 , it still consumes relatively large static current as time goes, even if it is not active.

Please refer to FIG. 8 , which shows the plurality of power sources 201 according to the first preferred embodiment of the present disclosure. The plurality of power sources 201 include a digitalized current supply unit 205 , wherein the digitalized current supply 205 includes a plurality of current sources 206 and a plurality of MOS switches 207 controlled by the plurality of control signals SW_CTRL 0 , SW_CTRL 1 , SW_CTRL 2 . . . SW_CTRL 7 respectively. Each of the plurality of MOS switches 207 has a source terminal coupled to each of the plurality of current source 206 respectively, and has a drain terminal which is all coupled to the inverting amplifier 202 , wherein each of the plurality of MOS switches 207 has the same ratio of channel width to channel length.

In some embodiment, there can be only one current source, and each of the plurality of MOS switches 207 has the source terminal coupled to the current source, and has the drain terminal which is all coupled to the inverting amplifier 202 , wherein each of the plurality of MOS switches 207 has the different ratio of channel width to channel length.

Please refer to FIG. 9 , which shows an implementation circuit of the CED 2031 in detail according to the second preferred embodiment of the present disclosure. The CED 2031 is implemented by a shift register 2033 , has an output OUT 1 , and receives a data signal Sd 0 and the clock signal CK 3 is powered by the inverting amplifier 202 and at least one of the plurality of power sources 201 . Please refer to FIGS. 5 and 9 , the state machine unit 2032 detects whether the output OUT 1 has the data signal Sd 0 within a predetermined period of time, wherein if the output OUT 1 has the data signal Sd 0 within the predetermined period of time, the state machine unit 2032 keeps the clock signal CK 3 powered by the at least one of the plurality of power sources 201 ; and if not, the state machine unit 2032 additionally powers the clock signal CK 3 by another one of the plurality of power sources.

In FIG. 9 , in some embodiments, the reset signal RST_bar, the set signal SET and the data signal Sd 0 are provided from the FSM unit 2032 , and the clock signal CK 3 provided from the resonator 204 needed to be checked. When the FSM unit 2032 is in the idle state S 12 , the data signal Sd 0 , the reset signal RST_bar and the set signal SET are always in low level states. When the FSM unit 2032 is in the calibration state S 10 , the data signal Sd 0 goes to be in a high level state, the reset signal RST_bar goes to be in a high level state to release all the individual registers, and the set signal SET keeps the low level state. The calibration signal MAN_CAL in FIG. 7 can be used to the reset signal RST_bar in FIG. 9 . If the clock signal CK 3 works normally, the shift register 2033 passes the data signal Sd 0 to the output OUT 1 when the amplitude of the plurality of power sources is large enough to shift the data signal Sd 0 to the output OUT 1 within the predetermined period of time. Unlike the conventional peak detector 1031 , there is no need to care whether the amplitude of the clock signal CK 3 swings sufficiently, the only thing needs to be checked is whether the output OUT 1 has the data signal Sd 0 within the predetermined period of time, or in other point of view, the shift register 2033 starts to detect the data signal Sd 0 at the output OUT 1 within the predetermined period of time when the reset signal RST_bar being in a high level state is received by the shift register 2033 . When the clock signal CK 3 is detected, it is necessary to make sure that the clock signal CK 3 is stable, thus the predetermined period of time is required. The number of the shift register 2033 can be used to determine the predetermined period of time. In some embodiments, a clock divider receiving the clock signal CK 3 may be arranged prior to the shift register 2033 , and the shift register 2033 can be replaced by only one register. For example, a 1/32 clock divider together with only one register can output the data signal Sd 0 after the predetermined period of time.

In some embodiments, when the shift register 2033 is operated in a “SET” scenario and the FSM unit 2032 is in the idle state S 12 , the set signal SET is always in a high level state, the reset signal RST_bar is in a low level state, and the data signal Sd 0 is always in a low level state. The inverse of the calibration signal MAN_CAL in FIG. 7( b ) is used to be the set signal SET when the shift register 2033 is operated in the SET scenario. Once the FSM unit 2032 enters the calibration state S 10 by manually triggering, the set signal SET goes to be in a low level state, the reset signal RST_bar keeps the low level state, thus the data signal Sd 0 passes through the registers sequentially and is shifted to the output OUT 1 . The FSM unit 2032 will detect the output OUT 1 having a level state changed from a high level state to a low level state, which indicates the clock signal CK 3 is normal. After the FSM unit 2032 detects this data transition within the predetermined period of time starting from a start time that a level state of the set signal SET is changed from a high level state to a low level state, the FSM unit 2032 controls the level state of the set signal SET to be changed from the low level state to a high level state to deactivate the shift register 2033 , and the FSM unit 2032 itself is back to be in the idle state S 12 . By this all digitized module and method of calibrating the clock signal CK 3 , the power consumption is almost zero in the idle state S 12 , which can prolong the battery life of the IoT device to ten years. Even if the FSM unit 2032 is in the calibration state S 10 , the all digitized module in a relative low frequency clock can also consume very few power compared with the conventional analog calibration circuit.

Please refer to FIG. 10 , which shows an implementation circuit of the CED 2031 in detail according to the third preferred embodiment of the present disclosure. The CED 2031 is implemented by two shift register 2034 , 2035 and a clock divider 2036 . The shift register 2034 includes an AND gate AND 1 , and flip flops FF 1 and FF 2 coupled serially and electrically, and is used to reset the clock divider 2036 and the shift register 2035 by outputting the reset signal rstx_bar to the clock divider 2036 and each R terminal of flip flops FF 3 , FF 4 , FF 5 and FF 6 . Even when the kick signal kick_bar kick_bar and the calibration signal MAN_CAL are in high level states, the data Vx and the reset signal rstx_bar will become in high level states to allow data Vx and DT 1 to be delivered. The clock divider 2036 divides the frequency of the clock signal CK 3 to provide the clock signal CK 5 to each clock input of the flip flops FF 3 , FF 4 and FF 5 . The shift register 2035 includes an AND gate AND 2 , the flip flops FF 3 , FF 4 and FF 5 connected serially, and an EXCLUSIVE OR gate EXOR 1 coupled serially and electrically between the flip flop FF 6 and the flip flop FF 5 . The shift register 2035 is used to detect whether the clock signal CK 3 is normal. The shift register 2034 is operated by another clock source CK 4 from a system. The clock signal CK 3 is also used to be the system clock as soon as it is normal, so it is beneficial to switch between them in case one of them is down.

Please refer to FIGS. 6, 7 ( a ), 7 ( b ) and 10 , when the FSM unit 2032 is in the idle state S 12 in FIG. 6 , the calibration signal MAN_CAL being not on duty is in a low level state, and the flip flops FF 1 , FF 2 are all reset to be in a low level state at each output terminal Q, and it results in resetting the flip flops FF 3 , FF 4 , FF 5 to be in a low level state at each output terminal Q.

When the manual calibration signal CSR_MAN_CAL is triggered by a software or a user, the FSM unit 2032 starts the calibration process, the calibration signal MAN_CAL becomes in a high level state, the reset signal rstx_bar provided from the output terminal Q of the flip flop FF 2 becomes in a high level state, and it allows the data DT 1 to be transmitted through the flip flops FF 3 , FF 4 and FF 5 . The output terminal Q_bar is connected back to the AND gate AND 2 , used to construct a T type flip flop, thus the skilled person knows that the T type flip flop outputs a flip data continuously, such as “0101 . . . ”. The flip data will be triggered by using the normal clock signal CK 3 to pass through flip flops FF 4 and FF 5 , and because two input terminals of the EXCLUSIVE OR gate EXOR 1 are electrically connected to an input data terminal and an output terminal Q of the flip flop FF 5 respectively, the flip data of the present clock and the flip data of the next clock must be complementary, causing the EXCLUSIVE OR gate EXOR 1 to change its output data from “0” in the idle state S 12 to “1”, then the clock signal CK 4 triggers flip flop FF 6 to send the message CKO_ALIVE indicating the clock signal CK 3 is normal in the next cycle as shown in the timing diagram in FIG. 7 . Once the FSM unit 2032 finds that the clock signal CK 3 is normal, it controls the calibration signal MAN_CAL to be back in the idle state S 12 , for example, to become in a low level state in this instance. Then all the outputs of flip flops FF 1 , FF 2 , FF 3 , FF 4 , FF 5 and FF 6 , and the data Vx become in low level states, and the data Vx and DT 1 won't be delivered.

Please refer to FIG. 11 , which shows a kick signal boosting the clock signal CK 3 of a clock calibration module 22 according to the preferred embodiment of the present disclosure. FIG. 11 is similar to FIG. 5 , but the only difference is three components added. They are PMOS M 6 and NMOS M 7 coupling to the resonator 204 and inverter 208 . The inverter 208 inverts the kick signal kick_bar, and the two kick signals kick_bar and kick couple to the gates of PMOS M 6 and NMOS M 7 respectively. The two kick signals kick_bar and kick give the resonator 204 an instant clock boost to help the clock signal CK 3 swing further. The PMOS transistor M 6 and the NMOS transistor M 7 are electrically coupled to terminal XI and XO of the resonator 204 respectively, and the inverting gate 208 is coupled to each gate of PMOS transistor M 6 and NMOS transistor M 7 respectively. Please refer to FIGS. 7 and 11 , when the FSM unit 2032 does not find any change at the message CKO_ALIVE during the first cycle time t_adj 1 , the FSM unit 2032 controls the kick signal kick_bar to become in a low level state, the PMOS transistor M 6 conducts to charge the capacitor C 3 , the NMOS transistor M 7 conducts to discharge the capacitor C 4 , and the clock signal CK 3 is boosted accordingly.

Please refer to FIG. 12 , which shows a driving circuit 30 according to the preferred embodiment of the present disclosure. The driving circuit 30 includes the digitalized current supply unit 205 including the plurality of current sources 206 and the plurality of MOS switches 207 controlled by the plurality of control signals, the inverting amplifier 202 including an array of amplifiers 2021 , 2022 . . . , 202 n . Each current source is electrically connected to a source terminal of each MOS switch, each amplifier 2012 , 2022 . . . , 202 n is coupled to a drain terminal of each MOS switch. The amplifier 2021 is coupled to the resistor R 2 and the switch S 2 in parallel. When the power is on, the switch S 2 is conducted, thus the array of amplifiers 2021 , 2022 . . . , 202 n has a relatively small gain After a startup time t_startup, the switch S 2 is open to cut off, the resistor R 2 is incorporated into a feedback loop of the amplifier 2021 , so the gain becomes relatively large.

Please refer to FIG. 13 , which shows waveforms of the clock signal CK 3 when it is initialized. The horizontal axis represents time, and the vertical axis represents voltage when the clock signal is initialized. The dash curve line shows a waveform V_XO of the point XO, and the solid curve line shows a waveform V_XI of the point XI. Please refer to FIGS. 12 and 13 , during the start up time t_startup, the voltage of the point XI reaches to the initial voltage V_initial very quickly because the gain is small. After the start up time, at the time of the trigger point P_trigger, the gain becomes relatively large because the resistor R 2 is incorporated, the operating point of the array of the amplifiers 2021 , 2022 . . . , 202 n shifts to increase its internal voltage and current, causing an oscillation boost at the points XI and XO, then the signal clock begins to oscillate continuously and steadily during the period t_osc. In some embodiments, during the start up time t_startup, the plurality of MOS switches 207 are all conducted, thus currents of the plurality of current sources are all flooded to the array of amplifiers 2021 , 2012 , . . . , 202 n respectively. In this embodiment, an initializing calibration process is reversed compared with the calibration process as in FIG. 7 .

Please refer to FIG. 14 , which shows a timing diagram of decreased power controlled by the FSM unit 2032 according to the preferred embodiment of the present disclosure. In FIG. 14 , the manual calibration signal CSR_MAN_CAL can be controlled by a software, for example, when the power is on, the initializing calibration process begins, the software is configured to set the level state of the manual calibration signal CSR_MAN_CAL from a low level state to a high level state. The kick signal KICK_bar is always in a high level state. After one period 1 T 1 , the level state of the calibration signal MAN_CAL is changed from a low level state to a high level state and a first detection cycle t_det 1 begins. Please refer to FIGS. 5, 8, 10 and 14 , the plurality of control signals AMP_CTRL <2:0> are set to a three-binary-bit value being equal to “111”, which indicates all the MOS switches 205 in FIG. 8 are conducted. The shift register 2035 in FIG. 10 begins to detect whether the message CKO_ALIVE indicates that the clock signal CK 3 is normal within a predetermined period of time, and if the message shows a high level state after the first period of time t_adj 3 , the calibration signal MAN_CAL will be in a low level state to reset all the flip flops FF 1 , FF 2 , FF 3 , FF 4 , FF 5 and FF 6 , thus the message CKO_ALIVE becomes in a low level state in order to start a second detection cycle t_det 2 . Meanwhile, the plurality of control signals AMP_CTRL <2:0> will be set to a three-binary-bit value “110”, indicating the current provided by the plurality of power sources 206 is decreased by one step. Then the level state of the calibration signal is changed from the low level state to a high level state again in order to start another detection cycle.

In FIG. 14 , the second detection cycle t_det 2 starts at the beginning of the second period of time t_adj 4 , which is the time when the level state of the calibration signal MAN_CAL is changed from the low level state to the high level state. The second period of time t_adj 4 as well as the first period of time t_adj 3 is related to the CED 2031 . For example, if a more steady clock detection is required, the clock divider 2036 of the CED 2031 in FIG. 10 can be designed as a 1/64 clock divider, it means that the message CKO_ALIVE shows a high level state after at least 64 consecutive clock cycle of the clock signal CK 3 to make sure that the clock signal CK 3 is stable and there is no fault detection happened. In this case, both periods of time t_adj 4 and t_adj 3 become longer. If the message still shows the clock signal CK 3 is normal, it indicates the current provided by the plurality of power sources 206 can be decreased by one step to save power, the plurality of control signals AMP_CTRL <2:0> will be set to a three-binary-bit value “101” at the time when the level state of the calibration signal MAN_CAL is changed from the high level state to a low level state, and a third detection cycle t_dec 3 continues.

In FIG. 14 , if the message CKO_ALIVE does not show the clock signal CK 3 is normal within the predetermined period of time, i.e., the message CKO_ALIVE is in a high level state, later at the end of the third detection cycle t_det 3 , the FSM unit 2032 detects there is no level transition of the message CKO_ALIVE, thus the FSM unit 2032 knows that the current provided by the plurality of power sources is not sufficient to support the clock signal CK 3 , so the FSM unit 2032 controls the plurality of control signals AMP_CTRL <2:0> to increase the current outputted from the plurality of power sources 206 by one step. At the end of the third detection cycle t_det 3 , the plurality of control signals AMP_CTRL <2:0> are set to a three-binary-bit value being equal to “110” by the FSM unit 2032 .

Similarly, the fourth detection cycle t_det 4 starts at the beginning of the period of time t_adj 6 , and ends at the time when the level state of the calibration signal MAN_CAL is from the high level state to a low level state. During the fourth detection cycle t_det 4 , if the FSM unit 2032 detects that the message CKO_ALIVE does show the clock signal CK 3 is normal after the period of time t_adj 6 , i.e., the message CKO_ALIVE is in a high level state, later at the end of the fourth detection cycle t_det 4 , the FSM unit 2032 determines to end this initializing calibration process and controls the level state of the calibration signal to be changed from the high level state to a low level state, thus the message CKO_ALIVE goes to be in a low level state, the plurality of control signals AMP_CTRL <2:0> are fixed, and the FSM 2032 enters the idle state.

Please refer to FIG. 15 , which shows an FSM state diagram of decreased power controlled by the FSM unit 2032 according to the preferred embodiment of the present disclosure. In FIGS. 14 and 15 , one condition must meet to go to an idle state S 22 for the FSM unit 2032 . It is that the message CKO_ALIVE indicating the clock signal CK 3 is abnormal, then is normal again after a check period of time (the period of time t_adj 6 ), then the calibration signal MAN_CAL is set to be in a low level state, and the FSM unit 2032 goes to be in the idle state S 22 . In some embodiment, when the power is on, the FSM unit 2032 will set the calibration signal MAN_CAL to be in a low level state and set the three-binary-bit value of the plurality of control signals AMP_CTRL <2:0> to be “111”, and the initializing calibration process begins.

In FIG. 15 , the state S 20 is an initializing calibration state. In the state S 201 , the initializing calibration process starts up, the plurality of control signals AMP_CTRL <2:0> are set to one for all bits, and it shows a full power in FIG. 14 during the first detection cycle t_det 1 . In the state S 202 , the CED 2031 monitors the message CKO_ALIVE and the clock signal CK 3 is checked by the message CKO_ALIVE. In the state S 203 , it is decided whether the message CKO_ALIVE indicating the status of the clock signal CK 3 is high. If the message CKO_ALIVE shows a high level state, it indicates the clock signal CK 3 is normal, and it still need to save power, so the calibration process is configured to have a state S 204 . In the state S 204 , the plurality of control signals AMP_CTRL <2:0> are used to digitally adjust the plurality of power source 201 by decreasing one step, i.e., from three binary bits “111” to “110”, it shows one step power is subtracted as in FIG. 14 at the end of the first detection cycle t_det 1 , then the initializing calibration process is configured to have a state S 205 . In FIGS. 14 and 15 , in the state S 205 , the first detection cycle t_det 1 is cleared and the second detection cycle t_det 2 is restarted. In the state S 203 , if the message CKO_ALIVE shows a low level state, then the initializing calibration process is configured to have a state S 206 . In the state S 206 , the power is adjusted by elevating one step, the plurality of control signals AMP_CTRL <2:0> are used to digitally adjust the plurality of power source 201 by elevating one step, i.e., from three binary bits “101” to “110”, and the initializing process is configured to have a state S 207 . In the state S 207 , the initializing calibration is done and the plurality of control signals AMP_CTRL are fixed. In some embodiments, after the state S 206 , the initializing process can go to be in the state S 205 and then detect whether the message CKO_ALIVE is in a high level state again. In the state S 205 , the third detection cycle t_det 3 is cleared, and the fourth detection cycle t_det 4 is restarted as shown in FIG. 14 .

The present invention discloses an initialization and calibration of the clock signal by all digitized calibration module and method. The power adjustment and detection supplied to the amplifier are operated in all digitized method regardless the amplitude of the clock signal calibrated by the analog method and device. During a decreased power calibration, the clock signal starts faster, then is digitally calibrated to save power in the idle state. During an increasing power calibration, the clock signal is powered in an optimal method, i.e., the power provided to the clock signal is smallest and large enough to support its normal operation in the idle state. The all digitized calibration module and method is helpful to save more power than that of the analog calibration circuit. Thus the all digitized calibration module and method can improve the chip's power efficiency so as to prolong the battery life and the operating time.

Please refer to FIG. 16( a ) , which shows an oscillator module 40 with a monitor circuit 42 according to the preferred embodiment of the present disclosure. The difference between the oscillator module 40 and the clock calibration module 20 in FIG. 5 is the monitor circuit 42 , for example, the oscillator module 40 includes the monitor circuit 42 , the clock calibration module 20 and a buffer 41 , and the buffer 41 can strengthen the clock signal CK 3 . The clock calibration module 20 is used to calibrate the clock signal CK 3 using the manual calibration signal CSR_MAN_CAL, while the monitor circuit 42 always detects whether the clock signal CK 3 is normal or abnormal. When the clock signal CK 3 is abnormal, the monitor circuit 42 will output the manual calibration signal CSR_MAN_CAL to calibrate the clock signal CK 3 , and thus the clock signal can recover from being abnormal automatically. On the contrary, if the monitor circuit 42 detects that the clock signal CK 3 is normal, then the digital calibration circuit 203 , which is all digitized circuit, powers down and enters the idle mode.

Please refer to FIG. 16( b ) , which shows an inverting amplifier 402 according to a preferred embodiment of the present disclosure. In some examples, the inverting amplifier 402 is a self-bias inverting amplifier including a NMOS transistor M 8 and a PMOS current source load 45 coupled together where a feedback resistor R 4 with resistance Rfb is connected between input IN 1 and output OUT 1 terminals of the inverting amplifier 402 , the PMOS current source load 45 has a first equivalent inner resistance r 1 , the NMOS transistor M 8 has a second equivalent trans-conductance gm 2 and a second equivalent inner resistance r 2 , and if Rfb is much larger than r 1 and r 2 , a voltage gain vo/vi of the amplifier is approximately equal to the following equation:

In FIG. 16( b ) , the feedback resistor M 8 is used to keep the inverting amplifier 402 in a linear amplified region. The PMOS current source load 45 includes a PMOS array 450 and a switch array 451 receiving signals from the decoder 48 . In FIG. 16( a ) , the monitor circuit 42 is coupled between the digital calibration circuit 203 and the crystal resonator 204 , and includes a clock monitor unit (CMU) 421 and a software module 422 electrically connected to the CMU 421 . The CMU 421 monitors the clock signal CK 3 to output an alarm signal ALR when the clock signal Ck 3 is abnormal. The software module 422 outputs the manual calibration signal CSR_MAN_CAL in response to the alarm signal ALR, then activates the calibration process as in FIGS. 14 and 15 . The plurality of power sources 201 are not only controlled by the plurality of control signals AMP_CTRL <2:0>, but are also controlled by the alarm signal ALR. In order to coordinate the alarm signal ALR and the plurality of control signals AMP_CTRL <2:0>, some components are required, for example, some logic gates and flip flops are added to control the plurality of power sources 201 .

Please refer to FIG. 17 , which shows a power control circuit according to the preferred embodiment of the present disclosure. The oscillator module 40 further includes a D flip flop circuit 44 , a set of OR gates 46 and a decoder 48 , which are included in the power control circuit. The detail of the set of OR gates is shown in FIG. 18 , which indicates that the OR gates 461 , 462 and 463 respectively output a plurality of decoding signals DEC <2:0> in response to the plurality of control signals AMP_CTRL <2>, AMP_CTRL <1> and AMP_CTRL <0>.

In some embodiments, please refer to FIGS. 16( a ) and 17 , when the CMU 421 outputs the alarm signal ALR to the D flip flop circuit 44 because the clock signal is abnormal, the D flip flop circuit 44 , in response to the alarm signal ALR having a high level state, transmits a high level data sd 3 , and outputs a monitor signal MONI having the high level state. Please refer to FIG. 18 , each of the OR gates 461 , 462 , 463 receives the monitor signal MONI, having the high level state, to output the plurality of decoding signals DEC <2:0> having a three binary bits “111”, which indicates that all of the plurality of power sources are turned on because the clock signal CK 3 fades out under such an emergency condition.

The decoder 48 can be a combination logic circuit having a truth table. Please refer to Table 1, which shows the truth table of the decoder 48 . In some embodiments, it can be designed as the following.

In FIG. 17 , the decoder 48 is coupled to the plurality of MOS switches 43 , and in response to the plurality of decoding signals DEC <2:0>, controls the plurality of MOS switches 43 by using a plurality of switch control signals SW_CTRL <7:0> individually. The plurality of MOS switches 43 can be implemented using NMOS or PMOS switches. Please refer to FIG. 17 and Table 1, when the clock signal CK 3 is abnormal, the plurality of decode signals DEC <2:0> will be equal to three binary bits “111”, therefore the decoder 48 output the plurality of switch control signals SW_CTRL <7:0> being equal to eight binary bits “11111111”, which will turn on all of the plurality of MOS switches 43 , and thus all of the plurality of power sources can provide the inverting amplifier 202 with full power.

Then, a monitor clear signal MONI_CLEAR_bar from the software module 422 resets the D flip flop circuit 44 to output the monitor signal MONI having a low level state after the alarm signal ALR occurs. Subsequently, the software module 422 sends CSR_MAN_CAL to invoke the digital calibration circuit 203 . The digital calibration circuit 203 can activate the calibration process as in FIGS. 6 and 7 ( a )-( b ) or in FIGS. 14 and 15 , i.e., increase or decrease power to more optimal one. In FIG. 18 , each of the OR gates 461 , 462 , 463 ignore the monitor signal MONI and pass through the plurality of control signals AMP_CTRL <2:0> to the decoder 48 . For the decreasing-power case, it can be “110” after “111” is received by the decoder 48 . The decoder 48 then outputs the plurality of switch control signals SW_CTRL <7:0> being equal to “01111111” according to the Table 1, and thus turns on seven MOS switches among the plurality of MOS switches 43 respectively. If there is a level transition of the message CKO_ALIVE, then the plurality of switch control signals SW_CTRL <7:0> change to “00111111” by decreasing power by one step. If there is no level transition of the message CKO_ALIVE as shown in third detection cycle t_det 3 of FIG. 14 , then the plurality of switch control signals SW_CTRL <7:0> changes back to “01111111” by increasing power by one step. In this way, the clock signal can not only operate in an optimal saving-power status, but can also be calibrated automatically whenever the clock signal is abnormal.

In some embodiments, it may prefer to switch to a second system clock source CK_SYSTEM as in FIG. 7( a ) while the clock signal CK 3 is being calibrated, and switch back to the clock signal CK 3 after the clock calibration is complete. Because the clock calibration procedure may take some time, this can guarantee a providing system clock to be stable, and then shut down the second system clock source CK_SYSTEM to save power.

Please refer to FIG. 19 , which shows the CMU 421 in detail according to the preferred embodiment of the present disclosure. In FIG. 19 , the CMU 421 includes a first current mirror 423 . The first current mirror 423 includes a P channel metal oxide semi-conductor (PMOS) transistor M 5 , a first NMOS transistor M 3 and a second NMOS transistor M 4 . The first NMOS transistor M 3 has a gate terminal GT 1 electrically connected to a drain terminal DT 1 of the first NMOS M 3 and a drain terminal of the PMOS M 5 . Each gate terminal GT 1 , GT 2 of the first and the second NMOS transistors M 3 , M 4 is electrically connected to a resistor R 3 , the clock signal CK 3 is coupled to the gate terminal GT 2 of the second NMOS transistor M 4 via a first capacitor C 5 , and a second capacitor C 6 is coupled to a source terminal ST 2 of the second NMOS transistor M 4 .

In FIG. 19 , the resistor R 3 and the first capacitor C 5 form a filter circuit to eliminate low frequency noise from the clock signal CK 3 to generate a filtered clock signal CK 3 _F. During the positive cycle of the filtered clock signal CK 3 _F, the second NMOS transistor is turned on because the filtered clock signal CK 3 _F has a positive amplitude which has a peak value Vamp, and then the current Idet flows through the second NMOS transistor and the second capacitor C 6 , and charges the second capacitor to a peak voltage Vx. During the negative cycle of the filtered clock signal CK 3 _F, the second NMOS transistor M 4 is turned off, and the second capacitor C 6 sustains the peak voltage Vx. If the peak voltage Vx drops below a predetermined threshold VTHL, the Schmitt trigger unit 424 , in response to this change, outputs a detected signal Sdet having a voltage Vy as shown in FIGS. 19 and 20 .

Please refer to FIG. 20 , which shows the characteristic waveform of the Schmitt trigger unit 424 according to the preferred embodiment of the present disclosure. The horizontal axis represents an input voltage VIN of the Schmitt trigger unit 424 , and the vertical axis represents an output voltage VOUT of the Schmitt trigger unit 424 . The waveform WAF indicates that the Schmitt trigger unit 424 is a bi-stable component, and the predetermined threshold VTHL and VTHH are near the middle level of the logic level range, for example, if the logic level ranges from 0 to 5 volts, the predetermined threshold VTHL may be 2 volts and the predetermined threshold VTHH may be 3 volts. This can prevent the CMU 421 from a false alarm because the noise from the clock signal CK 3 near the middle level will be filtered out.

In FIG. 19 , an AND gate 425 receives the detected signal Sdet and a calibration complete signal MAN_CAL_DONE from the digital calibration circuit 203 to output the alarm signal ALR. The software module 422 is coupled to the CMU 421 , and receives the alarm signal ALR to output the manual calibration signal CSR_MAN_CAL. Because the calibration operation and the monitor operation of the clock signal CK 3 are combined together, there is a need to separate these two operations from a conflict. For this purpose, the calibration complete signal MAN_CAL_DONE from the digital calibration circuit 203 can be used to enable or disable the alarm signal ALR depending on its high level state or low level state. Please refer to FIGS. 7 and 19 , when the calibration operation is performed, the calibration complete signal MAN_CAL_DONE has a low level state, so the AND gate 425 is disabled, and the alarm signal ALR is in a low level state, which will not interfere with the calibration operation. Once the calibration operation is completed, the calibration complete signal MAN_CAL_DONE has a high level state, so the alarm signal ALR is outputted from the AND gate 425 depending on the detected signal Sdet. In some embodiments, the software module 422 can also output an enable signal CSR CMU EN to enable the CMU 421 when the software module 422 receives the calibration complete signal MAN_CAL_DONE.

Please refer to FIG. 21 , which shows an oscillator module 50 according to the preferred embodiment of the present disclosure. The oscillator module 50 comprises an oscillator unit 501 and a digitized circuit 502 . The oscillator unit 501 generates a clock signal CK 6 . The digitized circuit 502 digitally detecting whether the clock signal CK 6 is normal, wherein if the clock signal CK 6 is normal, the digitized circuit 502 idles itself and the oscillator module 50 monitors whether the clock signal CK 6 remains normal.

Please refer to FIG. 22 , which shows a method of initializing an oscillator module generating a clock signal to be used with a plurality of power sources coupled to a plurality of amplifiers respectively, and the method comprises step S 301 : detecting whether the oscillator module has output a data signal within a predetermined period of time, wherein step S 302 : if the output has the data signal within the predetermined period of time, decreasingly power the clock signal by the at least one of the plurality of power sources; step S 303 : if not, additionally power the clock signal by another one of the plurality of power sources.

Embodiments

1. An oscillator module used with a plurality of power sources, comprising an oscillator unit, a clock monitor unit (CMU), a software module and a digital calibration circuit. The oscillator unit generates a clock signal. The CMU is coupled to the oscillator unit, determines whether an amplitude of the clock signal exceeds a predetermined threshold, and outputs an alarm signal if the amplitude of the clock signal is lower than the predetermined threshold. The software module is coupled to the CMU, and receives the alarm signal to output a calibration signal. The digital calibration circuit is coupled to the oscillator and the software module, outputs a control signal in response to the clock signal and the calibration signal, adjusts the plurality of power sources to modify the clock signal.

2. The module in Embodiment 1, wherein the CMU includes a first current mirror, a schmitt trigger unit and an AND gate. The first current mirror includes a first P channel metal oxide semi-conductor (PMOS) transistor, a first n channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, wherein the first NMOS transistor has a gate terminal electrically connected to a drain terminal of the first NMOS and a drain terminal of the first PMOS, the gate terminals of the first and the second NMOS transistors are electrically connected to a resistor, the clock signal is transmitted to the gate terminal of the second NMOS transistor via a first capacitor, and a second capacitor is coupled to a source terminal of the second NMOS transistor. The resistor and the first capacitor form a filter circuit to eliminate low frequency noise from the clock signal to generate a filtered clock signal. The second NMOS transistor, in response to the filtered clock signal, generates a voltage sustained by the second capacitor. The schmitt trigger unit is coupled to the first current mirror and receives the voltage to output a detected signal. The AND gate is coupled to the schmitt trigger unit and the digital calibration circuit, and receives the detected signal and a calibration complete signal from the schmitt trigger unit and the digital calibration circuit respectively to output the alarm signal.

3. The module of any one of Embodiments 1-2, wherein the plurality of power sources are a plurality of current sources electrically connected to a plurality of MOS switches respectively. The oscillator module further includes a D flip flop circuit, a set of OR gates and a decoder. The D flip flop circuit receiving a data signal having a high level state, the alarm signal from the CMU and a monitor clear signal from the software module to output a monitor signal. The set of OR gates, each of which receives the monitor signal and one of a plurality of control signals from the digital calibration circuit to output a plurality of decoding signals. The decoder is coupled to the plurality of MOS switches, and controls the plurality of MOS switches in response to the plurality of decoding signals individually.

4. The module of any one of Embodiments 1-3, wherein the oscillator module further includes an amplifier, a crystal resonator, a first load capacitor and a second load capacitor. The amplifier having an input terminal and an output terminal, receives a first pre-oscillation signal and a current which is from the plurality of power sources, and outputs a second pre-oscillation signal having a phase equal to minus 180 degrees of the first pre-oscillation signal. The crystal resonator is coupled to the input terminal and the output terminal, and provides the clock signal to the digital calibration circuit via the output terminal. The first load capacitor is coupled to the input terminal and a ground terminal. The second load capacitor is coupled to the output terminal and the ground terminal.

5. The module of any one of Embodiments 1-4, wherein the amplifier is a self-bias inverting amplifier including a NMOS transistor and a PMOS current source load coupled together where a feedback resistor with resistance Rfb is connected between input and output terminal of the amplifier, the PMOS current source load has a first equivalent inner resistance r 1 , the NMOS transistor has a second equivalent trans-conductance gm 2 and a second equivalent inner resistance r 2 , and if Rfb is much larger than r 1 and r 2 , a voltage gain vo/vi of the amplifier is approximately equal to the following equation:

6. The module of any one of Embodiments 1-5, wherein the digital calibration circuit includes a clock existence detector (CED) and a state machine unit. The CED receives the clock signal, and outputs a data signal when the data signal of the CED transits from a first output level to a second output level. The state machine unit is coupled to the CED, and detects whether the data signal from the CED has the second output level, wherein if the CED has the second level, the state machine keeps the clock signal at the amplitude; and if not, the state machine additionally powers the clock signal by another one of the plurality of power sources.

7. The module of any one of Embodiments 1-6, wherein the software module enables the CMU when the software module receives a calibration complete signal.

8. An oscillator module comprises an oscillator unit and a digitized circuit. The oscillator unit generates a clock signal. The digitized circuit is coupled to the oscillator unit and digitally detects whether the clock signal is normal, wherein if the clock signal is normal, the digitized circuit idles itself; and if not, the digitized circuit is activated digitally.

9. The module in Embodiment 8, wherein the oscillator module is used with a plurality of power sources. The oscillator module further includes a monitor circuit coupled to the oscillator unit, and detecting whether the clock signal is acceptable. The digitized circuit further comprises a digital calibration circuit coupled to the monitor circuit, wherein if the clock signal is acceptable, the monitor circuit idles the digital calibration circuit and monitors whether the clock signal remains acceptable; and if not, the monitor circuit activates the digital calibration circuit.

10. The module of any one of Embodiments 8-9, wherein the oscillator module further includes a software module. The monitor circuit determines whether an amplitude of the clock signal exceeds a predetermined threshold, and outputs an alarm signal if negative. The software module receives the alarm signal to output a calibration signal. The digital calibration circuit outputs a plurality of control signals in response to the clock signal and the calibration signal, wherein the plurality of control signals adjust the plurality of power sources respectively to modify the clock signal.

11. The module of any one of Embodiments 8-10, wherein the monitor circuit includes a filter circuit filtering the clock signal to eliminate low frequency noise therefrom. The monitor circuit includes a first MOS transistor detecting the amplitude of the filtered clock signal during its positive cycle. The monitor circuit idles the digital calibration circuit when the amplitude of the filtered clock signal reaches the predetermined threshold.

12. The module of any one of Embodiments 8-11, wherein the oscillator module further includes a clock monitor unit (CMU) having a voltage detector and a current mirror including a second MOS transistor converting the amplitude of the clock signal to a detected voltage. The voltage detector maintains the detected voltage.

13. The module of any one of Embodiments 8-12, wherein the oscillator module includes a clock monitor unit (CMU) including a schmitt trigger unit and an AND gate. The schmitt trigger unit digitally inverts a logic level of the amplitude of the clock signal when the amplitude of the clock signal is below the predetermined threshold. The AND gate outputs the alarm signal in response to the inverted logic level and a calibration complete signal from the digital calibration circuit.

14. The module of any one of Embodiments 8-13, wherein the plurality of power sources are coupled to a plurality of switches respectively. The oscillator module further includes a D flip flop circuit, a set of OR gates and a decoder. The monitor circuit triggers the D flip flop circuit to output a monitor signal having a high level state when the alarm signal occurs. Regardless of the plurality of control signals from the digital calibration circuit, the monitor signal having the high level state individually triggers the sets of OR gates to output a set of decoding signals. The decoder decodes the set of decoding signals to output a plurality of switch control signals. The plurality of switch control signals adjust the plurality of power sources respectively by turning on all of the plurality of switches

15. The module of any one of Embodiments 8-14, wherein a monitor clear signal from the software module resets the D flip flop circuit to output the monitor signal having a low level state after the alarm signal occurs. The plurality of control signals from the digital calibration circuit respectively adjust the plurality of power sources by one of turning on and off at least one of the plurality of switches. The set of OR gates keeps the plurality of power sources controlled by the plurality of control signals from the digital calibration circuit respectively when the alarm signal does not occur.

16. An oscillator module comprises an oscillator unit and a digitized circuit. The oscillator unit generates a clock signal. The digitized circuit digitally detecting whether the clock signal is normal, wherein if the clock signal is normal, the digitized circuit idles itself and the oscillator module monitors whether the clock signal remains normal.

17. The module in Embodiments 16, wherein the oscillator module is used with a plurality of power sources. The oscillator module further includes a monitor circuit coupled to the oscillator unit and detecting whether the clock signal is acceptable. The digitized circuit further comprises a digital calibration circuit coupled to the monitor circuit, wherein if the clock signal is acceptable, the monitor circuit idles the digital calibration circuit and monitors whether the clock signal remains acceptable; and if not, the monitor circuit activates the digital calibration circuit.

18. The module of any one of Embodiments 16-17, wherein the CMU includes a first current mirror, a schmitt trigger unit and an AND gate. The first current mirror includes a first P channel metal oxide semi-conductor (PMOS) transistor, a first n channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, wherein the first NMOS transistor has a gate terminal electrically connected to a drain terminal of the first NMOS and a drain terminal of the first PMOS, the gate terminals of the first and the second NMOS transistors are electrically connected to a resistor, the clock signal is transmitted to the gate terminal of the second NMOS transistor via a first capacitor, and a second capacitor is coupled to a source terminal of the second NMOS transistor. The resistor and the first capacitor form a filter circuit to eliminate low frequency noise from the clock signal to generate a filtered clock signal. The second NMOS transistor, in response to the filtered clock signal, generates a voltage sustained by the second capacitor. The schmitt trigger unit is coupled to the first current mirror and receives the voltage to output a detected signal. The AND gate is coupled to the schmitt trigger unit and the digital calibration circuit, and receives the detected signal and a calibration complete signal from the schmitt trigger unit and the digital calibration circuit respectively to output the alarm signal.

19. The module of any one of Embodiments 16-18, wherein wherein the plurality of power sources are a plurality of current sources electrically connected to a plurality of MOS switches respectively. The oscillator module further includes a D flip flop circuit, a set of OR gates and a decoder. The D flip flop circuit receiving a data signal having a high level state, the alarm signal from the CMU and a monitor clear signal from the software module to output a monitor signal. The set of OR gates, each of which receives the monitor signal and one of a plurality of control signals from the digital calibration circuit to output a plurality of decoding signals. The decoder is coupled to the plurality of MOS switches, and controls the plurality of MOS switches in response to the plurality of decoding signals individually.

20. The module of any one of Embodiments 16-19, wherein when the alarm signal having a high level state triggers the D flip flop circuit, the D flip flop circuit outputs the monitor signal having the high level state, the set of OR gates output the plurality of decoding signals having the high level state in response to a transition from a low level state to the high level state, and the decoder turns on all of the plurality of MOS switches to recover the clock signal. When the alarm signal has a low level state, the D flip flop circuit outputs the monitor signal having an unchanged level state, the set of OR gates output the plurality of decoding signals having the same states as those of the plurality of control signals in response to the digital calibration circuit, and the decoder control the plurality of MOS switches to calibrate the clock signal when the digital calibration circuit is triggered by a calibration signal from the monitor circuit; and the digital calibration circuit includes a clock existence detector (CED) and a state machine unit. The CED receives the clock signal, and outputs a data signal when the data signal of the CED transits from a first output level to a second output level. The state machine unit is coupled to the CED, and detects whether the CED has the second output level, wherein if the CED has the second level, the state machine keeps the clock signal at the same amplitude; and if not, the state machine additionally powers the clock signal using another one of the plurality of power sources.

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.