Amplifier and method of operating same

Amplifiers are classified based on certain operating characteristics. A low noise amplifier (LNA) is often used as a low power amplifier in communication systems. The recent trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices which consume less power, yet provide functionality at higher speeds. The miniaturization process has also resulted in stricter design and manufacturing specifications for LNAs.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic diagram of an amplifier, in accordance with some embodiments.

FIG. 2 is a schematic diagram of an amplifier usable as the amplifier in FIG. 1 , in accordance with some embodiments.

FIG. 3 is a flowchart of a method of operating an amplifier, in accordance with some embodiments.

FIG. 4 is a schematic drawing of different voltage levels of an amplifier usable in FIG. 1 , in accordance with some embodiments.

FIG. 5 is a schematic drawing of a coupling coefficient of a transformer usable in FIG. 1 , in accordance with some embodiments.

The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In some embodiments, an amplifier includes an input node, an output node, a transistor and a transformer. The input node is configured to receive a first signal. The output node is configured to output an amplified first signal. The transistor includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the input node and a first supply voltage source. The second terminal is coupled to a second supply voltage source and the output node. The third terminal is coupled to a reference node. The transformer is coupled to the first terminal and the third terminal. The transistor is configured to operate in a sub-threshold region and a near-triode region.

Low noise amplifiers (LNAs) are often located on the front-end portion of a receiver and are used to amplify signals with low signal to noise ratios (SNRs). Furthermore, as IC sizes continue to shrink, the available power supplied to LNAs continues to decrease as well. Therefore, LNAs have to amplify signals with low SNRs using low supply voltages and currents. By configuring a transistor in an LNA to operate in the sub-threshold region and the near-triode region, and coupling the transistor to a transformer, the LNA is configured to operate with a low DC power supply level (P DC ) and consumes a low amount of power.

FIG. 1 is a schematic diagram of an amplifier 100 , in accordance with some embodiments. Amplifier 100 includes an input node IN, an output node OUT, a resistor Rg, a transformer 102 , a transistor M 1 , an output capacitor Cout and a drain inductor Ld. Amplifier 100 is a single-stage common source amplifier. In some embodiments, amplifier 100 is a LNA.

Input node IN is configured to receive signal Sin. In some embodiments, signal Sin is a radio frequency (RF) signal. Output node OUT is configured to output an amplified signal Sout responsive to the signal Sin. In some embodiments, amplified signal Sout is an RF signal. Input node IN is coupled to the transformer 102 and a resistor Rg.

A first terminal of resistor Rg is coupled to input node IN and transformer 102 . A second terminal of resistor Rg is coupled to a first supply voltage source V G . In some embodiments, resistor Rg includes one or more resistive elements.

Transformer 102 is configured as an impedance matching network. Transformer 102 is configured to match an input impedance Zin of transistor M 1 with an output impedance Zout of a source (not shown) of RF signal Sin in order to minimize reflections. Transformer 102 includes a first inductor Lg and a second inductor Ls. In some embodiments, first inductor Lg includes one or more inductive elements. In some embodiments, second inductor Ls includes one or more inductive elements.

First inductor Lg is coupled between a gate terminal of transistor M 1 and input node IN and the first terminal of resistor Rg.

Second inductor Ls is coupled between the source terminal of transistor M 1 and a reference node Vss. The reference node Vss corresponds to ground. First inductor Lg and second inductor Ls are inductively or magnetically coupled to each other, as shown by element 104 of FIG. 1 . In some embodiments, first inductor Lg and second inductor Ls are mutually coupled to each other. For example, first inductor Lg and second inductor Ls are configured such that a change in a current through the first inductor Lg induces a voltage across the second inductor Ls by electromagnetic induction, and a change in a current through the second inductor Ls induces a voltage across the first inductor Lg by electromagnetic induction. The amount of inductive coupling between the first inductor Lg and the second inductor Ls is measured by the mutual inductance between the first inductor Lg and the second inductor Ls (e.g., Mgs and Msg shown in FIG. 2 ). First inductor Lg has a mutual inductance Mgs (shown in FIG. 2 ) with second inductor Ls. Second inductor Ls has a mutual inductance Msg (shown in FIG. 2 ) with first inductor Lg. In some embodiments, first inductor Lg and second inductor Ls are located on a same chip as the other components (e.g., input node IN, transistor M 1 , resistor Rg, drain inductor Ld and output node OUT) in amplifier 100 . In some embodiments, by mutually coupling first inductor Lg and second inductor Ls to each other, an impedance of first inductor Lg is matched with an impedance of second inductor Ls.

Transistor M 1 comprises a gate terminal, a drain terminal and a source terminal. The gate terminal is coupled to the first inductor Lg. The drain terminal is coupled to drain inductor Ld and output capacitor OUT. The source terminal is coupled to second inductor Ls. Transistor M 1 is an n-type or p-type metal oxide semiconductor field effect transistor (MOSFET). In some embodiments, transistor M 1 is a FinFET. In some embodiments, other transistor types are usable as transistor M 1 .

Transistor M 1 is configured to operate in a sub-threshold region and a near-triode region. Transistor M 1 is configured to operate in the sub-threshold region if a voltage Vgs of the gate terminal is less than a threshold voltage Vth of transistor M 1 , as expressed by formula 1:

Vgs<Vth of transistor M 1  (1)

where Vgs is the voltage between the gate terminal of transistor M 1 and the source terminal of transistor M 1 and Vth is the threshold voltage of transistor M 1 .

In some embodiments, transistor M 1 is configured to operate in the near-triode region if a voltage Vds between the drain terminal and the source terminal is proportional to a current Ids flowing through the drain terminal and the source terminal. In some embodiments, transistor M 1 is configured to operate in the near-triode region if the difference between the voltage Vgs between the gate terminal and the source terminal and the threshold voltage Vth of transistor M 1 is greater than voltage Vds between the drain terminal and the source terminal, as expressed by formula 2:

Vgs−Vth>Vds of transistor M 1  (2)

where Vgs is the voltage between the gate terminal of transistor M 1 and the source terminal of transistor M 1 , Vth is the threshold voltage of transistor M 1 , and Vds is the voltage between the drain terminal of transistor M 1 and the source terminal of transistor M 1 .

In some embodiments, transistor M 1 is configured to operate in the near-triode region if a voltage Vgd between the gate terminal and the drain terminal is greater than the threshold voltage Vth of transistor M 1 , as expressed by formula 3:

Vgd>Vth of transistor M 1  (3)

where Vgd is the voltage between the gate terminal of transistor M 1 and the drain terminal of transistor M 1 and Vth is the threshold voltage of transistor M 1 .

A first terminal of drain inductor Ld is coupled to a second supply voltage source V DD . A second terminal of drain inductor Ld is coupled to output capacitor OUT or the drain terminal of transistor M 1 . Drain inductor Ld is configured to pass direct current (DC) signals between transistor M 1 and second supply voltage source V DD . Drain inductor Ld is configured to block alternating current (AC) or RF signals from being passed from transistor M 1 to second supply voltage source V DD . In some embodiments, drain inductor Ld includes one or more inductive elements.

Output capacitor Cout is coupled between output node OUT and the drain terminal of transistor M 1 or the second terminal of drain inductor Ld. In some embodiments, output capacitor Cout includes one or more capacitive elements. Output capacitor Cout is configured to block DC signals from being provided to output node OUT. Output capacitor Cout is configured to pass AC or RF signals provided to output node OUT. Output node OUT is configured to output an amplified signal Sout responsive to the signal Sin.

In some embodiments, a voltage supplied by first supply voltage source V G ranges from about 0.1 volts to about 0.8 volts. In some embodiments, a voltage supplied by second supply voltage source V DD ranges from about 0 volts to about 0.8 volts.

In some embodiments, a voltage Vgs between the gate terminal of transistor M 1 and the source terminal of transistor M 1 ranges from about 0.1 volts to about 0.8 volts. In some embodiments, a voltage Vds between the drain terminal of transistor M 1 and the source terminal of transistor M 1 ranges from about 0 volts to about 0.8 volts. In some embodiments, a voltage Vgs between the gate terminal of transistor M 1 and the source terminal of transistor M 1 is greater than a voltage Vds between the drain terminal of transistor M 1 and the source terminal of transistor M 1 .

In some embodiments, an operating frequency of amplifier 100 ranges from about 0.1 Gigahertz (GHz) to about 10 GHz. In some embodiments, a fundamental frequency of the amplified signal Sout output by the amplifier 100 ranges from about 0.1 GHz to about 10 GHz. In some embodiments, amplifier 100 is conditionally stable when a voltage standing wave ratio (VSWR) is greater than 10. In some embodiments, an amplifier is conditionally stable if the amplifier will oscillate if load or source impedance conditions (e.g., VSWR) are not satisfied. Further, an amplifier is unconditionally stable if the amplifier does not oscillate regardless of load or source impedance conditions. In some embodiments, the VSWR is a ratio of the maximum voltage to the minimum voltage on the input node IN or output node OUT of amplifier 100 . In some embodiments, the stability of amplifier 100 is based upon the stability of transistor M 1 . In some embodiments, the stability of transistor M 1 is related to the forward trans-conductance g m and the feedback gate-drain capacitance Cgd of transistor M 1 . Transistor M 1 is stabilized by reducing either the forward trans-conductance g m or the feedback gate-drain capacitance Cgd. By configuring transistor M 1 of amplifier 100 to operate in the sub-threshold region and the near-triode region, the forward trans-conductance g m or the feedback gate-drain capacitance Cgd is reduced, yielding a stabilized transistor M 1 . In some embodiments, the forward trans-conductance g m of transistor M 1 is reduced by lowering the voltage Vgs of the gate terminal (e.g., supplied by first supply voltage source V G ) and reducing the voltage Vds (e.g., supplied by second supply voltage source V DD ) between the drain terminal and the source terminal. In some embodiments, an input impedance Zin of input node IN of amplifier 100 ranges from about 10 ohms to about 500 ohms. In some embodiments, amplifier 100 is an Ultra Low Power (ULP) RF integrated circuit. In some embodiments, amplifier 100 is configured to operate as an Ultra Low Voltage (ULV) RF integrated circuit.

FIG. 2 is a schematic diagram of an amplifier circuit 200 , in accordance with some embodiments. Amplifier circuit 200 is an equivalent circuit of a portion of amplifier 100 ( FIG. 1 ). As shown in FIG. 2 , similar elements have a same character number as shown in FIG. 1 .

Amplifier circuit 200 includes a first inductor Lg, a first mutual inductor Mgs, a portion of transistor M 1 ( FIG. 1 ), a second mutual inductor Msg and a second inductor Ls connected in series. The portion of transistor M 1 includes the gate terminal G and source terminal S. The portion of transistor M 1 includes a gate resistor R 1 , a capacitor Cgs, and a source resistor Rs. First inductor Lg, first mutual inductor Mgs, gate resistor R 1 , capacitor Cgs, source resistor Rs, second mutual inductor Msg and second inductor Ls are connected in series.

First inductor Lg has an impedance Z1. Second inductor Ls has an impedance Z2.

First mutual inductor Mgs is the mutual inductance between the first inductor Lg and the second inductor Ls. Second mutual inductor Msg is the mutual inductance between the second inductor Ls and the first inductor Lg. The inductance of first mutual inductor Mgs or the inductance of second mutual inductor Msg is expressed by equation 4 as:

Mgs=Msg=k ( LgLs ) 0.5   (4)

where Mgs is the mutual inductance of mutual inductor Mgs, where Msg is the mutual inductance of mutual inductor Msg, k is the coupling coefficient between first inductor Lg and second inductor Ls, Lg is the inductance of the first inductor, and Ls is the inductance of the second inductor. First mutual inductor Mgs has an impedance Z3. Second mutual inductor Msg has an impedance Z4.

Gate resistor R 1 corresponds to the resistance of the gate terminal of transistor M 1 . The resistance of the gate resistor R 1 is expressed by equation 5 as:

R 1 =k ( LgLs ) 0.5 *( g m /Cgs )  (5)

where R 1 is the resistance of the gate resistor, k is the coupling coefficient between first inductor Lg and second inductor Ls, Lg is the inductance of the first inductor, Ls is the inductance of the second inductor, g m is a transconductance of transistor M 1 , Cgs is the equivalent capacitance between the gate terminals and the source terminals of transistor M 1 . Gate resistor R 1 has an impedance Z5.

Capacitor Cgs corresponds to the equivalent capacitance between the gate terminals and the source terminals of transistor M 1 . Capacitor Cgs has an impedance Z6.

Source resistor Rs corresponds to the resistance of the source terminal of transistor M 1 . The resistance of the source resistor Rs is expressed by equation 6 as:

Rs=Ls *( g m /Cgs )  (6)

where Rs is the resistance of the source resistor, Ls is the inductance of the second inductor, g m is a transconductance of transistor M 1 and Cgs is the equivalent capacitance between the gate terminals and the source terminals of transistor M 1 . Source resistor Rs has an impedance Z7.

Amplifier circuit 200 has an input impedance Zin having a LaPlace S-domain expression. The input impedance Zin of amplifier circuit 200 of transistor M 1 is expressed by equation 7 as:

Z in= Z 1 +Z 2 +Z 3 +Z 4 +Z 5 +Z 6 +Z 7  (7)

where Z1 is the impedance of first inductor Lg, Z2 is the impedance of first mutual inductor Mgs, Z3 is the impedance of the gate resistor R 1 , Z4 is the impedance of capacitor Cgs, Z5 is the impedance of second inductor Ls, Z6 is the impedance of second mutual inductor Msg and Z7 is the impedance of the source resistor Rs.

After substituting the corresponding values from equations 4-7 into equation 7, the input impedance Zin of amplifier circuit 200 of transistor M 1 is expressed by equation 8 as:

Z in=( Lg+k ( LgLs ) 0.5 )*( g m /Cgs )+(1/( S*Cgs ))+ S *( Lg+Ls+ 2 k ( Ls*Lg ) 0.5 )  (8)

where Zin is the input impedance of amplifier circuit 200 of transistor M 1 , k is the coupling coefficient between first inductor Lg and second inductor Ls, Lg is the inductance of the first inductor, Ls is the inductance of the second inductor, g m is a transconductance of transistor M 1 , Cgs is the equivalent capacitance between the gate terminals and the source terminals of transistor M 1 and S is the Laplace coefficient.

In some embodiments, the size of the first inductor Lg of amplifier 100 or amplifier 200 is 25% smaller in comparison with a gate inductor connected to a gate terminal of a transistor, where the gate inductor is not mutually coupled to a source inductor connected to the source terminal of the same transistor, and the gate inductor and the source inductor are part of an impedance matching network. In some embodiments, the inductance of the first inductor Lg of amplifier 100 or amplifier 200 is 25% smaller in comparison with a gate inductor connected to a gate terminal of a transistor, where the gate inductor is not mutually coupled to a source inductor connected to the source terminal of the same transistor, and the gate inductor and the source inductor are part of an impedance matching network. In some embodiments, the size of the second inductor Ls of amplifier 100 or amplifier 200 is 75% smaller in comparison with a source inductor connected to a source terminal of a transistor, where the source inductor is not mutually coupled to a gate inductor connected to the gate terminal of the same transistor, and the gate inductor and the source inductor are part of an impedance matching network. In some embodiments, the inductance of the second inductor Ls of amplifier 100 or amplifier 200 is 75% smaller in comparison with a source inductor connected to a source terminal of a transistor, where the source inductor is not mutually coupled to a gate inductor connected to the gate terminal of the same transistor, and the gate inductor and the source inductor are part of an impedance matching network. In some embodiments, by mutually coupling the first inductor Lg and the second inductor Ls of amplifier 100 or amplifier 200 , the size or inductance of the first inductor Lg and the second inductor Ls is reduced in comparison with amplifiers not using the features of amplifier 100 or 200 . By reducing the size of the first inductor Lg and the second inductor Ls of amplifier 100 or amplifier 200 , the first inductor Lg and the second inductor Ls are located on a same chip as the other components (e.g., input node IN, transistor M 1 , resistor Rg, drain inductor Ld and output node OUT) in amplifier 100 or amplifier 200 . By reducing the size of the first inductor Lg and the second inductor Ls of amplifier 100 or amplifier 200 and amplifier 100 or 200 occupies less area than other amplifier designs (not utilizing the features of amplifier 100 or amplifier 200 ).

Amplifier 100 or amplifier 200 is configured to operate on a lower amount of power when compared with other amplifier's (not utilizing the features of amplifier 100 or amplifier 200 ). For example, by configuring amplifier 100 or amplifier 200 to operate in the sub-threshold region and the near-triode region, amplifier 100 or amplifier 200 is configured to operate with a lower DC power supply level (P DC ), a lower supply voltage source (e.g., second supply voltage source V DD ), or a lower noise figure (NF) and a larger Figure of Merit (FoM). In some embodiments, amplifier 100 or amplifier 200 is manufactured using 16 nanometer (nm) or larger complementary MOS (CMOS) technology. In some embodiments, the area of amplifier 100 or amplifier 200 is smaller when compared with other amplifier's (not utilizing the features of amplifier 100 or amplifier 200 ). In some embodiments, by using a single transistor M 1 , amplifier 100 or amplifier 200 occupies less area and consumes less power than other amplifier designs using more than one transistor.

FIG. 3 is a flowchart of a method 300 of operating amplifier 100 or amplifier 200 , in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method 300 depicted in FIG. 3 , and that some other processes may only be briefly described herein.

Method 300 begins with operation 302 , where a first signal (e.g., signal Sin ( FIG. 1 )) is received from a source (not shown). In some embodiments, the source of first signal is an RF source (not shown).

Method 300 continues with operation 304 , where a first voltage (e.g., voltage of gate terminal Vgs) is supplied to a first terminal of a transistor (e.g., gate terminal of transistor M 1 ) thereby operating the transistor (e.g., transistor M 1 ) in a sub-threshold region. In some embodiments, the supplying the first voltage (e.g., voltage of gate terminal Vgs) to the first terminal of the transistor (e.g., gate terminal of transistor M 1 ) of operation 304 thereby operating the transistor (e.g., transistor M 1 ) in a sub-threshold region comprises the first voltage (e.g., voltage of gate terminal Vgs) being less than a threshold voltage of the transistor (e.g., threshold voltage Vth of transistor M 1 ).

Method 300 continues with operation 306 , where a second voltage (e.g., voltage V DD ) is supplied to a second terminal of the transistor (e.g., drain terminal of transistor M 1 ) thereby operating the transistor (e.g., transistor M 1 ) in a near-triode region. In some embodiments, the supplying the second voltage (e.g., voltage V DD ) to the second terminal of the transistor (e.g., drain terminal of transistor M 1 ) of operation 306 thereby operating the transistor (e.g., transistor M 1 ) in a near-triode region comprises a voltage (e.g., voltage Vds) between the second terminal of the transistor (e.g., drain terminal of transistor M 1 ) and the third terminal of the transistor (e.g., source terminal of transistor M 1 ) being proportional to a current (e.g., current Ids) flowing through the second terminal of the transistor (e.g., drain terminal of transistor M 1 ) and the third terminal of the transistor (e.g., source terminal of transistor M 1 ).

Method 300 continues with operation 308 , where an input impedance (e.g., input impedance Zin) of the transistor (e.g., transistor M 1 ) is matched to an output impedance (e.g., output impedance Zout) of the source (not shown). In some embodiments, the matching of the input impedance of the transistor to the output impedance of the source of operation 308 comprises inductively coupling a first inductor (e.g., first inductor Lg ( FIG. 1 )) coupled to the first terminal of the transistor (e.g., gate terminal of transistor M 1 ) to a second inductor (e.g., second inductor Ls) coupled to the third terminal (e.g., source terminal of transistor M 1 ).

Method 300 continues with operation 310 , where an amplified first signal (e.g., signal Sout ( FIG. 1 )) is output responsive to the first signal (e.g., signal Sin). In some embodiments, the outputting of the amplified first signal (e.g., signal Sout) responsive to the first signal of operation 310 comprises passing the amplified first signal (e.g., signal Sout) through an output capacitor (e.g., output capacitor Cout) and blocking the second voltage (e.g., voltage V DD ) by the output capacitor (e.g., output capacitor Cout).

FIG. 4 is a schematic drawing of different voltage levels of an amplifier usable in FIG. 1 , in accordance with some embodiments.

Schematic drawing 400 includes a horizontal axis and a vertical axis. As shown in FIG. 4 , the horizontal axis shows a range of voltages V G provided to a gate of a transistor (e.g., transistor M 1 , FIG. 1 ). As shown in FIG. 4 , the vertical axis shows a range of transistor efficiencies (e.g., normalized trans-conductance g m /P DC ) achieved for different drain voltage levels V D provided to the transistor (e.g., transistor M 1 , FIG. 1 ).

In some embodiments, for a sub-threshold operation of a transistor (e.g., transistor M 1 , FIG. 1 ) having a voltage level V D substantially equal to 0.8 volts (shown as curve 402 ), as the voltage V G is reduced, the efficiency of the transistor is increased. For example, for a sub-threshold operation of a transistor having a voltage level V D substantially equal to 0.8 volts (shown as curve 402 ), and a voltage V G substantially equal to 0.8 volts, yields a transistor with an efficiency substantially equal to 1. For example, for a sub-threshold operation of a transistor having a voltage level V D substantially equal to 0.8 volts (shown as curve 402 ), and a voltage V G equal to 0.3 volts, yields a transistor with an efficiency substantially equal to 6. For example, for a sub-threshold operation of a transistor having a voltage level V D substantially equal to 0.8 volts (shown as curve 402 ), and a voltage V G equal to 0.15 volts, yields a transistor with an efficiency substantially equal to 12.

In some embodiments, for a near-triode operation of a transistor (e.g., transistor M 1 , FIG. 1 ) having a voltage level V G substantially equal to 0.15 volts (intersecting curve 404 ), as the voltage level V D is reduced, the efficiency of the transistor is increased. For example, for a near-triode operation of a transistor having a voltage level V G substantially equal to 0.15 volts (intersecting curve 404 ), and a voltage V D substantially equal to 0.8 volts, yields a transistor with an efficiency substantially equal to 12. For example, for a near-triode operation of a transistor having a voltage level V G substantially equal to 0.15 volts (intersecting curve 404 ), and a voltage V D substantially equal to 0.2 volts, yields a transistor with an efficiency substantially equal to 50. For example, for a near-triode operation of a transistor having a voltage level V G substantially equal to 0.15 volts (intersecting curve 404 ), and a voltage V D substantially equal to 0.1 volts, yields a transistor with an efficiency substantially equal to 100.

FIG. 5 is a schematic drawing of a coupling coefficient of a transformer usable in FIG. 1 , in accordance with some embodiments.

Schematic drawing 500 includes a horizontal axis and a vertical axis. As shown in FIG. 5 , the horizontal axis shows a range of coupling coefficients k for a transformer (e.g., transformer 102 ). As shown in FIG. 5 , the vertical axis shows a normalized inductance (%) range of the first inductor Lg and corresponding second inductor Ls of the transformer (e.g., transformer 102 , shown in FIG. 1 ) achieved by using amplifier 100 . The range of normalized inductances (%) of the first inductor Lg and the corresponding second inductor Ls is varied over a range of coupling coefficients k. The coupling coefficient k ranges from about 0 to about 1. As shown in FIG. 5 , as the coupling coefficient k increases, the normalized inductance of the first inductor Lg or the normalized inductance of the second inductor Ls decreases. For example, at a coupling coefficient k value of 0.8, shown as 502 , the normalized inductance of the first inductor Lg is reduced by 25%. For example, at a coupling coefficient k value of 0.8, shown as 504 , the normalized inductance of the second inductor Ls is reduced by 75%.

One aspect of this description relates to an amplifier. The amplifier includes an input node, an output node, a transistor and a transformer. The input node is configured to receive a first signal. The output node is configured to output an amplified first signal. The transistor includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the input node and a first supply voltage source. The second terminal is coupled to a second supply voltage source and the output node. The third terminal is coupled to a reference node. The transformer is coupled to the first terminal and the third terminal. The transistor is configured to operate in a sub-threshold region and a near-triode region.

Another aspect of this description relates to an amplifier. The amplifier includes an input node, an output node, a transformer and a transistor. The input node is configured to receive a first signal. The output node is configured to output an amplified first signal. The transformer has a first portion and a second portion. The first portion being inductively coupled to the second portion. The first portion being coupled to the input node and a first supply voltage source The second portion being coupled to a reference node. The transistor comprising a gate terminal coupled to the first portion of the transformer; a drain terminal coupled to the second supply voltage source and the output node; and a source terminal coupled to the second portion of the transformer. The transistor is configured to operate in a sub-threshold region and a near-triode region.

Still another aspect of this description relates to operating an amplifier. The method includes receiving a first signal from a first source; supplying a first voltage to a first terminal of a transistor thereby operating the transistor in a sub-threshold region; supplying a second voltage to a second terminal of the transistor thereby operating the transistor in a near-triode region; matching an input impedance of the transistor to an output impedance of the first source; and outputting an amplified first signal responsive to the first signal.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.