Power converter including an autotransformer and power conversion method

This disclosure in general relates to a power converter and a power conversion method.

Power conversion is an important issue in today's power supply systems. DC/AC power conversion is one type of power conversion which involves converting DC power into AC power. The DC power is provided by a DC power source such as, for example, photovoltaic (PV) panels, batteries or the like. The AC power may be fed into a power grid or used to drive a motor, to name only two examples.

An important aspect in every type of power conversion is to efficiently convert the power, that is, to keep losses that may occur in connection with the power conversion as low as possible.

One example relates to a power converter circuit. The power converter circuit includes a chopper circuit configured to receive an input voltage and generate a chopper voltage with an alternating voltage level based on the input voltage, an autotransformer with at least one tap, wherein the autotransformer is coupled to the chopper circuit and configured to generate a tap voltage at the at least one tap, and a selector circuit configured to receive a plurality of voltage levels. At least one of the voltage levels is based on the at least one tap voltage, and the selector circuit is configured to generate a selector output voltage based on the plurality of voltage levels such that the selector circuit selects two of the plurality of voltage levels and switches at a switching frequency between the two voltage levels.

One example relates to a method. The method includes receiving an input voltage and generating a chopper voltage with an alternating voltage level based on the input voltage by a chopper circuit, generating a tap voltage at the at least one tap by an autotransformer coupled to the chopper circuit, receiving a plurality of voltage levels by a selector circuit, wherein at least one of the voltage levels is based on the at least one tap voltage, and generating a selector output voltage based on the plurality of voltage levels by the selector circuit such that a voltage level of the selector output voltage alternates at a switching frequency between two selected ones of the plurality of voltage levels.

Another example relates to a power converter circuit. The power converter circuit includes a chopper circuit configured to receive an input voltage and generate a chopper voltage with an alternating voltage level based on the input voltage and with a chopper frequency, an autotransformer comprising at least one tap, wherein the autotransformer is coupled to the chopper circuit and configured to generate a tap voltage at the at least one tap, and a selector circuit configured to receive a plurality of voltage levels, wherein at least one of the voltage levels is based on the at least one tap voltage. The selector circuit is configured to generate a selector output voltage based on the plurality of voltage levels. The power converter circuit includes at least one series resonant circuit excited by the chopper voltage, wherein parameters of the at least one series resonant circuit are adapted to the chopper frequency such that the chopper frequency substantially equals a resonant frequency of the at least one series resonant circuit.

Yet another example relates to a method. The method includes receiving an input voltage and generating a chopper voltage with an alternating voltage level based on the input voltage and with a chopper frequency by a chopper circuit, receiving the chopper voltage and generating at least one tap voltage based on the chopper voltage by an autotransformer, and receiving a plurality of voltage levels by a selector circuit, wherein at least one of the voltage levels is based on the at least one tap voltage, and generating a selector output voltage based on the plurality of voltage levels by the selector circuit. The chopper frequency substantially equals a resonant frequency of at least one series resonant circuit that includes a parasitic inductance of the autotransformer.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features.

FIG. 1 shows one example of a power converter circuit that includes a chopper circuit, an autotransformer circuit, a rectifier circuit, and a selector circuit;

FIGS. 2A-2C show examples of timing diagrams of an input voltage, a chopper output voltage and a selector output voltage in the power converter circuit shown in FIG. 1 ;

FIGS. 3A and 3B show examples of timing diagrams of an output voltage of the rectifier circuit in the power converter circuit shown in FIG. 1 ;

FIG. 4 shows examples of the chopper circuit, the autotransformer circuit, the rectifier circuit, and the selector circuit in greater detail;

FIG. 5 shows timing diagrams of the drive signals of a half-bridge included in the chopper circuit shown in FIG. 4 ;

FIG. 6 shows one example of a controller in the selector circuit shown in FIG. 5 ;

FIG. 7 shows examples of timing diagrams of signals in the controller circuit shown in FIG. 6 ;

FIG. 8 shows one example of a rectifier stage in the rectifier circuit shown in FIG. 5 ;

FIG. 9 illustrates one example of a timing diagram of a tap voltage received at an input of the rectifier stage shown in FIG. 8 ;

FIG. 10 shows one example of a power converter circuit that is based on the power converter circuit shown in FIG. 5 and includes an optional filter circuit, which is illustrated in greater detail;

FIG. 11 shows timing diagrams that illustrate one way of operation of an unfolding circuit in the filter circuit shown in FIG. 10 ;

FIGS. 12-14B show timing diagrams of signals occurring in the power converter circuit shown in FIG. 10 ;

FIGS. 15A and 15B illustrate one method for determining parasitic inductances of an autotransformer;

FIGS. 16A-16C illustrate how the method shown in FIG. 15 may be applied to the autotransformer shown in FIG. 10 ;

FIG. 17 show a rectifier circuit and a selector circuit according to another example;

FIG. 18 show a chopper circuit, an autotransformer circuit and a rectifier circuit according to another example;

FIG. 19 show a chopper circuit and an autotransformer circuit according to another example;

FIG. 20 show a chopper circuit and an autotransformer circuit according to yet another example;

FIG. 21 shows a power converter circuit according to another example; and

FIG. 22 shows timing diagrams of a selector output voltage and a power converter output voltage of the power converter circuit shown in FIG. 21 .

In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and by way of illustration show specific embodiments in which the invention may be practiced. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

FIG. 1 shows one example of a power converter circuit configured to convert an input power P IN received at an input 11 , 12 into an output power pour provided at an output 13 , 14 . The input power P IN is defined as the product of an input current I IN received at the input 11 , 12 and an input voltage V IN between a first input node 11 and a second input node 12 of the input, so that P IN =V IN ·I IN . The output power pour is defined as the product of an output current i OUT provided at the output 13 , 14 and an output voltage v OUT between a first output node 13 and a second output node 14 of the output, so that p OUT =v OUT ·i OUT . A load Z (illustrated in dashed lines in FIG. 1 ) may receive the output power pour supplied by the power converter circuit.

According to one example, the input power P IN is a DC (Direct Current) power, that is, the input voltage V IN is a direct voltage and the input current I IN is a direct current. According to one example, the power converter circuit is configured to convert the DC power received at the input 11 , 12 into an AC (Alternating Current) power at the output 13 , 14 , so that the output current i OUT is an alternating current and the output voltage v OUT is an alternating voltage. According to one example, the load Z is a power grid. In this example, the waveform of the output voltage v OUT is defined by the load Z and the power converter circuit may generate the output current i OUT to be in phase with or to have a predefined phase difference relative to the output voltage v OUT . According to another example, the load Z is a motor that is driven by the output power pour. In this case, the power converter circuit defines the waveform of the output voltage v OUT . The DC power received at the input 11 , 12 may be provided by a conventional DC power source (not shown in the drawings) such as a photovoltaic (PV) panel, a battery arrangement, a fuel cell arrangement, or the like.

In the following, capital letters such as V and I are used to denote direct currents, direct voltages and average levels (mean levels) of alternating currents and voltages, respectively. Lowercase letters such as v and i are used to denote alternating voltages and alternating currents.

Referring to FIG. 1 , the power converter circuit includes a chopper circuit 2 . The chopper circuit is configured to receive the input voltage V IN and generate based on the input voltage V IN a chopper voltage v 2 with an alternating varying signal level. An autotransformer circuit 3 that includes an autotransformer 31 receives the chopper voltage v 2 and is configured to generate at least one tap voltage v 3 1 , v 3 2 based on the chopper voltage v 2 . Examples of how the autotransformer circuit 3 may generate the at least one tap voltage v 3 1 , v 3 2 from the chopper voltage v 2 are explained in greater detail herein below. A rectifier circuit 4 receives the at least one tap voltage v 3 1 , v 3 2 from the autotransformer circuit 3 and is configured to generate at least one intermediate voltage V 4 1 , V 4 2 from the at least one tap voltage v 3 1 , v 3 2 . The at least one intermediate voltage V 4 1 , V 4 2 is also referred to as DC link voltage in the following.

According to one example, as shown in FIG. 1 , the autotransformer circuit 31 provides a plurality of tap voltages v 3 1 , v 3 2 . Just for the purpose of illustration, the plurality of tap voltages v 3 1 , v 3 2 includes two voltages v 3 1 , v 3 2 in the example shown in FIG. 1 , wherein each of these tap voltages v 3 1 , v 3 2 is available at one tap 32 1 , 32 2 of the autotransformer 32 . This, however, is only an example, autotransformer circuit 3 can be implemented with an arbitrary number of taps, so that an arbitrary number of tap voltages a can be generated. Each tap 32 1 , 32 2 of the autotransformer circuit 3 is a circuit node between two respective windings 31 1 , 31 2 , 31 n of the autotransformer 31 . These windings 31 1 , 31 2 , 31 n are connected in series and inductively coupled. According to one example, each DC link voltage V 4 1 , V 4 2 is generated from one tap voltage v 3 1 , v 3 2 so that the number of tap voltages equals the number of DC link voltages V 4 1 , V 4 2 .

Referring to FIG. 1 , a selector circuit 5 receives the at least one DC link voltage V 4 1 , V 4 2 and generates a selector output voltage v 5 based on the at least one DC link voltage V 4 1 , V 4 2 . Optionally, the selector circuit 5 further receives the input voltage V IN in order to generate the selector output voltage v 5 based on the at least one DC link voltage V 4 1 , V 4 2 and the input voltage V IN . According to one example, the selector output voltage v 5 is the output voltage v OUT of the power converter circuit. According to another example, the output voltage v OUT is generated from the selector output voltage v 5 by a filter circuit 6 connected between the selector circuit 5 and the output 13 , 14 . According to yet another example, a series voltage regulator generates the output voltage v OUT based on the selector output voltage v 5 .

FIGS. 2A-2C show examples of timing diagrams of some of the signals that occur in a power converter circuit of the type shown in FIG. 1 during its operation. FIG. 2A shows a timing diagram of the input voltage V IN , FIG. 2B shows a timing diagram of the chopper voltage v 2 , and FIG. 2C shows timing diagrams of the selector output voltage v 5 and the output voltage v OUT . In the example shown in FIG. 2A , the input voltage V IN is a direct voltage with a voltage level V IN0 . Referring to FIG. 2B , the chopper circuit 2 may generate the chopper voltage v 2 to be a square-wave voltage based on the input voltage V IN . According to one example, the chopper voltage v 2 is a periodic voltage that periodically changes its signal level between V 2 +v 2 ′ and V 2 −v 2 ′, where V 2 denotes a mean of the chopper voltage v 2 and v 2 ′ denotes the amplitude. In FIG. 2B , T 2 denotes one period of the chopper voltage v 2 and f 2 =1/T 2 denotes the frequency of the chopper voltage v 2 . In every period of the chopper voltage v 2 , there is a time period, when the chopper voltage v 2 has the lower level V 2 −v 2 ′ and a time period, when the chopper voltage v 2 has the higher level V 2 +v 2 ′. According to one example, these time durations are equal, that is, the chopper voltage v 2 has the low level V 2 −v 2 ′ 50% of the period T 2 , and the high level V 2 +v 2 ′ 50% of the time period T 2 .

The selector circuit 5 may generate the output voltage v OUT . Alternatively, the selector circuit 5 generates a voltage based on which the optional filter 6 generates the output voltage your. FIG. 2C illustrates an example of how the selector circuit 5 may generate the selector output voltage based on two DC link voltages V 4 1 , V 4 2 and the input voltage V IN . FIG. 2C furthermore shows the waveform of an output voltage obtained by low-pass filtering the selector output voltage v 5 . In the example shown in FIG. 2C , the selector output voltage can have four different voltage levels which are selected from 0 (zero), the two tap voltages V 4 1 , V 4 2 , and the input voltage level V IN0 . Just for the purpose of explanation, the individual voltage levels are drawn such that V 4 1 =⅓·V IN0 and V 4 2 =⅔·V IN0 . In this case, voltage differences between neighboring voltage levels are equal, namely ⅓·V IN0 . This, however, is only an example. The voltage levels of the DC link voltages V 4 1 , V 4 2 could also be generated such that voltage differences between neighboring voltage levels are not equal.

The selector circuit 5 generates the selector output voltage v 5 such that at each time a voltage level of the selector output voltage v 5 equals one of the different voltage levels 0 , V 4 1 , V 4 2 , VIN 0 the selector circuit 5 receives. Referring to the above, the output voltage v OUT may be generated from the selector output voltage v 5 by low-pass filtering. If, for example, a desired (instantaneous) voltage level of the output voltage v OUT equals one of the voltage levels received by the selector circuit 5 , the selector circuit 5 may simply pass through the respective voltage level to its output. If, however, a desired (instantaneous) voltage level of the Output voltage v OUT is between two neighboring (consecutive) voltage levels received by the selector circuit 5 , the selector circuit may approximate the output voltage v OUT by switching between two neighboring DC voltage levels in accordance with a switching frequency. The output voltage v OUT is then the result of low-pass filtering the selector output voltage v 5 , wherein the low-pass filter may be implemented such that its cutoff frequency is below the switching frequency of the selector circuit 5 , but higher than a maximum frequency of the output voltage v OUT . In the example shown in FIG. 1 , the output voltage is a sinusoidal voltage (or a rectified sinusoidal voltage), respectively, wherein only one half-period (or one period) is shown. The frequency of such sinusoidal voltage is much lower such as less than 1/100, less than 1/1000, or even less than 1/10000 of the switching frequency of the selector circuit 5 . In the example shown in FIG. 2C , the selector circuit 5 only switches between consecutive voltage levels. This, however, is only an example. The selector circuit 5 may also switch between voltage levels that are not consecutive. That is, for example, the selector circuit 5 may switch between 0 and voltage level V 4 2 wherein 0 and V 4 2 are not consecutive voltage levels as there is another voltage level, V 4 1 , between 0 and V 4 2 .

According to one example, the selector circuit 5 operates in accordance with a modulation index m. The modulation index m is defined by a ratio between an instantaneous voltage level of the output voltage v OUT and the maximum DC link voltage, wherein the input voltage V IN is also regarded as one of the DC link voltages in this example. In the example shown in FIG. 2C , the maximum DC link voltage is the input voltage V IN0 . In the example shown in FIG. 2C , the modulation index m=1 if the instantaneous voltage level of the output voltage v OUT equals the input voltage V IN0 , m=0, if the output voltage v OUT is zero and m=⅓ if v OUT =V 4 1 , for example.

Referring to FIG. 2C , the DC link voltages V 4 1 , V 4 2 and the input voltage V IN define a plurality of consecutive voltage levels, with each pair of consecutive voltage levels defining a voltage interval. In the example shown in FIG. 2C , these voltage intervals are between 0 and V 4 1 , between V 4 , and V 4 2 and between V 4 2 and V IN . The selector output voltage v 5 is generated such that the selector circuit 5 at a switching frequency f 4 (which is explained below) switches between two of the voltage levels. According to one example, the selector circuit 5 is configured such that it only switches between voltage levels of one interval, wherein the choice of the interval is dependent on the desired voltage level of the output voltage. In the latter case, the maximum voltage swing at one time is given by the voltage defining one interval (only when the selector circuit 5 switches from a first interval to a second interval the swing may be higher, namely the sum of the voltages that define the first interval and the second interval. The “voltage defining an interval” is the voltage between the two voltage levels that define (border) the interval.

FIGS. 3A and 3B show two different examples of how the selector circuit 5 may approximate a certain instantaneous level of the output voltage v OUT based on two neighboring DC link voltages. These DC link voltages are denoted as V 4 1 and V 4 i+1 in FIGS. 3A and 3B . These DC link voltages V 4 i , V 4 i+1 may represent any two neighboring DC link voltages shown in FIG. 2C , wherein V IN0 is also referred to as V 4 n and zero (0) is also referred to as V 4 0 in FIG. 2C . Referring to FIGS. 3A and 3B , the selector circuit 5 operates at a switching frequency f 4 , so that there is a plurality of successive operation cycles each having a duration T 4 =1/f 4 . The switching frequency f 4 of the selector circuit 5 can be higher than, lower than or equal the frequency of the chopper voltage f 2 . According to one example, each of these frequencies f 2 and f 4 is selected from between several kilohertz (kHz) and several megahertz (MHz), in particular between 10 kHz and 1 MHz.

If the desired instantaneous voltage level of the output voltage v OUT is between the neighboring DC link voltages V 4 i , V 4 i+1 in each of the plurality of successive operation cycles there is a time period T 4 i when the lower one V 4 i of the two neighboring DC link voltages V 4 i , V i+1 is output by the selector circuit 5 , and a time period T 4 i+1 when the higher one V 4 i+1 of the two neighboring DC link voltages V 4 i , V 4 i+1 is output by the selector circuit 5 . A ratio between T 4 i+1 and T 4 i is dependent on the relationship between the instantaneous level of the input voltage v OUT and the two DC link voltages V 4 i , V 4 i+1 . FIG. 3A shows an example in which the output voltage v OUT is closer to the higher DC link voltage V 4 i+1 so that T 4 i+1 is longer than T 4 i . FIG. 3B shows an example in which the output voltage v OUT is closer to V 4 i so that T 4 i is longer than T 4 i+1 . In general, a relationship between T 4 i+1 and T 4 can be expressed as

T ⁢ ⁢ 4 i + 1 T ⁢ ⁢ 4 = a ,

⁢ if ⁢ ⁢ v OUT = V ⁢ ⁢ 4 i + ( V ⁢ ⁢ 4 i + 1 - V ⁢ ⁢ 4 i ) · a , ( 1 ⁢ a )

and T 4 i is given by

T 4 i =T 4− T 4 i+   (1b).

In general, if v OUT =m·V IN0 , whereas m is the modulation index, and if V 4 i ≤v OUT ≤V 4 i+1 “a” can also be expressed as

a = m - m i m i + 1 - m i , ( 2 )

wherein m i =V 4 i /V IN0 and m i+1 =V 4 i+1 /V IN0 .

FIG. 4 shows one example of a power converter circuit of the type shown in FIG. 1 in greater detail. In this example, the chopper circuit 2 includes a half-bridge with a high-side switch 21 H and a low-side switch 21 L . The high-side switch 21 H and the low-side switch 21 L are connected in series between the first input node 11 and the second input node 12 . A capacitor 22 , which is referred to as chopper capacitor 22 in the following, is connected between a tap of the half-bridge and an output 24 of the chopper circuit 2 . The “tap” of the half-bridge is a circuit node common to the high-side switch 21 H and the low-side switch 21 L . The chopper voltage v 2 is available between the output 24 of the chopper circuit 2 and a reference node, which is the second input node 12 in this example. Optionally, an input capacitor 23 is connected between the first input node 11 and the second input node 12 , respectively. The high-side switch 21 H and the low-side switch 21 L switch on and off in accordance with a respective drive signal S 21 H , S 21 L generated by a drive circuit 25 . The drive circuit 25 switches on and off the high-side switch 21 H and the low-side switch 21 L alternately so that only one of the high-side switch 21 H and the low-side switch 21 L is switched on at the same time. The drive circuit 25 operates the high-side switch 21 H and the low-side switch 21 L in accordance with the desired frequency f 2 of the chopper voltage v 2 , explained with reference to FIG. 2B . According to one example, the drive circuit 25 operates the high-side switch 21 H and the low-side switch 21 L at 50% duty-cycle. That is, each of the high-side switch 21 H and the low-side switch 21 L is switched on 50% of one period T 2 . This is explained with reference to FIG. 5 below.

FIG. 5 shows examples of timing diagrams of the drive signals S 21 H , S 21 L of the high-side switch 21 H and the low-side switch 21 L . Referring to FIG. 5 , each of these drive signals S 21 H , S 21 L can have an on-level that switches on the respective switch and an off-level that switches off the respective switch. Just for the purpose of explanation, the on-level is a high signal level and the off-level is a low signal level in the example shown in FIG. 5 . In the following, an on-period of the respective drive signal S 21 H , S 21 L is a time period in which the respective drive signal S 21 H , S 21 L has an on-level, and an off-period is a time period in which the respective drive signal S 21 H , S 21 L has an off-level. Referring to FIG. 5 , on-periods of the two drive signals S 21 H , S 21 L do not overlap, so that only one of the high-side switch 21 H and the low-side switch 21 L is switched on at the same time. According to one example (not shown in FIG. 5 ), there is a dead time between the time when one of the high-side switch 21 H and the low-side switch 21 L switches off and the time when the other one of the high-side switch 21 H and the low-side switch 21 L switches on. This may serve to safely prevent a cross current in the half-bridge. Referring to FIG. 5 , a duration of the on-periods of each of the drive signals S 21 H and 21 L drive signal S 21 L is T 4 /2. That is, each of the high-side switch 21 H and the low-side switch S 1 L is operated at a duty-cycle of 50% (the duty-cycle is the ratio between the on-period and the overall period T 4 of one drive cycle).

A chopper circuit 2 as explained with reference to FIGS. 4 and 5 , generates a chopper voltage v 2 that has a timing diagram as shown in FIG. 2B in which the average value (mean value) is zero, that is, V 2 =0 and in which the amplitude v 2 ′ is half the voltage level of the input voltage V IN , that is, v 2 ′=V IN0 /2. Thus, in the chopper circuit 2 shown in FIG. 4 , the chopper voltage v 2 alternates between +V IN0 /2 and −V IN0 /2 at a frequency of f 2 , wherein in each period of the chopper voltage, the lower voltage level −V IN0 prevails half of the time period T 4 , and the upper level +V IN0 prevails half of the time period T 4 .

In the power converter circuit shown in FIG. 4 , the autotransformer 31 receives the chopper voltage v 2 . That is, the autotransformer 31 is coupled to the output 24 of the chopper circuit 2 such that the chopper voltage v 2 is applied to the autotransformer 31 , which includes a series circuit with a plurality of windings 31 1 , 31 2 , 31 n that are inductively couples. Just for the purpose of illustration, the autotransformer 31 shown in FIG. 4 includes n=3 windings and n−1=2 taps 32 1 , 32 2 . At each of the taps 32 1 , 32 2 one tap voltage v 3 1 , v 3 2 is available. Each tap voltage v 3 1 , v 3 2 is substantially proportional to the chopper voltage v 2 received by the autotransformer 31 , wherein a proportionality factor between one tap voltage and the chopper voltage v 2 is dependent on the number of turns of the individual windings 31 1 , 31 2 , 31 n . A first tap voltage v 3 1 , for example, is the voltage across a first winding 31 1 . This first tap voltage v 3 1 is given by

v ⁢ ⁢ 3 1 = N 1 N tot · v ⁢ ⁢ 2 , ( 3 )

where N 1 is the number of turns of the first winding 31 1 and N tot is the overall number of windings of the autotransformer 31 . In the example shown in FIG. 4 , wherein the autotransformer 31 includes the three windings 31 1 , 31 2 , 31 n ,

N tot =N 1 +N 2 +N n   (4),

where N 2 is the number of turns of a second winding 31 2 and N n is the number of turns of an n-th (the third in this example) winding 31 n . In the example shown in FIG. 4 , a second tap voltage v 3 2 , which is the voltage between the second tap 32 2 and the reference node (the second input node in this example) is the voltage across the first winding 31 1 and the second winding 31 2 , so that the second tap voltage v 3 2 is given by

v ⁢ ⁢ 3 2 = N 2 + N 1 N TOT · v ⁢ ⁢ 2. ( 5 )

According to one example, the individual windings 31 1 , 31 2 , 31 n have the same number of turns, that is, N 1 =N 2 =N n . In this case, v 3 1 =⅓·v 2 and v 3 2 =⅔·v 2 . In general, if the autotransformer 31 includes an arbitrary number of n windings that each have the same number of turns, n−1 different tap voltages v 3 k can be obtained, wherein each of these tap voltages is given by

v ⁢ ⁢ 3 k = k n · v ⁢ ⁢ 2 , ( 6 )

wherein k is selected from between 0 and n−1.

In the example shown in FIG. 4 , the rectifier circuit 4 includes several rectifier stages in this example) 4 1 , 4 2 , with each of these rectifier stages 4 1 , 4 2 receiving one of the tap voltages v 3 1 , v 3 2 and being configured to generate one of the DC link voltages V 4 1 , V 4 2 based on the respective tap voltage v 3 1 , v 3 2 .

Referring to FIG. 4 , the selector circuit 5 , besides the DC link voltages V 4 1 , V 4 2 receives the input voltage V IN and includes a plurality of switches 51 0 - 51 n , wherein each of these switches is configured to connect one of the plurality of voltages received by the selector circuit 5 to an output 52 of the selector circuit 5 . The voltages (voltage levels) received by the selector circuit 5 shown in FIG. 4 are the DC link voltages V 4 1 , V 4 2 output by the rectifier stages 4 1 , 4 2 and the input voltage V IN . In this example, each of switches 51 1 , 51 2 shown in FIG. 4 serves to connect one of the DC link voltages V 4 1 , V 4 2 to the output 52 , and a switch 51 , serves to connect the input voltage V IN to the output 52 . Additionally, the selector circuit 5 includes a switch 51 0 coupled between the output 52 and the second input node 12 , which serves as the reference node in the power converter circuit shown in FIG. 4 , whereas the output voltage v 5 is zero if tis switch 51 0 is switched on. The individual switches 51 0 - 51 n are driven by drive signals S 51 0 -S 51 n generated by a control circuit 52 . According to one example, the control circuit 52 is configured to generate the drive signals S 51 0 -S 51 n such that only one of the switches 51 0 - 51 n is switched on at the same time.

One example of the control circuit 52 is explained with reference to FIG. 6 . FIG. 6 shows a block diagram of one example of the control circuit 52 that controls operation of the selector circuit 5 and, therefore, controls the selector output voltage v 5 . The control circuit 52 shown in FIG. 6 generates the selector output voltage v 5 such that the input voltage V IN is regulated and the output current v OUT (see FIG. 1 ) has a predefined signal waveform. This control circuit 52 receives an input voltage signal S VIN that represents the input voltage V IN . This input voltage signal S VIN can be obtained by any kind of voltage measurement circuit, which is not shown in the drawings. An error filter 521 receives the input voltage signal S VIN and compares the input voltage signal S VIN with an input voltage reference signal S VIN-REF . This input voltage reference signal S VIN-REF represents a desired voltage level of the input voltage V IN . The error filter 521 calculates a difference between the input voltage signal S VIN and the input voltage reference signal S VIN-REF and generates an input voltage error signal S VIN-ERR based on this difference. According to one example, the input voltage error signal S VIN-ERR is obtained by filtering this difference using one of an integral (I) filter, a proportional-integral (PI) filter, a proportional-integral-derivative (PID) filter, or the like. A multiplier 522 receives the input voltage reference signal S VIN-ERR and a signal representing a desired waveform of the output current I OUT .

According to one example, the power converter circuit supplies the output current i OUT to a power grid, so that the output voltage v OUT is defined by the power grid, and it is desired to generate the output current i OUT to be in phase with the output voltage v OUT or have a predefined phase difference relative to the output voltage v OUT . In each case, the desired waveform of the output current i OUT is given by the output voltage your. The signal defining the desired waveform of the output current i OUT is an output voltage signal S vOUT in this example. The output voltage signal S vOUT can be obtained by measuring the output voltage V OUT using any kind of current measurement circuit (not shown in the figures). By multiplying the output voltage signal S vOUT and the input voltage error signal S VIN-ERR , the multiplier 522 generates an output current reference signal S iOUT-REF which defines the desired output current i OUT . Based on this output current reference signal S iOUT-REF , the controller 52 generates an output current error signal S iOUT-ERR by subtracting an output current signal S iOUT , or a filtered version of this output current signal S iOUT , from the output current reference signal S iOUT-REF . An optional filter 524 that filters the output current signal S iOUT in order to obtain a filtered version of the output current signal S iOUT is a low-pass filter, for example. The output current signal S iOUT may be obtained by measuring the output current i OUT using any kind of current measurement circuit (not shown in the figures).

Referring to FIG. 6 , the output current error signal S iOUT-ERR is received by another filter 525 that generates the modulation index m from the output current error signal S iOUT-ERR . According to one example, the filter 525 has one of an integrating (I) characteristic, a proportional-integral (PI) characteristic, or a proportional-integral-derivative (PID) characteristic. A modulator 526 receives the modulation index in and generates the drive signals S 51 0 -S 51 n based on the modulation index m, in the way basically explained with reference to FIG. 2C herein before.

It can be shown that, in case the output voltage v OUT is a periodic voltage, the modulation index m is also a periodic signal, substantially with the same frequency as the output voltage v OUT . For the purpose of explanation, it is assumed that the output voltage v OUT is a rectified sine voltage with a frequency of 100 Hz or 120 Hz respectively. Based on such rectified sine voltage, a sine voltage with a frequency of 50 Hz or 60 Hz, respectively, can easily be generated by using an unfolding circuit explained herein further below.

FIG. 7 schematically illustrates the relationship between the output voltage v OUT and the modulation index m. As, referring to FIG. 6 , the output current reference signal S iOUT-REF is obtained by multiplying the output voltage signal S vOUT with the input voltage error signal S VIN-ERR , the output current reference signal S iOUT-REF is proportional to the output voltage v OUT (when assuming that the voltage level of the input voltage V IN does not change during the time period illustrated in FIG. 7 ). Referring to FIG. 7 , there may be a phase-shift Φ between the output current reference signal S iOUT-REF and the modulation index m. This phase difference Φ which is at most several degrees, may vary based on the difference between the output current reference signal S iOUT-REF and the filtered output current signal S iOUT . Further, it can be shown that an amplitude of the varying modulation index m is dependent on the amplitude of the input voltage V IN , so that the input voltage V IN can be regulated by suitably varying the modulation index m in the way explained with reference to FIG. 6 . According to one example, the filter 525 is configured to generate the modulation index m as a normalized signal with values of between 0 and 1, wherein the modulation index m is one in those cases in which the input voltage V IN is to be output as the selector voltage v 5 .

The control circuit 52 shown in FIG. 6 is only one example. This type of control may be used in a power converter that receives the input voltage V IN from a power source with a varying output power such as, for example, a PV panel. In this case, controlling the input voltage V IN to be constant is equivalent to adapting the input power P IN of the power converter circuit to the power supplied by the power source.

According to another example, the input voltage V IN is not regulated by the power converter circuit (because, for example, a regulator outside the power converter circuit regulates the input voltage V IN ). In this case, the error filter 521 and the multiplier 522 can be omitted. The subtractor 523 receives the signal defining the waveform of the output current instead of the output current reference signal S iOUT-REF , in this case. The signal defining the desired waveform of the output current i OUT is the output voltage signal S vOUT in the example shown in FIG. 6 .

According to another example, the waveform of the output voltage v OUT is not defined by an external source such as a voltage grid, but by the power converter circuit. One type of application where the power converter circuit generates the waveform of the output voltage v OUT is a motor drive application, where the load Z is a motor driven by the power converter circuit. In this case, a controller (not shown) generates a sequence of modulation indices (with each modulation index defining one instantaneous voltage level of the output voltage v OUT or the selector output voltage v 5 , respectively) such that the output voltage v OUT has a desired waveform and a desired frequency.

FIG. 8 shows one example of how the rectifier stages 4 1 , 4 2 in the power converter circuit shown in FIG. 4 may be implemented. In FIG. 8, 31 k denotes any of the windings 31 1 , 31 2 shown in FIG. 4, 32 k denotes the respective tap connected to the winding 31 k , 4 k denotes the respective rectifier stage, and V 4 k denotes the DC link voltage generated by the respective rectifier stage 4 k . Referring to FIG. 8 , the rectifier stage 4 k includes an output capacitor 43 k across which the DC link voltage V 4 k is available. Another capacitor 41 k , which is referred to as tap capacitor in the following, is connected to the tap 32 k . A first rectifier element 42 k , such as a diode, is connected between the tap capacitor 41 k and the output capacitor 43 k , and another rectifier element 44 k , such as a diode is connected between a circuit node common to the tap capacitor 41 k and the first rectifier element 42 k and the reference node (which is the second input node 12 in this example).

One way of operation of the rectifier stage 4 k shown in FIG. 8 is explained with reference to FIG. 9 that illustrates a timing diagram of the tap voltage v 3 k (which is the voltage between the tap 32 k and the reference node 12 ) during one period T 2 of the chopper circuit 2 . Referring to the above, the tap voltage v 3 k is proportional to the chopper voltage v 2 . As, referring to the above, the chopper voltage v 2 generated by the chopper circuit 2 shown in FIG. 4 is a zero-mean square voltage that varies between a negative signal level and a positive signal level the tap voltage v 3 k is also a zero-mean square voltage that varies between a negative signal level and a positive signal level. The negative signal level of the tap voltage v 3 k is referred to as −v 3 k ′ and the positive level is referred to as +v 3 k ′ in FIG. 9 . When the tap voltage v 3 k has the negative level, a voltage v 41 k across the tap capacitor 41 k substantially equals −v 3 k (if conduction losses in the rectifier element 44 k ) are neglected, so that a magnitude of the voltage v 41 equals the amplitude v 3 k ′ of the tap voltage v 3 k . When the tap voltage v 3 k becomes positive, the electrical potential at the tap 32 k rises to v 3 k ′, so that the output capacitor 43 k is charged via the first rectifier element 42 k by the charge stored in the tap capacitor 41 k . In this rectifier stage 4 k , the output capacitor V 4 k is charged to 2·v 3 k ′, which is twice the amplitude of the tap voltage v 3 k . Consequently, in the power converter circuit shown in FIG. 4 , the DC link voltages V 4 1 , V 4 2 are given by

FIG. 10 shows a power converter circuit with a chopper circuit 2 , an autotransformer circuit 3 , a rectifier circuit 4 and a selector circuit 5 of the type shown in FIG. 4 . In the power converter circuit shown in FIG. 10 , the rectifier stages 4 1 , 4 2 of the rectifier circuit 4 are implemented as explained with reference to FIG. 8 and drawn in detail in FIG. 10 . In the chopper circuit 2 , the high-side switch 21 H and the low-side switch 21 L are each implemented as a MOSFET, in particular as an n-type MOSFET. This however, is only an example, other types of electronic switches such as IGBTs (Insulated Gate Bipolar Transistors), IFETs (Junction Field Effect Transistors), Brfs (Bipolar Junction Transistors) or HEMTs (High Electron-Mobility Transistors) may be used as well. In FIG. 10 , a diode that is drawn to be connected between a drain node D and a source node S of the respective MOSFET 21 H , 21 L represents an internal body diode of the respective MOSFET 21 H , 21 L and/or an external diode connected in parallel with the drain-source path of the MOSFET.

In the example shown in FIG. 10 , the switch 51 0 that is connected between the output 52 of the selector circuit 5 and the reference node 12 is also implemented as a MOSFET, in particular an n-type MOSFET. This however, is only an example. Another type of electronic switch such as an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Field Effect Transistors), a BJT (Bipolar Junction Transistor) or a HEMT (High Electron-Mobility Transistors) may be used as well. The other switches 51 1 , 51 2 , 51 n of the selector circuit may each include two MOSFETs that are connected in series such that internal body diodes (which are also illustrated in FIG. 10 ) of these MOSFETs are connected back to back. In the example shown in FIG. 10 , the MOSFETs that are connected in series have the same type, which is an n-type in this example. The two MOSFETs forming one switch may receive the same drive signal. That is, for example, the MOSFETs forming switch 51 1 each receive the drive signal S 51 1 generated by the control circuit 52 . According to another example, the two MOSFETs of one switch are driven based on the same drive signal, but in accordance with a modulation scheme such as, for example, a modulation scheme known as current dependent matrix converter commutation strategy. Such modulation scheme, for example, may switches off only one of the MOSFETs but leave the other MOSFET in an on state so as to allow a current flow in one direction (via the MOSFET that is in the on-state and the body diode of the other MOSFET). This may be used to allow inductances in the circuit to commutate.

Using MOSFETs to implement the switches 51 1 , 51 2 , 51 n is only an example. Other types of electronic switches such as IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Field Effect Transistors), BJTs (Bipolar Junction Transistors) or HEMTs (High Electron-Mobility Transistors) may be used as well.

In the power converter circuit shown in FIG. 10 , the output filter 6 includes an LC filter 61 , 62 that receives the selector output voltage v 5 and generates an LC filter output voltage v 62 . The LC filter output voltage v 62 is a smoothed (filtered) version of the selector output voltage v 5 . If, for example, the selector output voltage v 5 has a waveform as shown in FIG. 2C , the smoothed version of the selector output voltage v 5 generated by the LC filter has a waveform as denoted by your shown in FIG. 2C , The LC filter includes a series circuit with an inductor 61 and a capacitor 62 . This series circuit is connected between the output 52 and the reference node 12 in the example shown in FIG. 10 , whereas the LC filter output voltage v 62 is available across the capacitor 62 .

Referring to FIG. 10 , the output filter 6 furthermore includes an unfolding bridge. The unfolding bridge includes two half-bridges each connected in parallel with the capacitor 62 of the LC filter. A first one of these two half-bridges includes a first high-side switch 63 H and a first low-side switch 63 L , and a second one of these two half-bridges includes a second high-side switch 64 H and a second low-side switch 64 L . A tap of the first half-bridge forms the first output node 13 and a tap of the second half-bridge forms the second output node 14 . The unfolding bridge is configured to generate an alternating output voltage v OUT based on the LC filter output voltage v 62 . According to one example, the power converter circuit generates the filter output voltage v 62 such that it has a rectified sine waveform and the unfolding bridge generates the output voltage v OUT to have a sine waveform based on the filter output voltage v 62 . This is explained with reference to FIG. 11 in which example timing diagrams of the filter output voltage v 62 , the corresponding output voltage v OUT of the power converter circuit and of drive signals S 63 H , S 63 L , S 64 H , S 64 L of the individual switches of the half-bridges of the unfolding bridge are shown. Just for the purpose of illustration it is assumed that a high-level of a drive signal S 63 H -S 64 L switches on the respective switch 63 H - 64 L and that a low-level switches off the respective switch 63 H - 64 L . Referring to FIG. 11 , the unfolding bridge changes its switching state only once in each period of the filter output voltage V 62 , namely at the beginning of each period. One period of the output voltage v OUT (wherein one such period is shown in FIG. 11 ) includes two periods of the filter output voltage v 62 . That is, each period of the filter output voltage v 62 forms one half-period of the final output voltage v OUT . In one of these two half-periods, the filter output voltage v 62 forms the output voltage your, and in the other half-period, the filter output voltage v 62 is inverted by the unfolding bridge. In the example shown in FIG. 11 , in a first half-period of these two half-periods, the first high-side switch 63 H and the second low-side switch 64 L are on in order to apply the filter output voltage v 62 to the output nodes 13 , 14 . In the second half-period, the first low-side switch 63 L and the first high-side switch 64 H are on in order to apply the inverted filter output voltage V 62 the output nodes 13 , 14 .

In case the power converter circuit includes an unfolding bridge, the selector circuit 5 generates an output voltage with only one polarity. In this case, the control circuit 52 shown in FIG. 6 can be modified such that the output voltage signal S vOUT represents a rectified output voltage v OUT instead of the output voltage v OUT , and the output current signal S iOUT represents the current i OUT-REC flowing from the LC filter into the unfolding bridge.

FIG. 12 shows timing diagrams of several signals occurring in the power converter circuit shown in FIG. 10 during operation. These timing diagrams serve to illustrate one way of operation of this power converter circuit. In particular, FIG. 12 shows timing diagrams of a current i C p through the chopper capacitor 22 , the selector output voltage v 5 , a current i 61 through the inductor 61 of the LC filter 61 , 62 and of the drive signals S 51 0 -S 51 n of the switches in the selector circuit 5 . In FIG. 10 , the timing diagrams are shown during one half-period of a sinusoidal output voltage v OUT or one period of a rectified sinusoidal output voltage, respectively. A rectified sinusoidal output voltage can be generated by the power converter circuit shown in FIG. 10 by omitting the unfolding bridge.

Referring to FIG. 12 , operation of the power converter circuit during one half-period (one period) of the output voltage v OUT can be subdivided into six sub-periods, namely a first sub-period, which is between a beginning of the half-period (period) and t 0 , a second sub-period, which is between t 0 and t 1 , a third sub-period, which is between t 1 and t 2 , a fourth sub-period, which is between t 2 and t 3 , a fifth sub-period, which is between t 3 and t 4 , and a sixth sub-period, which is between t 4 and t 5 . Referring to FIG. 12 , t 0 and t 5 are the times when the voltage level of the output voltage v OUT crosses the voltage level of the first DC link voltage V 4 1 , t 1 and t 3 are the times when the voltage level of the output voltage v OUT crosses the voltage level of the second DC link voltage V 4 2 , and t 2 is the time when the output voltage v OUT reaches its maximum. Operation in the first sub-period equals operation in the sixth sub-period, operation in the second sub-period equals operation in the fifth sub-period, and operation in the third sub-period equals operation in the fourth sub-period, so that only operation in the first, second and the third sub-period is explained in the following. These first, second and third sub-periods are sub-periods that cover a time period between a rime, when the output voltage v OUT is zero and a rime, when the output v OUT reaches its maximum. Thus, these three sub-periods cover one quarter (one half) of a period of a sinusoidal (a rectified sinusoidal) output voltage v OUT .

Referring to FIG. 12 , in the first sub-period, the selector circuit 5 switches between the first DC link voltage V 4 1 and zero. Consequently, switches 51 n and 51 1 of the selector 5 are switched on and off in an alternating fashion during this first sub-period. In the second sub-period, the selector 5 switches between the first DC link voltage V 4 1 and the second DC link voltage V 4 2 , so that switches 51 1 and 51 2 are switched on and off in an alternating fashion. In the third sub-period, the selector 5 switches between the second DC link voltage V 4 2 and the input voltage V IN0 , so that switches 51 2 and 51 n of the selector are switched on and off in an alternating fashion. During the first and second sub-period, the current i C p through the chopper capacitor 22 increases as the voltage level of the output voltage v OUT increases. Referring to FIG. 12 , the current i C p does not decrease to zero even if the output voltage V OUT is zero. This is due to a magnetizing current of the autotransformer 31 During the third sub-period the capacitor current i C p decreases as during this sub-period switch 51 n that is directly connected to the first input node 11 conducts (with the duty-cycle increases as the voltage level of the output voltage v OUT increases), whereas the current through switch 51 n (other than the currents through the switches 51 1 and 51 2 ) does not flow through the chopper capacitor 22 .

FIG. 13 illustrates the currents i 41 1 , i 41 2 through the tap capacitances 41 1 , 41 2 during the first three sub-periods.

FIG. 14A shows timing diagrams of the current i C p through the chopper capacitance 22 , the currents I 42 2 , I 42 1 through the second diodes 42 2 , 42 1 in the rectifier stages 4 2 , 4 1 and drive signals S 21 H of the high-side switch 21 H and S 21 L of the low-side switch 21 L of the chopper circuit 2 during two periods of the chopper circuit 2 . FIG. 14B illustrates timing diagrams of the selector output voltage v 5 currents i 51 2 , i 51 1 through the switches 51 2 , 51 1 of the selector circuit 5 , and drive signals S 51 1 , S 52 2 of these switches 51 1 , 51 2 during two periods of the selector circuit 5 . FIGS. 14A and 14B show the timing diagrams in the second sub-period (which is between t 0 and t 1 ) that is, when the selector circuit 5 switches between the second DC link voltage V 4 2 and the first DC link voltage V 4 1 . In the example shown in FIG. 14 , the switching frequency f 2 of the chopper circuit 2 is adapted to the inductances and capacitances in the power converter circuit such that the current i C p through the chopper capacitance 22 is a periodic current with a sinusoidal waveform. By this, the high-side switch 21 H and the low-side switch 21 L of the chopper circuit 2 can be operated in a zero current switching (ZCS) mode. That is, these switches 21 H , 21 L switch on and off when the current through the respective switch is substantially zero. By this, switching losses in the chopper circuit 2 can be reduced.

Referring to FIG. 14A , each of the DC link capacitors 43 1 , 43 2 is charged by the respective current i 42 1 , i 42 2 each time, the high-side switch 21 H is switched on. As the current i C p through the chopper capacitance 22 is a sinusoidal current, the charging currents of the DC link capacitors 43 1 , 43 2 have the form of one half-period of a sinusoidal signal each time, the high-side switch 21 H is switched on. When the low-side switch 21 is switched off the tap capacitances 41 1 , 41 2 are charged, as explained above, so that during these time periods, the charging currents i 42 1 , i 42 2 of the DC link capacitors 43 1 , 43 2 are zero.

Referring to FIG. 14B , the current i 51 2 through the switch 51 2 increases, when the switch 51 2 is switched on and is zero, when the switch 51 2 is switched off. When switch 51 2 is switched on, a voltage v 61 across the inductor 61 of the LC filter is given by V 4 2 -v OUT , that is, the second DC link voltage V 4 2 minus the output voltage your. As during the second sub-period the voltage level of the output voltage you is between the voltage level of the first DC link voltage V 4 1 and the voltage level of the second DC link voltage V 4 2 , the voltage v 61 across the inductor is higher than zero, which results in the increase of the current. Equivalently, when switch 51 1 of the selector circuit 5 is switched on, the voltage v 61 across the inductor 61 is given by V 4 1 -v OUT , that is, the first DC link voltage V 4 1 minus the output voltage v OUT . This voltage is negative, so that the current i 51 1 through this switch 51 1 decreases when the switch 51 1 is switched on and this current i 51 1 is zero, when the switch 51 1 is switched off. The current i 61 through the inductor 61 of the LC filter is given by the current i 51 1 plus the current i 51 2 so that the current i 61 has a triangular waveform during the second sub-period.

Referring to FIG. 10 , the power converter circuit includes several series resonant circuits that can be excited by the chopper circuit 2 . In order to obtain ZCS the parameters of these series resonant circuits and the switching frequency f 2 of the chopper circuit 2 are suitably adapted to one another. This is explained in further detail herein below. Referring to FIG. 10 , a first series resonant circuit includes the tap capacitance 41 1 of the rectifier stage 4 1 coupled to the first tap 32 1 , a first parasitic inductance 33 1 of the autotransformer 31 between the first tap 32 1 and the tap capacitor 41 1 , another parasitic capacitance 33 n of the autotransformer 31 in series with the n-th winding 31 n and the chopper capacitor 22 . Another series resonant circuit includes the tap capacitor 41 2 of the rectifier stage 4 2 coupled to the second tap 32 2 , a second parasitic inductance 33 2 , the parasitic inductance and the chopper capacitor 22 . The parasitic inductances 33 1 , 33 2 , 33 n of the autotransformer 31 result from leakage inductances of the autotransformer 31 . In general, a power converter circuit with an autotransformer with n windings and n−1 taps includes n−1 series resonant circuits. Each of these resonant circuits is associated with one tap 32 i and includes the tap capacitor 41 i connected to the respective tap 32 i , a leakage inductance 33 i at the respective tap 32 i , the chopper capacitance 22 , and the leakage inductance 33 n in series with the chopper capacitor 22 .

These parasitic inductances 33 1 , 33 2 , 33 n can be obtained by measuring and/or simulating the specific autotransformer 31 employed in the power converter circuit. Based on these parasitic inductances 33 1 , 33 2 , 33 n and based on the desired switching frequency f 2 of the chopper circuit 2 , capacitances of the tap capacitors 41 1 , 41 2 , and the chopper capacitor 22 can be designed such that the switching frequency f 2 of the chopper circuit 2 equals the resonant frequency of the individual series resonant circuits mentioned above so that these series resonant circuits operate in a resonant mode in each of the sub-periods explained before. Consequently, the current i C p is a sinusoidal current with a frequency equal the switching frequency f 2 so that the switches 21 H , 21 L of the chopper circuit can be operated in the ZCS mode.

The power converter circuit operates in the resonant mode if, in each of the sub-periods explained before, each of the current i C p through the chopper capacitor 22 , the currents i 31 1 , i 31 2 , i 31 n through the windings 31 1 , 31 2 , 31 n , and the currents i 41 1 , i 41 2 through the tap capacitors 41 1 , 41 2 , have a sinusoidal waveform with a frequency equal the switching frequency f 2 of the chopper circuit 2 . That is, the power converter circuit operates in the resonant mode if each of the currents mentioned above can be expressed as

i x ( t )= b·e x ( t )·sin(2 π·f 2 ·t )  (8),

where i x (t) denotes any of the currents explained above, e x is a timely varying envelope of the respective current i x (t), f 2 is the switching frequency of the chopper circuit, and b is a (constant) proportionality factor. In the power converter circuit shown in FIG. 10 , for example, the envelopes e x (t) of the individual currents in the individual sub-periods are given as shown in Table 1 below. Table 1 shows the envelopes e x (t) of the currents given in the left column in the three sub-periods 0<t<t 0 , t 0 <t<t 1 , and t 1 <t<t 2 .

In Table 1, i 31 1 , i 31 2 , i 31 n denote the currents through the respective windings of the autotransformer 31 , and d* is given by

As mentioned above, the leakage inductances 33 1 , 33 2 , 33 n can be obtained by measuring and/or simulating certain parameters of the autotransformer 31 before assembling the power converter circuit. As will be explained below, the inductances 33 1 , 33 2 , 33 n shown in FIG. 10 can be obtained from leakage inductances of the autotransformer 31 between taps of the autotransformer. These taps include taps 32 1 and 32 2 explained above. For the purpose of explanation, a first input node where the autotransformer 31 is connected to the output of the chopper circuit 2 is referred to as tap 32 n and a second input node where the autotransformer 31 is connected to the reference node 12 is referred to as tap 32 0 in the following.

FIG. 15A schematically illustrates an autotransfonner with n=3 windings L A , L B , and L C wound around the same core and with four taps A, B, C, D, where A and D are the input nodes of the autotransformer and B and C are taps between L A and L B and between L B and L C , respectively. FIG. 15B shows an equivalent circuit diagram of the autotransformer shown in FIG. 15B . In this autotransformer shown in FIG. 15A , an average length of one turn of each winding is l w , a width of a winding window of the core is w, and a height of the winding window is h. In the following, based on FIGS. 15A and 15B , it is explained how the leakage inductance between two taps of the autotransformer may be calculated based on a model of the autotransformer. With reference to FIGS. 16A to 16C it is then explained how the leakage inductances of the autotransformer 31 shown in FIG. 10 can be calculated.

In the following L s(i,j) denotes a leakage inductance between two taps i and j of an autotransformer. For the purpose of explanation, it is assumed that these taps are taps B and C of the autotransformer shown in FIGS. 15A and 15B . Referring to FIG. 15A , determining the leakage inductance L s(i,j) includes calculating the leakage inductance L s(i,j) based on the assumption that a current I p is driven into tap i and winding L C is short-circuited, that is, short tap C=j and tap D are short-circuited. A current I p driven into tap B generates a magnetic field H y . This magnetic field H y and the magnetic energy W M associated therewith is schematically illustrated in the graph drawn above the autotransformer shown in FIG. 15A . The magnetic energy stored in the autotransformer when operating the autotransformer in a configuration as shown in FIGS. 15A and 15B and when a current level of the current I p is given by I can be calculated as:

W M ⁡ ( i , j ) = 1 2 ⁢ L s ⁡ ( i , j ) ⁢ I 2 = μ 0 ⁢ l w ⁢ h 2 ⁢ ∫ 0 w ⁢ H y 2 ⁡ ( x ) ⁢ ⁢ dx = μ 0 ⁢ l w ⁢ h 2 [ ∫ 0 N C N tot ⁢ w ⁢ ( 1 h ⁢ N C ⁢ N B N C ⁢ I ⁢ x N C N tot ⁢ w ) 2 + ∫ N C N tot ⁢ w N B + N C N tot ⁢ w ⁢ ( - 1 h ⁢ N 2 ⁢ I ⁢ x - N B + N C N tot ⁢ w N B N tot ⁢ w ) 2 ] = 1 2 ⁢ μ 0 ⁢ l w ⁢ w h ⁢ ( N tot 3 ) 2 ⁢ I 2 ⁢ 3 ⁢ ( N B + N C ) ⁢ N ⁢ 2 B N tot 3 ≈ 1 2 ⁢ L 0 ⁢ I 2 ⁢ 3 ⁢ ( N B + N C ) ⁢ N B 2 N tot 3 ⁢ ⁢

⁢ ⁢ where ( 10 ) ⁢ L 0 ≈ μ 0 ⁢ l w ⁢ w h ⁢ ( N tot 3 ) 2 , ( 11 )

and wherein N B denotes the number of turns of winding L B , N C denotes the number of turns of winding L C , N D denotes the number of turns of winding L D , and N tot denotes the overall number of turns, which is N tot =N A +N B +N C . Based on equations (9) and (10), the leakage inductance L s(2,1) can be expressed as

L s ⁡ ( i , j ) = L s ⁡ ( B , C ) = L 0 ⁢ 3 ⁢ ( N B + N C ) ⁢ N B 2 N tot 3 ( 12 )

Thus, the leakage inductance L s(B,C) between two taps B, C of an autotransformer can be calculated based on the geometry of the transformer, which is included in L 0 , based on the number of turns N B that are located between the taps B and C, the number of turns N C that are short-circuited, and the overall number of turns N tot .

In the following, L s denotes the plurality of leakage inductances of the autotransformer 31 shown in FIG. 10 . In this transformer 31 , taps 32 n , 32 2 , 32 1 , 32 0 may briefly be referred to as taps n, 2 , 1 , and 0 , respectively. Thus, for example, L s(2,1) denotes the leakage inductance between taps 32 2 and 32 1 of the autotransformer shown in FIG. 10 . The plurality of leakage inductances includes a leakage inductance L s(n,2) between taps n and 2, a leakage inductance L s(n,1) between taps n and 1 , and a leakage inductance L s(2,1) between taps 2 and 1 . L s is therefore given as:

L s =[L s(n,2) L s(n,1) L (2,1) ] T ≈Λ T L 0   (13)

FIGS. 16A, 16B and 16C illustrate the set-up for calculating the leakage inductances L s(n,2) , L s(n,1) , and L s(2,1) , respectively, in the autotransformer 31 shown in FIG. 10 . Calculating the leakage inductance L s(n,2) , for example, includes referring to FIG. 16A driving a current I into tap n and short circuiting windings 31 2 and 31 1 . Comparing FIGS. 15B and 16A it can be seen that the number N B of turns between the taps where the leakage inductance is to be determined equals N n in FIG. 16A , and the number of turns N C that are short-circuited equals N 2 +N 1 in FIG. 16A . Inserting N B =N n and N C =N 1 +N 2 in equation (11) and assuming that the individual windings 31 1 , 31 2 , 31 n have the same number of turns, so that N 1 =N 2 =N n =⅓N tot , it can be shown that

L s(n,2) =⅓ ·L 0   (14),

where L 0 includes parameters of the transformer geometry and the overall number of turns, as explained with equation (10). Based on equation (12) and on what is shown in FIGS. 16B and 16C it can be shown that A is given as follows, if the individual windings 31 1 , 31 2 , 31 n have the same number of turns, so that N 1 =N 2 =N n =⅓N tot ,

Equation (10) and, therefore equation (12) from which equation (15a) had been derived, is based on the assumption that the windings of the autotransformer are connected in the same order as shown in FIGS. 10 and 16A to 16C , so that there is no interleaving in the winding arrangement. The curves drawn in dashed lines in the graphs shown in FIGS. 16A to 16C illustrate the magnetic field in the transformer in this case.

If the winding arrangement is modified, for example by interleaving the three windings 31 n , 31 2 , 31 1 , which may reduce the magnetic energy and, therefore, result in a more efficient magnetic design, equation (10) is not valid anymore. For example, swapping the windings associated to 31 2 and 31 1 and repeating the procedure explained with reference to FIGS. 15 and 16A to 16C results in a magnetic field that is represented by the solid lines in the graphs shown in FIGS. 16A to 16C . As can be seen from FIG. 16B , for example, the magnetic field is reduced to 50%. In this case, A is

The inductances gathered in Ls do not have a direct correspondence in the autotransformer equivalent circuit shown in FIGS. 10 and 15 . That is, inductances L s(n,2) , L s(n,1) , L s(2,1) are not the inductances 33 n , 33 2 , 33 1 shown in FIG. 10 . These inductances 33 n , 33 2 , 33 1 are also referred to as L σn , L σ2 , L σ1 in the following. One way of how L σn , L σ2 , L σ1 may be calculated based on Ls is explained below. For the purpose of explaining this calculation a compact notation is introduced as follows:

W M =[W M(n,2) W M(n,1) W M(2,1) ] T   (16)

W E = [ W E ⁡ ( n , 2 ) ⁢ W E ⁡ ( n , 1 ) ⁢ W E ⁡ ( 2 , 1 ) ] T ( 17 ) L σ = [ L σ ⁢ ⁢ n ⁢ L σ ⁢ ⁢ 2 ⁢ L σ ⁢ ⁢ 1 ] T ( 18 ) C σ - 1 = [ 1 C p ⁢ 1 C tap , 2 ⁢ 1 C tap , 1 ] ( 19 )

where W E(i,j) denotes the electrical energy and W M(i,j) denotes the magnetic energy stored in the autotransformer when measuring L s(i,j) as explained above. Furthermore, C p is the capacitance of the chopper capacitor 22 , C tap,2 is the capacitance of the second tap capacitor 41 2 , and C tap,1 is the capacitance of the first tap capacitor 41 1 .

Considering the current ratios shown in FIGS. 16A-C , the magnetic energy W M stored in the autotransformer in each experiment is

W M = 1 2 ⁢ L s ⁢ I 2 = 1 2 ⁢ ML σ ⁢ I 2 ( 20 )

so that

L σ =M −1 Λ T L 0   (21)

where

M = [ 1 ( 3 2 ) 2 0 1 0 3 2 0 1 2 2 ] ( 22 )

Consequently, the capacitors C σ −1 can be calculated as follows in order to tune the frequency of the currents in each sub-period to f 2 :

C σ −1 =(2 ·π·f 2) 2 M −1 Λ T L 0   (23).

Thus, based on parameters of the autotransformer and in consideration of a desired switching frequency f 2 of the chopper circuit 2 the capacitances of the chopper capacitor 22 , and the tap capacitors 41 1 , 41 2 can be suitably selected in order to obtain sinusoidal current waveforms, that is, in order to operate the power converter circuit, in particular the chopper circuit 2 and the rectifier circuit 4 in a resonant fashion. The parameters of the transformer, such as the leakage inductances may be calculated as explained above, measured and/or simulated before employing the autotransformer in the power converter circuit. Alternatively, these parameters may be obtained from a data sheet provided by the supplier of the autotransformer.

It should be noted that the topology shown in FIG. 10 is only one of a plurality of suitable power converter topologies. Examples of some other topologies are explained with reference to FIGS. 17 to 20 herein below.

FIG. 17 shows a chopper circuit 2 , a rectifier circuit 4 and a selector circuit 5 of a power converter circuit according to another example. In this example, the chopper circuit 2 has the same topology as explained with reference to FIGS. 4 and 10 herein before. The autotransformer 31 has the same topology as the autotransformer 31 explained before, but is connected between the output of the chopper circuit 2 and a reference node REF that is different from the second output node. This reference node REF is formed by a tap of a capacitive voltage divider with a first capacitor 23 1 and a second capacitor 23 2 wherein this capacitive voltage divider 23 1 , 23 2 is connected between the first input node 11 and the second input node 12 . According to example, voltage divider capacitors have the same capacitance so that the voltage at the reference node REF is V IN /2 as referenced to the second input node 12 . The chopper voltage v 2 is the voltage between the output 24 of the chopper circuit 2 and the reference node REF. This chopper voltage again is a zero-mean square wave voltage with a frequency of f 2 .

The rectifier stages 4 1 , 4 2 are different from the rectifier stages 4 1 , 4 2 shown in FIG. 10 in that each rectifier stage 4 1 , 4 2 includes two output capacitors 43 1+ , 43 1− , and 43 2+ , 43 2− , respectively, wherein one circuit node of each of these capacitors is connected to the reference node REF. One way of operation of these rectifier circuits 4 1 , 4 2 is explained with reference to the rectifier stage 4 1 in the following. The rectifier stage 4 2 operates equivalently.

The output capacitors 43 1+ , 43 1− of rectifier stage 4 1 are charged based on the tap voltage v 3 1 at the first tap 32 1 . In this rectifier stage 4 1 , output capacitor 43 1+ is charged each time the tap voltage v 3 1 has a first polarity, and output capacitor 43 1− is charged each time the tap voltage v 3 1 has a second polarity opposite the first polarity. The first output capacitor 43 1+ is connected in series with the first rectifier element 42 1+ and a first capacitor 41 1+ , whereas this series circuit is connected in parallel with the first winding 31 1 . The second output capacitor 43 1+ is connected in series with the second rectifier element 42 1− and a second capacitor 41 1− whereas this series circuit is also connected in parallel with the first winding 31 1 . The first DC link voltage V 4 1 is available across a series circuit of the two output capacitors 43 1+ , 43 1− . In this rectifier stage 4 1 , each of the output capacitors 43 1+ , 43 1− is charged to a voltage level that equals the amplitude of the tap voltage v 3 1 so that the DC link voltage V 4 1 equals twice the amplitude of the tap voltage v 3 1 , which is the same as in the power converter circuit shown in FIG. 10 . The first and second capacitors 41 1+ , 41 1− are equivalent to the tap capacitor 41 1 shown in FIG. 10 but do not serve to boost the DC link voltage in this example. Like tap capacitor 41 1 these tap capacitors 41 1+ , 41 1− are part of series resonant circuits, where inductors of these series resonant circuits are formed by leakage inductances of the autotransformer 31 . However, these leakage inductances, which are the same as shown in FIG. 10 , are not shown in FIG. 17 .

Equivalently to the first rectifier stage 4 1 , the second rectifier stage 4 2 includes a series circuit with a first output capacitor 43 2+ , a first rectifier element 42 2+ and a first capacitor 41 2+ , wherein this series circuit is connected in parallel with a series circuit that includes the first winding 31 1 and the second winding 31 2 . Furthermore, the second rectifier stage 4 2 includes a series circuit with the second output capacitor 43 2− , a second rectifier element 42 2− and the second capacitor 41 2− . The second DC link voltage V 4 2 is available across a series circuit of the output capacitor 43 2+ , 43 2− .

In the power converter circuit shown in FIG. 17 , the selector circuit 5 includes two switches connected to each rectifier stage 4 1 , 4 2 instead of only one switch, as in the example shown in FIG. 10 . For connecting the first DC link voltage V 4 1 to the output 52 , for example, the power converter circuit shown in FIG. 17 includes switches 51 1+ , 51 1− . From these switches, switch 51 1+ connects the series circuit with the output capacitors 43 1+ , 43 1− to the output 52 and switch 51 1− connects the series circuit with the output capacitors 43 1+ , 43 1− to the second input node 12 . Equivalently, the power converter circuit includes switches 51 2+ , 51 2− for connecting the series circuit with the output capacitors 43 2+ , 43 2− between the output 52 and the second input node 12 . Switches 51 1+ , 51 1− are operated simultaneously by a drive signals S 51 1 , and switches 51 2+ , 51 2− are operated simultaneously by a drive signal S 51 2 . Like in the power converter circuit shown in FIG. 10 , the capacitances of the tap capacitors 41 1+ - 41 2− can be designed such that, in consideration of the chopper frequency f 2 and the leakage inductances of the autotransformer 31 , the chopper circuit 2 and the rectifier circuit operate in a resonant mode.

FIG. 18 shows a chopper circuit 2 , an autotransformer circuit 3 and a rectifier circuit 4 according to another example. In this example, the autotransformer circuit 3 includes 2n windings 31 n+ , 31 2+ , 31 1+ , 31 1− , 31 2− , 31 n− connected in series. A first subset of these windings is connected in series with the first switch 21 + and the first chopper capacitor 22 + and the series circuit is connected between the first input node 11 and the second input node 12 , and a second subset of these windings is connected in series with the second switch 21 − and the second chopper capacitor 22 − and the series circuit is connected between the first input node 11 and the second input 12 . The first subset 31 n+ , 31 2+ , 31 1+ includes a first tap 32 1+ and a second tap 32 2+ and provides a first tap voltage v 3 1+ , v 3 2+ at each of these taps 32 1+ , 32 2+ , wherein the tap voltages v 3 2+ , v 3 1+ are referenced to the second input node 12 . Equivalently, the second subset 31 n− , 31 2− , 31 1− of the windings includes a first tap 32 1− , 32 2− and generates a tap voltage v 3 2− , v 3 1− at each of these taps 32 2− , 32 1− , wherein each of these tap voltages v 3 2− , v 3 1− is referenced to the second input node 12 .

The switches 21 +, 21 − of the chopper circuit 2 are operated in the same way as the high-side switch 21 H and the low-side switch 21 L explained herein before. That is, these switches are switched on and off in an alternating fashion at a switching frequency f 2 , wherein each switch 21 +, 21 − is switched on 50% of one switching period T 2 . The tap voltages v 3 1+ , v 3 2+ are different from zero each time the first switch 21 + is switched on, and the tap voltages v 3 1− , v 3 2− of the second subset are different from zero each time the second switch 21 − is switched on. According to one example, the windings 31 n+ - 31 n− have the same number of turns. In the example shown in FIG. 18 , maximum levels of the individual tap voltages are then given as follows:

v 3 1+ _ max =v 3 1− _ max =⅓ ·V IN   (24a)

v 3 2+ _ max =v 3 2− _ max =⅔ ·V IN   (24b)

Referring to FIG. 18 , a first output capacitor 43 1 across which the first DC link voltage V 4 1 is available is coupled to the first tap 32 1+ , 32 1− of each subset, and a second output capacitor 43 2 across which the second DC link voltage V 4 2 is available is coupled to the second tap 32 2+ , 32 2− of each subset. In particular, the first output capacitor 43 1 is coupled to the first tap 32 1+ of the first subset via a tap capacitor 41 1+ and a rectifier element 42 1+ and to the first tap 32 1− of the second subset via a capacitor 41 1− and a rectifier element 42 1− . The second output capacitor 43 2 is coupled to the second tap 32 2+ of the first subset via a tap capacitor 41 2+ and a rectifier element 42 2+ and to the second tap 32 2− of the second subset via a tap capacitor 41 2− and the rectifier element 42 2− . The first DC link voltage V 4 1 equals one third of the input voltage V IN , and the second DC link voltage V 4 2 equals ⅔ of the input voltage V IN in this example.

The dashed lines in FIG. 18 illustrate a modification of the rectifier circuit. In this example, a negative equivalent of each DC link voltage V 4 1 , V 4 2 is generated. These negative equivalents are referred to as V 4 1− and V 4 2− in FIG. 18 . Each of these further DC link voltages V 4 1− , V 4 2− is available across a respective capacitor 43 1− , 43 2− . Capacitor 43 1− is coupled to the first tap 32 1+ and 32 1− of each subset, and capacitor 43 2− is coupled to the second tap 32 2+ , 32 1− of each subset of windings. For this, capacitor 43 1− is coupled to capacitor 41 1+ via a rectifier element 44 1+ and to capacitor 41 1− via rectifier element 44 1− . Furthermore, output capacitor 43 2− is coupled to capacitor 41 2+ via rectifier element 44 2+ and to capacitor 41 2− via a rectifier element 44 2− . The input voltage V IN is available at the first input node 11 in this example. A negative equivalent V IN− of the input voltage V IN is available across another capacitor 43 n− connected between the second input node 12 and the second chopper capacitor 22 −, whereas capacitor 43 n− is connected to chopper capacitor 22 − via another rectifier element 44 n . In the modification shown in FIG. 18 positive and negative DC link voltages are available, so that a selector circuit 5 (not shown in FIG. 18 ) can synthesize an output voltage having positive or negative levels. For example, the selector circuit can synthesize a sinusoidal output voltage without requiring an unfolding bridge in the output filter. Like in the power converter circuit shown in FIG. 10 , the capacitances of the tap capacitors 41 1+ - 41 2− can be designed such that, in consideration of the chopper frequency f 2 and the leakage inductances of the autotransformer 31 , the chopper circuit 2 and the rectifier circuit operate in a resonant mode.

FIG. 19 shows a chopper circuit 2 and an autotransformer circuit 3 according to another example. In this example, the autotransformer circuit 3 is connected between a tap of the half-bridge 21 H , 21 L and a tap of a capacitive voltage divider. The capacitive voltage divider includes two capacitors 24 +, 24 −, which, according to one example, have the same capacitance. A voltage at the tap of the capacitive voltage divider therefore is V IN /2 relative to the second input node 12 . In this example, the autotransformer circuit 3 includes four windings 31 n , 31 22 , 31 1 , 31 1 , wherein the chopper voltage v 2 is applied to the series circuit with the windings 31 21 , 31 1 . A first tap voltage V 3 1 is available across winding 31 2 . A second tap voltage V 3 2 is available across the series circuit with the windings 31 1 , 31 21 , 31 22 , and a third tap voltage v 3 n is available across the overall series circuit with the windings 31 n , 31 22 , 31 21 , 31 1 . In this example, tap voltages v 3 2 , v 3 n are again proportional to the chopper voltage v 2 but have a higher amplitude than the chopper voltage v 2 . According to one example, windings 31 1 and 31 n have the same number of turns and each of windings 31 21 , 31 22 have a number of turns that equals half the number of turns of each of windings 31 1 , 31 n . In this case, the first tap voltage v 3 1 is 2/6 of the input voltage V IN , the second tap voltage v 3 2 is 4/6 of the input voltage V IN and the third tap voltage v 3 1 , is the input voltage V IN .

FIG. 20 shows a modification of the chopper circuit 2 and the autotransformer 31 shown in FIG. 19 . In the example shown in FIG. 20 , the chopper circuit includes two half-bridges, the half-bridge 21 H , 21 L explained before (referred to as first half-bridge in the following) and another half-bridge 25 H , 25 L (referred to as second half-bridge in the following). Both half-bridges are connected between the input nodes 11 , 12 to receive the input voltage V IN . An output (tap) of the first half-bridge 21 H , 21 L is connected to one tap of the autotransformer 31 , and an output (tap) of half-bridge 21 H , 21 L is connected to another tap of the autotransformer 31 . The autotransformer 31 includes a first and a second winding arrangement, wherein each of these winding arrangements is of the type shown in FIG. 19 . In FIGS. 19 and 20 like features of the winding arrangements have the same reference characters, wherein in FIG. 20 , like features of the two winding arrangements include the same reference character accompanied by a “+” in case of the first winding arrangement and a “−” in case of the second winding arrangement The first winding arrangement includes windings 31 n+ , 31 22+ , 31 21+ and 31 1+ and the second winding arrangement includes windings 31 n− , 31 22− , 31 21− and 31 1− . The windings of both winding arrangements are connected in series and inductively coupled. Furthermore, the winding two arrangements are symmetrical relative to a reference node REF, whereas tap voltages v 3 n+ , v 3 2+ , v 3 1+ , v 3 n− , v 3 2− , v 3 1− of the autotransformer 31 are referenced to the reference node REF. The first half-bridge 21 H , 21 L is connected to the tap between windings 31 22+ , 31 21+ of the first winding arrangement via chopper capacitor 22 , and the second half-bridge 24 H , 24 L is connected to the corresponding tap, that is, the tap between windings 31 22− , 31 21− of the second winding arrangement. The first winding arrangement may be implemented in the same way as the autotransformer shown in FIG. 19 , so that tap voltages v 3 n+ , v 3 2+ , v 3 1+ correspond to the tap voltages v 3 n , v 3 2 , v 3 1 explained with reference to FIG. 19 . The second winding arrangement may be implemented in the same way as the first winding arrangement so that waveforms of its tap voltages v 3 n− , v 3 2− , v 3 1− correspond to waveforms of the tap voltages of the first winding arrangement. Unlike the arrangement shown in FIG. 19 the arrangement shown in FIG. 20 supplies tap voltages of both polarities. The chopper circuit operates at the switching frequency 12 explained above,

FIG. 21 shows a power converter circuit according to another example. This power converter circuit is different from the power converter circuit shown in FIG. 1 in that it additionally includes a voltage regulator 7 that receives the selector output voltage v 5 and generates a voltage regulator output voltage v 7 based on the selector output voltage v 5 . Referring to the explanation below, the voltage regulator 7 , which may also be referred to a series voltage regulator (SVR), is configured to add a voltage to the selector output voltage v 5 so that the regulator output voltage v 7 equals the selector output voltage v 5 (if the added voltage is zero) or is higher the selector output voltage v 5 . One way of operation of the selector circuit 5 shown in FIG. 21 and the voltage regulator 7 is explained with reference to FIG. 22 below.

FIG. 22 shows timing diagrams of the selector output voltage v 5 and the power converter output voltage v OUT during one half cycle (one cycle) of a sinusoidal output voltage (a rectified sinusoidal output voltage). Referring to FIG. 22 , the selector 5 is configured to generate the selector output voltage v 5 such that a voltage level of the selector output voltage v 5 is below the desired voltage level of the output voltage v OUT . The voltage level of the output voltage v OUT can be defined by an external load, such as a power grid, or can be defined by some other signal received by the selector circuit 5 and the voltage regulator 7 . Just for the purpose of explanation it is assumed that the voltage level of the output voltage v OUT is defined by an external load. In this example, the selector circuit 5 receives the output voltage v OUT and, based on the instantaneous voltage level of the output v OUT , generates the selector output voltage v 5 based on the voltage levels 0 , V 4 1 , V 4 2 , V IN it receives. In particular, the selector circuit 5 , at each time, is configured to select one of the plurality of voltage levels such that the selected voltage level is equal to or below the instantaneous voltage level of the output voltage your. In FIG. 22 S vOUT is a signal that represents the output voltage v OUT . This signal is received by the selector circuit 5 and the voltage regulator 7 in the example shown in FIG. 21 .

The voltage regulator 7 is configured to internally generate a voltage that corresponds to a difference between the instantaneous voltage level of the output voltage v OUT and the voltage level of the selector output voltage v 5 and to add this internally generated voltage to the selector output voltage v 5 so that the voltage regulator output voltage v 7 is the output voltage v OUT . The filter circuit 6 is optional. As the selector output voltage v 5 does not switch between different voltage levels at a relatively high switching frequency (f 4 in the examples explained herein before) a low-pass filter in the filter circuit 6 is not required. Thus, the filter circuit 6 may only include an unfolding bridge according to one example. In this case, the filter circuit 6 may only change the polarity of the voltage regulator output voltage v 7 in order to generate the output voltage v OUT if, for example, the output voltage v OUT is a sinusoidal voltage and the voltage regulator output voltage v 7 is a rectified sinusoidal voltage.

For generating the voltage that is added to the selector output voltage v 5 the selector circuit receives a supply voltage from an auxiliary voltage source 8 . This auxiliary voltage source may include an auxiliary winding 81 of the autotransformer 31 . This auxiliary winding 81 is inductively coupled with the autotransformer windings 31 1 , 31 2 , 31 n explained before, but not connected in series with these windings 31 1 , 31 2 , 31 n Instead, the auxiliary winding is coupled to a rectifier 82 , 83 that generates the supply voltage V 8 from a voltage v 81 across the auxiliary winding. The voltage v 81 across the auxiliary winding, like the tap voltages, is an alternating voltage with a frequency defines by the chopper frequency f 2 . The rectifier circuit 82 , 83 generates a DC voltage, which forms the supply voltage V 8 , from this alternating voltage. The rectifier circuit may include a series circuit with a rectifier element 82 , such as a diode, and a capacitor 83 , whereas this series circuit is connected in parallel with the auxiliary winding 81 and the supply voltage V 8 is available across the capacitor 83 .

Although various exemplary embodiments of the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the spirit and scope of the invention. It will be obvious to those reasonably skilled in the art that other components performing the same functions may be suitably substituted. It should be mentioned that features explained with reference to a specific figure may be combined with features of other figures, even in those cases in which this has not explicitly been mentioned. Further, the methods of the invention may be achieved in either all software implementations, using the appropriate processor instructions, or in hybrid implementations that utilize a combination of hardware logic and software logic to achieve the same results. Such modifications to the inventive concept are intended to be covered by the appended claims.

Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second” and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.