Electronic device for a radiofrequency signal reception chain, comprising a low-noise transimpedance amplifier stage

This application is a continuation of U.S. application for patent Ser. No. 14/734,514 filed Jun. 9, 2015, which claims priority from French Application for Patent No. 1458865 filed Sep. 19, 2014, the disclosures of which are incorporated by reference.

Embodiments relate to the reception and processing of radiofrequency signals, in particular RADAR frequency signals, using a frequency transposition stage associated with a transimpedance amplifier (TIA) stage. The embodiments apply in particular, but without limitation, to the processing of motor-vehicle RADAR signals having, for example, a frequency of 77 GHz.

One embodiment provides a device for significantly improving the dynamic performance of the frequency transposition stage during reception by limiting the voltage swing, in order to work in current mode so as to not degrade the performance.

One embodiment provides, within this device, a transimpedance amplifier stage having low consumption, with an acceptable gain, low noise and a substantially rail-to rail differential voltage swing, that is to say one whose peak-to-peak voltage amplitude is close to the value of the supply voltage.

One embodiment thus provides a device comprising a differential circuit architecture having a frequency transposition stage with current output, with which a transimpedance amplifier stage having a low level of noise as well as a high gain, and having low consumption, is associated.

One aspect provides an electronic device, comprising an input for receiving signals having a first frequency, for example a radiofrequency frequency such as a RADAR frequency, and a differential architecture circuit comprising: at least one frequency transposition stage with current output, coupled to the input, a transimpedance amplifier stage having an amplifier end stage of the class AB type, a preamplifier stage coupled between the output of the frequency transposition stage and the input of the amplifier end stage and comprising first bipolar transistors as well as an active load, and a self-biased common-mode control stage configured in order to bias the preamplifier stage.

The amplifier end stage of the class AB type makes it possible to have low consumption. This type of circuit, however, has a low gain. A preamplifier stage is therefore added at the input of the end stage in order to have a higher gain.

Furthermore, a frequency transposition stage with current output (instead of a voltage output), for example a Gilbert cell, without such a structure implying limitation, makes it possible to have a good dynamic range.

According to one embodiment, the active load of the preamplifier stage comprises first PMOS transistors, and the output of the common-mode control stage is connected to the gates of the first PMOS transistors.

The use of a PMOS transistor in combination with a differential pair of bipolar transistors makes it possible to obtain low noise with a high gain, as well as good robustness in terms of temperature and in relation to fabrication method variations.

According to one embodiment, the amplifier end stage comprises a module, for example a resistive module, connected between the two outputs of this end stage and having a node, and the common-mode control stage comprises a differential pair of second bipolar transistors, the base of one of the second bipolar transistors being intended to receive a common-mode voltage, and the base of the other second bipolar transistor being connected to the node of the module, so that the voltage at this node is intended to be equal to half the sum of the voltages present at the two outputs of the end stage.

According to one embodiment, the collectors of the differential pair of second bipolar transistors are connected to two PMOS transistors connected as a current mirror, which allows self-biasing of this control stage.

According to one embodiment, the end stage comprises two class AB amplifiers, the bases of the pair of first bipolar transistors are respectively connected to the two current outputs of the frequency transposition stage and the two collectors of the pair of first bipolar transistors are respectively connected to the two inputs of the two class AB amplifiers.

According to one embodiment, the frequency transposition stage is configured in order to carry out direct baseband transposition of the input signal.

According to one embodiment, the first frequency of the input signal is a frequency of a RADAR signal.

Other advantages and characteristics of the invention will become apparent on studying the detailed description of entirely non-limiting embodiments and the appended drawings, in which:

FIG. 1 is a schematic representation of a radiofrequency signal reception chain;

FIG. 2 is a circuit diagram of a frequency transposition stage; and

FIG. 3 is a circuit diagram for a transimpedance amplifier.

FIG. 1 schematically represents a radiofrequency signal reception chain. In this chain, an antenna 1 receives a signal. This signal is prefiltered by a bandpass filter 2 then amplified by a low-noise amplifier 3 (known by those skilled in the art under the acronym LNA). The RF signal obtained in this way is sent to the input of a device 4 and a device 5 , each comprising a mixer 20 associated with a transimpedance amplifier 21 . The RF signal is respectively mixed with the signal generated by a local oscillator (LO) 6 , and with the same signal phase-shifted through 90° by a phase shifter 7 , so as to obtain two frequency shifted (transposed) signals in phase quadrature on the two channels I and Q. Although the invention may be applied to any type of reception chain, in particular of the type with a non-zero intermediate frequency, the chain is in this case of the zero intermediate frequency (ZIF) type, the transposed signals being directly in the baseband, that is to say the frequency of which lies around zero. The baseband signals at the output of the devices 4 and 5 are subsequently processed in conventional modules 8 and 9 having in particular equalization, amplification and lowpass and highpass filtering stages, then are sent to the input of analog/digital converters (ADC) 10 and 11 .

The differential architecture of the device 4 will now be described in more detail with reference to FIGS. 2 and 3 , it being understood that this architecture is similar to that of the device 5 .

In FIG. 2 , reference 20 denotes such a frequency transposition stage with current output.

In the example of FIG. 2 , the frequency transposition stage is a Gilbert cell, although the invention is not limited to this type of stage. Thus, it would also be possible to use a current switching device, for example, in particular a mixer with field-effect transistors (FET transistors), for example in the case of production in submicron MOS technology, such as a 28 nm technology on a substrate of the fully depleted silicon on insulator (FDSOI) type, or any type of frequency transposition stage structure with current output.

The Gilbert cell of FIG. 2 comprises three differential pairs of bipolar transistors of the NPN type: QC 1 /QC 2 , QC 3 /QC 4 and QC 5 /QC 6 , as well as input terminals RF INPUT and LO INPUT on which the radiofrequency signal RF and the signal generated by the local oscillator are respectively received, these terminals being respectively connected to the base electrodes of the transistors QC 5 and QC 6 , and to the base electrodes of the transistors QC 1 , QC 2 , QC 3 and QC 4 .

The collector of the transistor QC 1 is connected to the collector of the transistor QC 3 , to the current output terminal In, as well as to the drain of a PMOS transistor MC 2 connected as a current mirror with a PMOS transistor MC 1 , the drain of which is connected to an input terminal Irefn for the reference current.

Symmetrically, the collector of the transistor QC 4 is connected to the collector of the transistor QC 2 , to the current output terminal Ip, and to the drain of a PMOS transistor MC 3 connected as a current mirror with a PMOS transistor MC 4 , the drain of which is connected to an input terminal Irefp for the reference current. The sources of the PMOS transistors are for their part connected to a supply terminal VDD.

The current mirrors formed by the transistors MC 1 , MC 2 and MC 3 , MC 4 make it possible to set the bias current flowing through MC 2 and MC 3 .

The negative current output terminal In and the positive current output terminal Ip are coupled to the input terminals of a transimpedance amplifier stage 21 which will convert the dynamic current at the output of the frequency transposition stage into voltage.

FIG. 3 illustrates a transimpedance amplifier according to one embodiment.

The transimpedance amplifier 21 comprises an amplifier end stage 42 comprising two class AB amplifiers 43 and 44 , as well as a resistive load module 45 connected between the outputs OUT 1 and OUT 2 of these amplifiers and having a node VM.

Two feedback resistors 60 and 60 ′ are respectively connected between the outputs OUT 2 , OUT 1 and the negative In and positive Ip current output terminals.

The amplifiers 43 and 44 comprise a plurality of MOS transistors, and their output is a rail-to-rail output, that is to say the output voltage of these amplifiers can reach values close to the supply values.

The amplifier 44 , with a structure similar to that of the amplifier 43 , will now be described in more detail. The references of the elements of the amplifier 43 are suffixed by a “prime” designation (for example, I′ OUT ) relative to the references of the identical elements of the amplifier 44 (for example, I OUT ).

The AB amplifier per se comprises the MOS transistors M 1 and M 2 in PUSH-PULL configuration.

It will be recalled here that an amplifier of the class AB type is a compromise between class A and class B. The neutral point of the class AB amplifier lies between that of a class A amplifier and that of a class B amplifier.

The transistors M 3 , M 4 and the current sources I 3 and I 4 form a biasing stage of the amplifier M 1 , M 2 .

The transistors M 5 , M 7 and the current source I 7 , as well as the transistors M 6 , M 8 and the current source I 8 , make it possible to bias the biasing stage.

The voltage swing at the output OUT 2 varies between two values lying at a few tens of millivolts from each supply rail, for example but without limitation from 0.25 V to 2.25 V for a supply voltage VDD of 2.5 volts.

The voltage VSS is ground.

The gates of the transistors M 1 and M′ 1 form the inputs E 2 and E 1 of this end stage 42 .

The advantage of class AB amplifiers is that they have low consumption. However, the gain of such amplifiers is low.

In order to have a higher gain, a preamplifier stage 41 is coupled between the output In, Ip of the frequency transposition stage 20 and the input E 1 , E 2 of the amplifier end stage 42 .

The preamplifier stage 41 comprises a differential pair of bipolar transistors Q 1 and Q 2 , the bases of which are respectively connected to the current outputs Ip and In of the frequency transposition stage, and the collectors of which are respectively connected to the inputs of the amplifiers 43 and 44 .

The use of bipolar transistors makes it possible to have a low noise level.

The voltage preamplifier stage 41 furthermore comprises an active load 46 connected to the collectors of the bipolar transistors Q 1 and Q 2 , and in this case comprising two PMOS transistors M 9 and M 10 in order to increase the gain.

The gates of these PMOS transistors are connected via their gates (node VG) to the output of a self-biased common-mode control stage 40 configured in order to bias the preamplifier stage 41 .

This common-mode control stage 40 itself also comprises a differential pair of bipolar transistors Q 3 and Q 4 .

The base of the transistor Q 4 is connected to a terminal MC which receives a common-mode voltage, that is to say a voltage equal to the average of the supply voltages, here equal to VDD and VSS. In this example, this common-mode voltage is equal to 1.25 V.

The base of the transistor Q 3 is for its part connected to the node VM of the module 45 of the amplifier end stage. A common-mode control loop is thus produced, so that the voltage at the node VM is equal to the average of the voltages present at the output terminals OUT 1 and OUT 2 of the end stage. The two output voltages thus oscillate in phase opposition around the common-mode voltage VDD/2.

Lastly, the collectors of the bipolar transistors Q 3 and Q 4 are connected to the drains of the two PMOS transistors M 11 and M 12 , which are connected as a current mirror (so as to self-bias this stage 40 ) and the gates of which are connected via the node VG to those of the PMOS transistors M 9 and M 10 forming the active load 46 of the preamplifier stage 41 .

A transimpedance amplifier having a low noise level and a high gain, and having low consumption as well as a rail-to-rail output, is thus obtained.

Finally, a mixer with improved performance in terms of dynamic range is therefore obtained.

Thus, by way of example, for an RF signal with a RADAR frequency equal to 77 GHz, with the aid of 143 ohm feedback resistors a gain of 43 dBΩ is obtained, which for a dynamic current of 7 mA coming from the frequency transposition stage gives a voltage swing of 2 volts peak-to-peak for a supply of 2.5 volts, a dynamic consumption of the order of 8 mA and an idle consumption of 3 mA, and a noise of less than 17 nV/√Hz.

The invention is not limited to the embodiments which have just been described; rather, it encompasses all variants.

Thus, although the reception chain described above has an architecture of the ZIF type, as indicated above it is possible to have a chain with a plurality of frequency transposition stages, so as to carry out successive transpositions with intermediate frequencies in order to arrive in the baseband, and a transimpedance amplifier stage such as the stage 21 after each frequency transposition stage.