Low supply current mirror

The present application relates to systems for operating a current mirror under low power supply requirements.

A current mirror, as its name suggests, is utilized in integrated circuits to mirror (e.g., copy) a reference current flowing through one active device (e.g., transistor) in another active device (e.g., another transistor). The current mirror is intended to maintain the output current (e.g., the mirrored reference current) at a constant level regardless of load changes at the other active device. Further, the current being mirrored can be a direct current (“DC”) or an alternating current (“AC”). Current mirrors are generally utilized in integrated circuits to provide bias currents and/or active loads.

However, current mirrors are still susceptible to errors. For example, in many current mirrors, the current source transistor (e.g., the transistor utilized to generate the reference current) has low output impedance, leaving the current source transistor more sensitive to noise in the integrated circuit. For example, the current source transistor is less able to reject noise from a power supply when the output impedance is low. Further, the low output impedance also leads to a lower power supply rejection ratio (“PSRR”). The PSRR is a ratio of the change in supply voltage to the change in output voltage. As such, as the power supply modulates (e.g., due to noise), so will the V DS across the current source transistor and, therefore, the current generated by the current source transistor. As the reference current modulates, it becomes more difficult to effectively maintain a desired ratio of the output current to the reference current.

Further, the power requirements for the current mirror transistor and the output current transistor also affect the performance of the current source transistor. For example, both of the current mirror transistor and the output current transistor have to operate in the saturated region in order to mirror the reference current at the output current transistor. Therefore, the V DS of each transistor has to be greater than the difference between the V GS and V T of the transistor (e.g., V DSat >V GS −V T ). As the V DS for the transistors modulates, so will the V DS across the current source transistor, which, as stated above, makes it more difficult to maintain the desired ratio of the output current to the reference current.

In order to address the aforementioned effects of low output impedance, many current mirrors include a cascode transistor at the drain node of the current source transistor. The cascode transistor is essentially a gain amplifier that amplifies (e.g., multiplies) the low output impedance at the drain node of the current source transistor, resulting in a higher output impedance. Further, the cascode transistor disjoins the dependency of the V DS voltage across the current source transistor from (i) the power supply and (ii) the V DS voltage across the current mirror transistor. Therefore, any voltage modulations (e.g., due to noise or otherwise) from the power supply or the current mirror transistor would not affect the V DS voltage across the current source transistor, thereby maintaining the desired ratio of the output current to the reference current. However, in circuit designs with low power supply requirements, there may not be enough headroom (e.g., remaining voltage) to include the cascode transistor.

Noise in the system can be further mitigated by increasing the V DSat of the current mirror transistor and the output current transistor. However, as the V DSat of the current mirror and output current transistors are increased, less headroom will be available for the current source transistor. Further, if (i) the V DS across the transistors (e.g., current mirror and output current) are high and (ii) the reference current is also high, the reference current will likely compress. As the reference current compresses, it will again become more difficult to effectively maintain the desired ratio of the output current to the reference current.

Accordingly, there is a need for a low-noise current mirror to operate under low power supply requirements.

FIG. 1A illustrates a conventional current mirror.

FIG. 1B illustrates a conventional current mirror with a cascode transistor.

FIG. 2 illustrates a low supply current mirror in accordance with an example embodiment of the present invention.

FIG. 3A illustrates a specific example of the low supply current mirror of FIG. 2 .

FIG. 3B illustrates an equivalent circuit of the reference current transistors utilized in the low supply current mirror in FIG. 3A .

FIG. 4 illustrates another example embodiment of the low supply current mirror.

The following description of embodiments provides non-limiting representative examples referencing numerals to particularly describe features and teachings of different aspects of the invention. The embodiments described should be recognized as capable of implementation separately, or in combination, with other embodiments from the description of the embodiments. A person of ordinary skill in the art reviewing the description of embodiments should be able to learn and understand the different described aspects of the invention. The description of embodiments should facilitate understanding of the invention to such an extent that other implementations, not specifically covered but within the knowledge of a person of skill in the art having read the description of embodiments, would be understood to be consistent with an application of the invention.

One aspect of the present disclosure is to provide systems for operating a current mirror under low power supply requirements. The systems herein address at least one of the problems discussed above. Accordingly, a current mirror system with parallel input current paths is provided.

According to an embodiment, a current mirror system includes: a first current source transistor, wherein the first current source transistor includes a channel width of 1 W UNIT , wherein the W UNIT corresponds to a channel width of a unit transistor; a second current source transistor, wherein the second current source transistor includes a channel width of (N−1)×W UNIT , wherein N is an integer that corresponds to a desired width of a current source transistor; a first current mirror transistor, wherein the first current mirror transistor includes a channel width of (M)×W UNIT and a channel length of (N)×L UNIT , wherein the L UNIT corresponds to a channel length of the unit transistor, wherein M is an integer that corresponds to a desired width of a current mirror transistor; a second current mirror transistor, wherein the second current mirror transistor includes a channel width of (M)×W UNIT and a channel length of (P−1)×L UNIT , wherein P is an integer that corresponds to a desired length of the current mirror transistor; and an output current transistor, wherein the output current transistor includes a channel width of K×(M)×W UNIT and a channel length of (P−1)×L UNIT , wherein K is a current gain coefficient.

According to another embodiment, a current mirror system includes: a first current source transistor, wherein the first current source transistor is configured to generate a first current that is (1/N) of a total generated current, wherein N is an integer greater than zero; a second current source transistor, wherein the second current source transistor is configured to generate a second current that is ((N−1)/N) of the total generated current; a first current mirror transistor, wherein the first current mirror transistor is configured to receive the first current; a second current mirror transistor, wherein the second current mirror transistor is configured to receive a sum of the first and second currents; and an output current transistor, wherein the output current transistor is configured to receive an output current, wherein the output current is based on the sum of the first and second currents at the second current mirror transistor.

FIG. 1A illustrates a conventional current mirror. Current mirror 100 includes a current source transistor 101 , a current mirror transistor 102 , an output current transistor 103 , and a load 104 . As depicted in FIG. 1A , the current source transistor 101 is a PMOS transistor. In an embodiment, the current source transistor 101 includes a channel width of N×W UNIT and a channel length of Y×L UNIT , wherein W UNIT corresponds to the channel width of a unit transistor, N is an arbitrary integer that corresponds to a desired width of a current source transistor, L UNIT corresponds to a channel length of the unit transistor, and Y is an arbitrary integer that corresponds to a desired length of a current source transistor. In an embodiment, the desired length of the current source transistor 101 is usually set to a long length in order to improve (i) matching between the input current and the output current and (ii) the output impedance of the current source transistor 101 .

Further, the source node of the current source transistor 101 is connected to a positive power supply V DD , and the drain node of the current source transistor 101 is connected to the drain node of the current mirror transistor 102 . Further, the gate node of the current source transistor 101 receives a voltage V PB . Voltage V PB is the V GS of the current source transistor 101 . Therefore, once the voltage V GS is at V PB , the current source transistor 101 will turn on. As further depicted in FIG. 1A , the current source transistor 101 generates an input current I IN1 .

Further, as depicted in the figure, the current mirror transistor 102 is a NMOS transistor. In an embodiment, the current mirror transistor 102 includes a channel width of M×W UNIT and a channel length of P×L UNIT , wherein M is an arbitrary integer that corresponds to a desired width of a current mirror transistor and P is an arbitrary integer that corresponds to a desired length of a current mirror transistor. Further, the source node of the current mirror transistor 102 is connected to a negative power supply V SS . Further, the gate node of the current mirror transistor 102 is connected to the drain node of the current mirror transistor 102 via a short. The gate node of the current mirror transistor 102 receives a voltage V 1 . Voltage V 1 is the V GS of the current mirror transistor 102 . Therefore, once the voltage V GS is at V 1 , the current mirror transistor 102 will turn on.

Further, similar to the current mirror transistor 102 , the output current transistor 103 is also a NMOS transistor. In an embodiment, the output current transistor 103 includes a channel width of K×M×W UNIT and a channel length of P×L UNIT , wherein K is the current gain coefficient. Further, the source node of the output current transistor 103 is also connected to a negative power supply V SS . The drain node of the output current transistor 103 is connected to a first end of the load 104 . Further, the drain node of the output current transistor 103 is at a voltage V 2 . Further, the gate node of the output current transistor 103 receives the voltage V 1 , which is also the V GS of the output current transistor 103 . Therefore, once the voltage V GS is at V 1 , the output current transistor 103 will turn on. In an embodiment, the output current transistor 103 establishes an output current I OUT1 , which is a ratio of the input current I IN1 (e.g., K×I IN1 ). In other words, depending on the current gain coefficient K, the current mirror 100 can either amplify, replicate, or reduce the input current I IN1 . Specifically, the output current I OUT1 can be modified by increasing or decreasing the channel width of the output current transistor 103 by the factor K. However, other than the channel widths, it is important that the other characteristics of the current mirror transistor 102 and the output current transistor 103 are equivalent (e.g., channel length, V GS , etc.) in order for the current mirror 100 to properly operate.

In an embodiment, the output current I OUT1 originates from the load 104 . In an embodiment, the load 104 could be one of: (i) a resistor, (ii) another current mirror, or (iii) any other circuit that needs to draw a current from a current source. Further, the load 104 is connected to a voltage source V L at its second end. In an embodiment, the voltage source V L is set high enough such that the voltage V 2 is at a sufficient level for the output current transistor 103 to operate.

Further, as discussed above, in order for the current mirror 100 to mirror the input current I IN1 at the output current transistor 103 , both of the current mirror transistor 102 and the output current transistor 103 have to operate in the saturated region (e.g., V DSat >V GS −V T ). Therefore, the voltage V 1 (e.g., the V GS of both of the current mirror transistor 102 and the output current transistor 103 ) will be comprised of a threshold voltage V T (e.g., minimum voltage required to operate the transistor) and the overdrive voltage V DSat (minimum voltage required to operate the transistor in the saturated region). Similarly, the voltage V 2 has to be greater than the overdrive voltage V DSat of the output current transistor 103 for it to operate in the saturated region. V 1 will likely require a large portion of the power being supplied by the positive power supply V DD and the negative power supply V SS during the operation of the current mirror 100 . Further, assuming the current source transistor 101 has low impedance, the voltage V PB will vary at the drain node of the current source transistor 101 with any modulation in the voltage V 1 . Therefore, as the overdrive voltage V DSat of the current mirror transistor 102 is increased, less headroom will be available for the current source transistor 101 to properly operate. Further, if the current mirror transistor 102 is at a high enough V DS (e.g., due to a high threshold voltage V T and a high overdrive voltage V DSat ) and the current generated at the current source transistor 101 (i.e., input current I IN1 ) is also high, the generated input current I IN1 will likely begin to compress and, therefore, the K factor ratio for the output current I OUT1 will no longer hold. Further, as also discussed above, because the current source transistor 101 has low impedance, the current source transistor 101 is also associated with a lower PSRR. Accordingly, as the power supply V DD modulates (e.g., due to noise), so will the voltage V PB and, therefore, the input current I IN1 generated by the current source transistor 101 .

FIG. 1B illustrates a conventional current mirror with a cascode transistor. As depicted in FIG. 1B , the current mirror 100 includes a cascode transistor 105 . In an embodiment, the cascode transistor 105 is a PMOS transistor. In an embodiment, the cascode transistor 105 includes a channel width of N×W UNIT and a channel length of L UNIT . In another embodiment, the channel length of the cascode transistor 105 can be set to another length. Generally, the channel length is set low in order to keep the overdrive voltage V DSat and area of the cascode transistor 105 low. Further, (i) the source node of the cascode transistor 105 is connected to the drain node of the current source transistor 101 and (ii) the drain node of the cascode transistor 105 is connected to the drain node of the current mirror transistor 102 . Further, the gate node of the cascode transistor 105 receives a voltage V PC . The voltage V PC is the V GS of the cascode transistor 105 . The cascode transistor 105 acts as a gain amplifier. Specifically, the cascode transistor 105 amplifies the low output impedance at the drain node of the current source transistor 101 , resulting in a higher output impedance. Therefore, as the voltage V 1 moves (e.g., due to noise, increase in V DSat , large V T , etc.) at the drain node of the cascode transistor 105 , the voltage V 3 at the source node of the cascode transistor 105 only has to move a small amount to compensate for the movement of V 1 . Further, the cascode transistor 105 also operates in the saturated region (e.g., V DSat >V GS −V T ). Therefore, the current going through the cascode transistor 105 (e.g., the input current I IN1 ) will be independent of the V DS across the cascode transistor 105 . As such, the voltage V PC at the gate node of the cascode transistor 105 does not have to move very much in order compensate for the movement of the voltage V 1 , and, therefore, any changes in the V DS of the cascode transistor 105 , thereby isolating the V DS of the current source transistor 101 from changes at V 1 as well as V DD . Further, with a constant V DS across the current source transistor 101 , the input current I IN1 will also remain fixed. As such, the output current I OUT1 , which is meant to be a ratio of the input current I IN1 (e.g., K×I IN1 ), will also be maintained with some consistency. Further, because the current mirror 100 will be less sensitive to noise emanating from the power supply V DD , the PSRR will also be higher.

However, as mentioned above, in circuit designs with low power supply requirements (e.g., V DD <1 V), there may not be enough headroom to include the cascode transistor 105 . In lieu of the cascode transistor 105 , noise can also be mitigated by increasing the V DSat of the current mirror transistor 102 and the output current transistor 103 . In addition, the PSRR of the current mirror 100 can be improved by decreasing the V DSat of the current source transistor 101 (e.g., since the difference between V DS and V DSat will be higher). However, with a finite power supply, any increase in the V DSat voltages will likely lead to less headroom for the current source transistor 101 . Further, decreasing the V DSat of the current source transistor 101 will likely leave the device more susceptible to noise and, thus, result in worse matching between the input current I IN1 and the output current I OUT1 .

Further, as previously discussed, current compression can result if the generated input current I IN1 is high and the V DS of current mirror transistors 102 and 103 is also high (e.g., due to the higher overdrive voltage V DSat ). If the input current I IN1 is compressed, the desired ratio of the output current I OUT1 to the input current (e.g., K) will likely not hold, thereby defeating the purpose of utilizing a current mirror.

FIG. 2 illustrates a low supply current mirror in accordance with an example embodiment of the present invention. As depicted in FIG. 2 , current mirror 200 includes a first current source transistor 201 a , a second current source transistor 201 b , a first current mirror transistor 202 a , a second current mirror transistor 202 b , an output current transistor 203 , and a load 204 .

In an embodiment, the first current source transistor 201 a and the second current source transistor 201 b are PMOS transistors. In an embodiment, the first current source transistor 201 a includes a channel width of 1 W UNIT and the second current source transistor 201 b includes a channel width of (N−1)×W UNIT . Further, in an embodiment, the channel lengths of the first and second current source transistors 201 a and 201 b are both equal to Y×L UNIT . At equal channel lengths, the current matching between the input current and the output current improves. In another embodiment, the channel lengths of the first and second current source transistors 201 a and 201 b can be of different lengths. In an embodiment, each of the channel lengths is set to a long length, which also improves the current matching as well as reduces noise. In another embodiment, however, each of the channel lengths can be set to a short length. In an embodiment, the current mirror 200 includes two current input paths (e.g., I IN2A and I IN2B ). In an embodiment, (1/N) of the total generated input current will be generated by the first current source transistor 201 a (e.g., I IN2A ) and ((N−1)/N) of the total generated input current will be generated by the second current source transistor 201 b (e.g., I IN2B ).

In an embodiment, the source node of each of the first and second current source transistors 201 a and 201 b is connected to the positive power supply V DD . Further, the gate node of each of the first and second current source transistors 201 a and 201 b receives a voltage V PB . In an embodiment, the voltage V PB is the V GS of the first and second current source transistors 201 a and 201 b . Further, as depicted in FIG. 2 , the drain node of the first current source transistor 201 a is connected to the drain node of the first current mirror transistor 202 a . Further, the drain node of the second current source transistor 201 b is connected to (i) the source node of the first current mirror transistor 202 a and (ii) the drain node of the second current mirror transistor 202 b.

In an embodiment, the first and second current mirror transistors 202 a and 202 b are NMOS transistors. Further, the first current mirror transistor 202 a includes a channel width of M×W UNIT and a channel length of N×L UNIT . In an embodiment, the channel length of the first current mirror transistor 202 a is scaled by N in order to compensate for the smaller input current I IN2A (e.g., 1/N of the total generated input current) flowing through the first current mirror transistor 202 a . Further, the second current mirror transistor 202 b also includes a channel width of M×W UNIT but includes a channel length of (P−1)×L UNIT . In an embodiment, the source node of the first current mirror transistor 202 a is connected to the drain node of the second current mirror transistor 202 b . Further, the source node of the second current mirror transistor 202 b is connected to a negative power supply V SS . Further, the gate nodes of the first and second current mirror transistors 202 a and 202 b are connected to the drain node of the current mirror transistor 202 a via a short. In an embodiment, the gate nodes of the first and second current mirror transistors 202 a and 202 b receive a voltage V 1A . In an embodiment, the voltage V 1A is the V GS of the first and second current mirror transistors 202 a and 202 b . Further, as depicted in FIG. 2 , the sum of the input currents I IN2A and I IN2B flows through the second current mirror transistor 202 b.

Further, in an embodiment, similar to the first and second current mirror transistors 202 a and 202 b , the output current transistor 203 is also a NMOS transistor. In an embodiment, the output current transistor 203 includes a channel width of K×M×W UNIT and a channel length of P×L UNIT . Further, the source node of the output current transistor 203 is also connected to the negative power supply V SS . In an embodiment, the drain node of the output current transistor 203 is connected to a first end of the load 204 . Further, the gate node of the output current transistor 203 also receives the voltage V 1A . In an embodiment, the output current transistor 203 establishes an output current I OUT2 , which is a ratio of the sum of the input currents I IN2A and I IN2B (e.g., K×(I IN2A +I IN2B )). In other words, depending on the current gain coefficient K, the current mirror 200 can amplify, replicate, or reduce the sum of the input currents I IN2A and I IN2B . Specifically, the output current I OUT2 can be modified by increasing or decreasing the channel width of the output current transistor 203 by the factor K.

In an embodiment, the output current I OUT2 originates from the load 204 . In an embodiment, the load 204 could be one of: (i) a resistor, (ii) another current mirror, or (iii) any other circuit that needs to draw a current from a current source. Further, the load 204 is connected to a voltage source V L at its second end. In an embodiment, voltage source V L could be set to any arbitrary voltage.

In an embodiment, duplicates of the output current I OUT2 can be generated with additional output current transistors connected in parallel with the output current transistor 203 . In an embodiment, in order to generate duplicates of the output current I OUT2 , each of the additional output current transistors has to include the same transistor characteristics as the output current transistor 203 (e.g., same transistor type, channel length, channel width, V GS , etc.). As such, the additional output current transistors (not shown) are also NMOS transistors. Further, in an embodiment, each of the additional output current transistors is connected to: (i) the negative power supply V SS at its source node and (ii) the load 204 at its drain node. In another embodiment, the additional output transistors can be connected a plurality of other loads as well. Further, in an embodiment, similar to the output current transistor 203 , each of the gate nodes of the additional output transistors receives the voltage V 1A . In an embodiment, each of the additional output current transistors can be used to provide current for the same device. For example, the output current transistor 203 and the additional output current transistors can provide a total current of (A+1)×I OUT2 to the device, wherein A corresponds to a number of additional output currents transistors. In another embodiment, the total current from the output current transistor 203 and the additional output current transistors can also be provided to a plurality of different devices.

In an embodiment, the input current I IN2A drives the drain node of the first current mirror transistor 202 a . In an embodiment, the input current I IN2A flows through the series combination of the first current mirror transistor 202 a and the second current mirror transistor 202 b . Further, as depicted in FIG. 2 , the input current I IN2B drives: (i) the source node of the first current mirror transistor 202 a and (ii) the drain node of the second current mirror transistor 202 b . In other words, the input current I IN2B drives the midpoint of the series combination of the first current mirror transistor 202 a and the second current mirror transistor 202 b . Further, in an embodiment, the input current I IN2B also flows through the second current mirror transistor 202 b.

In an embodiment, the first current mirror transistor 202 a operates in the saturated region (e.g., V DSat >V GS −V T ). In an embodiment, the overdrive voltage V DSat of the first current mirror transistor 202 a can be increased in order to mitigate the effect of noise on the first current mirror transistor 202 a . As such, the input current I IN2A will be driving into a high voltage (e.g., V 1A ). Further, in an embodiment, similar to the current source transistor 101 of FIGS. 1A and 1B , the first current source transistor 201 a also has low impedance. Therefore, the input current I IN2A of the first current source transistor 201 a can still be affected by changes at: (i) the positive power supply V DD (e.g., due to noise or otherwise) and (ii) the voltage V 1A (e.g., due to noise, increase in V DSat , large V T , etc.). However, because the input current I IN2A is only (1/N) of the total generated input current, only (1/N) of the total generated input current will be subject to the current errors.

In an embodiment, there is no V T voltage at the source node of the first current mirror transistor 202 a or the drain node of the second current mirror transistor 202 b (e.g., the nodes that the input current I IN2B is driving into). Therefore, V 1B will be less than V 1A by at least the V T of the first current mirror transistor 202 a . In an embodiment, V 1B is essentially equivalent to the V DS of the second current mirror transistor 202 b . However, unlike the first current mirror transistor 202 a , which is operating in the saturated region (e.g., V DSat >V GS −V T ), the V DS across the second current mirror transistor 202 b is less than the difference between the voltage V GS (e.g., V 1A ) and the voltage V T of the second current mirror transistor 202 b (e.g., V DS <V GS −V T ). In an embodiment, the voltage at the drain node of the current mirror transistor 202 b (e.g., V 1B ) can be less than the voltage at the gate node (e.g., V 1A ) and still operate normally. However, unlike the first current mirror transistor 202 a , the second current mirror transistor 202 b is operating in the linear region (e.g., degeneration). In other words, the second current mirror transistor 202 b acts like a resistor (i.e., the voltage changes linearly as the current changes). In an embodiment, as compared to the input current I IN2A , the input current I IN2B is driving into a much lower voltage, e.g., V 1B . Therefore, most of the total generated input current (e.g., (N−1)/N) will see the much lower voltage (e.g., V 1B ). Accordingly, by splitting up the total generated current into: (i) a low current path seeing higher voltage and (ii) a higher current path seeing lower voltage, the current compression problem associated with the current mirror 100 is resolved. Further, because V 1B is at a much lower voltage than V 1A , there is a greater voltage difference between V PB and V 1B . Therefore, the V DS of the second current source transistor 201 b will be much larger than it would have been with the current source transistor 101 in the current mirror 100 . In an embodiment, with a higher V DS , the percentage that the V DS moves due to current error (e.g., due to noise from the positive power supply V DD or otherwise) is much less than had the V DS been smaller (e.g., as it is with the current source transistor 101 ). As such, noise from the positive power supply V DD is going to have less of an effect on most of the total generated input current (e.g., I IN2B ). Therefore, the current mirror 200 will be associated with a higher PSRR. Similarly, noise from the positive power supply V DD and the voltage V 1A in the I IN2A current path will have only a “1/N” effect on the total generated input current. As such, the PSRR for the current mirror 200 will be greater than the PSRR for the current mirror 100 by a factor of N.

FIG. 3A illustrates a specific example of the low supply current mirror of FIG. 2 . As depicted in FIG. 3A , the positive power supply V DD is set at 800 mV, the negative power supply V SS is set at 0 V (i.e., ground), the voltage V PB is set at 300 mV, the voltage V 1A is set at 500 mV, the voltage V 1B is set at 100 mV, and the voltage V L is set at 800 mV. Further, the input current I IN2A is 10 μA and the input current I IN2B is 30 μA. As such, the second current mirror transistor 202 b receives the combination of input currents I IN2A and I IN2B , i.e., 40 μA. Therefore, the generated output current I OUT2 is also equivalent to 40 μA. In an embodiment, the first current source transistor 201 a includes a channel width of 1 μm and a channel length of 0.1 μm. Further, the second current source transistor 201 b includes a channel width of 3 μm and a channel length of 0.1 μm. In an embodiment, as depicted in FIG. 3A , the first current mirror transistor 202 a can include a stack of four transistors, e.g., transistors 202 ai - 202 aiv . In an embodiment, the transistors 202 ai to 202 aiv are connected in series. Further, each of the four transistors includes a channel width of 4 μm and a channel length of 0.1 μm. In an embodiment, the second current mirror transistor 202 b includes a channel width of 4 μm and a channel length of 0.1 μm. In an embodiment, the series combination of the transistors 202 ai - 202 aiv and the second current mirror transistor 202 b is equivalent to a stack of two transistors each with a channel width of 4 μm and a channel length of 0.1 μm (see transistors 212 a and 212 b of FIG. 3B ). Further, the V GS across the transistors 202 ai to 202 aiv , which each receive 10 μA, is equivalent to the V GS of a device which (i) includes a channel width of 4 μm and a channel length of 0.1 μm (ii) and receives 40 μA. Therefore, the V GS across the transistors 202 ai to 202 aiv is equivalent to the V GS of the second current mirror transistor 202 b . Further, as depicted in FIG. 3A , transistor 203 can include a stack of two transistors, e.g., transistors 203 a and 203 b . In an embodiment, the transistors 203 a and 203 b are connected in series. Further, each of the two transistors includes a channel width of 4 μm and a channel length of 0.1 μm. In an embodiment, the device structure of the transistors 203 a and 203 b matches the device structure of transistors 212 a and 212 b of FIG. 3B (e.g., the equivalent circuit of the series combination of the transistors 202 ai - 202 aiv and the second current mirror transistor 202 b ). In an embodiment, based on the above transistor specifications (e.g., channel length, channel width, number of stacked devices), it can be deduced that N=4, W=4, P=2, and K=1. In another embodiment, instead of stacking transistors of specific channel lengths and widths, unit transistors can be stacked. In an embodiment, unit transistors include a channel width of 1 μm and a channel length of 0.1 μm. Further, the unit transistors can be (i) connected in series in order to increase the length and (ii) connected in parallel in order to increase the width.

FIG. 4 illustrates another example embodiment of the low supply current mirror. In an embodiment, the current mirror 200 further includes a cascode transistor 205 in the I IN2B current path. In an embodiment, because there is a greater voltage difference between V PB and V 1B in the current mirror 200 , there is now enough headroom to include at least one cascode transistor. In an embodiment, the cascode transistor 205 is a PMOS transistor. Further, like the second current source transistor 201 b , the cascode transistor 205 includes a channel width of (N−1)×W UNIT . Further, similar to the cascode transistor 105 , the channel length of the cascode transistor 205 is set low (e.g., L UNIT ) in order to keep the overdrive voltage V DSat and area of the cascode transistor 205 low. However, in another embodiment, the channel length of the cascode transistor 205 can be set to a long length. In an embodiment, the source node of the cascode transistor 205 is connected to the drain node of the second current source transistor 201 b , and the drain node of the cascode transistor 205 is connected to: (i) the source node of the first current mirror transistor 202 a and (ii) the drain node of the second current mirror transistor 202 b . Further, the gate node of the cascode transistor 205 receives a voltage V PBC . The voltage V PBC is the V GS of the cascode transistor 205 . In an embodiment, the voltage V PBC is less than the voltage difference between V PB and V 1B . In an embodiment, the cascode transistor 205 acts as a gain amplifier. Specifically, the cascode transistor 205 amplifies the low output impedance at the drain node of the second current source transistor 201 b , resulting in a higher output impedance. Therefore, as the voltage V 1B moves (e.g., due to noise, etc.) at the drain node of the cascode transistor 205 , the voltage at the source node of the cascode transistor 205 (e.g., V 3 ) only has to move a small amount to compensate for the voltage movement of V 1B . Further, the cascode transistor 205 operates in the saturated region (e.g., V DSat >V GS −V T ). Therefore, the current going through the cascode transistor 205 (e.g., the input current I IN2B ) will be independent of the V DS across the cascode transistor 205 . As such, the voltage V PBC at the gate node of the cascode transistor 205 does not have to move very much in order compensate for the movement of the voltage V 1B , and, therefore, any changes in the V DS of the cascode transistor 205 , thereby isolating the V DS of the current source transistor 201 b from changes at V 1B as well as V DD . Further, with a constant V DS across the current source transistor 201 b , the input current I IN2B will also remain fixed. As such, the output current I OUT2 , which is meant to be a ratio of the sum of the input currents I IN2A and I IN2B (e.g., K×(I IN2A +I IN2B )), will also be maintained with some consistency. Further, because the current mirror 200 will be less sensitive to noise emanating from the power supply V DD , it is also associated with a higher PSRR than the current mirror 200 in FIG. 2 . In another embodiment, at least one additional cascode transistor can be connected in series with the cascode transistor 205 .

In the foregoing Description of Embodiments, various features may be grouped together in a single embodiment for purposes of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claims require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the following claims are hereby incorporated into this Description of the Embodiments, with each claim standing on its own as a separate embodiment of the invention.

Moreover, it will be apparent to those skilled in the art from consideration of the specification and practice of the present disclosure that various modifications and variations can be made to the disclosed systems without departing from the scope of the disclosure, as claimed. Thus, it is intended that the specification and examples be considered as exemplary only, with a true scope of the present disclosure being indicated by the following claims and their equivalents.