Power supply apparatus for setting target times of control signals

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-129524, filed on Jun. 29, 2015, which is incorporated herein by reference in its entirety.

This disclosure relates to a power supply apparatus.

A power supply apparatus may include: first and second power supplies; and a converter having first to fourth switching elements, first to fourth diodes, and first and second reactors and connected to the first power supply, the second power supply, and a load and that boosts power from the first and second power supplies and supplies the power to the load by controlling the first to fourth switching elements (see Japanese Patent Application Publication No. 2012-070514, for example). This power supply apparatus generates control signals for the first to fourth switching elements based on a logical operation of a first control pulse signal for controlling output of the first power supply and a second control pulse signal for controlling output of the second power supply, and uses these control signals to execute switching control of the first to fourth switching elements. At this time, it is adapted such that rise timing of the first control pulse signal overlaps rise timing of the second control pulse signal.

The above-described power supply apparatus is required to sequentially perform the logical operation by an arithmetic unit or to be provided with a logic circuit between the arithmetic unit and the first to fourth switching elements in order to generate the control signals for the first to fourth switching elements from the first and second control pulse signals. Such a problem arises that a processing load of the arithmetic unit becomes relatively large in the former case and the number of components of the power supply apparatus becomes relatively large in the latter case.

This disclosure describes a power supply apparatus that can execute switching control of four switches of a converter and that does not have to sequentially perform a logical operation by a control unit for controlling the converter or provide a logic circuit between the control unit and the four switches of the converter.

Embodiments of this disclosure may include a power supply apparatus that includes: a first power supply; a second power supply; a converter that is connected to a first power line, to which the first power supply is connected, a second power line, to which the second power supply is connected, and a third power line, to which a load is connected, and can boost and supply power of the first and second power lines to the third power line; and a control unit for controlling the converter, in which the converter has: first to fourth switches that are connected in series between a positive bus bar of the third power line and negative bus bars of the first and third power lines; first to fourth diodes that are connected in parallel to the first to fourth switches, respectively; a first reactor that is connected to a connection point between the second switch and the third switch and a positive bus bar of the first power line; and a second reactor that is connected to a connection point between the first switch and the second switch and a positive bus bar of the second power line, in which a connection point between the third switch and the fourth switch is connected to a negative bus bar of the second power line, in which the control unit sets target timing for switching of each of the first to fourth switches in one cycle of first and second carrier waves in accordance with two of timing in the one cycle of the first carrier wave that are defined by a first duty ratio for controlling first power supplied from the first power line to the third power line and the first carrier wave for controlling said first power and two of timing in the one cycle of the second carrier wave that are defined by a second target duty ratio for controlling second power supplied from the second power line to the third power line and the second carrier wave that is a carrier wave for controlling said second power and is in the same cycle as the first carrier wave, and outputs a switching command to the first to fourth switch sides in accordance with each of the set target timing.

In an embodiment, the control unit may set the target timing for switching of each of the first to fourth switches in the one cycle of the first and second carrier waves in accordance with the two of the timing in the one cycle of the first carrier wave that is defined by the first target duty ratio for controlling the first power supplied from the first power line to the third power line and the first carrier wave for controlling the first power and the two of the timing in the one cycle of the second carrier wave that is defined by the second target duty ratio for controlling the second power supplied from the second power line to the third power line and the second carrier wave that is the carrier wave for controlling the second power and is in the same cycle as the first carrier wave, and outputs the switching command to the first to fourth switch sides in accordance with each of the set target timing. In this way, switching control of the first to fourth switches can be executed without sequentially performing logical operations in the control unit and providing a logic circuit between the control unit and the first to fourth switches. As a result, compared to a power supply apparatus in which the control unit sequentially performs the logical operations, a processing load of the control unit can be reduced. In addition, compared to a power supply apparatus that is provided with the logic circuit, the number of components of the power supply apparatus can be reduced.

In such a power supply apparatus, the first carrier wave may be a sawtooth wave or a reverse-sawtooth wave, the second carrier wave may be a sawtooth wave or a reverse-sawtooth wave, reset timing thereof may match that of the first carrier wave, the two of the timing in the one cycle of the first carrier wave may be the reset timing and timing other than said reset timing, the two of the timing in the one cycle of the second carrier wave may be the reset timing and timing other than said reset timing, and the control unit may set the target timing of the first to fourth switches in the one cycle of the first and second carrier waves in accordance with three of timing that are the reset timing and two of the timing other than the reset timing in the one cycle of the first and second carrier waves. In this way, the target timing of the first to fourth switches in the one cycle of the first and second carrier waves can be set in accordance with the three of the timing in the cycle.

In the power supply apparatus in which the target timing of the first to fourth switches in the one cycle of the first and second carrier waves are set in accordance with the three of the timing in the one cycle of the first and second carrier waves, the control unit may separately set the target timing of each of the first to fourth switches in the one cycle of the first and the second carrier waves in accordance with the three of the timing in the one cycle of the first and second carrier waves and output the switching command to the corresponding switch sides of the first to fourth switches when time reaches each of the set target timing. In this way, the first to fourth switches can be controlled by separately setting the target timing of each of the first to fourth switches in the one cycle of the first and second carrier waves.

In the power supply apparatus in which the target timing of each of the first to fourth switches in the one cycle of the first and second carrier waves are separately set, the control unit may separately set the target timing for each of the first to fourth switches in the one cycle of the first and second carrier waves in accordance with the three of the timing in the one cycle of the first and second carrier waves and either a magnitude relationship between a sum of the first and second target duty ratios and a value 1 or a magnitude relationship between the first target duty ratio and the second target duty ratio. In this case, the control unit may separately set the target timing for each of the first to fourth switches in the one cycle of the first and second carrier waves in accordance with the three of the timing in the one cycle of the first and second carrier waves, either the magnitude relationship between the sum of the first and second target duty ratios and the value 1 or the magnitude relationship between the first target duty ratio and the second target duty ratio, whether the first carrier wave is the sawtooth wave or the reverse-sawtooth wave, and whether the second carrier wave is the sawtooth wave or the reverse-sawtooth wave.

In addition, in the power supply apparatus in which the target timing for each of the first to fourth switches in the one cycle of the first and second carrier waves are separately set, the control unit may separately set the target timing for each of the first to fourth switches in consideration of a dead time that is required for switching of each of the first to fourth switches. In this way, the target timing for each of the first to fourth switches in the one cycle of the first and second carrier waves can be separately set in consideration of the dead time.

In the power supply apparatus in which the target timing of the first to fourth switches in the one cycle of the first and second carrier waves are set in accordance with the three of the timing in the one cycle of the first and second carrier waves, the control unit may set the three of the timing in the one cycle of the first and second carrier waves as three of the target timing of the first to fourth switches in the one cycle of the first and second carrier waves, may set a combination of ON/OFF states of the first to fourth switches for each of the three of the target timing in the one cycle of the first and second carrier waves, and may output the switching command or a keeping command to each side of the first to fourth switches in accordance with the set combination and the ON/OFF states of the first to fourth switches when the time reaches each of the set target timing. In this way, the first to fourth switches can be controlled by setting the combination of the ON/OFF states of the first to fourth switches for each of the three of the target timing in the one cycle of the first and second carrier waves.

In the power supply apparatus in which the combination of the ON/OFF states of the first to fourth switches is set for each of the three of the target timing in the one cycle of the first and second carrier waves, the control unit may set the combination for each of the three of the target timing in the one cycle of the first and second carrier waves in accordance with the magnitude relationship between the sum of the first and second target duty ratios and the value 1 or the magnitude relationship between the first target duty ratio and the second target duty ratio. In this case, the control unit may set the combination for each of the three of the target timing in the one cycle of the first and second carrier waves in accordance with either the magnitude relationship between the sum of the first and second target duty ratios and the value 1 or the magnitude relationship between the first target duty ratio and the second target duty ratio, whether the first carrier wave is the sawtooth wave or the reverse-sawtooth wave, and whether the second carrier wave is the sawtooth wave or the reverse-sawtooth wave.

In the power supply apparatus in which the combination of the ON/OFF states of the first to fourth switches is set for each of the three of the target timing in the one cycle of the first and second carrier waves, a dead time generation circuit for adding the dead time that may be adopted for switching of each of the first to fourth switches to output from the control unit and outputting the output, to which the dead time is added, to the first to fourth elements may be provided. In this embodiment, the dead time generation circuit may add the dead time to the output from the control unit and output the output when the output is the switching command from OFF to ON. The dead time generation circuit may output the output from the control unit without adding the dead time to the output when the output is the switching command from ON to OFF or the keeping command.

In the power supply apparatus, the control unit may generate a first control signal for controlling the first power by using the first target duty ratio and the first carrier wave, may generate a second control signal for controlling the second power by using the second target duty ratio and the second carrier wave, may set rise and fall timing of the first control signal as the two of the timing in the one cycle of the first carrier wave, and may set rise and fall timing of the second control signal as the two of the timing in the one cycle of the second carrier wave.

Some embodiments may include a power supply apparatus that includes: a first power supply; a second power supply; a converter that is connected to a first power line, to which the first power supply is connected, a second power line, to which the second power supply is connected, and a third power line, to which a load is connected, and can boost and supply power of the first and second power lines to the third power line; and a control unit for controlling the converter, in which the converter has: first to fourth switches that are connected in series between a positive bus bar of the third power line and negative bus bars of the first and third power lines; first to fourth diodes that are connected in parallel to the first to fourth switches, respectively; a first reactor that is connected to a connection point between the second switch and the third switch and a positive bus bar of the first power line; and a second reactor that is connected to a connection point between the first switch and the second switch and a positive bus bar of the second power line, in which a connection point between the third switch and the fourth switch is connected to a negative bus bar of the second power line, and in which the control unit sets target timing for switching of each of the first to fourth switches in one cycle of first and second carrier waves in accordance with rise and fall timing in one cycle of a first control signal for controlling the first power that is supplied from the first power line to the third power line and rise and fall timing in one cycle of a second control signal for controlling the second power that is supplied from the second power line to the third power line, and outputs a switching command to the first to fourth switch sides in accordance with each of the set target timing.

In the power supply apparatus, the control unit sets the target timing for switching of each of the first to fourth switches in the one cycle of the first and second carrier waves in accordance with the rise and fall timing in the one cycle of the first control signal for controlling the first power that is supplied from the first power line to the third power line and the rise and fall timing in the one cycle of the second control signal for controlling the second power that is supplied from the second power line to the third power line, and outputs the switching command to the first to fourth switch sides in accordance with each of the set target timing. In this way, the switching control of the switches can be executed without sequentially performing the logical operations by the control unit and providing the logic circuit between the control unit and the first to fourth switches. As a result, compared to the power supply apparatus in which the control unit sequentially performs the logical operations, the processing load of the control unit can be reduced. In addition, compared to the power supply apparatus that is provided with the logic circuit, the number of components of the power supply apparatus can be reduced.

Exemplary embodiments of the disclosure will be described below with reference to the accompanying drawings, in which like numerals denote like elements, and wherein:

FIG. 1 is a configuration diagram that schematically shows a configuration of a power supply apparatus 20 of a first embodiment;

FIG. 2 is an explanatory view that shows a situation where a converter 40 functions as a first power supply converter in accordance with disclosed embodiments;

FIG. 3 is an explanatory view that shows a situation where the converter 40 functions as the first power supply converter in accordance with disclosed embodiments;

FIG. 4 is an explanatory view that shows a situation where the converter 40 functions as a second power supply converter in accordance with disclosed embodiments;

FIG. 5 is an explanatory view that shows a situation where the converter 40 functions as the second power supply converter in accordance with disclosed embodiments;

FIG. 6 is a configuration diagram that schematically shows a configuration of a power supply apparatus 20 B of a comparative example in accordance with disclosed embodiments;

FIG. 7 is an explanatory view that shows one example of a timing chart in the power supply apparatus 20 B of the comparative example in accordance with disclosed embodiments;

FIG. 8 is a flowchart that shows one example of a processing routine executed by an electronic control unit 60 of the first embodiment;

FIG. 9 is an explanatory table that shows target timing of each of edges of control signals S 1 a to S 4 a for switches S 1 to S 4 in a next cycle of carrier waves Ca 1 , Ca 2 in accordance with disclosed embodiments;

FIG. 10 is an explanatory view that shows one example of a timing chart in the power supply apparatus 20 of the first embodiment;

FIG. 11 is a flowchart that shows one example of a processing routine of a modified example in accordance with disclosed embodiments;

FIG. 12 is an explanatory table that shows target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 in the modified example in accordance with disclosed embodiments;

FIG. 13 is an explanatory table that shows target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 in the modified example in accordance with disclosed embodiments;

FIG. 14 is an explanatory table that shows target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 in the modified example in accordance with disclosed embodiments;

FIG. 15 is a configuration diagram that schematically shows a configuration of a power supply apparatus 120 of a second embodiment in accordance with disclosed embodiments;

FIG. 16 is a flowchart that shows one example of a processing routine executed by the electronic control unit 60 of the second embodiment in accordance with disclosed embodiments;

FIG. 17 is an explanatory table that shows target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 and a combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 in accordance with disclosed embodiments;

FIG. 18 is an explanatory view that shows a situation where the combinations of the control signals S 1 a to S 4 a are set in a matching output section in the case where a sum of a target duty ratio Du 1 * and a target duty ratio Du 2 * is smaller than a value 1 in accordance with disclosed embodiments;

FIG. 19 is an explanatory view that shows one example of a timing chart in the power supply apparatus 120 of the second embodiment in accordance with disclosed embodiments;

FIG. 20 is a flowchart that shows one example of a processing routine of a modified example in accordance with disclosed embodiments;

FIG. 21 is an explanatory table that shows the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 of the modified example and a combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 in accordance with disclosed embodiments;

FIG. 22 is an explanatory table that shows the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 of the modified example and a combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 in accordance with disclosed embodiments; and

FIG. 23 is an explanatory table that shows the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 of the modified example and a combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 in accordance with disclosed embodiments.

Next, a mode in accordance with the disclosure will be described by using embodiments.

FIG. 1 is a configuration diagram that schematically shows a configuration of a power supply apparatus 20 of a first embodiment of the disclosure. The power supply apparatus 20 of the first embodiment is configured as an apparatus for supplying power to a load 10 , and, as shown in the drawing, includes a battery 22 as a first power supply, a battery 32 as a second power supply, a converter 40 , and an electronic control unit 60 . Noted that, as the load 10 , a motor, an inverter for driving this motor, and the like can be considered.

The converter 40 is connected to a power line 24 to which the battery 22 is connected, a power line 34 to which the battery 32 is connected, and a power line 14 to which the load 10 is connected, and is configured to be able to boost power of the power lines 24 , 34 (the batteries 22 , 32 ) and supply the power to the power line 14 (the load 10 ). This converter 40 includes switches S 1 to S 4 , diodes D 1 to D 4 , and reactors L 1 , L 2 . The switches S 1 to S 4 each may be an insulated gate bipolar transistor (IGBT), for example, and are sequentially connected in series between a positive bus bar 14 a of the power line 14 and negative bus bars 14 b , 24 b of the power lines 14 , 24 . The diodes D 1 to D 4 are respectively connected to the switches S 1 to S 4 in parallel in a reverse direction. The first reactor L 1 is connected to a connection point C 1 between the switch S 2 and the switch S 3 and to a positive bus bar 24 a of the power line 24 . The second reactor L 2 is connected to a connection point C 2 between the switch S 1 and the switch S 2 and to a positive bus bar 34 a of the power line 34 . Furthermore, a connection point C 3 between the switch S 3 and the switch S 4 is connected to a negative bus bar 34 b of the power line 34 . Noted that a smoothing capacitor 16 is connected to the power line 14 , a smoothing capacitor 26 is connected to the power line 24 , and a smoothing capacitor 36 is connected to the power line 34 .

The electronic control unit 60 is configured as a microprocessor that has a CPU as a central component, and includes, in addition to the CPU, a ROM for storing a processing program, a RAM for temporarily storing data, a timer for timekeeping, a matching output section for performing specific output at a time when a time keeping value of the timer matches a setting value, and input/output ports.

The electronic control unit 60 receives signals from various sensors via the input port. The following can be raised as the signals received by the electronic control unit 60 :

A voltage VH of the capacitor 16 (the power line 14 ) from a voltage sensor 16 a that is attached between terminals of the capacitor 16 . A voltage VL 1 of the capacitor 26 (the power line 24 ) from a voltage sensor 26 a that is attached between terminals of the capacitor 26 . A current IL 1 from a current sensor 41 that is attached between the connection point between the switch S 2 and the switch S 3 and the reactor L 1 . A current IL 2 from a current sensor 42 that is attached between the connection point between the switch S 1 and the switch S 2 and the reactor L 2 . A voltage VL 2 of the capacitor 36 (the power line 34 ) from a voltage sensor 36 a that is attached between terminals of the capacitor 36 . A power supply voltage VB 1 from a voltage sensor that is attached between terminals of the battery 22 . A battery current IB 1 from a current sensor that is attached to the positive electrode terminal of the battery 22 . A power supply voltage VB 2 from a voltage sensor that is attached between terminals of the battery 32 . A battery current IB 2 from a current sensor that is attached to the positive electrode terminal of the battery 32 .

The electronic control unit 60 outputs control signals S 1 a to S 4 a for the switches S 1 to S 4 via the output port. In addition, the electronic control unit 60 computes states of charge SOC 1 , SOC 2 of the batteries 22 , 32 based on the battery current IB 1 and the battery current IB 2 from the current sensors. Each of the states of charge SOC is a ratio of power capacity that can be discharged from each of the batteries 22 , 32 to full capacity of each of the batteries 22 , 32 .

In the power supply apparatus 20 of the first embodiment that is configured as described above, the converter 40 functions as a converter in which the switches S 1 , S 2 serve as an upper arm and the switches S 3 , S 4 serve as a lower arm (hereinafter referred to as a “first power supply converter”) between the power line 24 and the power line 14 , that is, for the battery 22 .

In this case, in a state where the lower arm (the switches S 3 , S 4 ) is ON and the upper arm (the switches S 1 , S 2 ) is OFF (hereinafter referred to as a “first storage state”), as shown in FIG. 2 , a circuit through which a current flows in order of the battery 22 , the positive bus bar 24 a of the power line 24 , the reactor L 1 , the switch S 3 , the switch S 4 , the negative bus bar 24 b of the power line 24 , and the battery 22 (hereinafter referred to as a “first storage circuit”) is formed. At this time, energy is stored in the reactor L 1 . Then, when the first storage state is switched to a state where the lower arm (the switches S 3 , S 4 ) is OFF and the upper arm (the switches S 1 , S 2 ) is ON (hereinafter referred to as a “first discharge state”), as shown in FIG. 3 , the first storage circuit is switched to a circuit through which the current flows in order of the battery 22 , the positive bus bar 24 a of the power line 24 , the reactor L 1 , the diode D 2 , the diode D 1 , the positive bus bar 14 a of the power line 14 , the load 10 , the negative bus bar 14 b of the power line 14 , the negative bus bar 24 b of the power line 24 , and the battery 22 (hereinafter referred to as a “first discharge circuit”). At this time, together with energy of the power line 24 (the battery 22 ), the energy of the reactor L 1 is supplied to the power line 14 (the load 10 ). Thus, the first storage circuit and the first discharge circuit are alternately formed by alternately generating the first storage state and the first discharge state. In this way, the power of the power line 24 is boosted and supplied to the power line 14 .

In addition, the converter 40 functions as a converter in which the switches S 1 , S 4 serve as an upper arm and the switches S 2 , S 3 serve as a lower arm (hereinafter referred to as a “second power supply converter”) between the power line 34 and the power line 14 , that is, for the battery 32 .

In this case, in a state where the lower arm (the switches S 2 , S 3 ) is ON and the upper arm (the switches S 1 , S 4 ) is OFF (hereinafter referred to as a “second storage state”), as shown in FIG. 4 , a circuit through which a current flows in order of the battery 32 , the positive bus bar 34 a of the power line 34 , the reactor L 2 , the switch S 2 , the switch S 3 , the negative bus bar 34 b of the power line 34 , and the battery 32 (hereinafter referred to as a “second storage circuit”) is formed. At this time, energy is stored in the reactor L 2 . Then, when the second storage state is switched to a state where the lower arm (the switches S 2 , S 3 ) is OFF and the upper arm (the switches S 1 , S 4 ) is ON (hereinafter referred to as a “second discharge state”), as shown in FIG. 5 , the second storage circuit is switched to a circuit through which the current flows in order of the battery 32 , the positive bus bar 34 a of the power line 34 , the reactor L 2 , the diode D 1 , the positive bus bar 14 a of the power line 14 , the load 10 , the negative bus bar 14 b of the power line 14 , the diode D 4 , the negative bus bar 34 b of the power line 34 , and the battery 32 (hereinafter referred to as a “second discharge circuit”). At this time, together with energy of the power line 34 (the battery 32 ), the energy of the reactor L 2 is supplied to the power line 14 (the load 10 ). Thus, the second storage circuit and the second discharge circuit are alternately formed by alternately generating the second storage state and the second discharge state. In this way, the power of the power line 34 is boosted and supplied to the power line 14 .

In light of these, in the first embodiment, the switches S 1 to S 4 of the converter 40 are subjected to switching control such that the voltage VH of the power line 14 becomes a target voltage VH* thereof (a difference between the target voltage VH* and the voltage VH is eliminated) by a function as the first power supply converter and that the current IL 2 flowing through the reactor L 2 becomes a target current IL 2 * (a difference between the target current IL 2 * and the current IL 2 is eliminated) by a function as the second power supply converter. Here, the target voltage VH* of the power line 14 can be set on the basis of target power of the load 10 (target torque and a rotational speed of a motor in the case where the load 10 is the motor) and the like. In addition, the target current IL 2 * of the reactor L 2 can be set on the basis of the states of charge SOC 1 , SOC 2 of the batteries 22 , 32 and the like.

Here, before describing the switching control of the switches S 1 to S 4 in the power supply apparatus 20 of the first embodiment, switching control of switches S 1 to S 4 in a power supply apparatus 20 B of a comparative example will be described. As shown in FIG. 6 , the power supply apparatus 20 B of the comparative example includes, in addition to a hardware configuration of the power supply apparatus 20 of the first embodiment, a logic circuit 50 B and a dead time generation circuit 52 B between an electronic control unit 60 B and the switches S 1 to S 4 . In addition, the electronic control unit 60 B in the power supply apparatus 20 B of the comparative example differs from the electronic control unit 60 in the power supply apparatus 20 of the first embodiment in a point that the electronic control unit 60 B outputs control signals B 1 U, B 1 L, B 2 U, B 2 L for upper and lower arms of first and second power supply converters, which will be described below, instead of the control signals S 1 a to S 4 a for the switches S 1 to S 4 .

FIG. 7 is an explanatory view that shows one example of a timing chart in the power supply apparatus 20 B of the comparative example. In the comparative example, a sawtooth wave is used as a carrier wave Ca 1 for controlling first power that is supplied from a power line 24 (a battery 22 ) to a power line 14 (a load 10 ), and a reverse-sawtooth wave that is in the same cycle as the carrier wave Ca 1 and whose reset timing matches that of the carrier wave Ca 1 is used as a carrier wave Ca 2 for controlling second power that is supplied from a power line 34 (a battery 32 ) to the power line 14 (the load 10 ). Here, the sawtooth wave means a waveform that repeats an increase from a value 0 to a value 1 and reset to the value 0, and the reverse-sawtooth wave means a waveform that repeats a decrease from a value 1 to a value 0 and reset to the value 1. In addition, in FIG. 7 , “τw” indicates a time that corresponds to one cycle of the carrier waves Ca 1 , Ca 2 (a cycle time), and “Tw” indicates final time of a current cycle of the carrier waves Ca 1 , Ca 2 (reset timing). Thus, a range that is later than time Tw−τw) and before the time Tw corresponds to the current cycle of the carrier waves Ca 1 , Ca 2 , and a range that is later than the time Tw and before time (Tw+τw) corresponds to a next cycle of the carrier waves Ca 1 , Ca 2 .

In this comparative example, in the current cycle of the carrier waves Ca 1 , Ca 2 , the electronic control unit 60 B first obtains a voltage VH of the power line 14 from a voltage sensor 16 a and a current IL 2 that flows through a reactor L 2 from a current sensor 42 . Next, the electronic control unit 60 B sets a target duty ratio Du 1 * of the first power supply converter in the next cycle of the carrier wave Ca 1 such that the voltage VI-H of the power line 14 becomes a target voltage VH*, and sets a target duty ratio Du 2 * of the second power supply converter in the next cycle of the carrier wave Ca 2 such that the current IL 2 flowing through the reactor L 2 becomes a target current IL 2 *. The target duty ratios Du 1 *, Du 2 * are used to control the above-described first and second power.

Then, in the next cycle of the carrier waves Ca 1 , Ca 2 , the electronic control unit 60 B sequentially generates the control signals B 1 U, B 1 L, B 2 U, B 2 L for the upper and lower arms of the first and second power supply converters on the basis of the target duty ratios Du 1 *, Du 2 * and the carrier waves Ca 1 , Ca 2 of the first and second power supply converters, and outputs the control signals B 1 U, B 1 L, B 2 U, B 2 L to the logic circuit 50 B. A method for generating the control signals B 1 U, B 1 L, B 2 U, B 2 L is specifically as will be described below. The control signal B 1 L for the lower arm of the first power supply converter is generated such that the lower arm of the first power supply converter is switched from ON to OFF at timing at which the carrier wave Ca 1 and the target duty ratio Du 1 * become equal to each other (time (Tw+τd 1 )) during the increase of the carrier wave Ca 1 and that the lower arm of the first power supply converter is switched from OFF to ON at reset timing of the carrier wave Ca 1 (time (Tw+τw)). The control signal B 1 U for the upper arm of the first power supply converter is generated so as to become symmetrical (complementary output) to the control signal B 1 L for the lower arm of the first power supply converter. The control signal B 2 L for the lower arm of the second power supply converter is generated such that the lower arm of the second power supply converter is switched from OFF to ON at timing at which the carrier wave Ca 2 and the target duty ratio Du 2 * become equal to each other (time (Tw+τw−τd 2 )) during a decrease of the carrier wave Ca 2 and that the lower arm of the second power supply converter is switched from ON to OFF at reset timing (the time (Tw+τw)) of the carrier wave Ca 2 . The control signal B 2 U for the upper arm of the second power supply converter is generated so as to become symmetrical (complementary output) to the control signal B 2 L for the lower arm of the second power supply converter. Here, “τd 1 ” is a time that is obtained by multiplying the cycle time τw of the carrier wave Ca 1 by the target duty ratio Du 1 *, and corresponds to an ON time of the control signal B 1 L for the lower arm of the first power supply converter in the cycle time τw of the carrier wave Ca 1 . In addition, “τd 2 ” is a time that is obtained by multiplying the cycle time Tw of the carrier wave Ca 2 by the target duty ratio Du 2 *, and corresponds to an ON time of the control signal B 2 L for the lower arm of the second power supply converter in the cycle time τw of the carrier wave Ca 2 .

The logic circuit 50 B is configured by using plural OR elements, generates control signals S 1 x to S 4 x for the switches S 1 to S 4 based on the control signals B 1 U, B 1 L, B 2 U, B 21 , for the upper and lower arms of the first and second power supply converters that are transmitted from the electronic control unit 60 B, and outputs these control signals S 1 x to S 4 x to the dead time generation circuit 52 B. As shown in FIG. 6 , a method for generating the control signals S 1 x to S 4 x is specifically as will be described below. The control signal S 1 x for the switch S 1 is generated as a logical disjunction of the control signals B 1 U, B 2 U. This is based on a fact that the switch S 1 forms a part of each of the upper arms of the first and second power supply converters. The control signal S 2 x of the switch S 2 is generated as a logical disjunction of the control signals B 1 U, B 2 L. This is based on a fact that the switch S 2 forms a part of the upper arm of the first power supply converter and also forms a part of the lower arm of the second power supply converter. The control signal S 3 x of the switch S 3 is generated as a logical disjunction of the control signals B 1 L, B 2 L. This is based on a fact that the switch S 3 forms a part of each of the lower arms of the first and second power supply converters. The control signal S 4 x of the switch S 4 is generated as a logical disjunction of the control signals B 1 L, B 2 U. This is based on a fact that the switch S 4 forms a part of the lower arm of the first power supply converter and also forms a part of the upper arm of the second power supply converter.

The dead time generation circuit 52 B is configured by using a resistor, a diode, and a capacitor, generates control signals S 1 y to S 4 y for the switches S 1 to S 4 by adding a dead time that is required for switching of each of the switches S 1 to S 4 (a time required to avoid a short circuit between the positive bus bar 14 a and the negative bus bar 14 b of the power line 14 ) to each of the control signals S 1 x to S 4 x for the switches S 1 to S 4 that are transmitted from the logic circuit 50 B, and outputs these control signals S 1 y to S 4 y to the switches S 1 to S 4 . A method for generating the control signals S 1 y to S 4 y is specifically as will be described below. The control signals S 1 y to S 4 y are generated such that the control signals S 1 y to S 4 y are switched from OFF (Low) to ON (High) in a delayed manner from the control signals S 1 x to S 4 x by the dead time in the case where each of the control signals S 1 x to S 4 x is switched from OFF to ON. In addition, the control signals S 1 y to S 4 y are generated such that the control signals S 1 x to S 4 x respectively match the control signals S 1 y to S 4 y for times other than the above case.

As described above, in a case of the comparative example, the logic circuit 50 and the dead time generation circuit 52 B have to be provided between the electronic control unit 60 B and the switches S 1 to S 4 . On the contrary, it is considered that the logic circuit 50 B is not provided and the electronic control unit 60 B sequentially performs logical operations that correspond to processing in the logic circuit 50 B. However, such a problem that a processing load of the electronic control unit 60 B becomes relatively large arises in this case. Thus, it has been requested that the switching control of the switches S 1 to S 4 can be executed without providing the logic circuit 50 B and sequentially performing the logical operations that correspond to the processing in the logic circuit 50 B by the electronic control unit 60 B.

Next, a description will be made on the switching control of the switches S 1 to S 4 in the power supply apparatus 20 of the first embodiment. Similar to the comparative example, in the first embodiment, the sawtooth wave is used as the carrier wave Ca 1 , and the reverse-sawtooth wave that is in the same cycle as the carrier wave Ca 1 and whose reset timing matches that of the carrier wave Ca 1 is used as the carrier wave Ca 2 . FIG. 8 is a flowchart that shows one example of a processing routine executed by the electronic control unit 60 of the first embodiment. This routine is executed when the voltage VH of the power line 14 from the voltage sensor 16 a and the current IL 2 flowing through the reactor L 2 from the current sensor 42 are obtained in the current cycle of the carrier waves Ca 1 , Ca 2 .

Once the processing routine in FIG. 8 is executed, the electronic control unit 60 first sets the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 (step S 100 ). This processing can be executed in a similar manner to that in the above-described comparative example.

Next, based on the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 , target timing of each of edges (rise and fall) of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the cycle are separately set (step S 110 ). FIG. 9 is an explanatory table that shows the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 . “Tw”, “τd 1 ”, and “τd 2 ” in FIG. 9 have been described above. “τdt” is the dead time. As shown in FIG. 9 , the target timing of each of the edges of the control signals S 1 a to S 4 a differ among a case where a sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than a value 1, a case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is larger than the value 1, and a case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is equal to the value 1.

In FIG. 9 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1, the target timing of each of the edges of the control signals S 1 a to S 4 a are set as will be described below. Because the switch S 1 is kept ON, the target timing of the edges is not set for the control signal S 1 a for the switch S 1 . For the control signal S 2 a for the switch S 2 , time (Tw+τd 1 +τdt) is set as target rise timing, and the time (Tw+τw) is set as target fall timing. For the control signal S 3 a for the switch S 3 , time (τw+τd 1 ) is set as target fall timing, and time (Tw+τw−τd 2 +τdt) is set as target rise timing. For the control signal S 4 a for the switch S 4 , the time (Tw+τw−τd 2 ) is set as target fall timing, and time (Tw+τw+τdt) is set as target rise timing.

In addition, in FIG. 9 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is larger than the value 1, the target timing of each of the edges of the control signals S 1 a to S 4 a is set as will be described below. For the control signal S 1 a for the switch S 1 , the time (Tw+τw−τd 2 ) is set as the target fall timing, and the time (Tw+τd 1 +τdt) is set as the target rise timing. For the control signal S 2 a for the switch S 2 , the time (Tw+τw−τd 2 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing. Because the switch S 3 is kept ON, the target timing of the edges is not set for the control signal S 3 a for the switch S 3 . For the control signal S 4 a for the switch S 4 , the time (Tw+τd 1 ) is set as the target fall timing, and time (Tw+τw+τdt) is set as the target rise timing.

Furthermore, in FIG. 9 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is equal to the value 1, the target timing of each of the edges of the control signals S 1 a to S 4 a is set as will be described below. Because the switch S 1 is kept ON, the target timing of the edges is not set for the control signal S 1 a for the switch S 1 . For the control signal S 2 a for the switch S 2 , the time (Tw+τd 1 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing. Because the switch S 3 is kept ON, the target timing of the edges is not set for the control signal S 3 a for the switch S 3 . For the control signal S 4 a for the switch S 4 , the time (Tw+τw−τd 2 ) is set as the target fall timing, and the time (Tw+τw+τdt) is set as the target rise timing.

As described above, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 can appropriately be set in accordance with magnitude relationships between the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * and the value 1. Noted that, in any case, the time (Tw+τw+τdt) is not time in the next cycle of the carrier waves Ca 1 , Ca 2 ; however, the time (Tw+τw+τdt) is time obtained by adding the dead time τdt to the time (Tw+τw) and thus is treated as the time in the next cycle of the carrier waves Ca 1 , Ca 2 in the first embodiment.

Then, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 is set in the matching output section (step S 120 ), and this routine is terminated. Thereafter, when the timekeeping value of the timer reaches the target timing of each of the edges of the control signals S 1 a to S 4 a , output of the corresponding control signal is switched from OFF (Low) to ON (High) or from ON to OFF.

Here, the processing in above-described step S 110 will be described. The case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1 is considered. In this case, as it is understood from FIG. 7 that has been used for the description of the comparative example, some of the control signals S 1 x to S 4 x for the switches S 1 to S 4 are switched between ON and OFF at each of three of time (the timing) of the time (Tw+τd 1 ), the time (Tw+τw−τd 2 ), and the time (Tw+τw) in the next cycle of the carrier waves Ca 1 , Ca 2 . The details thereon are as will be described below. At the time (Tw−τd 1 ), the control signal S 2 x for the switch S 2 is switched from OFF to ON, and the control signal S 3 x for the switch S 3 is switched from ON to OFF. In addition, at the time (Tw+τw−τd 2 ), the control signal S 3 x for the switch S 3 is switched from OFF to ON, and the control signal S 4 x for the switch S 4 is switched from ON to OFF. Furthermore, at the time (Tw+τw), the control signal S 2 x for the switch S 2 is switched from ON to OFF, and the control signal S 4 x for the switch S 4 is switched from OFF to ON. Based on these, and further in consideration of the dead time τdt, the target timing of each of the edges of the control signals S 1 a to S 4 a is defined in FIG. 9 . Accordingly, by separately setting the target timing of each of the edges of the control signals S 1 a to S 4 a by using FIG. 9 , waveforms of the control signals S 1 a to S 4 a can conform to waveforms of the control signals S 1 y to S 4 y (the control signals obtained by adding the dead time to the control signals S 1 x to S 4 x ) in the comparative example. For example, regarding the control signal S 2 a for the switch S 2 , the waveform of the control signal S 2 a can conform to the waveform of the control signal S 2 y in the comparative example by setting rise time (Tw+τd 1 +τdt) of the control signal S 2 y as the target rise timing of the control signal S 2 a and setting fall time (Tw+τw) of the control signal S 2 y as the target fall timing of the control signal S 2 a . The same idea as that in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1 can be applied to the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is larger than the value 1 and the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is equal to the value 1.

By adopting the method as described above, the switching control of the switches S 1 to S 4 can be executed by outputting the control signals S 1 a to S 4 a that conform to the control signals S 1 y to S 4 y in the comparative example to the switches S 1 to S 4 without providing the logic circuit and sequentially performing the logical operations that correspond to the processing in the logic circuit, and further without providing the dead time generation circuit. As a result, compared to a power supply apparatus that is provided with the logic circuit and the dead time generation circuit, the number of components of the power supply apparatus 20 can be reduced. In addition, compared to a power supply apparatus in which an electronic control unit sequentially performs the logical operations, a processing load of the electronic control unit 60 can be reduced.

Noted that, in the case where the reset timing of the carrier waves Ca 1 , Ca 2 do not match each other, the target timing of each of the edges of the control signals S 1 a to S 4 a has to be set separately in accordance with four of the timing in the next cycle of the carrier wave Ca 1 . On the contrary, because the reset timing of the carrier waves Ca 1 , Ca 2 match each other in the first embodiment, the target timing of each of the edges of the control signals S 1 a to S 4 a only has to be set separately in accordance with three of the timing in the next cycle of the carrier wave Ca 1 .

FIG. 10 is an explanatory view that shows one example of a timing chart in the power supply apparatus 20 of the first embodiment. Differing from the comparative example, the control signals B 1 U, B 1 L, B 2 U, B 2 L for the upper and lower arms of the first and second power supply converters are not generated in the first embodiment. Thus, these are not shown in FIG. 10 . In addition, FIG. 10 shows the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1. Furthermore, in FIG. 10 , time T 2 r *, T 2 f * respectively indicate the target rise and fall timing (Tw+τd 1 +τdt), (Tw+τw) of the control signal S 2 a for the switch S 2 . Time T 3 f *, T 3 r * respectively indicate the target fall and rise timing (Tw+τd 1 ), (Tw+τw−τd 2 +τdt) of the control signal S 3 a for the switch S 3 . Time T 4 f *, T 4 r * respectively indicate the target fall and rise timing (Tw+τw−τd 2 ), (Tw+τw+τdt) of the control signal S 4 a for the switch S 4 . In the first embodiment, the target timing of each of the edges of the control signals S 2 a to S 4 a in the next cycle of the carrier waves Ca 1 , Ca 2 is separately set in the current cycle of the carrier waves Ca 1 , Ca 2 and is set in the matching output section. In this way, the switching control of the switches S 1 to S 4 can be executed by outputting the control signals S 1 a to S 4 a that conform to the control signals S 1 y to S 4 y in the comparative example to the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 .

In the power supply apparatus 20 of the first embodiment that has been described so far, the electronic control unit 60 separately sets the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 in accordance with three of the timing in the cycle that are the timing at which the carrier wave Ca 1 and the target duty ratio Du 1 * become equal to each other during the increase of the carrier wave Ca 1 , the timing at which the carrier wave Ca 2 and the target duty ratio Du 2 * become equal to each other during the decrease of the carrier wave Ca 2 , and the reset timing of the carrier waves Ca 1 , Ca 2 . Then, the electronic control unit 60 sets each of the target timing in the matching output section, and, when the timekeeping value of the timer reaches the target timing of each of the edges of the control signals S 1 a to S 4 a , switches the output of the corresponding control signal from OFF (Low) to ON (High) or from ON to OFF. In this way, the switching control of the switches S 1 to S 4 can be executed without providing the logic circuit and sequentially performing the logical operations that correspond to the processing in the logic circuit. As a result, compared to the power supply apparatus that is provided with the logic circuit, the number of the components of the power supply apparatus 20 can be reduced. In addition, compared to the power supply apparatus in which the electronic control unit sequentially performs the logical operations, the processing load of the electronic control unit 60 can be reduced.

In addition, in the power supply apparatus 20 of the first embodiment, the electronic control unit 60 separately sets the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 in consideration of the dead time. In this way, because the dead time generation circuit does not have to be provided between the electronic control unit 60 and the switches S 1 to S 4 , the number of the components of the power supply apparatus 20 can further be reduced.

In the power supply apparatus 20 of the first embodiment, the electronic control unit 60 separately sets the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 based on the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the cycle. However, the electronic control unit 60 may separately set the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 based on timing of each of edges of the control signals B 1 U, B 1 L, B 2 U, B 2 L for the upper and lower arms of the first and second power supply converters in the cycle. One example of a processing routine in this case is shown in FIG. 11 .

Once the processing routine in FIG. 11 is executed, the electronic control unit 60 first sets the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 (step S 200 ). This processing can be executed in a similar manner to the processing in the above-described comparative example and the processing in step S 100 of the processing routine in FIG. 8 .

Next, the control signals B 1 U, B 1 L, B 2 U, B 2 L for the upper and lower arms of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 are generated on the basis of the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 (step S 210 ). This processing can be executed in a similar manner to the processing in the above-described comparative example.

Then, based on the timing of each of the edges (rise and fall) of the control signals B 1 U, B 1 L, B 2 U, B 2 L in the next cycle of the carrier waves Ca 1 , Ca 2 , the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the cycle is separately set (step S 220 ). Similar to the processing in step S 110 of the processing routine in FIG. 8 , this processing can be executed by using FIG. 9 . As it is understood from FIG. 7 , in the next cycle of the carrier waves Ca 1 , Ca 2 , the control signals B 1 U, B 1 L for the upper and lower arms of the first power supply converter are switched between ON and OFF at the time (Tw+τd 1 ) and the time (Tw+τw), and the control signals B 2 U, B 2 L for the upper and lower arms of the second power supply converter are switched between ON and OFF at the time (Tw+τw−τd 2 ) and the time (Tw+τw). Then, some of the control signals S 1 x to S 4 x for the switches S 1 to S 4 are switched between ON and OFF at each of the three of the time (the timing) that are the time (Tw+τd 1 ), the time (Tw+τw−τd 2 ), and the time (Tw+τw). Thus, in consideration of relationships between the timing of the edges of the control signals B 1 U, B 1 L, B 2 U, B 2 L and the timing of the edges of the control signals S 1 x to S 4 x , it is considered that the waveforms of the control signals S 1 a to S 4 a can conform to the waveforms of the control signals S 1 y to S 4 y (the control signals obtained by adding the dead time to the control signals S 1 x to S 4 x ) in the comparative example by executing the processing in step S 220 in a similar manner to the processing in step S 110 of the processing routine in FIG. 8 .

Then, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 is set in the matching output section (step S 230 ), and this routine is terminated. This processing can be executed in a similar manner to the processing in step S 120 of the processing routine in FIG. 8 .

By adopting the method as described above, similar to the first embodiment, the switching control of the switches S 1 to S 4 can be executed without providing the logic circuit and sequentially performing the logical operations that correspond to the processing in the logic circuit.

In the power supply apparatus 20 of the first embodiment, the electronic control unit 60 separately sets the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 in consideration of the dead time. However, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 may separately be set without considering the dead time. In this case, the dead time generation circuit has to be provided between the electronic control unit 60 and the switches S 1 to S 4 . However, similar to the first embodiment, the switching control of the switches S 1 to S 4 can be executed without providing the logic circuit and sequentially performing the logical operations that correspond to the processing in the logic circuit.

In the power supply apparatus 20 of the first embodiment, the sawtooth wave is used as the carrier wave Ca 1 , and the reverse-sawtooth wave is used as the carrier wave Ca 2 . However, the reverse-sawtooth wave may be used as the carrier wave Ca 1 , and the sawtooth wave may be used as the carrier wave Ca 2 . Alternatively, the sawtooth waves may be used as the carrier waves Ca 1 , Ca 2 , or the reverse-sawtooth waves may be used as the carrier waves Ca 1 , Ca 2 . FIG. 12 is an explanatory table that shows the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 in the case where the reverse-sawtooth wave is used as the carrier wave Ca 1 and the sawtooth wave is used as the carrier wave Ca 2 . FIG. 13 is an explanatory table that shows the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 in the case where the sawtooth waves are used as the carrier waves Ca 1 , Ca 2 . FIG. 14 is an explanatory table that shows the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 in the case where the reverse-sawtooth waves are used as the carrier waves Ca 1 , Ca 2 . Hereinafter, a description thereon will sequentially be made.

In FIG. 12 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set as will be described below. Because the switch S 1 is kept ON, the target timing of the edges is not set for the control signal S 1 a for the switch S 1 . For the control signal S 2 a for the switch S 2 , time (Tw+τw−τd 1 ) is set as the target fall timing, and the time (Tw+τw+τdt) is set as the target rise timing. For the control signal S 3 a for the switch S 3 , time (Tw+τd 2 ) is set as the target fall timing, and time (Tw+τw−τd 1 +τdt) is set as the target rise timing. For the control signal S 4 a for the switch S 4 , time (Tw+τd 2 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing.

In addition, in FIG. 12 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is larger than the value 1, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set as will be described below. For the control signal S 1 a for the switch S 1 , the time (Tw+τw−τd 1 ) is set as the target fall timing, and the time (Tw+τd 2 +τdt) is set as the target rise timing. For the control signal S 2 a for the switch S 2 , the time (Tw+τd 2 ) is set as the target fall timing, and the time (Tw+τw+τdt) is set as the target rise timing. Because the switch S 3 is kept ON, the target timing of the edges is not set for the control signal S 3 a for the switch S 3 . For the control signal S 4 a for the switch S 4 , the time (Tw+τw−τd 1 −τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing.

Furthermore, in FIG. 12 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is equal to the value 1, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set as will be described below. Because the switch S 1 is kept ON, the target timing of the edges is not set for the control signal S 1 a for the switch S 1 . For the control signal S 2 a for the switch S 2 , the time (Tw+τd 2 ) is set as the target tall timing, and the time (Tw+τw+τdt) is set as the target rise timing. Because the switch S 3 is kept ON, the target timing of the edges is not set for the control signal S 3 a for the switch S 3 . For the control signal S 4 a for the switch S 4 , the time (Tw+τw−τd 1 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing.

In FIG. 13 , in the case where the target duty ratio Du 1 * is smaller than the target duty ratio Du 2 *, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set as will be described below. For the control signal S 1 a for the switch S 1 , the time (Tw+τd 1 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing. Because the switch S 2 is kept ON, the target timing of the edges is not set for the control signal S 2 a for the switch S 2 . For the control signal S 3 a for the switch S 3 , the time (Tw+τd 2 ) is set as the target fall timing, and the time (Tw+τw+τdt) is set as the target rise timing. For the control signal S 4 a for the switch S 4 , the time (Tw+τd 1 ) is set as the target fall timing, and the time (Tw+τd 2 +τdt) is set as the target rise timing.

In addition, in FIG. 13 , in the case where the target duty ratio Du 1 * is larger than the target duty ratio Du 2 *, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set as will be described below. For the control signal S 1 a for the switch S 1 , the time (Tw+τd 2 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing. For the control signal S 2 a for the switch S 2 , the time (Tw+τd 2 ) is set as the target fall timing, and the time (Tw+τd 1 +τdt) is set as the target rise timing. For the control signal S 3 a for the switch S 3 , the time (Tw+τd 1 ) is set as the target fall timing, and the time (Tw+τw+τdt) is set as the target rise timing. Because the switch S 4 is kept ON, the target timing of the edges is not set for the control signal S 4 a for the switch S 4 .

Furthermore, in FIG. 13 , in the case where the target duty ratio Du 1 * is equal to the target duty ratio Du 2 *, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set as will be described below. For the control signal S 1 a for the switch S 1 , the time (Tw+τd 2 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing. Because the switch S 2 is kept ON, the target timing of the edges is not set for the control signal S 2 a for the switch S 2 . For the control signal S 3 a for the switch S 3 , the time (Tw+τd 1 ) is set as the target fall timing, and the time (Tw+τw+τdt) is set as the target rise timing. Because the switch S 4 is kept ON, the target timing of the edges is not set for the control signal S 4 a for the switch S 4 .

In FIG. 14 , in the case where the target duty ratio Du 1 * is smaller than the target duty ratio Du 2 *, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set as will be described below. For the control signal S 1 a for the switch S 1 , the time (Tw+τw−τd 1 ) is set as the target fall timing, and the time (Tw+τw) is set as the target rise timing. Because the switch S 2 is kept ON, the target timing of the edges is not set for the control signal S 2 a for the switch S 2 . For the control signal S 3 a for the switch S 3 , the time (Tw+τw−τd 2 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing. For the control signal S 4 a for the switch S 4 , the time (Tw+τw−τd 2 ) is set as the target fall timing, and the time (Tw+τw−τd 1 +τdt) is set as the target rise timing.

In addition, in FIG. 14 , in the case where the target duty ratio Du 1 * is larger than the target duty ratio Du 2 *, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set as will be described below. For the control signal S 1 a for the switch S 1 , the time (Tw+τw−τd 2 ) is set as the target fall timing, and the time (Tw+τw) is set as the target rise timing. For the control signal S 2 a for the switch S 2 , the time (Tw+τw−τd 1 ) is set as the target fall timing, and the time (Tw+τw−τd 2 +τdt) is set as the target rise timing. For the control signal S 3 a for the switch S 3 , the time (Tw+τw−τd 1 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing. Because the switch S 4 is kept ON, the target timing of the edges is not set for the control signal S 4 a for the switch S 4 .

Furthermore, in FIG. 14 , in the case where the target duty ratio Du 1 * is equal to the target duty ratio Du 2 *, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set as will be described below. For the control signal S 1 a for the switch S 1 , the time (Tw+τw−τd 2 ) is set as the target fall timing, and the time (Tw+τw) is set as the target rise timing. Because the switch S 2 is kept ON, the target timing of the edges is not set for the control signal S 2 a for the switch S 2 . For the control signal S 3 a for the switch S 3 , the time (Tw+τw−τd 1 +τdt) is set as the target rise timing, and the time (Tw+τw) is set as the target fall timing. Because the switch S 4 is kept ON, the target timing of the edges is not set for the control signal S 4 a for the switch S 4 .

As in these descriptions, the target timing of each of the edges of the control signals S 1 a to S 4 a for the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 is separately set by using FIG. 12 to FIG. 14 , respectively, in the case where the reverse-sawtooth wave is used as the carrier wave Ca 1 and the sawtooth wave is used as the carrier wave Ca 2 , in the case where the sawtooth waves are used as the carrier waves Ca 1 , Ca 2 , and in the case where the reverse-sawtooth waves are used as the carrier waves Ca 1 , Ca 2 . In this way, similar to the first embodiment, the switching control of the switches S 1 to S 4 can be executed without providing the logic circuit and sequentially performing the logical operations that correspond to the processing in the logical circuit.

In the power supply apparatus 20 of the first embodiment and the modified example thereof, the sawtooth wave(s) and/or the reverse-sawtooth wave(s) that are in the same cycle and whose reset timing match each other are used as the carrier waves Ca 1 , Ca 2 . However, the sawtooth wave(s) and/or the reverse-sawtooth wave(s), whose reset timing differ from each other, may be used as the carrier waves Ca 1 , Ca 2 as long as they are in the same cycle. In this case, the target timing of each of the edges of the control signals S 1 a to S 4 a only has to be separately set in accordance with the four of the timing in the one cycle of the carrier waves Ca 1 , Ca 2 .

In the power supply apparatus 20 of the first embodiment and the modified example thereof, the sawtooth wave(s) and/or the reverse-sawtooth wave(s) that are in the same cycle are used as the carrier waves Ca 1 , Ca 2 . However, triangle waves that are in the same cycle may be used as the carrier waves Ca 1 , Ca 2 . In this case, the target timing of each of the edges of the control signals S 1 a to S 4 a only has to be separately set in accordance with four of the timing in the one cycle of the carrier waves Ca 1 , Ca 2 . Noted that the four of the timing are timing at which the carrier wave Ca 1 and the target duty ratio Du 1 * become equal to each other during the increase and a decrease of the carrier wave Ca 1 and timing at which the carrier wave Ca 2 and the target duty ratio Du 2 * become equal to each other during an increase and the decrease of the carrier wave Ca 2 .

FIG. 15 is a configuration diagram that schematically shows a configuration of a power supply apparatus 120 of a second embodiment. The power supply apparatus 120 of the second embodiment has the same hardware configuration as the power supply apparatus 20 of the first embodiment except for a point that the power supply apparatus 120 includes a dead time generation circuit 152 between the electronic control unit 60 and the switches S 1 to S 4 . Accordingly, in order to avoid an overlapping description, the hardware configuration of the power supply apparatus 120 of the second embodiment that is the same as the hardware configuration of the power supply apparatus 20 of the first embodiment is denoted by the same reference numerals, and a description thereon will not be made. The dead time generation circuit 152 is similar to the dead time generation circuit that has been described in the above-described comparative example, generates control signals S 1 b to S 4 b by adding the dead time to each of the control signals S 1 a to S 4 a for the switches S 1 to S 4 that are transmitted from the electronic control unit 60 , and outputs these control signals S 1 b to S 4 b to the switches S 1 to S 4 .

Next, a description will be made on the switching control of the switches S 1 to S 4 in the power supply apparatus 120 of the second embodiment. In the second embodiment, similar to the first embodiment, the sawtooth wave is used as the carrier wave Ca 1 , and the reverse-sawtooth wave that is in the same cycle as the carrier wave Ca 1 and whose reset timing matches that of the carrier wave Ca 1 is used as the carrier wave Ca 2 . FIG. 16 is a flowchart that shows one example of a processing routine executed by the electronic control unit 60 of the second embodiment. This routine is executed at the same timing as the processing routine in FIG. 8 .

Once the processing routine in FIG. 16 is executed, the electronic control unit 60 first sets the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 (step S 300 ). This processing can be executed in a similar manner to the processing in step S 1100 of the processing routine in FIG. 8 .

Next, based on the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 , target timing T 11 to T 13 (T 11 <T 12 <T 13 ) in the cycle are set (step S 310 ), and a combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set for each of the target timing T 11 to T 13 (step S 320 ). FIG. 17 is an explanatory table that shows the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 and the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 . As shown in FIG. 17 , the target timing T 11 to T 13 and the combination of the control signals S 1 a to S 4 a for each of the target timing T 11 to T 13 differ among the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1, the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is larger than the value 1, and the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is equal to the value 1.

In FIG. 17 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1, the time (Tw+τd 1 ), (Tw+τw−τd 2 ), (Tw+τw) are respectively set as the target timing T 11 , T 12 , T 13 . This is because the time (Tw+τd 1 ) becomes earlier time than the time (Tw+τw−τd 2 ). In addition, for the target timing T 11 , (1, 1, 0, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 12 , (1, 1, 1, 0) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (1, 0, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

In addition, in FIG. 17 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is larger than the value 1, the time (Tw+τw−τd 2 ), (Tw+τd 1 ), (Tw+τw) are respectively set as the target timing T 11 , T 12 , T 13 . This is because the time (Tw+τd 1 ) becomes later time than the time (Tw+τw−τd 2 ). In addition, for the target timing T 11 , (0, 1, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 12 , (1, 1, 1, 0) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (1, 0, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

Furthermore, in FIG. 17 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is equal to the value 1, the time (Tw+τd 1 )=(Tw+τw−τd 2 ), (Tw+τw) are respectively set as the target timing T 11 =T 12 , T 13 . This is because the time (Tw+τd 1 ) and the time (Tw+τw−τd 2 ) become the same time. In addition, for the target timing T 11 , T 12 , (1, 1, 1, 0) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing 13 , (1, 0, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

As described above, the target timing T 11 to T 13 and the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 for each of the target timing T 11 to T 13 can appropriately be set in accordance with the magnitude relationships between the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * and the value 1.

Then, the target timing T 11 to T 13 and the combinations of the control signals S 1 a to S 4 a for the switches S 1 to S 4 for each of the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 are set in the matching output section (step S 330 ), and this routine is terminated. A situation where the combinations of the control signals S 1 a to S 4 a are set in the matching output section in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1 is shown in FIG. 18 . Just as described, the combinations of the control signals S 1 a to S 4 a are set in the matching output section. Thereafter, when the timekeeping value of the timer reaches each of the target timing T 11 to T 13 , the corresponding combination of the control signals S 1 a to S 4 a is output. In a case of FIG. 18 , first, when the timekeeping value reaches the time T 11 , the combination (1, 1, 0, 1) of the control signals S 1 a , S 2 a , S 3 a , S 4 a is output to the dead time generation circuit 152 . When the timekeeping value reaches the time T 12 , the combination (1, 1, 1, 0) of the control signals S 1 a , S 2 a , S 3 a , S 4 a is output to the dead time generation circuit 152 . When the timekeeping value reaches the time T 13 , the combination (1, 0, 1, 1) of the control signals S 1 a , S 2 a , S 3 a . S 4 a is output to the dead time generation circuit 152 . In the case where the value is 0→0 or 1→1, a keeping command of OFF (Low) or ON (High) is output to the dead time generation circuit 152 . In the case where the value is 0→1 or 1→0, a switching command from OFF to ON or from ON to OFF is output to the dead time generation circuit 152 . As described above, the dead time generation circuit 152 generates the control signals S 1 b to S 4 b for the switches S 1 to S 4 by adding the dead time to each of the control signals S 1 a to S 4 a for the switches S 1 to S 4 that are transmitted from the electronic control unit 60 and outputs these control signals S 1 b to S 4 b to the switches S 11 to S 4 .

Here, a description will be made on the processing in above-described steps S 310 , S 320 . The case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1 is considered. In this case, as it is understood from FIG. 7 , some of the control signals S 1 x to S 4 x for the switches S 1 to S 4 are switched between ON and OFF at each of the three of the time (the timing) that are the time (Tw+τd 1 ), the time (Tw+τw−τd 2 ), and the time (Tw+τw) in the next cycle of the carrier waves Ca 1 , Ca 2 . The details thereon are as will be described below. At the time (Tw+τd 1 ), the control signal S 2 x for the switch S 2 is switched from OFF to ON, and the control signal S 3 x for the switch S 3 is switched from ON to OFF. In addition, at the time (Tw+τw−τd 2 ), the control signal S 3 x for the switch S 3 is switched from OFF to ON, and the control signal S 4 x for the switch S 4 is switched from ON to OFF. Furthermore, at the time (Tw+τw), the control signal S 2 x for the switch S 2 is switched from ON to OFF, and the control signal S 4 x for the switch S 4 is switched from OFF to ON. Based on these, the combination of the control signals S 1 a to S 4 a for each of the time (Tw+τd 1 ), (Tw+τw−τd 2 ), (Tw+τw) is defined in FIG. 17 . Accordingly, by setting the time (Tw+τd 1 ), (Tw+Tw−τd 2 ), (Tw+τw) as the target timing T 11 to T 13 , respectively, and setting the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 for each of the target timing T 11 to T 13 by using FIG. 17 , the waveforms of the control signals S 1 a to S 4 a can conform to waveforms of the control signals S 1 x to S 4 x in the comparative example. The same as the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1 can be considered for the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is larger than the value 1 and the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is equal to the value 1.

By adopting the method as described above, the switching control of the switches S 1 to S 4 can be executed by outputting the control signals S 1 a to S 4 a that conform to the control signals S 1 x to S 4 x in the comparative example to the dead time generation circuit 152 and thereby outputting the control signals S 1 b to S 4 b that conform to the control signals S 1 y to S 4 y in the comparative example to the switches S 1 to S 4 without providing the logic circuit and sequentially performing the logical operations that correspond to the processing in the logic circuit. As a result, compared to the power supply apparatus that is provided with the logic circuit, the number of components of the power supply apparatus 120 can be reduced. In addition, compared to the power supply apparatus in which the electronic control unit sequentially performs the logical operations, the processing load of the electronic control unit 60 can be reduced.

Noted that, in the case where the reset timing of the carrier waves Ca 1 , Ca 2 do not match each other, it is necessary to set the four of the timing in the next cycle of the carrier wave Ca 1 as the target timing and thereby set the combination at each of the target timing. On the contrary, because the reset timing of the carrier waves Ca 1 , Ca 2 match each other in the second embodiment, only the three of the timing in the next cycle of the carrier wave Ca 1 have to be set as the target timing, and thereby the combination at each of the target timing is set. Thus, the number of the set combinations can be reduced.

In addition, when the method in the first embodiment and the method in the second embodiment are compared, the method in the second embodiment has such an advantage that the processing load of the electronic control unit 60 can further be reduced, and the method in the first embodiment has such an advantage that there is no need to provide the dead time generation circuit 152 between the electronic control unit 60 and the switches S 1 to S 4 .

FIG. 19 is an explanatory view that shows one example of a timing chart in the power supply apparatus 120 of the second embodiment. FIG. 19 shows the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1. In the second embodiment, in the current cycle of the carrier waves Ca 1 , Ca 2 , the time (Tw+τd 1 ), (Tw+τw−τd 2 ), (Tw+τw) in the next cycle of the carrier waves Ca 1 , Ca 2 are set as the target timing T 11 to T 13 , the combinations (1, 1, 0, 1), (1, 1, 1, 0), (1, 0, 1, 1) of the control signals S 1 a , S 2 a , S 3 a , S 4 a for each of the target timing T 11 to T 13 are set, and these are set in the matching output section. In this way, the switching control of the switches S 1 to S 4 can be executed by outputting the control signals S 1 a to S 4 a that conform to the control signals S 1 x to S 4 x in the comparative example to the dead time generation circuit 152 and thereby outputting the control signals S 1 b to S 4 b that conform to the control signals S 1 y to S 4 y in the comparative example to the switches S 1 to S 4 in the next cycle of the carrier waves Ca 1 , Ca 2 .

In the power supply apparatus 120 of the second embodiment that has been described so far, the electronic control unit 60 respectively sets the timing at which the carrier wave Ca 1 and the target duty ratio Du 1 * become equal to each other during the increase of the carrier wave Ca 1 , the timing at which the carrier wave Ca 2 and the target duty ratio Du 2 * become equal to each other during the decrease of the carrier wave Ca 2 , and the reset timing of the carrier waves Ca 1 , Ca 2 in the next cycle of the carrier waves Ca 1 , Ca 2 as the target timing T 11 to T 13 . Next, the electronic control unit 60 sets the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a for the switches S 1 to S 4 for each of the target timing T 11 to T 13 . Then, the electronic control unit 60 sets the target timing T 11 to T 13 and the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 for each of the target timing T 11 to T 13 in the matching output section. Thereafter, when the timekeeping value of the timer reaches each of the target timing T 11 to T 13 , the electronic control unit 60 outputs the corresponding combination to the dead time generation circuit 152 . The dead time generation circuit 152 generates the control signals S 1 b to S 4 b for the switches S 1 to S 4 by adding the dead time to each of the control signals S 1 a to S 4 a for the switches S 1 to S 4 that are transmitted from the electronic control unit 60 , and outputs these control signals S 1 b to S 4 b to the switches S 1 to S 4 . In this way, the switching control of the switches S 1 to S 4 can be executed without providing the logic circuit and sequentially performing the logical operations that correspond to the processing in the logic circuit. As a result, compared to the power supply apparatus that is provided with the logic circuit, the number of the components of the power supply apparatus 120 can be reduced. In addition, compared to the power supply apparatus in which the electronic control unit sequentially performs the logical operations, the processing load of the electronic control unit 60 can be reduced.

In the power supply apparatus 120 of the second embodiment, based on the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 , the electronic control unit 60 sets the target timing T 11 to T 13 in the cycle. However, the timing of each of the edges of the control signals B 1 U, B 1 L, B 2 U, B 2 L for the upper and lower arms of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 may be set as the target timing T 11 to T 13 in the cycle. One example of a processing routine in this case is shown in FIG. 20 .

Once the processing routine in FIG. 20 is executed, the electronic control unit 60 first sets the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 (step S 400 ). This processing can be executed in a similar manner to the processing in step S 300 of the processing routine in FIG. 16 .

Next, the control signals B 1 U, B 1 L, B 2 U, B 2 L for the upper and lower arms of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 are generated on the basis of the target duty ratios Du 1 *, Du 2 * of the first and second power supply converters in the next cycle of the carrier waves Ca 1 , Ca 2 (step S 410 ). This processing can be executed in a similar manner to the processing in step 210 of the processing routine in FIG. 11 .

Then, the timing of the edges (the rise and the fall) of the control signals B 1 U, B 1 L, B 2 U, B 2 L in the next cycle of the carrier waves Ca 1 , Ca 2 are set as the target timing T 11 to T 13 (T 11 <T 12 <T 13 ) in the cycle (step S 420 ), and the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 is set for each of the target timing T 11 to T 13 (step S 430 ). These of the processing can be executed in a similar manner to the processing in steps S 310 , S 320 of the processing routine in FIG. 16 . As described above, and, as it is understood from FIG. 7 , in the next cycle of the carrier waves Ca 1 , Ca 2 , the control signals B 1 U, B 1 L for the upper and lower arms of the first power supply converter are switched between ON and OFF at the time (Tw+τd 1 ) and the time (Tw+τw), and the control signals B 2 U, B 2 L for the upper and lower arms of the second power supply converter are switched between ON and OFF at the time (Tw+τw−τd 2 ) and the time (Tw+τw). Then, some of the control signals S 1 x to S 4 x for the switches S 1 to S 4 are switched between ON and OFF at each of the three of the time (the timing) that are the time (Tw+τd 1 ), the time (Tw+τw−τd 2 ), and the time (Tw+τw). Thus, in consideration of relationships between the timing of the edges of the control signals B 1 U, B 1 L, B 2 U, B 2 L and the timing of the edges of the control signals S 1 x to S 4 x , it is considered that the waveforms of the control signals S 1 a to S 4 a can conform to the waveforms of the control signals S 1 x to S 4 x in the comparative example by executing the processing in steps S 420 , S 430 in the similar manner to the processing in steps S 310 , S 320 of the processing routine in FIG. 16 .

Then, the target timing T 11 to T 13 and the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 are set in the matching output section (step S 440 ), and this routine is terminated. This processing can be executed in a similar manner to the processing in step S 330 of the processing routine in FIG. 16 .

By adopting the method as described above, similar to the second embodiment, the switching control of the switches S 1 to S 4 can be executed without providing the logic circuit and sequentially performing the logical operations that correspond to the processing in the logic circuit.

In the power supply apparatus 120 of the second embodiment, the sawtooth wave is used as the carrier wave Ca 1 , and the reverse-sawtooth wave is used as the carrier wave Ca 2 . However, the reverse-sawtooth wave may be used as the carrier wave Ca 1 , and the sawtooth wave may be used as the carrier wave Ca 2 . Alternatively, the sawtooth waves may be used as the carrier waves Ca 1 , Ca 2 , or the reverse-sawtooth waves may be used as the carrier waves Ca 1 , Ca 2 . FIG. 21 is an explanatory table that shows the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 and the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 in the case where the reverse-sawtooth wave is used as the carrier wave Ca 1 and the sawtooth wave is used as the carrier wave Ca 2 . FIG. 22 is an explanatory table that shows the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 and the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 in the case where the sawtooth waves are used as the carrier waves Ca 1 , Ca 2 . FIG. 23 is an explanatory table that shows the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 and the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 in the case where the reverse-sawtooth waves are used as the carrier waves Ca 1 , Ca 2 . Hereinafter, a description thereon will sequentially be made.

In FIG. 21 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is smaller than the value 1, the time (Tw+τd 2 ), (Tw+τw−τd 1 ), (Tw+τw) are respectively set as the target timing T 11 to T 13 . In addition, for the target timing T 11 , (1, 1, 0, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 12 , (1, 0, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing 13 , (1, 1, 1, 0) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

In addition, in FIG. 21 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is larger than the value 1, the time (Tw+τw−τd 1 ), (Tw+τd 2 ), (Tw+τw) are respectively set as the target timing T 11 to T 13 . In addition, for the target timing T 11 , (0, 1, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 12 , (1, 0, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (1, 1, 1, 0) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

Furthermore, in FIG. 21 , in the case where the sum of the target duty ratio Du 1 * and the target duty ratio Du 2 * is equal to the value 1, the time (Tw+τd 2 )=(Tw+τw−τd 1 ), (Tw+τw) are respectively set as the target timing T 11 =T 12 , T 13 . In addition, for the target timing T 11 , T 12 , (1, 0, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (1, 1, 1, 0) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

In FIG. 22 , in the case where the target duty ratio Du 1 * is smaller than the target duty ratio Du 2 *, the time (Tw+τd 1 ), (Tw+τd 2 ), (Tw+τw) are respectively set as the target timing T 11 to T 13 . In addition, for the target timing T 11 , (1, 1, 1, 0) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 12 , (1, 1, 0, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (0, 1, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a . S 4 a.

In addition, in FIG. 22 , in the case where the target duty ratio Du 1 * is larger than the target duty ratio Du 2 *, the time (Tw+τd 2 ), (Tw+τd 1 ), (Tw+τw) are respectively set as the target timing T 11 to T 13 . In addition, for the target timing T 11 , (1, 0, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 12 , (1, 1, 0, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (0, 1, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

Furthermore, in FIG. 22 , in the case where the target duty ratio Du 1 * is equal to the target duty ratio Du 2 *, the time (Tw+τd 1 )=(Tw+τd 2 ), (Tw+τw) are respectively set as the target timing T 11 =T 12 , T 13 . In addition, for the target timing T 11 , T 12 , (1, 1, 0, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (0, 1, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

In FIG. 23 , in the case where the target duty ratio Du 1 * is smaller than the target duty ratio Du 2 *, the time (Tw+τw−τd 2 ), (Tw+τw−τd 1 ), (Tw+Tw) are respectively set as the target timing T 11 to T 13 . In addition, for the target timing T 11 , (1, 1, 1, 0) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 12 , (0, 1, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (1, 1, 0, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

In addition, in FIG. 23 , in the case where the target duty ratio Du 1 * is larger than the target duty ratio Du 2 *, the time (Tw+τw−τd 1 ), (Tw+τw−τd 2 ), (Tw+τw) are respectively set as the target timing T 11 to T 13 . In addition, for the target timing T 11 , (1, 0, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a . S 4 a . For the target timing T 12 , (0, 1, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (1, 1, 0, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

Furthermore, in FIG. 23 , in the case where the target duty ratio Du 1 * is equal to the target duty ratio Du 2 *, the time (Tw+τw−τd 2 )=(Tw+τw−τd 1 ), (Tw+τw) are respectively set as the target timing T 11 =T 12 , T 13 . In addition, for the target timing T 11 , T 12 , (0, 1, 1, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a . For the target timing T 13 , (1, 1, 0, 1) is set as the combination of the control signals S 1 a , S 2 a , S 3 a , S 4 a.

As in these descriptions, the target timing T 11 to T 13 in the next cycle of the carrier waves Ca 1 , Ca 2 and the combination of the control signals S 1 a to S 4 a for the switches S 1 to S 4 at each of the target timing T 11 to T 13 are set by using FIG. 21 to FIG. 23 , respectively, in the case where the reverse-sawtooth wave is used as the carrier wave Ca 1 and the sawtooth wave is used as the carrier wave Ca 2 , in the case where the sawtooth waves are used as the carrier waves Ca 1 , Ca 2 , and in the case where the reverse-sawtooth waves are used as the carrier waves Ca 1 , Ca 2 . In this way, similar to the second embodiment, the switching control of the switches S 1 to S 4 can be executed without providing the logic circuit and sequentially performing the logical operations that correspond to the processing in the logical circuit.

In the power supply apparatus 120 of the second embodiment and the modified example thereof, the sawtooth wave(s) and/or the reverse-sawtooth wave(s) that are in the same cycle and whose reset timing match each other are used as the carrier waves Ca 1 , Ca 2 . However, the sawtooth wave(s) and/or the reverse-sawtooth wave(s), whose reset timing differ from each other, may be used as the carrier waves Ca 1 , Ca 2 as long as they are in the same cycle. In this case, the four of the timing in the one cycle of the carrier waves Ca 1 , Ca 2 are set as the target timing, and the combination of the control signals S 1 a to S 4 a at each of the target timing only has to be set.

In the power supply apparatus 120 of the second embodiment and the modified example thereof, the sawtooth wave(s) and/or the reverse-sawtooth wave(s) that are in the same cycle are used as the carrier waves Ca 1 , Ca 2 . However, the triangle waves that are in the same cycle may be used as the carrier waves Ca 1 , Ca 2 . In this case, the four of the timing in the one cycle of the carrier waves Ca 1 , Ca 2 are set as the target timing, and the combination of the control signals S 1 a to S 4 a at each of the target timing only has to be set. Noted that the four of the timing are the timing at which the carrier wave Ca 1 and the target duty ratio Du 1 * become equal to each other during the increase and the decrease of the carrier wave Ca 1 and the timing at which the carrier wave Ca 2 and the target duty ratio Du 2 * become equal to each other during the increase and the decrease of the carrier wave Ca 2 .

In each of the power supply apparatuses 20 , 120 of the first and second embodiments, the switching control of the switches S 1 to S 4 in the converter 40 is executed such that the voltage VH of the power line 14 becomes the target voltage VH* thereof by the function as the first power supply converter and that the current IL 2 flowing through the reactor L 2 becomes the target current IL 2 * by the function as the second power supply converter. However, the switching control of the switches S 1 to S 4 in the converter 40 may be executed such that the voltage VH of the power line 14 becomes the target voltage VH* thereof by the function as the second power supply converter and that the current IL 1 flowing through the reactor L 1 becomes a target current IL 1 * by the function as the first power supply converter. Here, the target current IL 1 * of the reactor L 1 can be set on the basis of the states of charge SOC 1 , SOC 2 of the batteries 22 , 32 and the like.

A description will be made on corresponding relationships between the primary elements of the embodiments and the primary elements of the disclosure that are described in the SUMMARY section. In the embodiments, the battery 22 is an example of the “first power supply”, the battery 32 is an example of the “second power supply”, the converter 40 that has the switches S 1 to S 4 , the diodes D 1 to D 4 , and the reactors L 1 , L 2 are examples of the “converter”, and the electronic control unit 60 is an example of the “control unit”.

The control unit (e.g., electronic control unit 60 ) may be configured to perform disclosed functions. For example, the control unit may be programmed to perform disclosed functions. The control unit may store or retrieve digitized instructions, which the control unit may execute to perform disclosed functions. The digitized instructions may be stored in a non-transitory computer-readable medium. Further, the control unit may include one or more electronic control units to perform disclosed processes.

The description has been made so far on the modes for carrying out the embodiments. However, it is needless to say that the disclosure is not limited to these embodiments in any respect and can be implemented in various modes within a scope that does not depart from the gist of the disclosure.

Disclosed embodiments can be used in a manufacturing industry of the power supply apparatus and the like.

Following is a summary of the disclosed embodiments. In accordance with three of timing that are time (Tw+τd 1 ), (Tw+τw−τd 2 ), (Tw+τw) in a next cycle of carrier waves Ca 1 , Ca 2 , an electronic control unit separately sets target timing of each of edges of control signals S 1 a to S 4 a for switches S 1 to S 4 in the cycle. Then, the electronic control unit switches output of the corresponding control signal from OFF to ON or from ON to OFF when a timekeeping value of a timer reaches the target timing of each of the edges of the control signals S 1 a to S 4 a.