Layout pattern for static random access memory

1. Field of the Invention

The invention relates to a static random access memory (SRAM), and more particularly, to a SRAM having the advantages of higher yield and faster read speed.

2. Description of the Prior Art

An embedded static random access memory (SRAM) comprises a logic circuit and a static random access memory connected to the logic circuit. SRAM is a kind of volatile memory cell, which means it preserves data only while power is continuously applied. SRAM is built of cross-coupled inverters that store data during the time that power remains applied, unlike dynamic random access memory (DRAM) that needs to be periodically refreshed. Because of its high access speed, SRAM is also used in computer systems as a cache memory.

However, as pitch of the exposure process decreases, it has been difficult for the current SRAM architecture to produce desirable patterns. Hence, how to enhance the current SRAM architecture for improving exposure quality has become an important task in this field.

The present invention provides a layout pattern of a static random access memory, including: a first inverter and a second inverter cross-coupled for data storage, each inverter including at least one pull-up device (PLs) and at least one pull-down devices (PDs), at least one pass gate devices (PGs) configured with the two cross-coupled inverters, wherein each of the at least one pull-up device (PLs), the at least one pull-down devices (PDs), and the at least one pass gate devices (PGs) includes a fin field-effect transistor (FinFET), a plurality of fin structures disposed on the substrate, the fin structures includes at least one first fin structure, at least one second fin structure, at least one third fin structure and at least one fourth fin structure, each inverter comprising a J-shaped structure disposed on the substrate, the J-shaped structure comprising a long part and a short part arranged along a first direction and a bridge part arranged along a second direction, wherein the first direction is perpendicular to the second direction, wherein the long part crosses over the at least one first fin structure and the short part crosses over the at least one second fin structure to from the at least one pull-down devices (PDs), wherein the long part crosses over the at least one third fin structure to from the at least one pull-up devices (PLs), each inverter having at least one first pass gate structure disposed on the substrate, the at least one first pass gate structure and the short part of the J-shaped structure being arranged along the first direction, and the at least one first pass gate structure and the short part of the J-shaped structure comprising a same symmetry axis, wherein the at least one first pass gate structure crosses over the at least one fourth fin structure to from the pass gate devices (PGs), and a first extending contact structure crossing over the at least one first fin structure and the at least one second fin structure, wherein the first extending contact structure does not overlap with the bridge part of the J-shaped structure.

The present invention further provides a layout pattern of a static random access memory, including: a first inverter and a second inverter cross-coupled for data storage, each inverter including at least one pull-up device (PLs) and at least one pull-down devices (PDs), at least one pass gate devices (PGs) configured with the two cross-coupled inverters, wherein each of the at least one pull-up device (PLs), the at least one pull-down devices (PDs), and the at least one pass gate devices (PGs) includes a fin field-effect transistor (FinFET), a plurality of diffusion regions disposed on the substrate, the diffusion regions includes at least one first diffusion region, at least one second diffusion region, at least one third diffusion region and at least one fourth diffusion region, each inverter comprising a J-shaped structure disposed on the substrate, the J-shaped structure comprising a long part and a short part arranged along a first direction and a bridge part arranged along a second direction, wherein the first direction is perpendicular to the second direction, wherein the long part crosses over the at least one first diffusion region and the short part crosses over the at least one second diffusion region to from the at least one pull-down devices (PDs), wherein the long part crosses over the at least one third diffusion region to from the at least one pull-up devices (PLs), each inverter having at least one first pass gate structure disposed on the substrate, the at least one first pass gate structure and the short part of the J-shaped structure being arranged along the first direction, and the at least one first pass gate structure and the short part of the J-shaped structure comprising a same symmetry axis, wherein the at least one first pass gate structure crosses over the at least one fourth diffusion region to from the pass gate devices (PGs), and a first extending contact structure crossing over the at least one first diffusion region and the at least one second diffusion region, wherein the first extending contact structure does not overlap with the bridge part of the J-shaped structure.

A key feature of this embodiment is that both the long part and the short part of the J-shaped structure cross over the same fin structure. In this way, in a limited range, the gate can cross more fin structures, thereby improving the read speed of one pull-down device. Furthermore, another feature of the present invention is when viewed in a top view, the extending contact structure does not overlap with the bridge part, and there is a gap disposed therebetween. By the applicant's experiment, if the extending contact structure does not overlap with the bridge part, the parasitic capacitance can be reduced, and thereby improving the yield, and further improving the stability and speed of the SRAM.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 illustrates a circuit diagram of a six-transistor SRAM (6T-SRAM) cell according to a first preferred embodiment of the present invention.

FIG. 2 illustrates a layout diagram of a 6T-SRAM according to a first preferred embodiment of the present invention.

FIG. 3 shows a cross section diagram along the cross section line A-A′ of FIG. 2 according to one embodiment of the present invention.

FIG. 4 shows a cross section diagram along the cross section line A-A′ of FIG. 2 according to another embodiment of the present invention.

FIG. 5 illustrates a circuit diagram of an eight-transistor SRAM (8T-SRAM) cell according to a second preferred embodiment of the present invention.

FIG. 6 illustrates a layout diagram of an 8T-SRAM according to a second preferred embodiment of the present invention.

FIG. 7 illustrates a layout diagram of a 6T-SRAM according to another preferred embodiment of the present invention.

FIG. 8 illustrates a layout diagram of an 8T-SRAM according to another preferred embodiment of the present invention.

To provide a better understanding of the present invention to users skilled in the technology of the present invention, preferred embodiments are detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and the effects to be achieved.

Please note that the figures are only for illustration and the figures may not be to scale. The scale may be further modified according to different design considerations. When referring to the words “up” or “down” that describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be inverted to obtain a similar structure, and these structures should therefore not be precluded from the scope of the claims in the present invention.

Referring to FIGS. 1-2 , FIG. 1 illustrates a circuit diagram of a six-transistor SRAM (6T-SRAM) cell according to a first preferred embodiment of the present invention, and FIG. 2 illustrates a layout diagram of a 6T-SRAM according to the first preferred embodiment of the present invention.

As shown in FIGS. 1-2 , the SRAM device of the present invention preferably includes at least one SRAM cell, each SRAM cell including a six-transistor SRAM (6T-SRAM) cell 10 .

In this embodiment, each 6T-SRAM cell 10 is composed of a first pull-up device PL 1 , a second pull-up device PL 2 , and a first pull-down device PD 1 , a second pull-down device PD 2 , a first pass gate device PG 1 and a second pass gate device PG 2 . These six devices (transistors) constitute a set of flip-flops. The first and the second pull-up devices PL 1 and PL 2 , and the first and the second pull-down devices PD 1 and PD 2 constitute a latch circuit 22 that stores data in the storage nodes 24 and 26 . Since the first and the second pull-up devices PL 1 and PL 2 act as power load devices, they can be replaced by resistors. Under this circumstance, the static random access memory becomes a four-transistor SRAM (4T-SRAM). In this embodiment, the first and the second pull-up devices PL 1 and PL 2 preferably share a source/drain region and electrically connect to a voltage source (voltage node) Vcc, and the first and the second pull-down devices PD 1 and PD 2 share a source/drain region and electrically connect to a voltage source (voltage node) Vss.

Preferably, the first and the second pull-up devices PL 1 and PL 2 of the 6T-SRAM cell 10 are composed of p-type metal oxide semiconductor (PMOS) transistors; the first and the second pull-down devices PD 1 and PD 2 , the first pass gate devices PG 1 and the second pass gate devices PG 2 composed of n-type metal oxide semiconductor (NMOS) transistors, but not limited thereto. The first pull-up device PL 1 and the first pull-down device PD 1 constitute an inverter, which further form a series circuit 28 . One end of the series circuit 28 is connected to a voltage source Vcc and the other end of the series circuit 28 is connected to a voltage source Vss. Similarly, the second pull-up device PL 2 and the second pull-down device PD 2 constitute another inverter and a series circuit 30 . One end of the series circuit 30 is connected to the voltage source Vcc and the other end of the series circuit 30 is connected to the voltage source Vss. The two inverters are cross-coupled to each other to storage data.

The storage node 24 is connected to the respective gates of the second pull-down device PD 2 and the second pull-up device PL 2 . The storage node 24 is also connected to the drains of the first pull-down device PD 1 , the first pull-up device PL 1 and the first pass gate device PG 1 . Similarly, the storage node 26 is connected to the respective gates of the first pull-down device PD 1 and first the pull-up device PL 1 . The storage node 26 is also connected to the drains of the second pull-down device PD 2 , the second pull-up device PL 2 and the second pass gate device PG 2 . The gates of the first pass gate device PG 1 and the second pass gate device PG 2 are respectively coupled to a word line (WL); the source of the first pass gate device PG 1 and the second pass gate device PG 2 are respectively coupled to a first bit line (BL 1 ) and a second bit line (BL 2 ).

In this embodiment, a 6T-SRAM cell 10 is disposed on a substrate 52 , such as a silicon substrate or silicon-on-insulator (SOI) substrate. The substrate may be a planar substrate, or a plurality of fin structures 54 may be formed on the substrate 52 . In this embodiment, take a 6T-SRAM with fin structures 54 as an example, but the present invention is not limited thereto. In another case, the planar SRAM (the SRAM without comprising fin structures) may also be comprised within the scope of the present invention. In addition, a shallow trench isolation (STI, not shown) is disposed between each fin structure 54 .

Generally, one fin transistor includes a gate structure crossing over at least one fin structure. However, if one gate structure crosses over a plurality of paralleled arranged fin structures, in the equivalent circuit, it's equal to a plurality of transistors connected in parallel to each other, thereby helping to increase the channel width of the fin transistor, and the read current (Tread) of one fin transistor can also be improved, so as to improve the operation speed of the whole SRAM (due to one SRAM includes a plurality of fin transistors).

Therefore, one purpose of the present invention is make one gate structure cross more fin structures within a limited range, so as to improve the operation speed of the whole SRAM.

A key feature of the present invention is the invention further comprises at least two J-shaped structures 56 disposed on the substrate 52 , and the two J-shaped structures 56 are symmetrically arranged. To simplify the description, this embodiment only describes one of the J-shaped structures 56 (e.g., the left J-shaped structure 56 in FIG. 2 ). Except for the symmetrical arrangement, the other characteristics of the two J-shaped structures 56 are completely identical.

The J-shaped structures 56 includes a long part 56 A, a short part 56 B and a bridge part 56 C which is connected to the long part 56 A and the short part 56 B. More precisely, the long part 56 A and the short part 56 B of the J-shaped structure 56 are arranged along a first direction (such as the X-direction in FIG. 2 ), and the bridge part 56 C of the J-shaped structure 56 is arranged along a second direction (such as the Y-direction in FIG. 2 ). The first direction and the second direction are preferably perpendicular to each other, but not limited thereto.

It is noteworthy that the 6T-SRAM cell 10 is disposed within a specific range 11 , in other words, the specific range 11 only includes one 6T-SRAM cell 10 disposed therein. The bridge part 56 C is disposed adjacent to one edge of the specific range 11 (such as the edge 11 A shown in FIG. 2 ). In addition, FIG. 3 and FIG. 4 respectively show two cross section diagrams along the cross section line A-A′ in FIG. 2 according to two embodiments of the present invention. As shown in FIG. 3 , the bridge part 56 C may include a high-k layer (not shown) and a metal electrode (labeled as 56 C′ in FIG. 3 ), which contacts the long part 56 A and the short part 56 B directly. Or in another case (not shown), the bridge part 56 C, the long part 56 A and the short part 56 B is a monolithically formed structure. In another case, as shown in FIG. 4 , the bridge part 56 C may be a metal layer (labeled as 56 C″ in FIG. 4 ), which is electrically connected to the long part 56 A and the short part 56 B through two contact structures 57 . To simplify the figure, the interlayer dielectric (ILD) is not shown in FIGS. 3-4 , but it can be understood that the ILD should be disposed on the substrate 52 , and each element (including the long part 56 A, the short part 56 B, the bridge part 56 C and the contact structures 57 , etc. . . . ) are disposed in the ILD.

fin structures 54 . Here the fin structures 54 are labeled as the first fin structures 54 A, the second fin structures 54 B, the third fin structure 54 C and the fourth fin structure 54 D. It is noteworthy that in this embodiment, there are more than one first fin structure 54 A, more than one second fin structure 54 B and more than one fourth fin structure 54 D, including four parallel arranged first fin structures 54 A, two parallel arranged second fin structures 54 B, one third fin structure 54 C and two parallel arranged fourth fin structures 54 D (in each one inverter). However, the amount of the first fin structures 54 A, the second fin structures 54 B, the third fin structure 54 C and the fourth fin structure 54 D may include any integer greater than or equal to 1, and it can be adjusted according to actual requirements.

In this embodiment, the long part 56 A of the J-shaped structure 56 crosses over the first fin structures 54 A and the third fin structure 54 C, and the short part 56 B of the J-shaped structure 56 crosses over the second fin structures 54 B. The portion that the long part 56 A crosses over the third fin structure 54 C constitutes a gate of the first the pull-up device PL 1 . In addition, the portion that the long part 56 A crosses over the first fin structures 54 A, and the portion that the short part 56 B crosses over the second fin structures 54 B constitutes a gate of the first the pull-down device PD 1 (the range of the dotted line in FIG. 2 shows the range of the first the pull-down device PD 1 ).

Therefore, in terms of the first pull-down device PD 1 , which comprises the J-shaped structure 56 , and the J-shaped structure 56 crosses over total six fin structures (including the long part 56 A crosses four first fin structures 54 A, and the short part 56 B crosses two second fin structures 54 B). In this way, in a limited range, the gate can cross more fin structures. This increases the channel width of the first pull-down device PD 1 , and the read current (Tread) of one first pull-down device PD 1 can also be improved, so as to improve the read speed of the first pull-down device PD 1 .

Besides the J-shaped structure 56 , the 6T-SRAM cell 10 also comprises two symmetrically arranged first pass gate structures 60 A, 60 B disposed on the substrate 52 . To simplify the description, this embodiment only describes the first pass gate structures 60 A (e.g., the left first pass gate structure 60 A in FIG. 2 ). Except for the symmetrical arrangement, the other characteristics of the two first pass gate structures 60 A, 60 B are completely identical.

Preferably, the first pass gate structure 60 A is arranged along the first direction, and it's also arranged along the extending direction of the short part 56 B. In other words, the short part 56 B and the first pass gate structure 60 A have a same symmetry axis S. The first pass gate structure 60 A crosses over the fourth fin structures 54 D, to constitute the gate of the first pass gate device PG 1 mentioned above. Similarly, another first pass gate structure 60 B crosses over other fourth fin structures 54 D, to constitute the gate of the second pass gate device PG 2 mentioned above.

Besides the fin structures and the gate structures mentioned above, the 6T-SRAM cell 10 further includes a plurality of contact structures, including two symmetrically arranged extending contact structures 72 A and 72 B (here takes the extending contact structures 72 A as an example), disposed between the long part 56 A and the short part 56 B of the J-shaped structure 56 , and crossing over each first fin structure 54 A, each second fin structure 54 B, each the third fin structure 54 C and each fourth fin structure 54 D, to electrically connect each parallel arranged fin structure together. Please also refer to FIG. 1 , where the extending contact structure 72 A electrically connects to the drain of the first pull-down device PD 1 , the first pull-up device PL 1 and the first pass gate device PG 1 . Besides, when viewed in a top view, the shape of the extending contact structure 72 A may be a strip shape or other shapes (such as L-shaped), and the present invention is not limited thereto.

Furthermore, the other contact structures disposed on the substrate 52 include:

Two symmetrically arranged contact structures 74 A, 74 B, for example, the contact structure 74 A electrically connected to each third fin structure 54 C, and also electrically connected to the voltage source Vcc (please refer to FIG. 1 , where the contact structure 74 A electrically connected the source of the first pull-up device PL 1 and the second pull-up device PL 2 to the voltage source Vcc).

Two symmetrically arranged contact structures 76 A, 76 B, for example, the contact structure 76 A crosses over each first fin structure 54 A, and is electrically connected to the voltage source Vss (please refer to FIG. 1 , where the contact structure 76 A electrically connected the source of the first pull-down device PD 1 and the second pull-down device PD 2 to the voltage source Vss).

Two symmetrically arranged contact structures 78 A, 78 B, for example, the contact structure 78 A crosses over each second fin structure 54 B, and is electrically connected to the voltage source Vss (please refer to FIG. 1 , where the contact structure 78 A electrically connected the source of the first pull-down device PD 1 and the second pull-down device PD 2 to the voltage source Vss).

Two symmetrically arranged contact structures 80 A, 80 B, for example, the contact structure 80 A crosses over each fourth fin structure 54 D, and is electrically connected to the bit line BL 1 or the bit line BL 2 (please refer to FIG. 1 , where the contact structure 80 A electrically connected the source of the first pass gate device PG 1 and the second pass gate device PG 2 to the bit line BL 1 and the bit line BL 2 respectively).

Two symmetrically arranged contact structures 82 A, 82 B, for example, the contact structure 82 A disposed on each first pass gate structure 60 A, and electrically connected to the word line WL (please refer to FIG. 1 , where the contact structure 82 A electrically connected the gate of the first pass gate device PG 1 and the second pass gate device PG 2 to the word line WL).

Two symmetrically arranged contact structures 84 A, 84 B, for example, the contact structure 84 A disposed on the third fin structure 54 C, and electrically connected to the J-shaped structure 56 and the extending contact structure 72 A (please refer to FIG. 1 , where the contact structure 84 A electrically connected the gate of the first pull-up device PL 1 to the storage node 26 , and electrically connected the gate of the second pull-up device PL 2 to the storage node 24 ). Besides, the contact structures mentioned above are also arranged symmetrically, and will not be described again.

Furthermore, another feature of the present invention is when viewed in a top view, the extending contact structure 72 A does not overlap with the bridge part 56 C, and there is a gap G disposed therebetween. By the applicant's experiment, if the extending contact structure 72 A does not overlap with the bridge part 56 C, and the parasitic capacitance can be reduced, thereby improving the yield, and further improving the stability and speed of the SRAM.

The following description will detail the different embodiments of the SRAM of the present invention. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.

Referring to FIGS. 5-6 , FIG. 5 illustrates a circuit diagram of an eight-transistor SRAM (8T-SRAM) cell according to a second preferred embodiment of the present invention, and FIG. 6 illustrates a layout diagram of an 8T-SRAM according to the second preferred embodiment of the present invention.

As shown in FIGS. 5-6 , the SRAM device of the present invention preferably includes at least one SRAM cell, each SRAM cell including an eight-transistor SRAM (8T-SRAM) cell 12 .

In this embodiment, each 8T-SRAM cell 12 is composed of a first pull-up device PL 1 , a second pull-up device PL 2 , a first pull-down device PD 1 , a second pull-down device PD 2 , a first pass gate device PG 1 , a second pass gate device PG 2 , a third pass gate device PG 3 and a fourth pass gate device PG 4 . These eight devices (transistors) constitute a set of flip-flops. The first and the second pull-up devices PL 1 and PL 2 , and the first and the second pull-down devices PD 1 and PD 2 constitute a latch circuit 22 that stores data in the storage nodes 24 and 26 . Since the first and the second pull-up devices PL 1 and PL 2 act as power load devices, they can be replaced by resistors. Under this circumstance, the static random access memory becomes a four-transistor SRAM (4T-SRAM). In this embodiment, the first and the second pull-up devices PL 1 and PL 2 preferably share a source/drain region and electrically connect to a voltage source (voltage node) Vcc, and the first and the second pull-down devices PD 1 and PD 2 share a source/drain region and electrically connect to a voltage source (voltage node) Vss.

The storage node 24 is connected to the respective gates of the second pull-down device PD 2 and the second pull-up device PL 2 . The storage node 24 is also connected to the drains of the first pull-down device PD 1 , the first pull-up device PL 1 , the third pass gate device PG 3 and the second pass gate device PG 2 . Similarly, the storage node 26 is connected to the respective gates of the first pull-down device PD 1 and first the pull-up device PL 1 . The storage node 26 is also connected to the drains of the second pull-down device PD 2 , the second pull-up device PL 2 , the first pass gate device PG 1 and the fourth pass gate device PG 4 . The gates of the first pass gate device PG 1 and the third pass gate device PG 3 are respectively coupled to a first word line (WL 1 ); the gates of the second pass gate device PG 2 and the fourth pass gate device PG 4 are respectively coupled to a second word line (WL 2 ); the source of the first pass gate device PG 1 is coupled to a first bit line (BL 1 ); the source of the second pass gate device PG 2 is coupled to a second bit line (BL 2 ); the source of the third pass gate device PG 3 is coupled to a third bit line (BL 3 ); and the source of the fourth pass gate device PG 4 is coupled to a fourth bit line (BL 4 ).

Please refer to FIG. 6 , the layout pattern of the 8T-SRAM cell 12 and the layout pattern of the 6T-SRAM cell 10 (please refer to FIG. 2 ) are substantially the same, and the duplicate elements will not be described again. The difference between this embodiment and the first preferred embodiment is in this embodiment further comprising the third pass gate device PG 3 and the fourth pass gate device PG 4 . Therefore, besides the first fin structures 54 A (this embodiment includes six parallel arranged first fin structures 54 A), the second fin structures 54 B, the third fin structures 54 C and the fourth fin structures 54 D, this embodiment further comprises at least two fifth fin structures 54 E (also arranged symmetrically) disposed on the substrate 52 . Each fifth fin structure 54 E is disposed between the second fin structure 54 B and the fourth fin structure 54 D. In this embodiment, the left part (or the right part) of the 8T-SRAM cell 12 has two parallel arranged fifth fin structures 54 E. However, the amount of the fifth fin structure 54 E may include any integer greater than or equal to 1, and it can be adjusted according to actual requirements.

The 8T-SRAM cell 12 also comprises two symmetrically arranged second pass gate structures 62 A, 62 B disposed on the substrate 52 (here takes the second pass gate structures 62 A as an example). Preferably, the second pass gate structure 62 A is arranged along the first direction, and it's also arranged along the extending direction of the short part 56 B. In other words, the short part 56 B and the second pass gate structure 62 A have a same symmetry axis S. The second pass gate structure 62 A crosses over fifth fin structure 54 E, to constitute the gate of the second pass gate device PG 2 and the gate of the first pass gate device PG 1 mentioned above.

In addition, in this embodiment, the extending contact structure 72 A is disposed between the long part 56 A and the short part 56 B of the J-shaped structure 56 , and cross over each first fin structure 54 A, each second fin structure 54 B, each the third fin structure 54 C, each fourth fin structure 54 D and each fifth fin structure 54 E, to electrically connect each parallel arranged fin structure together. Please also refer to FIG. 5 , where the extending contact structure 72 A is electrically connected to the drain of the first pull-down device PD 1 , the first pull-up device PL 1 , the second pass gate device PG 2 and the third pass gate device PG 3 . Besides, when viewed in a top view, the shape of the extending contact structure 72 A may be a strip shape or other shapes (such as L-shaped), and the present invention is not limited thereto.

Furthermore, the other contact structures disposed on the substrate 52 including:

Two symmetrically arranged contact structures 74 A, 74 B, for example, the contact structure 74 A electrically connected to each third fin structure 54 C, and also electrically connected to the voltage source Vcc (please refer to FIG. 1 , where the contact structure 74 A electrically connected the source of the first pull-up device PL 1 and the second pull-up device PL 2 to the voltage source Vcc).

Two symmetrically arranged contact structures 76 A, 76 B, for example, the contact structure 76 A crosses over each first fin structure 54 A, and is electrically connected to the voltage source Vss (please refer to FIG. 1 , where the contact structure 76 A electrically connected the source of the first pull-down device PD 1 and the second pull-down device PD 2 to the voltage source Vss).

Two symmetrically arranged contact structures 78 A, 78 B, for example, the contact structure 78 A crosses over each second fin structure 54 B, and is electrically connected to the voltage source Vss (please refer to FIG. 1 , where the contact structure 78 A electrically connected the source of the first pull-down device PD 1 and the second pull-down device PD 2 to the voltage source Vss).

Two symmetrically arranged contact structures 80 A, 80 B, for example, the contact structure 80 A crosses over each fourth fin structure 54 D, and is electrically connected to the bit line BL 1 or the bit line BL 2 (please refer to FIG. 1 , where the contact structure 80 A electrically connected the source of the first pass gate device PG 1 and the second pass gate device PG 2 to the bit line BL 1 and the bit line BL 2 respectively).

Two symmetrically arranged contact structures 82 A, 82 B, for example, the contact structure 82 A disposed on each first pass gate structure 60 A, and electrically connected to the word line WL (please refer to FIG. 1 , where the contact structure 82 A electrically connected the gate of the first pass gate device PG 1 and the second pass gate device PG 2 to the word line WL).

Two symmetrically arranged contact structures 84 A, 84 B, for example, the contact structure 84 A disposed on the third fin structure 54 C, and electrically connected to the J-shaped structure 56 and the extending contact structure 72 (please refer to FIG. 1 , where the contact structure 84 A electrically connected the gate of the first pull-up device PL 1 to the storage node 26 , and electrically connected the gate of the second pull-up device PL 2 to the storage node 24 ).

Two symmetrically arranged contact structures 86 A, 86 B, for example, the contact structure 86 A disposed on each second pass gate structure 62 A, and electrically connected to the word line WL 2 or the word line WL 1 (please refer to FIG. 5 , where the contact structure 86 A electrically connected the gate of the second pass gate device PG 2 to the word line WL 2 , and electrically connected the gate of the first pass gate device PG 1 to the word line WL 1 ).

Two symmetrically arranged contact structures 88 A, 88 B, for example, the contact structure 88 A crosses over each fifth fin structure 54 E, and is electrically connected to the bit line BL 1 or the bit line BL 2 (please refer to FIG. 5 , where the contact structure 88 A electrically connected the source of the second pass gate device PG 2 to the bit line BL 2 , and electrically connected the source of the first pass gate device PG 1 to the bit line BL 1 respectively). Besides, the contact structures mentioned above are also arranged symmetrically, and will not be described again.

A key feature of this embodiment is in terms of the first pull-down device PD 1 , which comprises the J-shaped structure 56 , and the J-shaped structure 56 crosses over total eight fin structures (including the long part 56 A crossing six first fin structures 54 A, and the short part 56 B crossing two second fin structures 54 B). In this way, in a limited range, the gate can cross more fin structures. This increases the channel width of the first pull-down device PD 1 , and the read current (Iread) of one first pull-down device PD 1 can also be improved, so as to improve the read speed of the first pull-down device PD 1 . Furthermore, another feature of the present invention is when viewed in a top view, the extending contact structure 72 A does not overlap with the bridge part 56 C, and there is a gap G disposed therebetween. By the applicant's experiment, if the extending contact structure 72 A does not overlap with the bridge part 56 C, the parasitic capacitance can be reduced, thereby improving the yield, and further improving the stability and speed of the SRAM.

Each embodiment mentioned above includes a plurality of fin structures 54 disposed on the substrate 52 . However, in another embodiment of the present invention, there are no fin structures formed on the substrate, but a plurality of diffusion regions are formed in the substrate through an ion implantation process. Next, the processes mentioned above, including forming the J-shaped structures, forming the first pass gate structures and forming the contact structures, are performed. In other words, in the following embodiment, planar transistors are used to replace the finFET mentioned above. Please refer to FIG. 7 . FIG. 7 illustrates a layout diagram of a 6T-SRAM according to another preferred embodiment of the present invention. In this embodiment, the fin structures are not formed, and two symmetrically arranged first diffusion regions 58 A, two symmetrically arranged second diffusion regions 58 B, two symmetrically arranged third diffusion regions 58 C and two symmetrically arranged fourth diffusion regions 58 D are formed in the substrate 52 through an ion implantation process. Next, similar to the processes mentioned in the first preferred embodiment, the J-shaped structures 56 , the first pass gate structures 60 A, 60 B, the extending contact structures 72 A, 72 B, and a plurality of contact structures (including the contact structures 74 A, 74 B, 76 A, 76 B, 78 A, 78 B, 80 A, 80 B, 82 A, 82 B, 84 A and 84 B) are formed. The J-shaped structure 56 is disposed on the first diffusion region 58 A and on the second diffusion region 58 B, and each first pass gate structure 60 A (or 60 B) is disposed on the fourth diffusion region 58 D. In this embodiment, the gate of the first pull-down device PD 1 includes the J-shaped structure 56 , and the long part 56 A of the J-shaped structure 56 is disposed on the first diffusion region 58 A, the short part 56 B of the J-shaped structure 56 is disposed on the second diffusion region 58 B. Therefore, this embodiment has the same advantage as the one in the first preferred embodiment: the channel width of the first pull-down device PD 1 can be increased, and the read current (Iread) of one first pull-down device PD 1 can also be improved, so as to improve the read speed of the first pull-down device PD 1 . Except for the features mentioned above, the other components, material properties, and manufacturing method of this embodiment are similar to the first preferred embodiment detailed above (it can also refer to FIG. 2 ) and will not be redundantly described.

Similarly, in the layout pattern of the 8T-SRAM of the second preferred embodiment (please refer to FIG. 6 ), the planar transistors can be used to replace the finFET too. Please refer to FIG. 8 . FIG. 8 illustrates a layout diagram of an 8T-SRAM according to another preferred embodiment of the present invention. In this embodiment, the fin structures are not formed, and two symmetrically arranged first diffusion regions 58 A, two symmetrically arranged second diffusion regions 58 B, two symmetrically arranged third diffusion regions 58 C, two symmetrically arranged fourth diffusion regions 58 D and two symmetrically arranged fifth diffusion regions 58 E are formed in the substrate 52 through an ion implantation process. Next, similar to the processes mentioned in the second preferred embodiment, the J-shaped structures 56 , the first pass gate structures 60 A, 60 B, the second pass gate structures 62 A, 62 B, the extending contact structures 72 A, 72 B, and a plurality of contact structures (including the contact structures 74 A, 74 B, 76 A, 76 B, 78 A, 78 B, 80 A, 80 B, 82 A, 82 B, 84 A, 84 B, 86 A, 86 B, 88 A and 88 B) are formed. The J-shaped structure 56 is disposed on the first diffusion region 58 A and on the second diffusion region 58 B, the first pass gate structure 60 A is disposed on the fourth diffusion region 58 D, the second pass gate structure 62 A is disposed on the fifth diffusion region 58 E. In this embodiment, the gate of the first pull-down device PD 1 includes the J-shaped structure 56 , the long part 56 A of the J-shaped structure 56 is disposed on the first diffusion region 58 A, the short part 56 B of the J-shaped structure 56 is disposed on the second diffusion region 58 B. Therefore, this embodiment has the same advantage as the one in the first preferred embodiment: the channel width of the first pull-down device PD 1 can be increased, and the read current (Tread) of one first pull-down device PD 1 can also be improved, so as to improve the read speed of the first pull-down device PD 1 . Except for the features mentioned above, the other components, material properties, and manufacturing method of this embodiment are similar to the second preferred embodiment detailed above (it can also refer to FIG. 6 ) and will not be redundantly described.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.