DC-DC converter having predicted zero inductor current

The ever increasing demand of integrated electronic devices in automotive, industrial, and customer platforms requires more sophisticated power conversion and distribution designs. Often these electronic devices include embedded processors, memories, and other electronic components that are operated from one battery source. DC-to-DC voltage converters are used to supply different voltages to the different electronic components. These DC-to-DC converters operate in continuous and discontinuous conduction modes depending on the output load requirements.

The DC-to-DC converters typically enter the discontinuous mode under light load conditions to improve efficiency. However, the DC-to-DC converters can have operating anomalies that degrade their efficiency when operating in the discontinuous mode.

A DC-to-DC voltage converter includes a converter input for receiving a DC voltage. A first switch is coupled between the input and a first node. A second switch is coupled between the first node and a ground. An inductor is coupled between the first node and a converter output. A capacitor is coupled between the converter output and ground. An output voltage synthesizer is coupled to the converter input and the converter output for synthesizing the voltage at the converter output and for generating a control signal for at least one of the first switch and the second switch in response to the voltages at the converter input and the converter output.

FIG. 1 is a schematic diagram of a DC-to-DC converter.

FIG. 2 is a graph showing the current through the inductor L 1 of FIG. 1 as a function of the states of transistors Q 1 and Q 2 of FIG. 1 .

FIG. 3 is a schematic diagram of an example output voltage synthesizer of a DC-to-DC converter.

FIG. 4A is a graph of a synthesized output voltage from the output voltage synthesizer of FIG. 3 and the output voltage from the DC-to-DC converter of FIG. 1 .

FIG. 4B is a graph of a synthesized output voltage from the output voltage synthesizer of FIG. 3 and the output voltage from the DC-to-DC converter of FIG. 1 .

FIG. 5 is a schematic diagram of another example of an output voltage synthesizer.

FIG. 6 is a block diagram of a DC-to-DC converter having an output voltage synthesizer included therein.

FIG. 7 is a flowchart describing a method for operating a DC-to-DC converter.

FIG. 1 is a schematic diagram of a DC-to-DC converter 100 . The converter 100 includes a high-side switch, which is referred to as transistor Q 1 , and a low-side switch, which is referred to as transistor Q 2 . In the example of FIG. 1 , transistor Q 1 is a p-channel transistor and transistor Q 2 is an n-channel transistor. The source of transistor Q 1 is coupled to an input 102 . During operation of the converter 100 , the input 102 operates at an input voltage V IN , which is a DC voltage that is to be converted to another DC voltage by the converter 100 . The drain of transistor Q 1 is coupled to a node N 1 . The drain of transistor Q 2 is coupled to the node N 1 and the source of transistor Q 2 is coupled to a ground node. The ground node may operate at a potential of ground or a potential that is different than or lower than the input voltage V In .

A first terminal of an inductor L 1 is coupled to the node N 1 . The second terminal of the inductor L 1 is coupled to a capacitor C OUT . The junction of the inductor L 1 and the capacitor C OUT is the output 104 or output node of the converter 100 , which operates at an output voltage V OUT . The voltage V OUT is the DC voltage generated by the converter 100 .

The gates of transistors Q 1 and Q 2 are coupled to a gate controller 110 that generates gate voltages to turn the transistors Q 1 and Q 2 off and on. Accordingly, the gate controller 110 serves as a switch controller to control the switching function of transistors Q 1 and Q 2 . The converter 100 receives the input voltage V IN at the input 102 . The gate controller 110 turns transistors Q 1 and Q 2 off and on, so that one transistor is on while the other transistor is off. The off and on period controls the current I L flowing through the inductor L 1 . The current I L generates a voltage across the capacitor C OUT , which is the output voltage V OUT of the converter 100 . In discontinuous modes of operation, both transistor Q 1 and transistor Q 2 are turned off at the same time for a period.

FIG. 2 is a graph showing the current I L through the inductor L 1 as a function of time. The waveform 200 of the current I L is substantially triangular in response to the switching of transistors Q 1 and Q 2 . When transistor Q 1 is on, transistor Q 2 is off and when transistor Q 1 is off, transistor Q 2 is on as shown by a triangular waveform 202 . Both transistors Q 1 and Q 2 are off during the periods between triangular waveforms, which are designated T NO . The gate controller 110 determines the on and off time of the transistors Q 1 and Q 2 to obtain the correct output voltage V OUT . During a period referred to as the on-time T ON , transistor Q 1 is on and transistor Q 2 is off, so the inductor current I L increases. During a period referred to as the off-time T OFF , transistor Q 1 is off and transistor Q 2 is on, so the current I L decreases. The operation of the converter 100 as shown by the waveform 200 of FIG. 2 is in a discontinuous mode (DCM) because there is period T NO when neither transistor Q 1 nor transistor Q 2 is on. The period of the waveform 200 is referred to as the DCM operating period and the inverse is the DCM operating frequency.

The DCM operation of the converter 100 maintains the efficiency of the converter 100 when very light loads are coupled to the output 104 . In the DCM, the current I L in the inductor L 1 should not reverse because the reversal degrades the efficiency of the converter 100 . At higher loads, resistive losses are the main contributor to efficiency losses in the converter 100 . At light loads where DCM is used, switching and current reversal are the main contributors of efficiency losses. Current reversal in DCM has a two-fold impact on efficiency degradation. First, current reversal degrades efficiency by discharging the capacitor C OUT and second, it increases the switching frequency of the transistors Q 1 and Q 2 , which contributes to switching losses. For example, the converter 100 may use pulse frequency modulation (PFM) during DCM, so the switching frequency of the transistors Q 1 and Q 2 will increase if the inductor current I L reverses. Therefore, a need exists to switch off transistor Q 2 when the inductor current I L reaches zero to maximize the light load efficiency during DCM operation.

Many conventional techniques have been employed to prevent the inductor current I L from reversing. Some techniques include a diode to commutate the inductor current I L during the “de-energizing phase” of the inductor L 1 when the inductor current I L would otherwise reverse. The reversal of the inductor current I L does not occur because of the rectifying characteristics of the diode. When the load current, which is the output current, reduces to a point where the inductor current I L would reverse, the diode becomes high impedance and the converter 100 goes into the DCM or “pulse skipping mode” where the operating frequency of the converter 100 reduces linearly in proportion to the further reduction in load current. One of the problems with the rectifying diode is that it accounts for substantial losses when forward current flows through the diode.

In other implementations, the reversal of the inductor current I L is reduced by detecting the reversal and turning transistor Q 2 off. Such converters have a fast zero crossing comparator (not shown) that detects the reversal of the inductor current I L and then turns off the transistor Q 2 . The technique of a zero crossing comparator does not function adequately with high frequency converters because of the comparator delay in detecting the current reversal. More specifically, the comparators are not fast enough to detect the current reversal, which results in substantial losses and inefficiencies. With the industry trends of higher current converters and higher operating frequency converters, entry into the DCM is bottlenecked by this problem of current reversal.

The circuits and methods described herein predict rather than detect the inductor current I L . More specifically, the circuits and methods synthesize output voltage from on/off timers to predict zero inductor current I L by relying on the volt*second balance of an inductor. As applied to the converter 100 , the on-time T ON is proportional to the inverse of the difference between the input voltage V IN and the output voltage V OUT . The off-time T OFF is proportional to the inverse of the output voltage V OUT . The synthesizers described herein synthesize the converter 100 and estimate zero inductor current I L to control the states of the transistors Q 1 and Q 2 . The on-time T ON is fixed for a given V IN , V OUT and the off-time T OFF is controllable to generate the required off-time T OFF in a closed loop for a given V IN and V OUT . During the on-time T ON , the synthesizers charge a capacitor with a current proportional to the difference between the input voltage V IN and output voltage V OUT . During the off-time T OFF , the synthesizers discharge the same capacitor with a current proportional to the output voltage V OUT .

The on-time T ON and off-time T OFF are used to synthesize the output voltage V OUT . A synthesized output voltage V SYN is compared with the actual output voltage V OUT generated by the converter 100 and the differences between the two voltages V SYN and V OUT are balanced out or equalized in a control loop by adjusting the off-time T OFF , which controls the off-time T OFF of transistor Q 2 . Similar methods may be applied to other converter topologies, such as boost converters, constant on-time converters, and constant off-time converters.

FIG. 3 is a schematic diagram of an example of an output voltage synthesizer 300 that employs the voltage conversion techniques described above. The synthesizer 300 includes a transistor Q 3 and a transistor Q 4 , which are identical or substantially similar sized replicas of transistors Q 1 and Q 2 , respectively, of FIG. 1 . Transistors Q 3 and Q 4 function as switches and may be substituted by other switching components. The source of transistor Q 3 is coupled between an input 302 and a node N 3 . The input 302 is coupled to a node or the like that is coupled to the input voltage V IN of FIG. 1 . Accordingly, the source of transistor Q 3 is at the V IN voltage potential. The drain of transistor Q 4 is coupled to the node N 3 and the source of transistor Q 4 is coupled to ground. The ground is a potential that is different than the operating potential of the input voltage V IN and may be the same potential that the source of transistor Q 2 is coupled to.

A resistor R SYN is coupled between the node N 3 and a node N 4 . The resistor R SYN synthesizes the current drawn through the converter 100 of FIG. 1 as described below. A capacitor C SYN is coupled between the node N 4 and ground. The voltage potential at the node N 4 is the synthesized output voltage V SYN . An integrating transconductance stage 310 has a first input coupled to the node N 4 and a second input coupled to the output 104 of the converter 100 . Accordingly, the second input is at the potential of the output voltage V OUT of the converter 100 . The output of the transconductance stage 310 is coupled to a switch SW 1 , wherein the switch SW 1 is open during the T NO periods of FIG. 2 . The output of the transconductance stage 310 is described herein as being a voltage; however, the transconductance stage 310 may generate signals other than voltages. The other side of the switch SW 1 is coupled to a node N 5 . A capacitor C 2 and a T OFF controller 312 are both coupled to the node N 5 . A processor 314 is coupled to the gates of transistors Q 3 and Q 4 and controls the state of the switch SW 1 .

The value of R SYN is selected so that the current flow through resistor R SYN has the same form as the inductor current I L of FIG. 1 . The resistor R SYN and the capacitor C SYN form a low pass filter for the input waveform generated at the node N 3 . The selection of the time constant of the low pass filter of R SYN and C SYN provides a trade-off between speed and accuracy of the volt-sec balance regulation loop. If the time constant is small, the regulation loop settles faster but will have more inaccuracy. If the time constant is long, the regulation loop will take longer to settle, but will have fewer inaccuracies. In some examples, the time constant is selected to be 1/10 of the switching frequency of the transistors Q 3 and Q 4 to achieve a balance between accuracy and settling speed of the regulation loop.

Charging and discharging currents that synthesize the inductor current I L of FIG. 1 are developed as voltages across the resistor R SYN . In this case the charging current is proportional to the difference between the input voltage V IN and the output voltage V SYN at node N 4 . The discharging current is proportional to the synthesized output voltage V SYN at node N 4 . The voltage V SYN is filtered by the low pass filter of the resistor R SYN and the capacitor C SYN , which replicates the output of a buck converter, such as the converter 100 of FIG. 1 . The synthesized output voltage V SYN is compared to the actual output voltage V OUT of the converter 100 by the transconductance stage 310 . The switch SW 1 closes to charge the capacitor C 2 to the voltage output by the transconductance stage 310 and opens to hold the voltage for input to the T OFF controller 312 .

The T OFF controller 312 generates a signal that controls the off-time T OFF in both the converter 100 and the synthesizer 300 . For example, the signal generated by the T OFF controller 312 is processed by the processor 314 and the gate controller 110 to set the off-time T OFF . As can be seen in FIG. 3 , the signal generated by the T OFF controller 312 closes a feedback loop in the synthesizer 300 . In summary, the on-time T ON is always controlled by the processor 314 . The off-time T OFF is regulated and controlled by the T OFF controller 312 in DCM and is controlled by the processor 314 in CCM. In CCM, the converter 100 has much higher losses, such as power stage losses, so the actual off-time T OFF is smaller than the theoretical off-time T OFF . Therefore, the processor 314 overwrites the T OFF controller 312 in CCM.

FIGS. 4A and 4B are graphs of examples of the synthesized output voltage V SYN generated by the synthesizer 300 of FIG. 3 and the output voltage V OUT generated by the converter 100 of FIG. 1 . If the off-time T OFF of FIG. 2 is too long, then the synthesized output voltage V SNY will be lower than the actual output voltage V OUT as shown in FIG. 4A . A correction voltage generated by the transconductance stage 310 goes low to reduce the off-time T OFF . If the off-time T OFF is too short, then the synthesized output voltage V SYN will be higher than the actual output voltage V OUT as shown in FIG. 4B . The output of the transconductance stage 310 increases to increase the off-time T OFF . In steady state, the off-time T OFF will settle down to the required off-time T OFF .

The synthesizer 300 places an extra pole in the control loop of the converter 100 . The control loop includes the transconductance stage 310 and the gate controller 110 . The synthesizer 300 is simple to implement, so the pole may be worked around or avoided during operation of the synthesizer 300 . Because the resistor R SYN is being effectively switched at the DCM operating frequency, the pole introduced varies in direct proportion to the operating frequency. It is akin to a switched resistor filter. Thus, a compensation pole associated with the transconductance of the transconductance stage 310 and the capacitor C 2 also needs to vary in frequency proportional to the DCM operating frequency.

FIG. 5 is another example of an output voltage synthesizer 500 that overcomes the above-described pole problem. The synthesizer 500 is identical or similar to the synthesizer 300 of FIG. 3 except for the addition of a switch SW 2 and the location of the capacitor C 2 . In the example of FIG. 5 , the state of the switches SW 1 and SW 2 are controlled by the processor 314 . The above-described problems are overcome by commutating the output of the transconductance stage 310 into the capacitor C 2 during the generation time of the synthesized output voltage V SYN . The voltage V SYN is held by the capacitor C 2 during this time. Therefore, the non-dominant pole and its compensating dominant pole track one another, ensuring a constant phase margin over a wide DCM operating frequency range.

FIG. 6 is a block diagram of a DC-to-DC converter 600 that includes a voltage synthesizer 602 . The converter 600 is substantially similar to the converter 100 of FIG. 1 with the addition of the synthesizer 602 . The voltage synthesizer 602 may be any of the synthesizers described above. A gate controller 610 controls the on-times and off-times of two transistors Q 5 and Q 6 much in the same manner that the gate controller 110 of FIG. 1 controls the on-times and off-times of transistors Q 1 and Q 2 . The on-times and off-times of the transistors Q 5 and Q 6 determine the current flow I L through an inductor L 2 and an output capacitor C OUT .

The input voltage V IN and the output voltage V OUT are coupled to the synthesizer 602 as shown in FIGS. 3, 5, and 6 . The voltages V IN and V OUT are input to the synthesizer 602 to generate the T OFF signals, which are output to the gate controller 610 to control the on-time T ON and/or the off-time T OFF . The synthesizer 602 prevents or reduces the likelihood that the current I L reverses through the inductor L 2 , which improves the efficiency of the converter 600 . In some examples, the synthesizer 602 and the gate controller 610 are a single processor.

FIG. 7 is a flowchart 700 describing a method for operating a DC-to-DC converter based on the synthesizers described herein. In step 702 the current through an inductor is synthesized by generating a current through a resistor and a capacitor. In step 704 the voltage across the capacitor is compared to the output voltage of the converter. In step 706 the period in which current is conducted through the inductor is set in response to the comparison of the synthesized voltage to the output voltage.

While some examples of output voltage synthesizers and methods for synthesizing output voltages have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed and that the appended claims are intended to be construed to include such variations except insofar as limited by the prior art.