Method of driving display panel and display apparatus for performing the same

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0092451, filed on Jun. 29, 2015, the disclosure of which is incorporated by reference in its entirety herein.

1. Technical Field

Exemplary embodiments of the inventive concept relate to a method of driving a display panel and a display apparatus for performing the method.

2. Discussion of Related Art

A liquid crystal display (LCD) apparatus is typically thin, light and uses very little power consumption. Thus the LCD apparatus is used in monitors, laptop computers and cellular phones. The LCD apparatus includes an LCD panel displaying images using a light transmittance of a liquid crystal, a backlight assembly disposed under the LCD panel that provides light to the LCD panel and a driving circuit driving the LCD panel.

The liquid display panel includes an array substrate having gate lines, data lines, pixels and an opposing substrate, which has a common electrode. A liquid crystal layer is disposed between the array substrate and the opposing substrate. The driving circuit includes a gate driving part that drives the gate lines with gate signals and a data driving part that drives the data lines with data signals.

However, a RC time delay of the gate signal transferred through a gate line and the data signal transferred through a data line occurs when a liquid display panel has a large size. For example, the RC time delay of the gate signal occurs in an area far away from the gate driving part outputting the gate signal the gate driving part. The gate signal controls a charging period during which the data signal is charged in the pixel so that a charging ratio may be decreased by the RC time delay of the gate signal. The RC time delay may reduce the quality of the display panel. For example, luminance lowering, color mixing, and ghosting may be caused by the RC time delay.

At least one embodiment of the inventive concept provides a method of driving a display panel that is capable of decreasing a data charging ratio difference by a delay of a gate signal.

At least one embodiment of the inventive concept provides a display apparatus that performs a method of driving the display panel.

According to an exemplary embodiment of the inventive concept, a method of driving a display panel includes providing a positive polarity data signal to a first data line during an odd-numbered frame, and providing a negative polarity data signal to the first data line during an even-numbered frame. The positive polarity data signal has a first polarity. The negative polarity data signal has a second polarity. Output timing of the positive polarity data signal is different from output timing of the negative polarity data signal.

In an exemplary embodiment, the output timing of the positive polarity data signal precedes the output timing of the negative polarity data signal by a predetermined time period.

In an exemplary embodiment, during the odd-numbered frame, a negative polarity data signal having the second polarity is provided to a second data line which is adjacent to the first data line, and during the even-numbered frame, a positive polarity data signal having the first polarity is provided to the second data line.

In an exemplary embodiment, the predetermined time period is shorter than one horizontal period.

In an example embodiment, the predetermined time period is set to be proportional to a RC delay time period of a gate signal.

In an exemplary embodiment, the predetermined time period is about 30% of an RC delay time period of a gate signal.

In an exemplary embodiment, the method further includes generating a first clock signal, and generating a second clock signal, where the first clock signal and the second clock signal have rising times different from each other.

In an exemplary embodiment, during the odd-numbered frame, the first clock signal controls the output timing of data signal which is provided to the first data line, and during the even-numbered frame, the second clock signal controls the output timing of a data signal which is provided to the second data line.

In an exemplary embodiment, the first clock signal controls the output timing of the positive polarity data signal, and the second clock signal controls the output timing of the negative polarity data signal.

According to an exemplary embodiment of the inventive concept, a display apparatus includes a display panel including a plurality of data lines, a plurality of gate lines and a plurality of pixels, a data driver configured to provide a positive polarity data signal and a negative polarity data signal to the display panel. Each of the pixels includes a switching element electrically connected to a corresponding one of the gate lines and a corresponding one of the data lines. The positive polarity data signal has a first polarity. The negative polarity data signal has a second polarity. Output timing of the positive polarity data signal is different from output timing of the negative polarity data.

In an exemplary embodiment, the output timing of the positive polarity data signal precedes the output timing of the negative polarity data signal by a predetermined time period.

In an exemplary embodiment, the positive polarity data signal is provided to a first data line among the data lines during an odd-numbered frame, and the negative polarity data signal is provided to the first data line during an even-numbered frame.

In an exemplary embodiment, the data driver is configured to control output timing of the first data line using a first clock signal, and configured to control output timing of a second data line using a second clock signal.

In an exemplary embodiment, the data driver is configured to control output timing of the positive polarity data signal using a first clock signal, and configured to control output timing of a negative polarity data signal using a second clock signal.

In an exemplary embodiment, a second negative polarity data signal having the second polarity is provided to a second data line among the data lines during an odd-numbered frame, and a second positive polarity data signal having the first polarity is provided to the second data line during an even-numbered frame.

In an exemplary embodiment, the data driver is configured to control output timing of the first data line using a first clock signal, and configured to control output timing of a second data line using a second clock signal, where the second clock signal has a rising edge different from that of the first clock signal.

In an example embodiment, the predetermined time period is shorter than one horizontal period.

In an exemplary embodiment, the predetermined time period is set to be proportional to an RC delay time period of a gate signal.

In an exemplary embodiment, the predetermined time period is about 30% of an RC delay time period of a gate signal.

In an exemplary embodiment, during one frame, data signals having a same polarity are provided to a same data line.

According to an exemplary embodiment of the inventive concept, a driving apparatus for a display panel of a display apparatus includes a controller circuit configured to output a first clock signal with a first timing and a second clock signal with a second different timing; and a data driving circuit configured to provide a positive polarity data signal having a first polarity to a first data line of the display panel in response to the first clock signal, and provide a negative polarity data signal having a second polarity to a second adjacent data line of the display panel in response to the second clock signal.

In an embodiment, pulses of the second clock signal follow respective pulses of the first clock signal without overlap during an odd-numbered frame period, and pulses of the second clock signal precede respective pulses of the first clock signal without overlap during an even-numbered frame period.

In an embodiment, wherein pulses of the second clock signal follow respective pulses of the first clock signal with overlap during an odd-numbered frame period, and pulses of the second clock signal precede respective pulses of the first clock signal with overlap during an even-numbered frame period,

In an embodiment, wherein pulses of the second clock signal follow respective pulses of the first clock signal without overlap.

According to exemplary embodiments of the present inventive concept, output timing of a positive polarity data signal and output timing of a negative polarity data signal may be different each other, so that display quality degradation due to a charging ratio difference between positive and negative polarities according to an RC delay of a scan signal may be reduced.

The inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

FIG. 1 is a plan view illustrating a display panel according to an exemplary embodiment of the inventive concept;

FIG. 2 is a block diagram illustrating a display driving part of FIG. 1 according to an exemplary embodiment of the inventive concept;

FIG. 3 is a waveform diagram illustrating signals of the display driving part of FIG. 2 ;

FIGS. 4A and 4B are waveform diagrams illustrating a data charging ratio according to a gate signal and a data signal;

FIG. 5 is a graph illustrating set-up of a control time of an output enable signal and a predetermined time which is a difference of output timings of data signals according to an exemplary embodiment of the inventive concept;

FIG. 6 is a waveform diagram illustrating signals of a display driving part according to an exemplary embodiment of the inventive concept; and

FIG. 7 is a waveform diagram illustrating signals of a display driving part according to an exemplary embodiment of the inventive concept.

Hereinafter, exemplary embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

FIG. 1 is a plan view illustrating a display panel according to an exemplary embodiment of the inventive concept. FIG. 2 is a block diagram illustrating a display driving part of FIG. 1 .

Referring to FIGS. 1 and 2 , the display panel includes a display panel 100 and a display driving part 200 (e.g., a driver or a driver circuit).

The display panel 100 includes a plurality of data lines DL 1 , . . . , DLm, a plurality of gate lines GL 1 , . . . , GLn and a plurality of pixels P. Each of the pixels P includes a switching element TR connected to a data line DL 1 and a gate line GL 1 and a liquid crystal capacitor CLC connected to the switching element TR.

The pixels P are arranged as a matrix type which includes a plurality of pixel rows and a plurality of pixel columns. The data lines DL 1 , . . . , DLm are extended in a first direction D 1 , that is a column direction, and arranged in a second direction D 2 , that is, a row direction, crossing the first direction D 1 . Each of the data lines is electrically connected to the pixels of a same pixel column arranged in the first direction D 1 .

The gate lines GL 1 , . . . , GLn are extended in the second direction D 2 and arranged in the first direction D 1 . Each of the gate lines is electrically connected to the pixels of a same pixel row arranged in the second direction D 2 .

The display driving part 200 includes a control circuit part 210 (e.g., a controller or a control circuit), a data driving part 230 (e.g., a data/source driver or a data/source driver circuit) and a gate driving part 250 (e.g., a gate/scan driver or gate/scan driver circuit). The control circuit part 210 controls operation of the data driving part 230 . In an embodiment the control circuit part 210 is incorporated within a timing controller.

For example, the control circuit part 210 provides the data driving part 230 with at least one of a data signal DATA and a data control signal. In an embodiment, the data signal DATA includes a color data signal and may be a signal corrected using compensation algorithms for improving a response time of liquid crystal and for compensating a white.

In an embodiment, the data control signal includes a first clock signal CLK 1 , a second clock signal CLK 2 and a polarity inversion signal POL.

The data driving part 230 provides data signals YO 1 , YE 1 , . . . , YOm/2, YEm/2 to the data lines DL 1 , . . . , DLm according to a column inversion mode. The data driving part 230 outputs the data signals YO 1 , YE 1 , . . . , YOm/2, YEm/2 based on the first clock signal CLK 1 , the second clock signal CLK 2 and the polarity inversion signal POL.

For example, the data driving part 230 may provide data signals having polarities different from each other to adjacent data lines. In an embodiment, the data signals have different polarities each one frame period. In an embodiment, one frame period is a period during which data signals are output an entire group of pixel rows (e.g., all odd pixel rows or all even pixel rows). Thus, odd-numbered data signals YO 1 , . . . , YOm/2 may be provided to odd-numbered data lines (e.g., D 1 , D 3 , etc.) and even-numbered data signal YE 1 , . . . , YEm/2 may be provided to even-numbered data lines (e.g., D 2 , D 4 , etc.). The odd-numbered data signals YO 1 , . . . , YOm/2 may have first polarity or second polarity with respect to reference signal according to the polarity inversion signal POL. The even-numbered data signals YE 1 , . . . , YEm/2 may have first polarity or second polarity with respect to the reference signal according to the polarity inversion signal POL. The polarity inversion signal POL may have different value in every frame. For example, the voltage level of the polarity inversion signal POL may toggle between first and a second different logic levels each next frame period. Accordingly, the display panel 100 may be driven by a column inversion mode and a frame inversion mode.

In an embodiment, the control circuit part 210 controls the gate driving part 250 .

In an embodiment, the control circuit part 210 provides a gate control signal GCONT to the gate driving part 250 .

The gate driving part 250 may include a plurality of shift resistors which generate gate signals G 1 , G 2 , G 3 , . . . , Gn. The gate driving part 250 receives the gate control signal GCONT from the control circuit part 210 . The gate control signal GCONT may include a gate on signal, a gate off signal, a vertical start signal, a gate clock signal, an output enable signal (e.g., refer to OE of FIG. 4B ).

The vertical start signal may control a start timing at which an operation of the gate driving part 250 is started. The gate clock signal may control a rising timing, that is, a start timing of a rising period during which each of the gate signals G 1 , . . . , Gn rises from a low level to a high level. The output enable control signal OE may control a falling timing, that is, a start timing of a falling period during which each of the gate signals G 1 , . . . , Gn falls from the high level to the low level.

The gate on signal may control a gate-on level (or voltage) of the gate signals G 1 , . . . , Gn and the gate-off signal (or voltage) may control a gate-off level of the gate signals G 1 , . . . , Gn. In an embodiment, the level of the gate-on signal differs from the level of the gate-off signal.

FIG. 3 is a waveform diagram illustrating signals of the display driving part of FIG. 2 .

Referring to FIGS. 2 and 3 , a data driving part 230 receives a first clock signal CLK 1 , a second clock signal CLK 2 and a polarity inversion signal POL from a control circuit part 210 , and outputs the data signals YO 1 , YE 1 . Thus, odd-numbered data signals YO 1 , . . . , YOm/2 may be provided to odd-numbered data lines, and even-numbered data signals YE 1 , . . . , YEm/2 may be provided to even-numbered data lines. A gate driving part 250 receives the gate control signal GCONT from the control circuit part 210 and outputs gate signals G 1 , G 2 . The display driving part 200 may be driven by a column inversion mode and a frame inversion mode.

For convenience of explanation, only gate signals G 1 , G 2 for first and second gate lines, and odd-numbered data signal YO 1 and even-numbered data signal YE 1 will be explained.

The first clock signal CLK 1 may control a rising time, that is, a start timing of a rising period during which each the odd-numbered data signal YO 1 rises from a low level to a high level. Thus, each of the data values that is included in the odd-numbered data signal YO 1 may be outputted with reference to the first clock signal CLK 1 every one horizontal period 1 H.

In addition, although the data values are changed with reference to a rising edge of the first clock signal CLK 1 , the inventive concept is not limited thereto. For example, the data values of the odd-numbered data signal YO 1 in every horizontal period 1 H may be outputted in synchronization with a rising edge or a falling edge of the first clock signal CLK 1 .

The second clock signal CLK 2 may control a rising time, that is, a start timing of a rising period during which the even-numbered data signal YE 1 rises from a low level to a high level. Thus, each of the data values which is included in the even-numbered data signal YE 1 may be outputted with reference to the second clock signal CLK 2 every one horizontal period 1 H.

In addition, although the data values are changed with reference to a rising edge of the second clock signal CLK 2 , the inventive concept is not limited thereto. For example, the data values of the even-numbered data signal YE 1 every one horizontal period 1 H may be outputted in synchronization with a rising edge or a falling edge of the second clock signal CLK 2 .

During an odd-numbered frame period O_FRAME, the first clock signal CLK 1 precedes the second clock signal CLK 2 by a predetermined time period Δt. During an even-numbered frame period E_FRAME, the second clock signal CLK 2 precedes the first clock signal CLK 1 by a predetermined time period Δt. In an embodiment, during part of the odd-numbered frame period O_FRAME, a pulse of the first clock signal CLK 1 precedes a pulse of the second clock signal CLK 2 without overlapping. In an embodiment, during part of the even-numbered frame period E_FRAME, a pulse of the second clock signal CLK 2 precedes a pulse of the first clock signal CLK 1 without overlapping. In an embodiment, first pulses of the first clock signal CLK 1 during the odd-numbered frame period O_FRAME are out of phase with first pulses of the second clock signal CLK 2 during the odd-numbered frame period O_FRAME by a first angle. In an embodiment, second pulses of the first clock signal CLK 1 during the even-numbered frame period E_FRAME are out of phase with second pulses of the second clock signal CLK 2 during the even-numbered frame period E_FRAME by a second angle.

A clock signal (first clock signal CLK 1 or second clock signal CLK 2 ) which is synchronized to the data value which has a positive polarity may precede a clock signal (second clock signal CLK 2 or first clock signal CLK 1 ) which is synchronized to the data value which has a negative polarity by the predetermined time Δt. Thus, a data signal which has a positive polarity value may be outputted before a data signal which has a negative polarity value by the predetermined time Δt. In an embodiment, the predetermined time Δt has a duration that is the same as the duration of one of the pulses of the clock signals.

In an embodiment, the polarity inversion signal POL reverses the data signals YO 1 , YE 1 . For example, the polarity inversion signal POL may have a low level during the odd-numbered frame period O_FRAME, and have a high level during even-numbered frame period E_FRAME. Accordingly, the odd-numbered data signal YO 1 has data values which have different polarities in the odd-numbered frame period O_FRAME and the even-numbered frame period E_FRAME. The even-numbered data signal YE 1 has data values which have different polarities in the odd-numbered frame period O_FRAME and the even-numbered frame period E_FRAME.

The gate driving part 250 may generate the gate signals G 1 , G 2 which have a gate-on level and a gate-off level using a gate-on signal having a high level and a gate-off signal having a low level. Each of the gate signals G 1 , G 2 may be provided to each of the first and second gate lines first during two horizontal periods 2 H, in order. The falling timing of gate signals G 1 , G 2 may be set by a control period W of an output enable control signal (e.g., refer to OE of FIG. 4B ).

The odd-numbered data signal YO 1 has a positive (+) data value with reference to a reference signal VCOM during the odd-numbered frame period O_FRAME. The odd-numbered data signal YO 1 has a negative (−) data value with reference to the reference signal VCOM during the even-numbered frame period E_FRAME.

The even-numbered data signal YE 1 has a negative (−) data value with reference to the reference signal VCOM during the odd-numbered frame period O_FRAME. The even-numbered data signal YE 1 has a positive (+) data value with reference to the reference signal VCOM during the even-numbered frame period E_FRAME.

According to the present exemplary embodiment, a data signal having the positive data value precedes the data signal having the negative data value by the predetermined time Δt, so that a positive data charging time is longer than a negative data charging time by the predetermined time Δt. Thus, display quality degradation due to a charging ratio difference according to polarities may be reduced.

FIGS. 4A and 4B are waveform diagrams illustrating a data charging ratio according to a gate signal and a data signal.

FIG. 4A is a waveform diagram illustrating a data charging ratio by a gate signal according to a comparative embodiment. FIG. 4B is a waveform diagram illustrating a data charging ratio by a gate signal according to an exemplary embodiment of the inventive concept.

Generally, the output-enable control signal controls the falling timing of the gate signal to prevent the data signals applied to adjacent pixel rows from mixing. The RC delay time period of the gate signal is increased in an area far away from the gate driving part. For example, when the gate driving part is respectively disposed in areas adjacent to both ends of the gate line, such as a dual-bank structure, the RC delay time period of the gate signal is largest in a central area of the display panel in a horizontal direction. Therefore, the output-enable control signal is determined depending on a delay condition of the central area, in which the RC delay time period of the gate signal is largest.

Referring to FIG. 4A , according to the comparative embodiment, the output-enable control signal OEc has a control period Wc which controls a falling timing Fc of a gate signal Gd. The control period Wc is determined depending on the negative polarity data signal (−) which is a worst case to prevent the data signals of adjacent pixel rows from mixing.

Thus, the positive polarity data signal (+) has a first charging time period Tc 1 and the negative polarity data signal (−) has a second charging time period Tc 2 , by the gate signal Gd having the falling timing which is determined by the control period We of the output-enable control signal OEc. The second charging time period Tc 2 is greater than the first charging time Tc 1 by Δt.

In other words, a gate/source voltage ON_Vgs 1 of the positive polarity (+) is less than a gate/source voltage ON_Vgs 2 of the negative polarity (−). When the gate/source voltage Vgs is increased, an output current Id of the transistor is increased. Thus, a data charging ratio of the negative polarity (−) is more than a data charging ratio of the positive polarity (+). As described above, a charging ratio difference between the positive polarity (+) and the negative polarity (−) causes a lower-quality display with a flicker or an after-image.

In addition, the gate/source voltage OFF_Vgs 1 of the positive polarity (+) is different from the gate/source voltage OFF_Vgs 2 of the negative polarity (−) so that a turn-off period of the positive polarity (+) is different from that of the negative polarity (−), in a voltage-current curve of a transistor. Therefore, an off-leakage current of the positive polarity (+) is different from an off-leakage current of the negative polarity (−), so that an off-leakage current difference causes a lower-quality display with a flicker or an after-image.

Referring to FIG. 4B , according to an exemplary embodiment of the inventive concept, the positive polarity data signal (+) precedes the negative polarity data signal (−) by a predetermined time Δt.

The output-enable control signal OE has a control period W which controls a falling timing F of a gate signal Gd. The control period W is determined depending on the negative polarity data signal (−) which is a worst case to prevent the data signals of adjacent pixel rows from mixing.

Accordingly, the positive polarity data signal (+) has a first charging time period T 1 , and the negative polarity data signal (−) has a second charging time period T 2 , by the gate signal Gd which corresponds to the control period of the output-enable control signal OE. Since the positive polarity data signal (+) precedes the negative polarity data signal (−) by the predetermined time Δt, the positive polarity data signal (+) has a charging time that is longer than that of FIG. 4A by the predetermined time Δt. Thus, display quality degradation due to charging ratio differences according to polarities may be reduced.

FIG. 5 is a graph illustrating set-up of a control time of an output enable signal and a predetermined time which is a difference of output timings of data signals.

Referring to FIG. 5 , the graph has an x-axis which means time, and a y-axis which means voltage V. An ideal gate signal G and a delayed gate signal Gd are illustrated.

An RC delay value GRC of a gate signal may be calculated by a traditional method. A predetermined time (refers to Δt of FIG. 4B ) which is a time interval of the positive polarity data signal (+) and the negative polarity data signal (−) may be set according to the RC delay value GRC, a reference voltage, a voltage range of a positive polarity data signal (+), and a voltage range of a negative polarity data signal (−).

In an embodiment, the predetermined time is proportional to the RC delay value GRC.

In addition, an output-enable control signal (refer to OE of FIG. 4B ) may be set based on the negative polarity data signal (−), or based on the positive polarity data signal (+).

For example, when voltage range of the positive polarity data signal (+) is 8V to 15V and voltage range of the negative polarity data signal (−) is 0V to 7V, a control period of the output-enable control signal (refer to W of FIG. 4B ) may be set to 0.7*RC delay value GRC=dt 1 by calculating with reference to a reference time when the negative polarity data signal (−) is 0V (white for normally black mode).

In this example, 0.4*RC delay value GRC=dt 2 may be calculated with reference to a reference time when the positive polarity data signal (+) is 8V (black for normally black mode). Thus, the positive polarity data signal (+) has more charging time as a difference between dt 1 and dt 2 , is about 30% of the RC delay value GRC. In an embodiment, the difference between dt 1 and dt 2 is the same as the predetermined time.

FIG. 6 is a waveform diagram illustrating signals of a display driving part according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 2 and 6 , a data driving part 230 outputs the data signals YO 1 , YE 1 based on the first clock signal CLK 1 , the second clock signal CLK 2 and the polarity inversion signal POL from a control circuit part 210 . Thus, odd-numbered data signal YO 1 may be provided to odd-numbered data lines and even-numbered data signal YE 1 may be provided to even-numbered data lines. The gate driving part 250 receives the gate control signal GCONT from a control circuit part 210 and outputs gate signals G 1 , G 2 . The display driving part may be driven by a column inversion mode and a frame inversion mode.

For convenience of explanation, only gate signals G 1 , G 2 for first and second gate lines, and odd-numbered data signal YO 1 and even-numbered data signal YE 1 will be explained.

The first clock signal CLK 1 may control a rising time, that is, a start timing of a rising period during which each of the odd-numbered data signals YO 1 rise from a low level to a high level. Thus, the each of the data values which is included in the odd-numbered data signal YO 1 may be outputted with reference to the first clock signal CLK 1 every one horizontal period 1 H.

In addition, although the data values are changed with reference to a rising edge of the first clock signal CLK 1 , the inventive concept is not limited thereto. For example, the data values of the odd-numbered data signal YO 1 every one horizontal period 1 H may be outputted in synchronization with a rising edge or a falling edge of the first clock signal CLK 1 .

The second clock signal CLK 2 may control a rising time, that is, a start timing of a rising period during which the even-numbered data signal YE 1 rises from a low level to a high level. Thus, each of the data values which is included in the even-numbered data signal YE 1 may be outputted with reference to the second clock signal CLK 2 every one horizontal period 1 H.

In addition, although the data values are changed with reference to a rising edge of the second clock signal CLK 2 , the inventive concept is not limited thereto. For example, the data values of the even-numbered data signal YE 1 every one horizontal period 1 H may be outputted in synchronization with a rising edge or a falling edge of the second clock signal CLK 2 .

During an odd-numbered frame period O_FRAME, the second clock signal CLK 2 follows the first clock signal CLK 1 by a predetermined time Δt. For example, during part of an odd-numbered frame period O_FRAME, a pulse of the second clock signal CLK 2 follows and partially overlaps a pulse of the first clock signal CLK 1 . In an embodiment, first pulses of the first clock signal CLK 1 during the odd-numbered frame period O_FRAME are out of phase with first pulses of the second clock signal CLK 2 during the odd-numbered frame period O_FRAME by a first angle. During an even-numbered frame period E_FRAME, the first clock signal CLK 1 follows the second clock signal CLK 2 by a predetermined time Δt. For example, during part of the even-numbered frame E_FRAME, a pulse of the first clock signal CLK 1 follows and partially overlaps a pulse of the second clock signal CLK 2 . In an embodiment, second pulses of the first clock signal CLK 1 during the even-numbered frame period E_FRAME are out of phase with second pulses of the second clock signal CLK 2 during the even-numbered frame period E_FRAME by a second angle.

Thus, a clock signal (second clock signal CLK 2 or first clock signal CLK 1 ) which is synchronized to the data value which has a negative polarity follows a clock signal (first clock signal CLK 1 or second clock signal CLK 2 ) which is synchronized to the data value which has a positive polarity by the predetermined time Δt. Thus, a data signal which has a negative polarity value may be outputted next to a data signal which has positive polarity value by the predetermined time Δt.

The polarity inversion signal POL reverses the data signals YO 1 , YE 1 . For example, the polarity inversion signal POL may have a low level during the odd-numbered frame period O_FRAME, and have a high level during the even-numbered frame period E_FRAME. Accordingly, the odd-numbered data signal YO 1 has data values which have different polarities in the odd-numbered frame period O_FRAME and the even-numbered frame period E_FRAME. The even-numbered data signal YE 1 has data values which have different polarities in the odd-numbered frame period O_FRAME and the even-numbered frame period E_FRAME.

The gate driving part 250 may generate the gate signal G 1 , G 2 which have a gate-on level and a gate-off level using a gate-on signal having a high level and a gate-off signal having a low level. Each of the gate signals G 1 , G 2 may be provided to each of the first and second gate lines first during two horizontal periods 2 H, in order. The falling timing of gate signals G 1 , G 2 may be set by a control period W of an output enable control signal (e.g., refers to OE of FIG. 4B ).

In an embodiment, the output enable control signal is set with reference to a negative polarity data signal, so that the control period W is set in consideration of the predetermined time Δt.

The odd-numbered data signal YO 1 may have a positive (+) data value with reference to a reference signal VCOM during the odd-numbered frame period O_FRAME. The odd-numbered data signal YO 1 may have a negative (−) data value with reference to the reference signal VCOM during the even-numbered frame period E_FRAME.

The even-numbered data signal YE 1 may have a negative (−) data value with reference to the reference signal VCOM during the odd-numbered frame period O_FRAME. The even-numbered data signal YE 1 may have a positive (+) data value with reference to the reference signal VCOM during the even-numbered frame period E_FRAME.

According to the present exemplary embodiment, a data signal having a negative data value follows a data signal having a positive data value by the predetermined time Δt, so that a positive data charging time is longer than a negative data charging time by the predetermined time Δt. Thus, display quality degradation due to charging ratio differences according to polarities may be reduced.

FIG. 7 is a waveform diagram illustrating signals of a display driving part according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 2 and 7 , a data driving part 230 may output the data signals YO 1 , YE 1 based on the first clock signal CLK 1 , the second clock signal CLK 2 and the polarity inversion signal POL from a control circuit part 210 . Thus, odd-numbered data signal YO 1 may be provided to odd-numbered data lines and even-numbered data signal YE 1 may be provided to even-numbered data lines. The gate driving part 250 may receive the gate control signal GCONT from the control circuit part 210 and output gate signals G 1 , G 2 . The display driving part may be driven by a column inversion mode and a frame inversion mode.

For convenience of explanation, only gate signals G 1 , G 2 for first and second gate lines, and odd-numbered data signal YO 1 and even-numbered data signal YE 1 will be explained.

The first clock signal CLK 1 precedes the second clock signal CLK 2 by a predetermined time Δt. For example, pulses of the first clock signal CLK 1 precede respective pulses of the second clock signal CLK 2 in the odd-numbered frame period O_FRAME and the even-numbered frame period E_FRAME.

The first clock signal CLK 1 may control output timing of data signal which includes positive polarity data values. The second clock signal CLK 2 may control output timing of data signals which includes negative polarity data value.

For example, during an odd-numbered frame period O_FRAME, each of the data values of the odd-numbered data signal YO 1 may be outputted with reference to the first clock signal CLK 1 every one horizontal period 1 H. In an embodiment, during the odd-numbered frame period O_FRAME, each of the data values of the even-numbered data signal YE 1 are outputted with reference to the second clock signal CLK 2 every one horizontal period 1 H.

In addition, during an even-numbered frame period E_FRAME, each of the data values of the odd-numbered data signal YO 1 may be outputted with reference to the second clock signal CLK 2 every one horizontal period 1 H. In an embodiment, during the even-numbered frame period E_FRAME, each of the data values of the even-numbered data signal YE 1 is outputted with reference to the first clock signal CLK 1 every one horizontal period 1 H.

In addition, although the data values are changed with reference to a rising edge of the second clock signal CLK 2 , the inventive concept is not limited thereto. For example, the data values of the even-numbered data signal YE 1 every one horizontal period 1 H may be outputted in synchronization with a rising edge or a falling edge of the second clock signal CLK 2 .

The polarity inversion signal POL reverses the data signals YO 1 , YE 1 . For example, the polarity inversion signal POL may have a low level during the odd-numbered frame period O_FRAME, and have a high level during even-numbered frame period E_FRAME. Accordingly, the odd-numbered data signal YO 1 may have data values which have different polarities in the odd-numbered frame period O_FRAME and the even-numbered frame period E_FRAME. The even-numbered data signal YE 1 may have data values which have different polarities in the odd-numbered frame period O_FRAME and the even-numbered frame period E_FRAME.

In addition, the first and second clock signals CLK 1 , CLK 2 may be synchronized to the odd or even-numbered data signal YO 1 , YE 1 based on the polarity inversion signal POL. For example, during the odd-numbered frame period O_FRAME, when the polarity inversion signal POL has the low level, the first clock signal CLK 1 is synchronized to the odd-numbered data signal YO 1 , and the second clock signal CLK 2 is synchronized to the even-numbered data signal YE 1 . In addition, during the even-numbered frame period E_FRAME, when the polarity inversion signal POL has the high level, the first clock signal CLK 1 is synchronized to the even-numbered data signal YE 1 , and the second clock signal CLK 2 is synchronized to the odd-numbered data signal YO 1 .

The gate driving part 250 may generate the gate signal G 1 , G 2 which have gate-on level and gate-off level using a gate-on signal having a high level and a gate-off signal having a low level. Each of the gate signals G 1 , G 2 may be provided to each of the first and second gate lines first during two horizontal periods 2 H, in order. The falling timing of gate signals G 1 , G 2 may be set by a control period W of an output enable control signal (e.g., refer to OE of FIG. 4B ).

The odd-numbered data signal YO 1 may have a positive (+) data value with reference to a reference signal VCOM during the odd-numbered frame period O_FRAME. The odd-numbered data signal YO 1 may have a negative (−) data value with reference to the reference signal VCOM during the even-numbered frame period E_FRAME.

The even-numbered data signal YE 1 may have a negative (−) data value with reference to the reference signal VCOM during the odd-numbered frame period O_FRAME. The even-numbered data signal YE 1 may have a positive (+) data value with reference to the reference signal VCOM during the even-numbered frame period E_FRAME.

According to the present exemplary embodiment, a data signal having the negative data value follows a data signal having a positive data value by the predetermined time Δt, so that positive data charging time is longer than negative data charging time by the predetermined time Δt. Thus, display quality degradation due to charging ratio differences according to polarities may be reduced.

According to exemplary embodiments of the present inventive concept, output timing of positive polarity data signals and output timing of negative polarity data signals may be different from each other, so that display quality degradation due to charging ratio differences between positive and negative polarities according to an RC delay of a scan signal (e.g., a gate signal) may be reduced.

The foregoing is illustrative of the inventive concept and is not to be construed as limiting thereof. Although a few exemplary embodiments of the inventive concept have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept.