Control apparatus for AC rotary machine and control apparatus for electric power steering

This application is a National Stage of International Application No. PCT/JP2014/054146 filed Feb. 21, 2014, the contents of all of which are incorporated herein by reference in their entirety.

This invention is a control apparatus for an AC rotary machine and a control apparatus for an electric power steering, with which an output of the AC rotary machine can be improved without the need to modify a control period.

In a phase current detection device of a conventional three-phase PWM inverter apparatus, a control period Tsw is varied in length in accordance with a phase command value θ* and a voltage command value V*. In an example disclosed in the prior art (see PTL 1, for example), when a holding time (t 1 or t 2 ) of a switching mode corresponding to a basic voltage vector other than a zero vector, the basic voltage vector being determined in accordance with the phase command value θ* and the voltage command value V*, is longer than a sum (tdd+tsw) of a dead time tdd of an inverter main circuit and a time tsw required for current detection by a hole CT 9 , a fixed short control period Tsw is selected. When the holding time of the switching mode is shorter than the time (tdd+tsw), on the other hand, the control period Tsw is lengthened so that the holding time is longer than the time (tdd+tsw).

Patent Literature

[PTL 1]

Japanese Patent Application Publication No. H3-230767

Technical Problem

However, the prior art contains the following problem. When the control period Tsw is lengthened, a PWM period (which is equal to the control period Tsw) output by the three-phase PWM inverter apparatus increases in length, leading to a reduction in a PWM frequency, which is given by the inverse of the PWM period. When an AC rotary machine is connected to the output of the three-phase PWM inverter, a component having the PWM frequency is included in a current flowing through the AC rotary machine. Therefore, when the PWM frequency decreases, the frequency of the component included in the current also decreases, with the result that noise is generated by the AC rotary machine.

In an AC rotary machine used in an electric power steering in particular, quietness is required, and therefore the PWM frequency is set to be no lower than 20 kHz (a frequency band exceeding an audible range), for example. Here, when a method of lengthening the control period Tsw (lowering the PWM frequency), such as that of PTL 1, is applied to an AC rotary machine used in an electric power steering, the PWM frequency falls below 20 kHz. As a result, noise is generated by the AC rotary machine, causing a person traveling in a vehicle installed with the electric power steering to experience discomfort.

This invention has been designed to solve the problem described above, and an object thereof is to provide a control apparatus for an AC rotary machine and a control apparatus for an electric power steering, with which an output of the AC rotary machine can be improved without the need to modify a control period.

Solution to Problem

A control apparatus for an AC rotary machine according to this invention includes: an AC rotary machine that includes a first winding and a second winding which have a phase difference; a first current detection unit that detects a current of the first winding; a second current detection unit that detects a current of the second winding; a control unit that calculates a first voltage command and a second voltage command on the basis of a detected current value of the AC rotary machine; a first voltage application unit that applies a voltage to the first winding on the basis of the first voltage command; a second voltage application unit that applies a voltage to the second winding on the basis of the second voltage command; and a first detectability determination unit that determines a detectability of the current of the first winding, detected by the first current detection unit, on the basis of at least one of the first voltage command and the second voltage command, wherein the control unit calculates the first voltage command on the basis of the current of the first winding, detected by the first current detection unit, when the first detectability determination unit determines that the current of the first winding is detectable, and calculates the first voltage command and the second voltage command on the basis of the current of the second winding, detected by the second current detection unit, when the first detectability determination unit determines that the current of the first winding is undetectable.

Further, a control apparatus for an electric power steering according to this invention includes the control apparatus for an AC rotary machine according to this invention, wherein the control unit calculates the first voltage command and the second voltage command such that the AC rotary machine generates torque for assisting steering torque of a steering system.

Advantageous Effects of Invention

According to this invention, when the first detectability determination unit determines that the current of the first winding is detectable, the first voltage command is calculated on the basis of the current of the first winding, detected by the first current detection unit, and when the first detectability determination unit determines that the current of the first winding is undetectable, the first voltage command and the second voltage command are calculated on the basis of the current of the second winding, detected by the second current detection unit. As a result, a striking effect not evident in the prior art, according to which the output of the AC rotary machine can be increased while reducing noise generated by the AC rotary machine, is obtained.

FIG. 1 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a first embodiment of this invention.

FIG. 2 is a view illustrating a configuration of a three-phase AC rotary machine used as an example of the AC rotary machine according to the first embodiment of this invention.

FIG. 3 is a view showing relationships between a first voltage vector corresponding to ON/OFF conditions of respective semiconductor switches and a current flowing through a DC bus line of a first voltage application unit, according to the first embodiment of this invention.

FIG. 4 is a view showing a relationship between a second voltage vector corresponding to the ON/OFF conditions of the respective semiconductor switches and a current flowing through a DC bus line of a second voltage application unit, according to the first embodiment of this invention.

FIG. 5 is an illustrative view showing a first voltage command vector based on first voltage commands and a second voltage command vector based on second voltage commands, according to the first embodiment of this invention.

FIG. 6 is a waveform diagram showing the first voltage commands and the second voltage commands according to the first embodiment of this invention.

FIGS. 7A, 7B and 7C are views illustrating relationships between the voltage commands and ON ratios of upper side arm elements of respective phases with respect to the first voltage application unit, according to the first embodiment of this invention.

FIGS. 8A, 8B and 8C are views illustrating relationships between the voltage commands and the ON ratios of the upper side arm elements of the respective phases with respect to the second voltage application unit, according to the first embodiment of this invention.

FIG. 9 is a view illustrating operations relating to ON/OFF patterns of the semiconductor switches and a period of a switching signal in current detection units, according to the first embodiment of this invention.

FIG. 10 is a view illustrating different operations to those of FIG. 9 relating to the ON/OFF patterns of the semiconductor switches and the period of the switching signal in the current detection units, according to the first embodiment of this invention.

FIG. 11 is a view illustrating different operations to those of FIGS. 9 and 10 relating to the ON/OFF patterns of the semiconductor switches and the period of the switching signal in the current detection units, according to the first embodiment of this invention.

FIGS. 12A, 12B, 12C and 12D are illustrative views relating to a function of a first detectability determination unit according to the first embodiment of this invention.

FIG. 13 is a flowchart showing a series of operations performed by the first detectability determination unit according to the first embodiment of this invention.

FIG. 14 is a flowchart showing a series of operations performed by a first detectability determination unit according to a second embodiment of this invention.

FIGS. 15A, 15B, 15C and 15D are views showing waveforms described in the steps of FIG. 14 in a case where a third predetermined value is set at 0.1 Vdc, according to the second embodiment of this invention.

FIG. 16 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a fourth embodiment of this invention.

FIG. 17 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a fifth embodiment of this invention.

FIG. 18 is a view showing a relationship between the first voltage vector corresponding to the ON/OFF conditions of the respective semiconductor switches and the currents of the first windings, according to the fifth embodiment of this invention.

FIG. 19 is a view showing a relationship between the second voltage vector corresponding to the ON/OFF conditions of the respective semiconductor switches and the currents of the second windings, according to the fifth embodiment of this invention.

FIG. 20 is a view illustrating an operation relating to the ON/OFF patterns of the semiconductor switches and the period of the switching signal in the current detection units, according to the fifth embodiment of this invention.

FIGS. 21A, 21B, 21C and 21D are illustrative views relating to a function of a first detectability determination unit according to the fifth embodiment of this invention.

FIG. 22 is a flowchart showing a series of operations performed by the first detectability determination unit according to the fifth embodiment of this invention.

FIG. 23 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a sixth embodiment of this invention.

FIG. 24 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a seventh embodiment of this invention.

FIG. 25 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to an eighth embodiment of this invention.

FIG. 26 is a flowchart showing a series of operations performed by a second detectability determination unit according to the eighth embodiment of this invention.

FIG. 27 is a flowchart showing a series of operations performed by a switch according to the eighth embodiment of this invention.

FIG. 28 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a ninth embodiment of this invention.

FIG. 29 is a view showing a condition in which differential current gains are varied on the basis of the first voltage commands, according to the ninth embodiment of this invention.

FIG. 30 is a view showing a condition in which sum current gains are varied on the basis of the first voltage commands, according to the ninth embodiment of this invention.

FIG. 31 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a tenth embodiment of this invention.

Preferred embodiments of a control apparatus for an AC rotary machine and a control apparatus for an electric power steering according to this invention will be described below using the drawings.

First Embodiment

FIG. 1 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a first embodiment of this invention. Further, FIG. 2 is a view illustrating a configuration of a three-phase AC rotary machine used as an example of the AC rotary machine according to the first embodiment of this invention. As shown in FIG. 2 , an AC rotary machine 1 a shown in FIG. 1 is a three-phase AC rotary machine in which first three-phase windings U 1 , V 1 , W 1 connected at a neutral point N 1 and second three-phase windings U 2 , V 2 , W 2 connected at a neutral point N 2 are housed in a stator of a rotary machine without being electrically connected to each other.

Note that 30 degree phase differences exist respectively between the U 1 winding and the U 2 winding, the V 1 winding and the V 2 winding, and the W 1 winding and the W 2 winding. FIG. 2 shows a case in which the first three-phase windings and the second three-phase windings forming the AC rotary machine 1 a are respectively Y-connected. However, this invention may also be applied to a case in which the windings are Δ-connected.

A DC power supply 2 a outputs a DC voltage Vdc 1 to a first voltage application unit 3 a , and a DC power supply 2 b outputs a DC voltage Vdc 2 to a second voltage application unit 3 b . The DC power supplies 2 a , 2 b include any device that outputs a DC voltage, such as a battery, a DC-DC converter, a diode rectifier, or a PWM rectifier. Further, a configuration in which a DC voltage is output to the first voltage application unit 3 a and the second voltage application unit 3 b using either one of the DC power supplies 2 a , 2 b is also included in the scope of this invention.

The first voltage application unit 3 a performs PWM on first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ and switches semiconductor switches Sup 1 , Sun 1 , Svp 1 , Svn 1 , Swp 1 , Swn 1 (in the following description, these six semiconductor switches will be referred to as the semiconductor switches Sup 1 to Swn 1 ) ON and OFF using an inverter circuit (an inverter). Thus, the first voltage application unit 3 a converts the DC voltage Vdc 1 input from the DC power supply 2 a into an alternating current and applies an AC voltage to the first three-phase windings U 1 , V 1 , W 1 of the AC rotary machine 1 a . Here, switches formed by connecting a semiconductor switch such as an IGBT, a bipolar transistor, or a MOS power transistor to a diode in anti-parallel are used as the semiconductor switches Sup 1 to Swn 1 .

The second voltage application unit 3 b performs PWM on second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ and switches semiconductor switches Sup 2 , Sun 2 , Svp 2 , Svn 2 , Swp 2 , Swn 2 (in the following description, these six semiconductor switches will be referred to as the semiconductor switches Sup 2 to Swn 2 ) ON and OFF using an inverter circuit (an inverter). Thus, the second voltage application unit 3 b converts the DC voltage Vdc 2 input from the DC power supply 2 b into an alternating current and applies an AC voltage to the second three-phase windings U 2 , V 2 , W 2 of the AC rotary machine 1 a . Here, switches formed by connecting a semiconductor switch such as an IGBT, a bipolar transistor, or a MOS power transistor to a diode in anti-parallel are used as the semiconductor switches Sup 2 to Swn 2 .

A first current detection unit 4 a detects a current Idc 1 flowing through a DC bus line of the first voltage application unit 3 a using a current sensor such as a shunt resistor or a current transformer (CT). FIG. 3 is a view showing relationships between a first voltage vector V 0 ( 1 ) to V 7 ( 1 ) corresponding to the ON/OFF conditions of the semiconductor switches Sup 1 to Swn 1 and the current Idc 1 flowing through the DC bus line of the first voltage application unit 3 a , according to the first embodiment of this invention. Note that with respect to Sup 1 to Swn 1 in FIG. 3 , “1” and “0” respectively indicate a condition in which the switch is ON and a condition in which the switch is OFF.

The first current detection unit 4 a detects currents Iu 1 , Iv 1 , Iw 1 of the first windings on the basis of the relationships shown in FIG. 3 . Note that the first current detection unit 4 a may detect two of the currents Iu 1 , Iv 1 , Iw 1 of the first windings from Idc 1 , and determine the remaining current by calculation using the fact that the sum of the currents of the three phases is zero.

A second current detection unit 4 b detects a current Idc 2 flowing through a DC bus line of the second voltage application unit 3 b using a current sensor such as a shunt resistor or a current transformer (CT). FIG. 4 is a view showing relationships between a second voltage vector V 0 ( 2 ) to V 7 ( 2 ) corresponding to the ON/OFF conditions of the semiconductor switches Sup 2 to Swn 2 and the current Idc 2 flowing through the DC bus line of the second voltage application unit 3 b , according to the first embodiment of this invention. Note that with respect to Sup 2 to Swn 2 in FIG. 4 , “1” and “0” respectively indicate a condition in which the switch is ON and a condition in which the switch is OFF.

The second current detection unit 4 b detects currents Iu 2 , Iv 2 , Iw 2 of the second windings on the basis of the relationships shown in FIG. 4 . Note that the second current detection unit 4 b may detect two of the currents Iu 2 , Iv 2 , Iw 2 of the second windings from Idc 2 , and determine the remaining current by calculation using the fact that the sum of the currents of the three phases is zero.

Further, the numeral ( 1 ) in parentheses in the first voltage vector shown in FIG. 3 and the numeral ( 2 ) in parentheses in the second voltage vector shown in FIG. 4 are provided to differentiate between the first voltage vector and the second voltage vector. Hence, ( 1 ) is appended to the first voltage vector based on the first voltage commands, and ( 2 ) is appended to the second voltage vector based on the second voltage commands.

A first detectability determination unit 12 a determines whether or not the currents of the first windings can be detected on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′, and outputs a first detectability determination signal flag_ 1 .

Next, a control unit 5 a will be described. A coordinate converter 6 a calculates currents Id 1 , Iq 1 of the first windings on two rotational axes by converting the currents Iu 1 , Iv 1 , Iw 1 of the first windings, detected by the first current detection unit 4 a , into currents on rotating coordinates on the basis of a rotation position θ of the AC rotary machine 1 a.

A coordinate converter 6 b calculates currents Id 2 , Iq 2 of the second windings on two rotational axes by converting the currents Iu 2 , Iv 2 , Iw 2 of the second windings, detected by the second current detection unit 4 b , into currents on rotating coordinates on the basis of the rotation position θ of the AC rotary machine 1 a.

When the currents of the first windings are determined to be detectable on the basis of the first detectability determination signal flag_ 1 , a switch 7 a is switched so that the currents Id 1 , Iq 1 of the first windings are output respectively as currents Id′, Iq′ on rotating biaxial coordinates. Further, when the currents of the first windings are determined to be undetectable on the basis of the first detectability determination signal flag_ 1 , the switch 7 a is switched so that the currents Id, Iq of the second windings are output respectively as currents Id′, Iq′ on rotating biaxial coordinates.

A subtractor 8 a calculates a deviation dId between a d axis current command Id* of the AC rotary machine 1 a and the current Id′ on rotating biaxial coordinates output by the switch 7 a . Further, a subtractor 8 b calculates a deviation dIq between a q axis current command Iq* of the AC rotary machine 1 a and the current Iq′ on rotating biaxial coordinates output by the switch 7 a.

A controller 9 a calculates a voltage command Vd on rotating biaxial coordinates using a P controller and a PI controller so that the deviation dId is controlled to zero. Further, a controller 9 b calculates a voltage command Vq on rotating biaxial coordinates using a P controller and a PI controller so that the deviation dIq is controlled to zero.

A coordinate converter 10 a calculates first voltage commands Vu 1 , Vv 1 , Vw 1 by performing coordinate conversion to convert the voltage commands Vd, Vq on rotating biaxial coordinates into three-phase AC coordinates on the basis of the rotation position θ of the AC rotary machine 1 a.

Further, a coordinate converter 10 b calculates second voltage commands Vu 2 , Vv 2 , Vw 2 by performing coordinate conversion to convert the voltage commands Vd, Vq on rotating biaxial coordinates into three-phase AC coordinates on the basis of a position θ−30, which is obtained by subtracting 30 degrees from the rotation position θ of the AC rotary machine 1 a.

An offset calculator 11 a adds an offset voltage Voffset 1 to the first voltage commands Vu 1 , Vv 1 , Vw 1 , as shown below in Equations (1) to (3), and outputs the results as the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′.

Vu 1′= Vu 1 +V offset1  (1)

Vv 1′= Vv 1 +V offset1  (2)

Vw 1′= Vw 1 +V offset1  (3)

An offset calculator 11 b adds an offset voltage Voffset 2 to the second voltage commands Vu 2 , Vv 2 , Vw 2 , as shown below in Equations (4) to (6), and outputs the results as the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′.

Vu 2′= Vu 2 +V offset2  (4)

Vv 2′= Vv 2 +V offset2  (5)

Vw 2′= Vw 2 +V offset2  (6)

The first detectability determination unit 12 a outputs the first detectability determination signal flag_ 1 on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′.

Next, the first and second voltage commands and operations performed by the first detectability determination unit 12 a will be described in detail. FIG. 5 is an illustrative view showing a first voltage command vector V 1 * based on the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ and a second voltage command vector V 2 * based on the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′, according to the first embodiment of this invention. As shown in FIG. 5 , the first voltage command vector V 1 * and the second voltage command vector V 2 * are vectors that rotate about a U ( 1 )−V ( 1 )−W ( 1 ) axis and a U ( 2 )−V ( 2 )−W ( 2 ) axis, respectively.

Note that numerals shown in parentheses in FIG. 5 denote either axes corresponding to the first windings or axes corresponding to the second windings. More specifically, U ( 1 ), V ( 1 ), W ( 1 ), to which ( 1 ) is appended, respectively denote axes corresponding to the U phase, the V phase, and the W phase of the first windings, while U ( 2 ), V ( 2 ), W ( 2 ), to which ( 2 ) is appended, respectively denote axes corresponding to the U phase, the V phase, and the W phase of the second windings. Here, phase angles of the first voltage command vector V 1 * and the second voltage command vector V 2 * when the U ( 1 ) axis is used as a reference are both θv. In other words, there is no phase difference therebetween.

FIG. 6 is a waveform diagram showing the first voltage commands Vu 1 , Vv 1 , Vw 1 and the second voltage commands Vu 2 , Vv 2 , Vw 2 according to the first embodiment of this invention. The U ( 2 ), V ( 2 ), and W ( 2 ) axes shown in FIG. 5 are respectively retarded by a phase of 30 degrees relative to the U ( 1 ), V ( 1 ), and W ( 1 ) axes. Therefore, as shown in FIG. 6 , the second voltage commands Vu 2 , Vv 2 , Vw 2 are respectively retarded by a phase of 30 degrees relative to the first voltage commands Vu 1 , Vv 1 , Vw 1 .

In FIG. 6 , the abscissa shows the voltage phase angle θv when the U ( 1 ) axis is used as a reference. Hence, with respect to the AC rotary machine 1 a , in which a 30 degree phase difference exists between the first windings and the second windings, a 30 degree phase difference exists between the first voltage commands and the second voltage commands. Similarly, with respect to an AC rotary machine in which a phase difference of 30+60×N (where N is an integer) exists between the first windings and the second windings, a 30+60×N degree phase difference exists between the first voltage commands and the second voltage commands.

FIGS. 7A, 7B and 7C are views illustrating relationships between the voltage commands and ON ratios of upper side arm elements of the respective phases with respect to the first voltage application unit 3 a , according to the first embodiment of this invention. FIG. 7A shows the first voltage commands Vu 1 , Vv 1 , Vw 1 shown in FIG. 6 , which serve as the output of the coordinate converter 10 a . FIG. 7B shows the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ serving as the output of the offset calculator 11 a , which are calculated using Equations (1) to (3).

The offset voltage Voffset 1 of Equations (1) to (3) is given by Equation (7), shown below, using a maximum value Vmax 1 and a minimum value Vmin 1 of the first voltage commands Vu 1 , Vv 1 , Vw 1 .

V offset1=−0.5( V min1+ V max1)  (7)

Note, however, that a voltage output range of a phase voltage that can be output by the first voltage application unit 3 a extends from zero to the bus line voltage Vdc 1 . Therefore, when the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ are smaller than −0.5 Vdc 1 or exceed 0.5 Vdc 1 , the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ are limited to −0.5 Vdc 1 or 0.5 Vdc 1 so as to remain within the voltage Vdc 1 that can be output by the first voltage application unit 3 a.

Further, Voffset 1 may be determined using another known offset voltage calculation method such as a two phase modulation method or a third harmonic wave superimposing method instead of Equation (7).

FIG. 7C shows ON duties Dsup 1 , Dsvp 1 , Dswp 1 denoting ON ratios of the upper side arm elements (Sup 1 , Svp 1 , Swp 1 ) of the respective phases of the first voltage application unit 3 a . These ON duties Dsup 1 , Dsvp 1 , Dswp 1 are determined from

Dsxp 1=0.5+ Vx 1′/ Vdc 1

using Vu 1 ′, Vv 1 ′, Vw 1 ′, respectively. Here, x=U, V, W. When Dsup 1 is 0.6, for example, the first voltage application unit 3 a sets the ON ratio of Sup 1 within a switching period Tsw at 0.6.

In the first voltage application unit 3 a , either the upper side arm elements (Sup 1 , Svp 1 , Swp 1 ) or lower side arm elements (Sun 1 , Svn 1 , Swn 1 ) are switched ON at all times in each phase. Accordingly, relationships shown below in Equations (8) to (10) are established between the ON duties (Dsup 1 , Dsvp 1 , Dswp 1 ) of the upper side arm elements of the respective phases and ON duties (Dsun 1 , Dsvn 1 , Dswn 1 ) of the lower side arm elements.

Dsup 1 +Dsun 1=1  (8)

Dsvp 1 +Dsvn 1=1  (9)

Dswp 1 +Dswn 1=1  (10)

Therefore, in accordance with Equation (8), when Dsup 1 is 0.6, for example, Dsun 1 is 0.4. Thus, the ON duties of the respective switching elements in the first voltage application unit 3 a are determined on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′.

FIGS. 8A, 8B and 8C are views illustrating relationships between the voltage commands and the ON ratios of the upper side arm elements of the respective phases with respect to the second voltage application unit 3 b , according to the first embodiment of this invention. FIG. 8A shows the second voltage commands Vu 2 , Vv 2 , Vw 2 shown in FIG. 6 , which serve as the output of the coordinate converter 10 b . FIG. 8B shows the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ serving as the output of the offset calculator 11 b , which are calculated using Equations (4) to (6).

The offset voltage Voffset 2 of Equations (4) to (6) is given by Equation (11), shown below, using a maximum value Vmax 2 and a minimum value Vmin 2 of the second voltage commands Vu 2 , Vv 2 , Vw 2 .

V offset2=−0.5( V min2 +V max2)  (11)

Note, however, that the voltage output range of the phase voltage that can be output by the second voltage application unit 3 b extends from zero to the bus line voltage Vdc 2 . Therefore, when the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ are smaller than −0.5 Vdc 2 or exceed 0.5 Vdc 2 , the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ are limited to −0.5 Vdc 2 or 0.5 Vdc 2 so as to remain within the voltage Vdc 2 that can be output by the second voltage application unit 3 b.

Further, Voffset 2 may be determined using another known offset voltage calculation method such as a two phase modulation method or a third harmonic wave superimposing method instead of Equation (11).

FIG. 8C shows ON duties Dsup 2 , Dsvp 2 , Dswp 2 denoting ON ratios of the upper side arm elements (Sup 2 , Svp 2 , Swp 2 ) of the respective phases of the second voltage application unit 3 b . These ON duties Dsup 2 , Dsvp 2 , Dswp 2 are determined from

Dsxp 2=0.5+ Vx 2′/ Vdc 2

using Vu 2 ′, Vv 2 ′, Vw 2 ′, respectively. Here, x=U, V, W. When Dsup 2 is 0.6, for example, the second voltage application unit 3 b sets the ON ratio of Sup 2 within the switching period Tsw at 0.6.

In the second voltage application unit 3 b , either the upper side arm elements (Sup 2 , Svp 2 , Swp 2 ) or lower side arm elements (Sun 2 , Svn 2 , Swn 2 ) are switched ON at all times in each phase. Accordingly, relationships shown below in Equations (12) to (14) are established between the ON duties (Dsup 2 , Dsvp 2 , Dswp 2 ) of the upper side arm elements of the respective phases and ON duties (Dsun 2 , Dsvn 2 , Dswn 2 ) of the lower side arm elements.

Dsup 2 +Dsun 2=1  (12)

Dsvp 2 +Dsvn 2=1  (13)

Dswp 2 +Dswn 2=1  (14)

Therefore, in accordance with Equation (12), when Dsup 2 is 0.6, for example, Dsun 2 is 0.4. Thus, the ON duties of the respective switching elements in the second voltage application unit 3 b are determined on the basis of the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′.

FIG. 9 is a view illustrating operations relating to ON/OFF patterns of the semiconductor switches and a period of a switching signal in the current detection units, according to the first embodiment of this invention. More specifically, FIG. 9 is a view showing a relationship between ON/OFF patterns of the semiconductor switches Sup 1 , Svp 1 , Swp 1 of the first voltage application unit 3 a and the semiconductor switches Sup 2 , Svp 2 , Swp 2 of the second voltage application unit 3 b and the period Tsw of the switching signal in the first current detection unit 4 a and the second current detection unit 4 b.

Note that Sun 1 , Svn 1 , Swn 1 , Sun 2 , Svn 2 , Swn 2 have inverse relationships to Sup 1 , Svp 1 , Swp 1 , Sup 2 , Svp 2 , Swp 2 , respectively (i.e. 0 in place of 1 and 1 in place of 0, excluding a dead time period), and are not therefore described.

In FIG. 9 , when a first maximum phase voltage Emax 1 , a first intermediate phase voltage Emid 1 , and a first minimum phase voltage Emin 1 are set in descending order in relation to the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′, relationships shown below in Equations (15) to (17) are assumed to be established.

Emax1=Vu1′  (15)

Emid1=Vv1′  (16)

Emin1=Vw1′  (17)

Similarly, when a second maximum phase voltage Emax 2 , a second intermediate phase voltage Emid 2 , and a second minimum phase voltage Emin 2 are set in descending order in relation to the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′, relationships shown below in Equations (18) to (20) are assumed to be established.

Emax2=Vu1′  (18)

Emid2=Vv1′  (19)

Emin2=Vw1′  (20)

At a time t 1 (n), Sup 1 and Sup 2 are set at 1 and Svp 1 , Swp 1 , Svp 2 , and Swp 2 are set at 0, whereupon this condition is maintained until a time t 2 (n) arrives following the elapse of Δt 1 . In accordance with FIGS. 3 and 4 , the first voltage vector and the second voltage vector are at V 1 ( 1 ) and V 1 ( 2 ), respectively, between the times t 1 (n) and t 2 (n). Idc 1 is detected at a time ts 1 - 1 (n) between the times t 1 (n) and t 2 (n).

The time shift Δt 1 is set to be longer than a sum of a dead time of the first voltage application unit 3 a and the second voltage application unit 3 b and a time required for the first current detection unit 4 a to detect Idc 1 or for the second current detection unit 4 b to detect Idc 2 (for example, a time required for ringing included in a detected waveform to converge and a sample holding time). For example, Δt 1 =5 μs.

In accordance with FIG. 3 , the first voltage vector is at V 1 ( 1 ) between the times t 1 (n) and t 2 (n), and therefore Idc 1 is equal to Iu 1 when detected at the time ts 1 - 1 (n). Further, in accordance with FIG. 4 , the second voltage vector is at V 1 ( 2 ) between the times t 1 (n) and t 2 (n), and therefore Idc 2 is equal to Iu 2 when detected at the time ts 1 - 1 (n).

Next, at the time t 2 (n), Svp 1 and Svp 2 are set at 1, and this switching pattern is maintained until a time t 3 (n). In accordance with FIGS. 3 and 4 , the first voltage vector and the second voltage vector are at V 2 ( 1 ) and V 2 ( 2 ), respectively, between the times t 2 (n) and t 3 (n).

At a time ts 1 - 2 (n), Idc 1 and Idc 2 are detected again. A time shift Δt 2 , similarly to the time shift Δt 1 , is set to be longer than the sum of the dead time of the first voltage application unit 3 a and the second voltage application unit 3 b and the time required for the first current detection unit 4 a to detect Idc 1 or for the second current detection unit 4 b to detect Idc 2 . Typically, Δt 1 =Δt 2 .

In accordance with FIG. 3 , the first voltage vector is at V 2 ( 1 ) between the times t 2 (n) and t 3 (n), and therefore Idc 1 is equal to −Iw 1 when detected at the time ts 1 - 2 (n). Further, in accordance with FIG. 4 , the second voltage vector is at V 2 ( 2 ) between the times t 2 (n) and t 3 (n), and therefore Idc 2 is equal to −Iw 2 when detected at the time ts 1 - 2 (n).

The currents Iu 1 , Iw 1 of the first windings and the currents Iu 2 , Iw 2 of the second windings can be detected in the manner described above, and therefore the currents Iu 1 , Iv 1 (=−Iu 1 −Iw 1 ), Iw 1 of the first windings and the currents Iu 2 , Iv 2 (=−Iu 2 −Iw 2 ), Iw 2 of the second windings can be detected using the fact that the sum of the currents of the three phases is zero.

At a time t 3 (n), Swp 1 and Swp 2 are set at 1. A pulse width (a time during which “1” is maintained) between Sup 1 and Swp 2 is determined from a product of the ON duties Dsup 1 to Dswp 2 corresponding to the respective switches and the switching period Tsw.

In the first embodiment, as described above, the switch of the upper side arm element of the phase corresponding to the first maximum phase voltage Emax 1 , the switch of the upper side arm element of the phase corresponding to the first intermediate phase voltage Emid 1 , and the switch of the upper side arm element of the phase corresponding to the first minimum phase voltage Emin 1 are switched ON in that order at the time shifts Δt 1 and Δt 2 . By performing switching in this manner, the two types of first voltage vectors shown in FIG. 3 , with which two of the currents Iu 1 , Iv 1 , Iw 1 of the first windings can be detected from Idc 1 , are formed and the two types of second voltage vectors shown in FIG. 4 , with which two of the currents Iu 2 , Iv 2 , Iw 2 of the second windings can be detected from Idc 2 , are formed.

Depending on the voltage command value of the phase corresponding to the first intermediate phase voltage Emid 1 , however, it may be impossible to form the two types of first voltage vectors with which two of the currents Iu 1 , Iv 1 , Iw 1 of the first windings can be detected from Idc 1 , and as a result, it may be impossible to detect the currents Iu 1 , Iv 1 , Iw 1 of the first windings.

FIG. 10 is a view illustrating different operations to those of FIG. 9 relating to the ON/OFF patterns of the semiconductor switches and the period of the switching signal in the current detection units, according to the first embodiment of this invention, FIG. 10 showing an example of a case in which the currents Iu 1 , Iv 1 , Iw 1 of the first windings cannot be detected. FIG. 10 shows a condition in which Vv 1 ′ is small such that Dsvp 1 ×Tsw is smaller than Δt 2 . When Svp 1 is switched ON at the time t 2 (n) in this condition, Svp 1 is switched OFF before the time t 3 (n) arrives, and therefore the first voltage vector V 2 ( 1 ) cannot be formed within the time shift Δt 2 .

Further, FIG. 11 is a view illustrating different operations to those of FIGS. 9 and 10 relating to the ON/OFF patterns of the semiconductor switches and the period of the switching signal in the current detection units, according to the first embodiment of this invention, FIG. 11 showing an example of a similar case to that of FIG. 10 , in which the currents Iu 1 , Iv 1 , Iw 1 of the first windings cannot be detected. FIG. 11 shows a condition in which Vv 1 ′ is large such that Dsvp 1 ×Tsw is larger than Tsw−Δt 1 . In this condition, even when Svp 1 is switched OFF at a time t 4 (n) at which the switching period Tsw ends, a pulse width corresponding to Dsvp 1 ×Tsw cannot be obtained unless Svp 1 is switched ON before the time t 2 (n) arrives. As a result, V 1 ( 1 ) cannot be formed within the time zone Δt 1 .

Likewise with regard to the second voltage application unit 3 b , when Vv 2 ′ is small in FIG. 9 , V 2 ( 2 ) cannot be formed within the time shift Δt 2 . Moreover, when Vv 2 ′ is large, V 1 ( 2 ) cannot be formed within the time zone Δt 1 .

This problem can be solved by increasing the switching period Tsw described in PTL 1 (referred to as the control period in PTL 1). When the time shift Δt 1 and the time shift Δt 2 are set at fixed times, the proportion of Tsw occupied by the time shift Δt 1 and the time shift Δt 2 can be reduced by increasing Tsw. As a result, current detection can be performed even when the intermediate phase voltage is small such that Dsvp 1 is small or when the intermediate phase voltage is large such that Dsvp 1 is large, as described above.

However, when Tsw is increased, a switching frequency given by the inverse of Tsw decreases, and when this frequency enters the audible range, noise from the switching frequency component increases. When the AC rotary machine 1 a is used as a motor for an electric power steering, for example, the switching frequency is set to be no lower than 20 kHz (i.e. outside the band of the audible range).

The reason for this is that the audible range of a human being is between 20 Hz and 20 kHz, and therefore, by setting the switching frequency to be no lower than 20 kHz (i.e. outside the band of the audible range), the sound of the switching frequency component cannot be heard by human ears. When the switching frequency is reduced below 20 kHz in order to secure the time shift Δt 1 and the time shift Δt 2 , however, the sound of the switching frequency component can be heard by human ears as noise.

Further, when noise is avoided by limiting an amplitude of the first voltage command so that the first intermediate phase voltage Emid 1 remains within a range in which the time shifts Δt 1 and Δt 2 can be secured, the voltage applied to the AC rotary machine 1 a is limited, and therefore a high output cannot be generated by the AC rotary machine 1 a.

Returning to this invention, FIGS. 12A, 12B, 12C and 12D are illustrative views relating to a function of the first detectability determination unit 12 a according to the first embodiment of this invention. More specifically, the first detectability determination unit 12 a determines whether the currents of the first windings can be detected by the first current detector 4 a or whether the currents of the second windings can be detected by the second current detector 4 b by determining whether or not the voltage command value of the phase corresponding to the first intermediate phase voltage Emid 1 and the voltage command value of the phase corresponding to the second intermediate phase voltage Emid 2 are within a range no lower than a first predetermined value Vs 1 and no higher than a second predetermined value Vs 2 .

Here, when the first intermediate phase voltage Emid 1 and the second intermediate phase voltage Emid 2 are equal to Vs 1 , this means that the ON time of the upper side arm element at the intermediate phase voltage during Tsw is equal to Tsw−Δt 1 . Hence, the first predetermined value Vs 1 corresponds to an upper limit value at which the time shift Δt 1 can be secured.

Meanwhile, when the first intermediate phase voltage Emid 1 and the second intermediate phase voltage Emid 2 are equal to Vs 2 , this means that Δt 2 can be secured within Tsw by the ON time of the upper side arm element at the intermediate phase voltage. Hence, the second predetermined value Vs 2 corresponds to a lower limit value at which the time shift Δt 2 can be secured.

In FIG. 12A , a dotted line indicates the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ shown in FIG. 7B , a solid line indicates the first intermediate phase voltage Emid 1 , and dot-dash lines indicate the first predetermined value Vs 1 and the second predetermined value Vs 2 . Here, Vs 1 =0.4 Vdc 1 and Vs 2 =−0.4 Vdc 1 .

FIG. 12B shows the output of the first detectability determination unit 12 a . The first detectability determination unit 12 a determines whether or not the currents of the first windings can be detected by determining whether or not the first intermediate phase voltage Emid 1 is within the range extending from the first predetermined value Vs 1 to the second predetermined value Vs 2 . The first detectability determination unit 12 a outputs the first detectability determination signal flag _ 1 at 1 when the first intermediate phase voltage Emid 1 is within the range extending from the first predetermined value Vs 1 to the second predetermined value Vs 2 , and outputs the first detectability determination signal flag _ 1 at 0 when the first intermediate phase voltage Emid 1 is outside the range.

In FIG. 12C , a dotted line indicates the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ shown in FIG. 8B , a solid line indicates the second intermediate phase voltage Emid 2 , and dot-dash lines indicate Vs 1 and Vs 2 . FIG. 12D shows a second detectability determination signal flag_ 2 indicating whether or not the second intermediate phase voltage Emid 2 is within the range extending from the first predetermined value Vs 1 to the second predetermined value Vs 2 . The second detectability determination signal flag_ 2 is set at 1 when the second intermediate phase voltage Emid 2 is within the range extending from the first predetermined value Vs 1 to the second predetermined value Vs 2 , and set at 0 when the second intermediate phase voltage Emid 1 is outside the range.

Note that the second detectability determination signal flag_ 2 serves as the output of a second detectability determination unit 701 a to be described below in eighth to tenth embodiments using FIGS. 25, 28, and 31 . As shown in FIG. 1 , a second detectability determination unit is not used in the first embodiment, but is illustrated in FIGS. 12A to 12D for descriptive purposes.

Focusing on the first detectability determination signal flag_ 1 , the first detectability determination signal flag_ 1 shifts to 0 in the vicinity of a voltage phase angle θv of 60×x (x: 0, 1, 2, 3, 4, 5, 6) degrees. Focusing on the second detectability determination signal flag_ 2 , the second detectability determination signal flag_ 2 shifts to 0 in the vicinity of a voltage phase angle θv of 30+60×x (x: 0, 1, 2, 3, 4, 5) degrees. Hence, the voltage phase angles θv at which the first detectability determination signal flag_ 1 and the second detectability determination signal flag_ 2 shift to 0 deviate from each other by 30 degrees, and therefore, when flag_ 1 is at 0, flag_ 2 is at 1, and conversely when flag_ 1 is at 1, flag_ 2 is at 0.

FIG. 13 is a flowchart showing a series of operations performed by the first detectability determination unit 12 a according to the first embodiment of this invention. In step S 1000 a , the first detectability determination unit 12 a calculates the first intermediate phase voltage Emid 1 on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′. In step S 1000 b , the first detectability determination unit 12 a determines whether or not the first intermediate phase voltage Emid 1 is equal to or smaller than the first predetermined value Vs 1 . When “YES” is obtained, the routine advances to step S 1000 c , and when “NO” is obtained, the routine advances to step S 1000 e.

In step S 1000 c , the first detectability determination unit 12 a determines whether or not the first intermediate phase voltage Emid 1 equals or exceeds the second predetermined value Vs 2 . When “YES” is obtained, the routine advances to step S 1000 d , and when “NO” is obtained, the routine advances to step S 1000 e.

In a case where the routine advances to step S 1000 d , the first detectability determination unit 12 a inserts 1 into the first detectability determination signal flag_ 1 . In a case where the routine advances to step S 1000 e , the first detectability determination unit 12 a inserts 0 into the first detectability determination signal flag_ 1 .

Finally, when the first detectability determination signal flag_ 1 is at 1, the first detectability determination unit 12 a determines that the currents of the first windings are detectable, and therefore switches the switch 7 a so that the currents Id 1 , Iq 1 on two rotational axes, determined from the first winding currents, are output respectively as Id′, Iq′. When the first detectability determination signal flag_ 1 is at 0, on the other hand, the first detectability determination unit 12 a determines that the currents of the first windings are undetectable, and therefore switches the switch 7 a so that the currents Id 2 , Iq 2 on two rotational axes, determined from the second winding currents, are output respectively as Id′, Iq′.

According to the first embodiment, as described above, a determination as to whether or not the first current detection unit 4 a can detect the currents of the first windings is made on the basis of the first voltage commands. When it is determined that the currents of the first windings are detectable, the first voltage commands and second voltage commands are calculated on the basis of the currents of the first windings, and when it is determined that the currents of the first windings are undetectable, the first voltage commands and second voltage commands are calculated on the basis of the currents of the second windings.

By providing this configuration, the amplitude of the first voltage commands and the second voltage commands can be increased without lengthening the switching period Tsw, as in PTL 1, and without limiting the amplitude of the first voltage commands in order to secure a time shift for the first intermediate phase voltage. As a result, the output of the AC rotary machine 1 a can be increased while keeping noise generated thereby low.

Second Embodiment

In a second embodiment, a first detectability determination unit 12 b that determines whether or not the currents of the first windings are detectable by different processing to that of the first detectability determination unit 12 a according to the first embodiment will be described. The second embodiment is configured basically identically to the first embodiment shown in FIG. 1 , and differs only in that the first detectability determination unit 12 a shown in FIG. 1 is replaced with the first detectability determination unit 12 b . Accordingly, the following description centers on the first detectability determination unit 12 b that differs from the first embodiment.

FIG. 14 is a flowchart showing a series of operations performed by the first detectability determination unit 12 b according to the second embodiment of this invention. In step S 2000 a , the first detectability determination unit 12 b determines the first maximum phase voltage Emax 1 , the first intermediate phase voltage Emid 1 , and the first minimum phase voltage Emin 1 from the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′.

In step S 2000 b , the first detectability determination unit 12 b determines whether or not a difference Emax 1 −Emid 1 between the first maximum phase voltage and the first intermediate phase voltage equals or exceeds a third predetermined value Vs 3 . When “YES” is obtained, the routine advances to step S 2000 c , and when “NO” is obtained, the routine advances to step S 2000 e.

In step S 2000 c , the first detectability determination unit 12 b determines whether or not a difference Emid 1 −Emin 1 between the first intermediate phase voltage and the first minimum phase voltage equals or exceeds the third predetermined value Vs 3 . When “YES” is obtained, the routine advances to step S 2000 d , and when “NO” is obtained, the routine advances to step S 2000 e.

In a case where the routine advances to step S 2000 d , the first detectability determination unit 12 b inserts 1 into the first detectability determination signal flag_ 1 . In a case where the routine advances to step S 2000 e , the first detectability determination unit 12 b inserts 0 into the first detectability determination signal flag_ 1 .

Here, the third predetermined value Vs 3 may be determined on the basis of a ratio between the time shift Δt 1 or Δt 2 and the switching period Tsw. For example, when the time shift Δt 1 =Δt 2 =5 μs and the switching period is set as Tsw, the third predetermined value Vs 3 is Δt 1 /Tsw×Vdc=0.1 Vdc.

FIGS. 15A, 15B, 15C and 15D are views showing waveforms described in the steps of FIG. 14 in a case where the third predetermined value Vs 3 is set at 0.1 Vdc, according to the second embodiment of this invention. More specifically, FIG. 15A shows the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′, and FIG. 15B shows the first maximum phase voltage Emax 1 , the first intermediate phase voltage Emid 1 , and the first minimum phase voltage Emin 1 mentioned in step S 2000 a.

FIG. 15C shows the difference Emax 1 −Emid 1 between the first maximum phase voltage and the first intermediate phase voltage and the difference Emid 1 −Emin 1 between the first intermediate phase voltage and the first minimum phase voltage, mentioned respectively in steps S 2000 b and S 2000 c . Further, FIG. 15D shows the first detectability determination signal flag_ 1 mentioned in steps S 2000 d and S 2000 e.

According to the second embodiment, as described above, the difference between the first maximum phase voltage and the first intermediate phase voltage and the difference between the first intermediate phase voltage and the first minimum phase voltage are respectively calculated, and when the values thereof are smaller than the third predetermined value, the currents of the first windings are determined to be undetectable. By performing this determination processing, identical effects to those of the first embodiment can be obtained.

Note that in the second embodiment, the first detectability determination unit 12 b determines the detectability of the currents of the first windings on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ serving as the output of the offset calculator 11 a . However, identical calculation results are obtained for Emax 1 −Emid 1 and Emid 1 −Emin 1 when Emax 1 −Emid 1 and Emid 1 −Emin 1 are calculated on the basis of the first voltage commands Vu 1 , Vv 1 , Vw 1 serving as the input of the offset calculator 11 a instead of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ serving as the output of the offset calculator 11 a . Hence, identical effects to those obtained when Emax 1 −Emid 1 and Emid 1 −Emin 1 are calculated on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ are obtained with a configuration in which the first voltage commands Vu 1 , Vv 1 , Vw 1 are input into the first detectability determination unit 12 b.

Third Embodiment

In a third embodiment, a first detectability determination unit 12 c that determines whether or not the currents of the first windings are detectable by different processing to that of the first detectability determination unit 12 a according to the first embodiment and the first detectability determination unit 12 b according to the second embodiment will be described. The third embodiment is configured basically identically to the first embodiment shown in FIG. 1 , and differs only in that the first detectability determination unit 12 a shown in FIG. 1 is replaced with the first detectability determination unit 12 c . Accordingly, the following description centers on the first detectability determination unit 12 c that differs from the first and second embodiments.

The first detectability determination unit 12 c calculates the voltage phase angle θv on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ using Equation (21), shown below, and determines the detectability of the currents of the first windings in accordance with a region of the voltage phase angle θv.

In the first embodiment described above, the currents of the first windings are determined to be undetectable when the voltage phase angle θv is in the vicinity of 60×x (x: 0, 1, 2, 3, 4, 5, 6) degrees. Therefore, when θv obtained in the calculation based on the first voltage commands is within a range no lower than 60×x−α and no higher than 60×x+α (where α is a margin), the first detectability determination unit 12 c determines that the currents of the first windings are undetectable, and outputs 0 as flag_ 1 . When θv is outside this range, on the other hand, the first detectability determination unit 12 c determines that the currents of the first windings are detectable, and outputs 1 as flag_ 1 .

Note that the margin α is determined from the time shifts Δt 1 and Δt 2 , the maximum value of the first voltage commands, and so on, but is set at a magnitude no greater than 30 degrees.

According to the third embodiment, as described above, the voltage phase angle of the first voltage commands is calculated, whereupon the detectability of the currents of the first windings is determined in accordance with the region of the voltage phase angle. Likewise with this configuration, identical effects to those of the first and second embodiments can be obtained.

Note that in the third embodiment, the first detectability determination unit 12 c determines the detectability of the currents of the first windings on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ serving as the output of the offset calculator 11 a . However, an identical calculation result to that of Equation (21) is obtained when the detectability of the currents of the first windings is calculated on the basis of the first voltage commands Vu 1 , Vv 1 , Vw 1 serving as the input of the offset calculator 11 a instead of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ serving as the output of the offset calculator 11 a . Hence, identical effects to those obtained when the detectability of the currents of the first windings is calculated on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ are obtained with a configuration in which the first voltage commands Vu 1 , Vv 1 , Vw 1 are input into the first detectability determination unit 12 c.

All other methods of determining the detectability of the currents of the first windings on the basis of the voltage phase angle θv after determining the voltage phase angle θv on the basis of the voltage commands, such as a method of determining the voltage phase angle θv on the basis of the voltage commands Vd, Vq on two rotational axes, are included in this invention.

Fourth Embodiment

In a fourth embodiment, a first detectability determination unit 12 d that determines whether or not the currents of the first windings are detectable by different processing to that of the first detectability determination units 12 a , 12 b , and 12 c according to the first to third embodiments will be described. FIG. 16 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to the fourth embodiment of this invention. In the fourth embodiment, the first detectability determination unit 12 d determines the detectability of the currents of the first windings on the basis of the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ rather than the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′. Accordingly, the following description centers on the first detectability determination unit 12 d that differs from the first to third embodiments.

The first detectability determination unit 12 d shown in FIG. 16 calculates the voltage phase angle θv on the basis of the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ using Equation (22), shown below, and determines the detectability of the currents of the first windings in accordance with the region of the voltage phase angle θv.

In the first embodiment described above, the currents of the first windings are determined to be undetectable when the voltage phase angle θv is in the vicinity of 60×x (x: 0, 1, 2, 3, 4, 5, 6) degrees. Therefore, when θv obtained in the calculation based on the second voltage commands is within a range of no lower than 60×x−α and no higher than 60×x+α (where α is a margin), the first detectability determination unit 12 d determines that the currents of the first windings are undetectable, and outputs 0 as flag_ 1 . When θv is outside this range, on the other hand, the first detectability determination unit 12 d determines that the currents of the first windings are detectable, and outputs 1 as flag_ 1 .

Note that the margin α is determined from the time shifts Δt 1 and Δt 2 , the maximum value of the first voltage commands, and so on, but is set at a magnitude no greater than 30 degrees.

According to the fourth embodiment, as described above, the voltage phase angle of the second voltage commands is calculated, whereupon the detectability of the currents of the first windings is determined in accordance with the region of the voltage phase angle. Likewise with this configuration, identical effects to those of the first to third embodiments can be obtained.

Note that in the fourth embodiment, the first detectability determination unit 12 d determines the detectability of the currents of the first windings on the basis of the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ serving as the output of the offset calculator 11 b . However, an identical calculation result to that of Equation (22) is obtained when the detectability of the currents of the first windings is calculated on the basis of the second voltage commands Vu 2 , Vv 2 , Vw 2 serving as the input of the offset calculator 11 b instead of the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ serving as the output of the offset calculator 11 b . Hence, identical effects to those obtained when the calculation is performed on the basis of the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ are obtained with a configuration in which the second voltage commands Vu 2 , Vv 2 , Vw 2 are input into the first detectability determination unit 12 d.

Furthermore, an average of the voltage phase angle θv based on the first voltage commands, obtained from the third embodiment, and the voltage phase angle θv based on the second voltage commands, obtained from the fourth embodiment, may be calculated, whereupon the detectability of the currents of the first windings may be determined on the basis of the averaged voltage phase angle θv. In this case, an effect of suppressing a noise component included in the voltage phase angle θv by averaging the voltage phase angle θv can be obtained.

Fifth Embodiment

FIG. 17 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a fifth embodiment of this invention. The fifth embodiment differs from the first to fourth embodiments in including a first current detection unit 4 c , a second current detection unit 4 d , and a first detectability determination unit 12 e in place of the first current detection unit 4 a , the second current detection unit 4 b , and the first detectability determination unit 12 a ( 12 b to 12 d ). Accordingly, the following description centers on these differences.

The first current detection unit 4 c according to the fifth embodiment is formed by providing current sensors such as shunt resistors or current transformers (CTs) respectively in series with the lower side arm elements of the respective phases (Sun 1 , Svn 1 , Swn 1 ) of the first voltage application unit 3 a . FIG. 18 is a view showing relationships between the first voltage vector V 0 ( 1 ) to V 7 ( 1 ) corresponding to the ON/OFF conditions of the semiconductor switches Sup 1 to Swn 1 and the currents Iu 1 , Iv 1 , Iw 1 of the first windings, according to the fifth embodiment of this invention. Note that with respect to Sup 1 to Swn 1 in FIG. 18 , “1” and “0” respectively indicate a condition in which the switch is ON and a condition in which the switch is OFF. The first current detection unit 4 c detects the currents Iu 1 , Iv 1 , Iw 1 of the first windings individually on the basis of the relationships shown in FIG. 18 .

In the fifth embodiment, current sensors are provided in series with the lower arm elements of the respective phases, and therefore current detection is possible only in a phase where the lower side arm elements are switched ON. For example, when the first voltage vector is at V 1 ( 1 ), the switches Sup 1 , Svn 1 , and Swn 1 are switched ON, and therefore, in the U 1 phase, the upper side arm elements are switched ON, whereas in the V 1 phase and the W 1 phase, the lower side arm elements are switched ON. As a result, the current Iv 1 that flows in the V 1 phase and the current Iw 1 that flows in the W 1 phase are detectable, but the current Iu 1 that flows in the U 1 phase is undetectable. Accordingly, Iu 1 is detected from Iv 1 and Iw 1 using the fact that the sum of the currents of the three phases is zero.

Hence, when the first voltage vector is at V 1 ( 1 ), currents Iu 1 _s, Iv 1 _s, Iw 1 _s flowing through the current sensors provided on the U 1 , V 1 , and W 1 phases are 0, −Iv 1 , and −Iw 1 , respectively (see FIG. 18 ). Similarly, currents Iu_s, Iv_s, Iw_s flowing through the current sensors when the first voltage vector is at V 3 ( 1 ) and V 5 ( 1 ) are as shown in FIG. 18 .

When the first voltage vector is at V 2 ( 1 ), V 4 ( 1 ), and V 6 ( 1 ), only one of the currents Iu 1 , Iv 1 , Iw 1 of the first windings is detectable, and therefore the currents of the three phases cannot be obtained.

The second current detection unit 4 d is formed by providing current sensors such as shunt resistors or current transformers (CTs) respectively in series with the lower side arm elements of the respective phases (Sun 2 , Svn 2 , Swn 2 ) of the second voltage application unit 3 b . FIG. 19 is a view showing relationships between the second voltage vector V 0 ( 2 ) to V 7 ( 2 ) corresponding to the ON/OFF conditions of the semiconductor switches Sup 2 to Swn 2 and the currents Iu 2 , Iv 2 , Iw 2 of the second windings, according to the fifth embodiment of this invention. Note that with respect to Sup 2 to Swn 2 in FIG. 19 , “1” and “0” respectively indicate a condition in which the switch is ON and a condition in which the switch is OFF. The second current detection unit 4 d detects the currents Iu 2 , Iv 2 , Iw 2 of the second windings individually on the basis of the relationships shown in FIG. 19 .

Since the current sensors are provided in series with the lower arm elements of the respective phases, current detection is possible only in a phase where the lower side arm elements are switched ON. For example, when the second voltage vector is at V 1 ( 2 ), the switches Sup 2 , Svn 2 , and Swn 2 are switched ON, and therefore, in the U 2 phase, the upper side arm elements are switched ON, whereas in the V 2 phase and the W 2 phase, the lower side arm elements are switched ON. As a result, the current Iv 2 that flows in the V 2 phase and the current Iw 2 that flows in the W 2 phase are detectable, but the current Iu 2 that flows in the U 2 phase is undetectable. Accordingly, Iu 2 is detected from Iv 2 and Iw 2 using the fact that the sum of the currents of the three phases is zero.

Hence, when the second voltage vector is at V 1 ( 2 ), currents Iu 2 _s, Iv 2 _s, Iw 2 _s flowing through the current sensors provided on the U 2 , V 2 , and W 2 phases are 0, −Iv 2 , and −Iw 2 , respectively (see FIG. 19 ). Similarly, the currents Iu 2 _s, Iv 2 _s, Iw 2 _s flowing through the current sensors when the second voltage vector is at V 3 ( 2 ) and V 5 ( 2 ) are as shown in FIG. 19 .

When the second voltage vector is at V 2 ( 2 ), V 4 ( 2 ), and V 6 ( 2 ), only one of the currents Iu 2 , Iv 2 , Iw 2 of the first windings is detectable, and therefore the currents of the three phases cannot be obtained.

FIG. 20 is a view illustrating an operation relating to the ON/OFF patterns of the semiconductor switches and the period of the switching signal in the current detection units, according to the fifth embodiment of this invention. More specifically, FIG. 20 is a view showing relationships between the ON/OFF patterns of the semiconductor switches Sup 1 , Svp 1 , Swp 1 of the first voltage application unit 3 a and the semiconductor switches Sup 2 , Svp 2 , Swp 2 of the second voltage application unit 3 b and the switching period Tsw in the first current detection unit 4 c and the second current detection unit 4 d.

In FIG. 20 , similarly to FIG. 9 described above, when the first maximum phase voltage Emax 1 , the first intermediate phase voltage Emid 1 , and the first minimum phase voltage Emin 1 are set in descending order in relation to the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′, the relationships shown in Equations (15) to (17) are assumed to be established.

Similarly, when the second maximum phase voltage Emax 2 , the second intermediate phase voltage Emid 2 , and the second minimum phase voltage Emin 2 are set in descending order in relation to the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′, the relationships shown in Equations (18) to (20) are assumed to be established.

At the time t 1 (n), Sup 1 and Sup 2 are set at 1 and Svp 1 , Swp 1 , Svp 2 , and Swp 2 are set at 0, whereupon this condition is maintained until the time t 2 (n) arrives following the elapse of Δt 1 . In accordance with FIGS. 18 and 19 , the first voltage vector and the second voltage vector are at V 1 ( 1 ) and V 1 ( 2 ), respectively, between the times t 1 (n) and t 2 (n). The currents of the first windings are detected at the time ts 1 - 1 (n) between the times t 1 (n) and t 2 (n).

The first voltage vector is at V 1 ( 1 ), and therefore, in accordance with FIG. 18 , Iv 1 _s and Iw 1 _s are respectively equal to Iv 1 , Iw 1 , while Iu 1 is determined from Iv 1 and Iw 1 using the fact that the sum of the currents of the three phases is zero. Further, at the time ts 1 - 1 (n), the currents of the second windings are detected. Here, the second voltage vector is at V 1 ( 2 ), and therefore, in accordance with FIG. 19 , Iv 2 _s and Iw 2 _s are respectively equal to Iv 2 , Iw 2 , while Iu 2 is determined from Iv 2 and Iw 2 using the fact that the sum of the currents of the three phases is zero.

Next, at the time t 2 (n), Svp 1 , Svp 2 , Swp 1 , and Swp 2 are set at 1. A pulse width (a time during which “1” is maintained) of Sup 1 to Swp 2 is determined from a product of the ON duties Dsup 1 to Dswp 2 corresponding to the respective switches and the switching period Tsw.

In the fifth embodiment, as described above, the switches of the upper side arm elements are switched ON initially in the phase corresponding to the first maximum phase voltage Emax 1 , and then switched ON in the phase corresponding to the first intermediate phase voltage Emid 1 and the phase corresponding to the first minimum phase voltage Emin 1 at intervals of the time shift Δt 1 . By performing switching in this manner, a first voltage vector (V 1 ( 1 ) or V 1 ( 3 ) or V 1 ( 5 )) with which two of the currents Iu 1 , Iv 1 , Iw 1 of the first windings can be detected is formed, as shown in FIG. 18 , and a second voltage vector (V 1 ( 2 ) or V 3 ( 2 ) or V 5 ( 2 )) with which two of the currents Iu 2 , Iv 2 , Iw 2 of the second windings can be detected is formed, as shown in FIG. 19 .

Depending on the voltage command value of the phase corresponding to the first intermediate phase voltage Emid 1 , however, it may be possible to detect only one of the currents Iu 1 , Iv 1 , Iw 1 of the first windings. A case of this type is illustrated in the example shown in FIG. 20 . When Vv 1 is larger than the first predetermined value Vs 1 and Dsvp 1 ×Tsw is larger than Tsw−Δt 1 , a pulse width corresponding to Dsvp 1 ×Tsw cannot be obtained unless Svp 1 is switched ON before the time t 2 (n), even in a case where Svp 1 is switched OFF at the time t 4 (n) indicating the end of the switching period Tsw. As a result, V 1 ( 1 ) cannot be formed within the time zone of Δt 1 , and therefore the currents of the first windings cannot be detected.

Likewise with respect to the second voltage application unit 3 b , when Vv 2 ′ is larger than the first predetermined value Vs 1 in FIG. 20 , V 1 ( 2 ) cannot be formed within the time zone of the time shift Δt 1 , and therefore the currents of the second windings cannot be detected.

FIGS. 21A, 21B, 21C and 21D are illustrative views relating to a function of the first detectability determination unit 12 e according to the fifth embodiment of this invention. More specifically, the first detectability determination unit 12 e determines whether or not the voltage command value of the phase corresponding to the first intermediate phase voltage Emid 1 and the voltage command value of the phase corresponding to the second intermediate phase voltage Emid 2 are within a range not exceeding the first predetermined value Vs 1 . In FIG. 21A , a dotted line indicates the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ shown in FIG. 7B , a solid line indicates the first intermediate phase voltage Emid 1 , and a dot-dash line indicates the first predetermined value Vs 1 . Similarly to the first embodiment, as shown in FIG. 12A to 12D , Vs 1 =0.4 Vdc 1 is set.

FIG. 21B shows the output of the first detectability determination unit 12 e . The first detectability determination unit 12 e determines whether or not the currents of the first windings are detectable by determining whether or not the first intermediate phase voltage Emid 1 is within a range not exceeding the first predetermined value Vs 1 . The first detectability determination unit 12 e outputs the first detectability determination signal flag_ 1 at 1 when the first intermediate phase voltage Emid 1 is within a range not exceeding the first predetermined value Vs 1 , and outputs the first detectability determination signal flag_ 1 at 0 when the first intermediate phase voltage Emid 1 is outside this range.

In FIG. 21C , a dotted line indicates the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ shown in FIG. 8B , a solid line indicates the second intermediate phase voltage Emid 2 , and a dot-dash line indicates Vs 1 . FIG. 21D shows the second detectability determination signal flag_ 2 indicating whether or not the second intermediate phase voltage Emid 2 is within a range not exceeding the first predetermined value Vs 1 . The second detectability determination signal flag_ 2 is set at 1 when the second intermediate phase voltage Emid 2 is within this range, and set at 0 when the second intermediate phase voltage Emid 1 is outside the range.

Note that the second detectability determination signal flag_ 2 serves as the output of the second detectability determination unit 701 a to be described below in eighth to tenth embodiments using FIGS. 25, 28, and 31 . As shown in FIG. 17 , a second detectability determination unit is not used in the fifth embodiment, but is illustrated in FIGS. 21A to 21D for descriptive purposes.

Focusing on the first detectability determination signal flag_ 1 , the first detectability determination signal flag_ 1 shifts to 0 in the vicinity of a voltage phase angle θv of 60+120×x (x: 0, 1, 2) degrees. Focusing on the second detectability determination signal flag_ 2 , the second detectability determination signal flag_ 2 shifts to 0 in the vicinity of a voltage phase angle θv of 90+120×x (x: 0, 1, 2) degrees. Hence, the voltage phase angles θv at which the first detectability determination signal flag_ 1 and the second detectability determination signal flag_ 2 shift to 0 deviate from each other by 30 degrees, and therefore, when flag_ 1 is at 0, flag_ 2 is at 1, and conversely when flag_ 1 is at 1, flag_ 2 is at 0.

FIG. 22 is a flowchart showing a series of operations performed by the first detectability determination unit 12 e according to the fifth embodiment of this invention. In step S 4000 a , the first detectability determination unit 12 e calculates the first intermediate phase voltage Emid 1 on the basis of the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′. In step S 4000 b , the first detectability determination unit 12 e determines whether or not the first intermediate phase voltage Emid 1 is equal to or smaller than the first predetermined value Vs 1 . When “YES” is obtained, the routine advances to step S 4000 c , and when “NO” is obtained, the routine advances to step S 4000 d.

In a case where the routine advances to step S 4000 c , the first detectability determination unit 12 e inserts 1 into the first detectability determination signal flag_ 1 . In a case where the routine advances to step S 4000 d , on the other hand, the first detectability determination unit 12 e inserts 0 into the first detectability determination signal flag_ 1 .

Finally, when the first detectability determination signal flag_ 1 is at 1, the first detectability determination unit 12 e determines that the currents of the first windings are detectable, and therefore switches the switch 7 a so that the currents Id 1 , Iq 1 on two rotational axes, determined from the first winding currents, are output respectively as Id′, Iq′. When the first detectability determination signal flag_ 1 is at 0, on the other hand, the first detectability determination unit 12 e determines that the currents of the first windings are undetectable, and therefore switches the switch 7 a so that the currents Id 2 , Iq 2 on two rotational axes, determined from the second winding currents, are output respectively as Id′, Iq′.

According to the fifth embodiment, as described above, the currents of the first windings are detected on the basis of the currents flowing through the lower side arm elements of the respective phases of the first voltage application unit, and the currents of the second windings are detected on the basis of the currents flowing through the lower side arm elements of the respective phases of the second voltage application unit. Likewise with this configuration, identical effects to those of the first embodiment can be obtained.

Further, flag_ 1 indicates 0 when the voltage phase angle θv is in the vicinity of 60+120×x (x: 0, 1, 2) degrees. Therefore, by referring to the changes implemented in the third embodiment from the first embodiment, the detectability of the first windings can be determined on the basis of the voltage phase angle θv calculated from the first voltage commands likewise in a configuration where the first current detection unit detects the currents of the first windings on the basis of the currents flowing through the lower side arm elements of the respective phases of the first voltage application unit.

Moreover, by referring to the changes implemented in the fourth embodiment from the first embodiment, the detectability of the first windings can be determined on the basis of the voltage phase angle θv calculated from the second voltage commands likewise in a configuration where the first current detection unit detects the currents of the first windings on the basis of the currents flowing through the lower side arm elements of the respective phases of the first voltage application unit.

Furthermore, in the fifth embodiment, the first current detection unit detects the currents of the first windings on the basis of the currents flowing through the lower side arm elements of the respective phases of the first voltage application unit, while the second current detection unit detects the currents of the second windings on the basis of the currents flowing through the lower side arm elements of the respective phases of the second voltage application unit. Instead, however, this invention may be implemented with a similar configuration in which the first current detection unit detects the currents of the first windings on the basis of the currents flowing through the lower side arm elements of any two of the three phases of the first voltage application unit and the second current detection unit detects the currents of the second windings on the basis of the currents flowing through the lower side arm elements of any two of the three phases of the second voltage application unit.

Sixth Embodiment

FIG. 23 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a sixth embodiment of this invention. The sixth embodiment differs from the first to fifth embodiments, described above, in that the first current detection unit 4 a is used to detect the currents of the first windings and a second current detection unit 4 d is used to detect the currents of the second windings. Accordingly, the following description centers on this difference.

In the sixth embodiment, the first voltage application unit 3 a generates the ON/OFF patterns indicated by Sup 1 , Svp 1 , Swp 1 in FIG. 9 , as described in the first embodiment, while the second voltage application unit 3 b generates the ON/OFF patterns indicated by Sup 2 , Svp 2 , Swp 2 in FIG. 20 , as described in the fifth embodiment.

As shown in FIGS. 12A to 12D of the first embodiment, when the currents Iu 1 , Iv 1 , Iw 1 of the first windings are detected on the basis of the current flowing through the DC bus line of the first voltage application unit 3 a , which is detected by the first current detection unit 4 a , flag_ 1 is set at 0 in the vicinity of a voltage phase angle θv of 60×x (x: 0, 1, 2, 3, 4, 5, 6) degrees, and in this case, the currents of the first windings cannot be detected.

Further, as shown in FIGS. 21A to 21D of the fifth embodiment, when the currents Iu 2 , Iv 2 , Iw 2 of the second windings are detected on the basis of the currents flowing through the lower arm elements of the second voltage application unit 3 b , which are detected by the second current detection unit 4 d , flag_ 2 is set at 0 in the vicinity of a voltage phase angle θv of 90+120×x (x: 0, 1, 2) degrees, and in this case, the currents of the second windings cannot be detected.

Hence, even when a configuration such as that shown in FIG. 23 is employed, flag_ 1 and flag_ 2 do not shift to 0 simultaneously, and at least one of flag_ 1 and flag_ 2 is set at 1. Therefore, likewise with the configuration of the sixth embodiment, similarly to the first to fifth embodiments, the first voltage commands and second voltage commands can be calculated on the basis of the currents Iu 1 , Iv 1 , Iw 1 of the first windings when flag_ 1 is at 1 (i.e. when the currents of the first windings are detectable), and the first voltage commands and second voltage commands can be calculated on the basis of the currents Iu 2 , Iv 2 , Iw 2 of the second windings when flag_ 1 is at 0 (i.e. when the currents of the first windings are undetectable).

According to the sixth embodiment, as described above, the first current detection unit detects the currents of the first windings on the basis of the current flowing through the DC bus line of the first voltage application unit, while the second current detection unit detects the currents of the second windings on the basis of the currents flowing through the lower arm elements of the respective phases of the second voltage application unit. With this configuration, identical effects to those of the first to fifth embodiments can be obtained.

Seventh Embodiment

FIG. 24 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a seventh embodiment of this invention. The seventh embodiment differs from the first to sixth embodiments in that a first current detection unit 4 c is used to detect the currents of the first windings and the second current detection unit 4 b is used to detect the currents of the second windings. Accordingly, the following description centers on this difference.

In the seventh embodiment, the first voltage application unit 3 a generates the ON/OFF patterns indicated by Sup 1 , Svp 1 , Swp 1 in FIG. 20 , as described in the fifth embodiment, while the second voltage application unit 3 b generates the ON/OFF patterns indicated by Sup 2 , Svp 2 , Swp 2 in FIG. 9 , as described in the first embodiment.

As shown in FIGS. 21A to 21D of the fifth embodiment, when the currents Iu 1 , Iv 1 , Iw 1 of the first windings are detected on the basis of the currents flowing through the lower arm elements of the respective phases of the first voltage application unit 3 a , which are detected by the first current detection unit 4 c , flag_ 1 is set at 0 in the vicinity of a voltage phase angle θv of 60+120×x (x: 0, 1, 2) degrees, and in this case, the currents of the first windings cannot be detected.

Further, as shown in FIGS. 12A to 12D of the first embodiment, when the currents Iu 2 , Iv 2 , Iw 2 of the second windings are detected on the basis of the current flowing through the DC bus line of the second voltage application unit 3 b , which is detected by the second current detection unit 4 b , flag_ 2 is set at 0 in the vicinity of a voltage phase angle θv of 30+60×x (x: 0, 1, 2, 3, 4, 5) degrees, and in this case, the currents of the second windings cannot be detected.

Hence, even when a configuration such as that shown in FIG. 24 is employed, flag_ 1 and flag_ 2 do not shift to 0 simultaneously, and at least one of flag_ 1 and flag_ 2 is set at 1. Therefore, likewise with the configuration of the seventh embodiment, similarly to the first to fifth embodiments, the first voltage commands and second voltage commands can be calculated on the basis of the currents Iu 1 , Iv 1 , Iw 1 of the first windings when flag_ 1 is at 1 (i.e. when the currents of the first windings are detectable), and the first voltage commands and second voltage commands can be calculated on the basis of the currents Iu 2 , Iv 2 , Iw 2 of the second windings when flag_ 1 is at 0 (i.e. when the currents of the first windings are undetectable).

According to the seventh embodiment, as described above, the first current detection unit detects the currents of the first windings on the basis of the currents flowing through the lower arm elements of the respective phases of the first voltage application unit, while the second current detection unit detects the currents of the second windings on the basis of the current flowing through the DC bus line of the second voltage application unit. With this configuration, identical effects to those of the first to sixth embodiments can be obtained.

Eighth Embodiment

FIG. 25 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to an eighth embodiment of this invention. The configuration of the eighth embodiment differs from that of the first embodiment in further including the second detectability determination unit 701 a , and in an internal configuration of a control unit 5 b . Accordingly, the following description centers on these differences.

The second detectability determination unit 701 a outputs the second detectability determination signal flag_ 2 for determining whether or not the currents of the second windings are detectable on the basis of the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′.

Next, changes implemented on the control unit 5 b according to the eighth embodiment from the control unit 5 a according to the first embodiment will be described. A switch 7 b according to the eighth embodiment switches selectively between currents Id 1 ′, Iq 1 ′ on two rotational axes and currents Id 2 ′, Iq 2 ′ on two rotational axes, among the currents Id 1 , Iq 1 of the first windings and the currents Id 2 , Iq 2 of the second windings, on the basis of the first detectability determination signal flag_ 1 and the second detectability determination signal flag_ 2 , and outputs the selected currents.

A subtractor 708 a calculates a deviation dId 1 between a d axis current command Id* of the AC rotary machine 1 a and the current Id 1 ′ on two rotational axes, output by the switch 7 b.

A subtractor 708 b calculates a deviation dIq 1 between a q axis current command Iq* of the AC rotary machine 1 a and the current Iq 1 ′ on two rotational axes, output by the switch 7 b.

A subtractor 708 c calculates a deviation dId 2 between the d axis current command Id* of the AC rotary machine 1 a and the current Id 2 ′ on two rotational axes, output by the switch 7 b.

A subtractor 708 d calculates a deviation dIq 2 between the q axis current command Iq* of the AC rotary machine 1 a and the current Iq 2 ′ on two rotational axes, output by the switch 7 b.

A controller 709 a calculates a first voltage command Vd 1 for controlling the deviation dId 1 to zero using a P controller, a PI controller, and so on.

A controller 709 b calculates a first voltage command Vq 1 for controlling the deviation dIq 1 to zero using a P controller, a PI controller, and so on.

A controller 709 c calculates a second voltage command Vd 2 for controlling the deviation dId 2 to zero using a P controller, a PI controller, and so on.

A controller 709 d calculates a second voltage command Vq 2 for controlling the deviation dIq 2 to zero using a P controller, a PI controller, and so on.

A coordinate converter 710 a calculates the first voltage commands Vu 1 , Vv 1 , Vw 1 by performing coordinate conversion to convert the first voltage commands Vd 1 , Vq 1 to three-phase AC coordinates on the basis of the first voltage commands Vd 1 , Vq 1 and the rotation position θ of the AC rotary machine 1 a.

A coordinate converter 710 b calculates the second voltage commands Vu 2 , Vv 2 , Vw 2 by performing coordinate conversion to convert the second voltage commands Vd 2 , Vq 2 to three-phase AC coordinates on the basis of the second voltage commands Vd 2 , Vq 2 and the position θ−30, which is obtained by subtracting 30 degrees from the rotation position θ of the AC rotary machine 1 a.

In a case where the second current detection unit 4 b detects the currents of the second windings on the basis of the current flowing through the DC bus line of the second voltage application unit 3 b , as in the first embodiment, the currents of the second windings are detectable when the second intermediate phase voltage Emid 2 is no higher than the first threshold Vs 1 and no lower than the second threshold Vs 2 , and undetectable when the second intermediate phase voltage Emid 2 exceeds the first threshold Vs 1 or is lower than the second threshold Vs 2 .

A function of the second detectability determination unit 701 a newly added in the eighth embodiment will now be described on the basis of the above description. FIG. 26 is a flowchart showing a series of operations performed by the second detectability determination unit 701 a according to the eighth embodiment of this invention. In step S 7000 a , the second detectability determination unit 701 a calculates the second intermediate phase voltage Emid 2 on the basis of the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′.

In step S 7000 b , the second detectability determination unit 701 a determines whether or not the second intermediate phase voltage Emid 2 is equal to or lower than the first predetermined value Vs 1 . When “YES” is obtained, the routine advances to step S 7000 c , and when “NO” is obtained, the routine advances to step S 7000 e.

In step S 7000 c , the second detectability determination unit 701 a determines whether or not the second intermediate phase voltage Emid 2 equals or exceeds the second predetermined value Vs 2 . When “YES” is obtained, the routine advances to step S 7000 d , and when “NO” is obtained, the routine advances to step S 7000 e . In a case where the routine advances to step S 7000 d , the second detectability determination unit 701 a inserts 1 into the second detectability determination signal flag_ 2 . In a case where the routine advances to step S 7000 e , the second detectability determination unit 701 a inserts 0 into the second detectability determination signal flag_ 2 .

Next, operations of the switch 7 b will be described using FIG. 27 . FIG. 27 is a flowchart showing a series of operations performed by the switch 7 b according to the eighth embodiment of this invention. Switching operations are performed by the switch 7 b in steps S 7100 c , S 7100 d , and S 7100 e in accordance with the determination result obtained in step S 7100 a as to whether or not the first detectability determination signal flag_ 1 is equal to 1 and the determination result obtained in step S 7100 b as to whether or not the second detectability determination signal flag_ 2 is equal to 1.

When flag_ 1 is equal to 1 and flag_ 2 is equal to 1, the routine advances to step S 7100 c , where the currents Id 1 , Iq 1 of the first windings are selected as Id 1 ′, Iq 1 ′ and the currents Id 2 , Iq 2 of the second windings are selected as Id 2 ′, Iq 2 ′. The selected currents are then output.

When flag_ 1 is equal to 1 but flag_ 2 is not equal to 1, the routine advances to step S 7100 d , where the currents Id 1 , Iq 1 of the first windings are selected as Id 1 ′, Iq 1 ′ and the currents Id 1 , Iq 1 of the first windings are also selected as Id 2 ′, Iq 2 ′. The selected currents are then output.

When flag_ 1 is not equal to 1, the routine advances to step S 7100 e , where the currents Id 2 , Iq 2 of the second windings are selected as Id 1 ′, Iq 1 ′ and the currents Id 2 , Iq 2 of the second windings are also selected as Id 2 ′, Iq 2 ′, regardless of the value of flag_ 2 . The selected currents are then output.

In the eighth embodiment, the first voltage commands Vd 1 , Vq 1 are determined by the subtractors 708 a , 708 b and the controllers 709 a , 709 b using the current commands Id*, Iq* and Id 1 ′, Iq 1 ′. As a result, the first voltage commands Vd 1 , Vq 1 are calculated on the basis of Id 1 ′, Iq 1 ′.

Further, the second voltage commands Vd 2 , Vq 2 are determined by the subtractors 708 c , 708 d and the controllers 709 c , 709 d using the current commands Id*, Iq* and Id 2 ′, Iq 2 ′. As a result, the second voltage commands Vd 2 , Vq 2 are calculated on the basis of Id 2 ′, Iq 2 ′.

When the first detectability determination unit 12 a determines that the currents of the first windings are detectable and the second detectability determination unit 701 a determines that the currents of the second windings are detectable (i.e. when the routine advances to step S 7100 c ), the switch 7 b switches the currents Id 1 , Iq 1 of the first windings to Id 1 ′, Iq 1 ′, respectively, and switches the currents Id 2 , Iq 2 of the second windings to Id 2 ′, Iq 2 ′, respectively, and then outputs the switched currents. Hence, in this case, the first voltage commands are calculated on the basis of the currents of the first windings and the second voltage commands are calculated on the basis of the currents of the second windings.

Further, when the first detectability determination unit 12 a determines that the currents of the first windings are undetectable (i.e. when the routine advances to step S 7100 e ), the switch 7 b switches the currents Id 2 , Iq 2 of the second windings to Id 1 ′, Iq 1 ′, respectively, and also switches the currents Id 2 , Iq 2 of the second windings to Id 2 ′, Iq 2 ′, respectively, and then outputs the switched currents. Hence, in this case, the first voltage commands and the second voltage commands are calculated on the basis of the currents of the second windings.

Furthermore, when the first detectability determination unit 12 a determines that the currents of the first windings are detectable but the second detectability determination unit 701 a determines that the currents of the second windings are undetectable (i.e. when the routine advances to step S 7100 d ), the switch 7 b switches the currents Id 1 , Iq 1 of the first windings to Id 1 ′, Iq 1 ′, respectively, and also switches the currents Id 1 , Iq 1 of the first windings to Id 2 ′, Iq 2 ′, respectively, and then outputs the switched currents. Hence, in this case, the first voltage commands and the second voltage commands are calculated on the basis of the currents of the first windings.

In the first to seventh embodiments, when the currents of the first windings are undetectable, the first voltage commands and second voltage commands are calculated using the currents of the second windings. In this case, as shown in FIG. 12B , the currents of the first windings are undetectable (flag_ 1 =0) only in a section where the voltage phase angle θv is in the vicinity of 60×x (x: 0, 1, 2, 3, 4, 5) degrees, and therefore a section in which the currents of the second windings are used is small.

In the eighth embodiment, on the other hand, the second detectability determination unit 701 a is provided in addition to the first detectability determination unit 12 a , and therefore the second voltage commands can be calculated on the basis of the currents of the second windings when flag_ 2 is at 1, as shown in FIG. 12D . Hence, in addition to the effects of the first to seventh embodiments, the controllability of the currents of the second windings can be improved, enabling further reductions in torque ripple, vibration, and noise from the AC rotary machine 1 a.

Moreover, by referring to the second embodiment, a method of calculating the difference between the second maximum phase voltage and the second intermediate phase voltage and the difference between the second intermediate phase voltage and the second minimum phase voltage, and determining that the currents of the second windings are undetectable when the respective values thereof are smaller than the third predetermined value, may be employed as the method used by the second detectability determination unit 701 a to determine the detectability of the currents of the second windings.

Further, by referring to the third and fourth embodiments so as to determine the detectability of the currents of the second windings by determining the voltage phase angle θv from at least one of the first voltage commands and the second voltage commands, identical effects to the first embodiment can be obtained.

Ninth Embodiment

FIG. 28 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a ninth embodiment of this invention. A configuration of the ninth embodiment differs from the configuration of the eighth embodiment in that a control unit 5 c is used in place of the control unit 5 b , and the following description centers on this difference. Hence, the following description focuses on changes implemented on the control unit 5 c from the control unit 5 b.

An adder 801 a outputs an added value (Id 1 ′+Id 2 ′) obtained by adding together the current Id 1 ′ on two rotational axes and the current Id 2 ′ on two rotational axes.

An adder 801 b outputs an added value (Iq 1 ′+Iq 2 ′) obtained by adding together the current Iq 1 ′ on two rotational axes and the current Iq 2 ′ on two rotational axes.

A subtractor 802 a outputs a value (Id 1 ′−Id 2 ′) obtained by subtracting the current Id 1 ′ on two rotational axes from the current Id 2 ′ on two rotational axes.

A subtractor 802 b outputs a value (Iq 1 ′−Iq 2 ′) obtained by subtracting the current Iq 1 ′ on two rotational axes from the current Iq 2 ′ on two rotational axes.

A multiplier 803 a multiplies the added value (Id 1 ′+Id 2 ′) output by the adder 801 a by K 1 , and outputs the result as a sum current Id_sum. Here, K 1 =0.5.

A multiplier 803 b multiplies the added value (Iq 1 ′+Iq 2 ′) output by the adder 801 b by K 1 , and outputs the result as a sum current Iq_sum. Here, K 1 =0.5.

A multiplier 804 a multiplies the subtracted value (Id 1 ′−Id 2 ′) output by the subtractor 802 a by K 2 , and outputs the result as a differential current delta_Id. Here, K 2 =0.5.

A multiplier 804 b multiplies the subtracted value (Iq 1 ′−Iq 2 ′) output by the subtractor 802 b by K 2 , and outputs the result as a differential current delta_Iq. Here, K 2 =0.5.

A subtractor 805 a calculates a deviation dId_sum between the d axis current command Id* of the AC rotary machine 1 a and the sum current Id_sum.

A subtractor 805 b calculates a deviation dIq_sum between the q axis current command Iq* of the AC rotary machine 1 a and the sum current Iq_sum.

A controller 806 a outputs a sum voltage Vd_sum at which the deviation dId_sum is controlled to zero using a P controller, a PI controller, and the like on the basis of a product of a proportional gain Kpd_sum of the used controllers and the deviation dId_sum.

A controller 806 b outputs a sum voltage Vq_sum at which the deviation dIq_sum is controlled to zero using a P controller, a PI controller, and the like on the basis of a product of a proportional gain Kpq_sum of the used controllers and the deviation dIq_sum.

A controller 806 c outputs a differential voltage delta_Vd at which the differential current delta_Id is controlled to zero using a P controller, a PI controller, and the like on the basis of a product of a proportional gain Kpd_delta of the used controllers and a deviation delta_dId.

A controller 806 d outputs a differential voltage delta_Vq at which the differential current delta_Iq is controlled to zero using a P controller, a PI controller, and the like on the basis of a product of a proportional gain Kpq_delta of the used controllers and a deviation delta_dIq.

An adder 807 a outputs a value obtained by adding together the sum voltage Vd_sum and the differential voltage delta_Vd as the first voltage command Vd 1 .

An adder 807 b outputs a value obtained by adding together the sum voltage Vq_sum and the differential voltage delta_Vq as the first voltage command Vq 1 .

A subtractor 808 a outputs a value obtained by subtracting the sum voltage Vd_sum from the differential voltage delta_Vd as the second voltage command Vd 2 .

A subtractor 808 b outputs a value obtained by subtracting the sum voltage Vq_sum from the differential voltage delta_Vq as the second voltage command Vq 2 .

Next, the operations performed by the control unit 5 c according to the ninth embodiment will be described in detail.

When the first detectability determination signal flag_ 1 and the second detectability determination signal flag_ 2 are both at 1 (in other words, when the currents of the first windings and the currents of the second windings are both determined to be detectable), the currents Id 1 ′, Iq 1 ′ on two rotational axes and the currents Id 2 ′, Iq 2 ′ on two rotational axes are equal to the currents Id 1 , Iq 1 of the first windings and the currents Id 2 , Iq 2 of the second windings, respectively.

Hence, the sum currents Id_sum, Iq_sum and the differential currents delta_Id, delta_Iq are as shown below in Equations (23) to (26), respectively.

Id _sum= K 1×( Id 1′+ Id 2′)

= K 1×( Id 1+ Id 2)  (23)

Iq _sum= K 1×( Iq 1′+ Iq 2′)

= K 1×( Iq 1+ Iq 2)  (24)

delta_ Id=K 2×( Id 1′− Id 2′)

= K 2×( Id 1− Id 2)  (25)

delta_ Iq=K 2×( Iq 1′− Iq 2′)

= K 2×( Iq 1− Iq 2)  (26)

Hence, the sum currents are expressed by the sum of the currents of the first windings, detected by the first current detection unit 4 a , and the currents of the second windings, detected by the second current detection unit 4 b , while the differential currents are expressed by the difference between the currents of the first windings, detected by the first current detection unit 4 a , and the currents of the second windings, detected by the second current detection unit 4 b.

The sum voltages Vd_sum, Vq_sum are calculated on the basis of the sum currents Id_sum, Iq_sum and a sum current gain, while the differential voltages delta_Vd, delta_Vq are calculated on the basis of the differential currents delta_Id, delta_Iq and a differential current gain. Further, the first current commands Vd 1 , Vq 1 and the second current commands Vq 1 , Vq 2 are calculated by the adders 807 a , 807 b and the subtractors 808 a , 808 b.

Here, the first three-phase windings U 1 , V 1 , W 1 and the second three-phase windings U 2 , V 2 , W 2 of the AC rotary machine 1 a are joined to each other magnetically, but are not electrically connected. Hence, voltages that are proportionate to products of respective differential values of the currents of the first windings and a mutual inductance between the first windings and the second windings are generated in the second three-phase windings. Meanwhile, voltages that are proportionate to products of respective differential values of the currents of the second windings and the mutual inductance between the first windings and the second windings are generated in the first three-phase windings. In other words, the first windings and the second windings interfere with each other magnetically.

In the ninth embodiment, however, the first voltage commands Vd 1 , Vd 2 and the second voltage commands Vq 1 , Vq 2 are calculated on the basis of the sum currents and the differential currents. As a result, when the currents of the first windings and the currents of the second windings are both detectable, the voltage commands Vd 1 , Vq 1 of the first windings are calculated in consideration of not only the currents of the first windings, detected by the first current detection unit 4 a , but also the currents of the second windings, detected by the second current detection unit 4 b.

Similarly, the second voltage commands Vd 2 , Vq 2 are calculated in consideration of not only the currents of the second windings, detected by the second current detection unit 4 b , but also the currents of the first windings, detected by the first current detection unit 4 a . Therefore, by providing the configuration of the ninth embodiment, a more stable control system can be constructed with respect to magnetic interference between the first windings and the second windings.

When the first detectability determination signal flag_ 1 is at 0 and the second detectability determination signal flag_ 2 is at 1 (in other words, when the currents of the first windings are determined to be undetectable but the currents of the second windings are determined to be detectable), the currents Id 1 ′, Iq 1 ′ on two rotational axes are equal to the currents Id 2 , Iq 2 of the second windings and the currents Id 2 ′, Iq 2 ′ on two rotational axes are also equal to the currents Id 2 , Iq 2 of the second windings, as shown in FIG. 27 .

Hence, the sum currents Id_sum, Iq_sum and the differential currents delta_Id, delta_Iq are as shown below in Equations (27) to (30), respectively.

Id _sum= K 1×( Id 1′+ Id 2′)

= K 1×(2× Id 2)  (27)

Iq _sum= K 1×( Iq 1′+ Iq 2′)

= K 1×(2× Iq 2)  (28)

delta_ Id=K 2×( Id 1′− Id 2′)

=0  (29)

delta_ Iq=K 2×( Iq 1′− Iq 2′)

=0  (30)

As shown in Equations (27) to (30), the sum currents are expressed by the currents of the second windings, detected by the second current detection unit 4 b , while the differential currents are 0. Hence, the first voltage commands Vd 1 , Vq 1 and the second voltage commands Vd 2 , Vq 2 are calculated on the basis of the currents of the second windings and the sum current gain.

When the first detectability determination signal flag_ 1 is at 1 and the second detectability determination signal flag_ 2 is at 0 (in other words, when the currents of the first windings are determined to be detectable but the currents of the second windings are determined to be undetectable), the currents Id 1 ′, Iq 1 ′ on two rotational axes are equal to the currents Id 1 , Iq 1 of the first windings and the currents Id 2 ′, Iq 2 ′ on two rotational axes are also equal to the currents Id 1 , Iq 1 of the first windings, as shown in FIG. 27 .

Hence, the sum currents Id_sum, Iq_sum and the differential currents delta_Id, delta_Iq are as shown below in Equations (31) to (34), respectively.

Id _sum= K 1×( Id 1′+ Id 2′)

= K 1×(2× Id 1)  (31)

Iq _sum= K 1×( Iq 1′+ Iq 2′)

= K 1×(2× Iq 1)  (32)

delta_ Id=K 2×( Id 1′− Id 2′)

=0  (33)

delta_ Iq=K 2×( Iq 1′− Iq 2′)

=0  (34)

As shown in Equations (31) to (34), the sum currents are expressed by the currents of the first windings, detected by the first current detection unit 4 a , while the differential currents are 0. Hence, the first voltage commands Vd 1 , Vq 1 and the second voltage commands Vd 2 , Vq 2 are calculated on the basis of the currents of the first windings and the sum current gain.

Here, the differential currents are set at 0 in accordance with Equations (29) and (30) when the first detectability determination unit 12 a outputs 0 as flag_ 1 , and are set at 0 in accordance with Equations (33) and (34) when the second detectability determination unit 701 a outputs 0 as flag_ 2 . Accordingly, the differential voltages obtained by multiplying the differential voltage gain by the sum currents also equal zero. In this case, therefore, the differential voltages delta_Vd, delta_Vq may be set at 0, and the subtractors 802 a , 802 b , the multipliers 804 a , 804 b , and the controllers 806 c , 806 d that calculate the differential voltages from the differential currents may be omitted.

Further, by varying the differential current gains Kpd_delta, Kpq_delta on the basis of at least one of the first voltage commands, the second voltage commands, the sum voltage, and the rotation speed of the AC rotary machine 1 a , pulsation in the differential voltages delta_Vd, delta_Vq caused by pulsation in the differential currents delta_Id, delta_Iq during switches in the first detectability determination signal flag_ 1 and the second detectability determination signal flag_ 2 from 0 to 1 and from 1 to 0 can be reduced.

FIG. 29 is a view showing a condition in which the differential current gains are varied on the basis of the first voltage commands, according to the ninth embodiment of this invention. FIG. 29 shows an example of a case in which the differential current gains Kpd_delta, Kpq_delta are varied in accordance with an amplitude V 1 of the first voltage commands. When the amplitude V 1 of the first voltage commands is no higher than a threshold Vsa 1 , the differential current gains Kpd_delta, Kpq_delta are set respectively at fixed values Kpd_delta 1 , Kpq_delta 1 . When the amplitude V 1 of the first voltage commands exceeds the threshold Vsa 1 , on the other hand, the differential current gains Kpd_delta, Kpq_delta are reduced along a straight line. The threshold Vsa 1 and an incline of the straight line may be determined in accordance with a generated pulsation level. Here, the amplitude V 1 of the first voltage commands may be determined using Equation (35), shown below.

[Math. 1]

V 1=√{square root over (2( V u1 2 +V u1 2 +V u1 2 ))}=√{square root over (2( V d1 2 +V q1 2 ))}  (35)

Further, when a calculation load of a CPU that performs calculations as the control unit 5 c increases due to calculating the square root in Equation (35), the abscissa of FIG. 29 may be set as the square of the amplitude. Furthermore, an amplitude V 2 of the second voltage commands, which is given below in Equation (36), an amplitude V_sum of the sum voltage, which is given below in Equation (37), or a combination of V 1 , V 2 , and V_sum may be used as the abscissa of FIG. 29 .

[Math. 4]

V 2=√{square root over (2( V u2 2 +V u2 2 +V u2 2 ))}=√{square root over (2( V d2 2 +V q2 2 ))}  (36)

V _sum=√{square root over (2( V dsum 2 +V qsum 2 ))}  (37)

By varying the sum current gains Kpd_sum, Kpq_sum on the basis of at least one of the first voltage commands, the second voltage commands, and the sum voltage, pulsation in the sum voltages Vd_sum, Vq_sum caused by pulsation in the sum currents Id_sum, Iq_sum during switches in the first detectability determination signal flag_ 1 and the second detectability determination signal flag_ 2 can be reduced.

FIG. 30 is a view showing a condition in which the sum current gains are varied on the basis of the first voltage commands, according to the ninth embodiment of this invention. FIG. 30 shows an example of a case in which the sum current gains Kpd_sum, Kpq_sum are varied in accordance with the amplitude V 1 of the first voltage commands. When the amplitude V 1 of the first voltage commands is no higher than the threshold Vsa 1 , the sum current gains Kpd_sum, Kpq_sum are set respectively at fixed values Kpd_sum 1 , Kpq_sum 1 . When the amplitude V 1 of the first voltage commands exceeds Vsa 1 , on the other hand, the sum current gains Kpd_sum, Kpq_sum are reduced along a straight line. The threshold Vsa 1 and the incline of the straight line may be determined in accordance with the generated pulsation level.

Further, the amplitude V 1 of the first voltage commands is used as the abscissa in FIG. 29 , but the amplitude V 2 of the second voltage commands, which is given above in Equation (36), the amplitude V_sum of the sum voltage, which is given above in Equation (37), or a combination of V 1 , V 2 , and V_sum may be used instead. Moreover, the gains may be switched in accordance with effective values rather than the amplitude of the first voltage commands, the second voltage commands, or the sum voltage.

Furthermore, similar effects are obtained with a configuration in which the abscissae of FIGS. 29 and 30 are set as the rotation speed of the AC rotary machine 1 a such that the sum current gains and differential current gains are set at fixed values at or below a predetermined threshold relating to the speed and reduced in accordance with the speed above the predetermined threshold.

Tenth Embodiment

FIG. 31 is a view showing an overall configuration of a control apparatus for an AC rotary machine according to a tenth embodiment of this invention. A configuration of the tenth embodiment differs from the ninth embodiment in that the first current detection unit 4 a is replaced with the first current detection unit 4 c and the second current detection unit 4 b is replaced with the second current detection unit 4 d . Accordingly, the following description centers on these differences.

In the configuration of the ninth embodiment, shown in FIG. 28 , the first current detection unit 4 a and the second current detection unit 4 b are used. Therefore, as shown in FIGS. 12A to 12D , the first current detection unit 4 a is unable to detect the currents of the first windings in the vicinity of a voltage phase angle θv of 60×x (x: 0, 1, 2, 3, 4, 5) degrees, and the second current detection unit 4 b is unable to detect the currents of the second windings in the vicinity of a voltage phase angle θv of 30+60×x (x: 0, 1, 2, 3, 4, 5) degrees.

In the tenth embodiment, however, the first current detection unit 4 c and the second current detection unit 4 d are used. Therefore, as shown in FIGS. 21A to 21D , the first current detection unit 4 c becomes unable to detect the currents of the first windings in the vicinity of a voltage phase angle θv of 60+120×x (x: 0, 1, 2) degrees, and the second current detection unit 4 d becomes unable to detect the currents of the second windings in the vicinity of a voltage phase angle θv of 90+120×x (x: 0, 1, 2) degrees. As a result, in the tenth embodiment, a voltage phase interval in which one of the first and second current detection units is unable to perform current detection can be reduced in comparison with the ninth embodiment.

Accordingly, a period in which the currents of the first windings and the currents of the second windings are both detectable is increased. As a result, a period in which the voltage commands Vd 1 , Vq 1 of the first windings are calculated in consideration of the currents of the second windings, detected by the second current detection unit, in addition to the currents of the first windings, detected by the first current detection unit, is increased. Similarly, a period in which the second voltage commands Vd 2 , Vq 2 are calculated in consideration of the currents of the first windings, detected by the first current detection unit, in addition to the currents of the second windings, detected by the second current detection unit, is increased. Therefore, an even more stable control system than that of the ninth embodiment can be constructed with respect to magnetic interference between the first windings and the second windings.

Note that in the first to tenth embodiments described above, an AC rotary machine including a first winding and a second winding was subjected to control. This invention is not limited to an AC rotary machine of this type, however, and the control method of this invention may be applied as is to an AC rotary machine having an Nth (where N is an integer no smaller than 3) winding indicating a third winding or more windings by substituting the first winding and the second to Nth windings respectively for the first and second windings described in the first to tenth embodiments.

Further, in the first to tenth embodiments described above, an AC rotary machine including first three-phase windings and second three-phase windings having a 30 degree phase difference was subjected to control. This invention is not limited to an AC rotary machine of this type, however, and by providing phase differences between the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ and the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′, the control method of this invention may be applied to an AC rotary machine including first three-phase windings and second three-phase windings having a phase difference of 30+60×N (where N is an integer) degrees or an AC rotary machine including first three-phase windings and second three-phase windings not having a phase difference.

For example, when the phase difference is 30 degrees, the first voltage commands Vu 1 ′, Vv 1 ′, Vw 1 ′ and the second voltage commands Vu 2 ′, Vv 2 ′, Vw 2 ′ are similar to FIGS. 12A to 12D . As a result, the first detectability determination signal flag_ 1 and the second detectability determination signal flag_ 2 do not switch to 0 simultaneously, and therefore the control method of this invention can be applied.

Furthermore, the control apparatus for an AC rotary machine described in the first to tenth embodiments may be applied to control of an electric power steering having a control apparatus for an AC rotary machine. An electric power steering apparatus requires a control unit that calculates a first voltage command and a second voltage command to ensure that the AC rotary machine generates torque for assisting steering torque of a steering system.

By applying the control apparatus for an AC rotary machine according to this invention as a control unit for an electric power steering, the first voltage command and the second voltage command can be calculated at a high amplitude while maintaining a switching period Tsw. As a result, a steering system in which the switching frequency, which is given by the inverse of the switching period, is removed from the audible range such that increased output is obtained at an identical volume ratio while maintaining low noise can be constructed. In other words, the apparatus can be reduced in size while obtaining an identical output ratio, and therefore a steering system that is easy to install can be realized.