Scanning drive circuit and organic light-emitting display

Referring to FIG. 1 and FIG. 2 , a scanning drive circuit is provided in this embodiment. The scanning drive circuit includes a first scan driver for sequentially outputting selection signals and a second scan driver for sequentially outputting transmission signals. The first scan driver includes a plurality of first cascade structures and the second scan driver includes a plurality of second cascade structures. Each cascade structure of the first cascade structures and/or the second cascade structures may have the following structure. In this embodiment, each cascade structure of the first cascade structures and the second cascade structures includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , a fifth transistor M 5 , a sixth transistor M 6 , a seventh transistor M 7 , an eighth transistor M 8 , a ninth transistor M 9 , a first capacitor C 1 , a second capacitor C 2 , a third capacitor C 3 , a scanning signal input terminal IN, a scanning signal output terminal OUT, a first clock end CKL 1 , a second clock end CLK 2 , a first level end VGH, a second level end VGL 1 , a third level end VGL 2 and a driving signal output terminal EM.

The first transistor M 1 includes an input terminal connected to the scanning signal output terminal OUT or the scanning signal input terminal IN of a precedent cascade structure, a gate terminal connected to the first clock end CKL 1 , and an output terminal. The second transistor M 2 includes a gate terminal connected to the output terminal of the first transistor M 1 , an input terminal connected to the second clock end CKL 2 , and an output terminal connected to the scanning signal output terminal OUT. The third transistor M 3 includes an input terminal connected to the first level end VGH, a gate terminal connected to the scanning signal output terminal OUT, and an output terminal. The fourth transistor M 4 includes an input terminal connected to the output terminal of the third transistor M 3 , a gate terminal connected to the first clock end CKL 1 , and an output terminal connected to the second level end VGL 1 . The fifth transistor M 5 includes an input terminal connected to the first level end VGH, a gate terminal connected to the output terminal of the third transistor M 3 , and an output terminal connected to the scanning signal output terminal OUT. The sixth transistor M 6 includes an input terminal connected to the first level end VGH, a gate terminal connected to the scanning signal output terminal OUT, and an output terminal. The seventh transistor M 7 includes an input terminal connected to the output terminal of the sixth transistor M 6 , a gate terminal connected to the first clock end CKL 1 , and an output terminal connected to the second level end VGL 1 . The eighth transistor M 8 includes an input terminal connected to the first level end VGH, a gate terminal connected to the scanning signal output terminal OUT, and an output terminal connected to a driving signal output terminal EM. The ninth transistor M 9 includes an input terminal connected to the driving signal output terminal EM, a gate terminal connected to the output terminal of the sixth transistor M 6 , and an output terminal connected to the third level end VGL 2 .

The gate electrode of the first transistor M 1 , the gate electrode of the fourth transistor M 4 and the gate electrode of the seventh transistor M 7 are shorted, a second electrode of the first transistor M 1 , the gate electrode of the second transistor M 2 and the first side of the first capacitor C 1 are shorted, the second electrode of the second transistor M 2 , the gate electrode of the third transistor M 3 , the second electrode of the fifth transistor M 5 , the gate electrode of the sixth transistor M 6 , the gate electrode of the eighth transistor M 8 , the first side of the first capacitor C 1 and the second side of the second capacitor C 2 are shorted, the first electrode of the third transistor M 3 , the first electrode of the fifth transistor M 5 , the first electrode of the sixth transistor M 6 , the first electrode of the eighth transistor M 8 and the first side of the second capacitor C 2 are shorted, the second electrode of the third transistor M 3 , the first electrode of the fourth transistor M 4 and the gate electrode of the fifth transistor M 5 are shorted, the second electrode of the fourth transistor M 4 , the second electrode of the seventh transistor M 7 and the second side of the third capacitor C 3 are shorted, the second electrode of the sixth transistor M 4 , the first electrode of the seventh transistor M 7 , the first side of the third transistor M 3 and the gate electrode of the ninth transistor M 9 are shorted, the second electrode of the eighth transistor M 8 and the first electrode of the ninth transistor M 9 are shorted.

The first electrode of the first transistor M 1 is connected to the scanning signal input terminal IN, the second electrode of the second transistor M 2 is connected to the scanning signal output terminal OUT, the gate electrode of the first transistor M 1 is connected to the clock end CLK 1 , the first electrode of the second transistor M 2 is connected to the second clock end CLK 2 , the first electrode of the third transistor M 3 is connected to the first level end VGH, the second electrode of the fourth transistor M 4 is connected to the second level end VGL 1 , the second electrode of the ninth transistor M 9 is connected to the second low level signal input terminal VGL 2 , and the second electrode of the eighth transistor M 8 is connected to the scanning signal output terminal EM.

High level signals are inputted from the first level end VGH (which means the input voltage of the first level end VGH is positive), the first clock signal is inputted from the first clock end CLK 1 , the second clock signal is inputted from the second clock end CLK 2 , the scanning signal is inputted from the scanning signal input terminal IN, the first low level signal is inputted from the second level end VGL 1 (which means that the input voltage of the second level end VGL 1 is negative), the second low level signal is inputted from the second low level signal input terminal VGL 2 (which means that the input voltage of the second level signal input terminal VGL 2 is negative), the driving signal is outputted from the driving signal output terminal EM, and the output scanning signal is outputted from the scanning signal output terminal OUT.

The first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 , the seventh transistor M 7 , the eighth transistor M 8 and the ninth transistor M 9 are Field Effect Transistors, preferably are P-channel type Field Effect Transistors. More specifically, they are Thin Film Field Effect Transistors (TFT), and preferably are P-channel type Thin Film Field Effect Transistors.

Since each of the cascade structures of the first scan driver and the second scan driver of the scanning drive circuit includes nine transistors and requires only two clock signals, it is possible to reduce the number of transistors used by the scanning drive circuit. Therefore, this greatly enhances the reliability of the product, and reduces the costs of design and manufacture. In addition, the presence of the sixth transistor M 6 , the seventh transistor M 7 , the eighth transistor M 8 and the ninth transistor M 9 enables more a precise and reliable output terminal of the driving signal output terminal EM of the scanning drive circuit.

It should be noted that the second capacitor C 2 and the third capacitor C 3 can also be omitted when there is a load capacitance connected to the scanning signal output terminal OUT. In this embodiment, the second capacitor C 2 and the third capacitor C 3 are provided to reduce the current of the first level end VGH, the second level end VGL 1 and the third level end VGL 2 .

The connection relationship of the plurality of cascade structures will now be described taken the first scan driver as an example.

The first scan driver includes N levels of cascade structures. The scanning signal output terminal of the first level cascade structure is connected to the scanning signal input terminal of the second level cascade structure, and the scanning signal output terminal of the second level cascade structure is connected to the scanning signal input terminal of the third level cascade structure, and so on. The scanning signal output terminal of the N−1 level cascade structure is connected to the scanning signal input terminal of the N level cascade structure.

The first clock end of an odd numbered level cascade structure is shorted to the second clock end of an even numbered level cascade structure, and the second clock end of an odd numbered level cascade structure is shorted to the first clock end of an even numbered level cascade structure.

The first clock signal CLK 1 is inputted into the first clock end of the first level cascade structure, and the second clock signal CLK 2 is inputted into the second clock end of the first level cascade structure.

The driving signal output terminals of each levels of the cascade structures output respectively output the driving signals EM. 1 , EM. 2 , EM. 3 . . . EM.N to the plurality of pixel circuits of the organic light-emitting display to drive the pixel circuits.

The working principle of the circuit in a scanning cycle T will now be described with reference to the drawings. Referring to FIG. 1 , FIG. 2 and FIG. 3 , the voltage inputted from the first level end VGH is high, and the voltage inputted from the second level end VGL 1 and the third level end VGL 2 is low. The signals received by the first clock end CLK 1 and the second clock end CLK 2 of each cascade structure of the first cascade structures and the second cascade structures are the same in frequency. The signal received by the second clock end CLK 2 is low level when the signal received by the first clock end CLK 1 is high level, and the signal received by the second clock end CLK 2 is high level when the signal received by the first clock end CLK 1 is low level. This means that the signals received by the first clock end CLK 1 and the second clock end CLK 2 of each cascade structure of the first cascade structures and the second cascade structures are opposite in phase. To better understand, the terminal numerals are used to represent corresponding signals, e.g. the scanning signal IN, the output scanning signal OUT, the first clock signal CKL 1 , the second clock signal CKL 2 , and the driving signal EM. Different components are distinguished by using reference numerals, for example, the first transistor M 1 as transistor M 1 , the first capacitor C 1 as capacitor C 1 .

In the first clock cycle t1: the clock signal (CLK 1 ) received by the first clock end CLK 1 is low level, the transistors M 1 , M 4 and M 7 are ON, IN is low level (capacitor C 1 is being charged), the clock signal (CLK 2 ) received by the second clock end CLK 2 is high level, and thus transistor M 2 is ON, with the output scanning signal OUT being high level; the transistor M 7 is ON and thus the gate terminal of the transistor M 9 is low level; M 9 is ON and EM is low level.

In the second clock cycle t2: CLK 1 is high level, Transistors M 1 , M 4 and M 7 are OFF, and capacitor C 1 discharges and CLK 2 is low level. Due to the coupling of the capacitor C 1 , the gate terminal of the transistor M 2 becomes lower level, such that M 2 is ON, M 3 is ON, and M 5 is OFF, thus OUT is low level; M 2 is ON, causing M 6 and M 8 to be ON and M 9 to be OFF, and thus EM is high level.

In the third clock cycle t3: CLK 1 is low level, and CLK 2 is high level. Transistors M 1 , M 4 and M 7 are ON, IN is high level, and thus M 2 is OFF; M 4 is ON and thus M 5 is ON (capacitor C 2 being charged), and OUT is high level; the transistor M 7 is ON and thus the gate terminal of the transistor M 9 is low level ((Capacitor C 3 being charged), M 9 is ON, and EM is low level.

In the fourth clock cycle t4: CLK 1 is high level, CLK 2 is low level, and IN is high level. Transistors M 1 , M 2 , M 4 and M 7 are OFF, so M 3 and M 5 are OFF, and the capacitor C 2 discharges, and thus OUT is high level; capacitor C 3 discharges and thus M 9 is ON, and EM is low level.

Accordingly, OUT is at high level in the rest of the scanning cycle, and EM is at low level in the rest of the scanning cycle, which enables the output of the driving signal EM and the shift of one clock signal of the scanning signal IN (i.e., OUT is shifted backward by one clock signal cycle than IN).

OUT is shifted backward by one clock signal cycle than IN. In addition, because each of the cascade structures are connected in opposite parity by CLK 1 and CLK 2 , and CLK 1 and CLK 2 are also staggered by their opposition in high and low levels, i.e., the synchronized shifting of CLK 1 , CLK 2 and OUT is realized. Thus, each cascade structure can output the required driving signal (EM. 1 , EM. 2 , EM. 3 . . . EM.N).

Only two clock signals and nine transistors are used in the above scanning drive circuit, less than the traditional scan drive circuits. This can greatly enhance the reliability of the circuit, and reduce costs of design and manufacture.

Referring to FIG. 4 , in this embodiment, the first low level signal (VGL 1 ) and the second low level signal (VGL 2 ) are the same low level signal. That is, the second low level signal input terminal VGL 2 is connected to the second low level VGL 1 , which is equivalent to that the second electrode of the ninth transistor M 9 is connected directly to the second level end VGL 1 , and at this time the input voltage of the first low level signal (VGL 1 ) and the second low level signal (VGL 2 ) are the same. During the operation of the circuit, when the seventh Transistor M 7 is ON, the gate electrode of the ninth transistor M 9 is low level vgl1+Vth (vgl1 is the voltage value of the first low level signal, and Vth is the absolute value of the threshold voltage of the P-channel type Thin Film Field Effect Transistor), thus, the ninth transistor M 9 is ON, and at this time the source of the ninth transistor M 9 is low level (vgl1). This is equivalent to that the gate electrode and drain of the ninth transistor M 9 are shorted, and the ninth transistor M 9 forms a diode connection. The source output voltage of the ninth transistor M 9 is vgl1+Vth, which causes the driving signal to be higher than the required vgl1 by Vth. As a result, in order to keep the driving signal outputted by the driving signal output terminal EM as vgl1, the voltage value (vgl2) of the second low level signal is smaller than the voltage value (vgl1) of the first low level signal in other embodiments, and preferably the voltage value (vgl2) of the second low level signal is smaller by Vth than the voltage value (vgl1) of the first low level signal.

It should be noted that the second capacitor C 2 can be omitted when there is a load capacitance connected to the scanning signal output terminal OUT, but the third capacitor C 3 cannot be omitted. The function of the third capacitor C 3 is to stabilize the gate electrode voltage of the ninth transistor M 9 .

The scanning signal IN is a low level signal in the first clock cycle t of a scanning cycle T of the scanning signal IN, and is a high level signal in the rest of the time; when the scanning signal IN is a low level signal, the first clock signal CLK 1 is also a low level signal. The first clock signal CLK 1 and the second clock signal CLK 2 are the same in frequency. When the first clock signal CLK 1 is high level, the second clock signal CLK 2 is low level, and when the first clock signal CLK 1 is low level, the second clock signal CLK 2 is high level. That is, the scanning signal IN is synchronized in the first clock cycle t of a scanning cycle T to low level with the first clock signal CLK 1 .

In this embodiment, it is possible to improve the swift high level transformation of the input signal EM by only changing the connection of the third capacitor C 3 . Specifically, the third capacitor C 3 is connected between the driving signal output terminal EM and the gate terminal of the ninth transistor M 9 , as illustrated in FIG. 5 .

It should be noted that the second capacitor C 2 can be omitted when there is a load capacitance connected to the scanning signal output terminal OUT, but the third capacitor C 3 cannot be omitted. The third capacitor C 3 has a positive feedback effect.

During the operation of the circuit, when flipping from the first clock cycle t1 to the second clock cycle t2, the output signal EM is changed swiftly from the low level to the high level by the voltage jumping across the third capacitor C 3 and the positive feedback effect. When flipping from the second clock cycle t2 to the third clock cycle t3, the output signal EM is changed swiftly from the high level to the low level by the voltage jumping across the third capacitor C 3 and the positive feedback effect. In the present embodiment the third capacitor C 3 is used to provide positive feedback for stable and swift output terminal of high and low level. Thus, it is possible to enhance the load capacity and transformation ability between the high and low levels of the drive circuit, making the output terminal of high and low levels closer to the power level.

Referring to FIG. 6 , an organic light-emitting display is provided, which includes a scanning drive circuit of any of the above Embodiments One to Three, and a plurality of pixel circuits 112 of the organic light-emitting display. The scanning drive circuit includes a first scan driver 110 and a second scan driver 116 . The driving signal output terminal (EM. 1 , EM. 2 , EM. 3 . . . EM.N) of each cascade structure of the first scan driver 110 is connected a driving signal input terminal of the pixel circuit 112 of the organic light-emitting display, so as to output driving signal (EM. 1 , EM. 2 , EM. 3 . . . EM.N) to drive the pixel circuit 112 of the organic light-emitting display.

The organic light-emitting display further includes a data driver 114 and a timing controller 118 . The data driver 114 is configured to supply data signal to the pixel circuit 112 of the organic light-emitting display, the second scan driver 116 is configured to supply scanning signal to the pixel circuit 112 of the organic light-emitting display, the timing controller 118 is configured to supply timing signal and high and low level signals to the first clock end, the second clock end, the scanning signal input terminal, the first level end, the second level end and the third level end of the first scan driver 110 and the second scan driver 116 , and ELVDD is configured to supply power signal to all the pixel circuits 112 of the organic light-emitting display.

With the organic light-emitting display using the above scanning drive circuit, it is possible to greatly enhance the reliability of the circuit, and reduce costs of design and manufacture.

The above are embodiments of the invention described in detail, and should not be deemed as limitations to the scope of the present invention. It should be noted that variations and improvements will become apparent to those skilled in the art to which the present invention pertains without departing from its spirit and scope. Therefore, the scope of the present disclosure is defined by the appended claims.