Multi-level inverter

This application claims the benefit of Korean Patent Application No. 10-2015-0050143, filed on Apr. 9, 2015, which is hereby incorporated by reference in its entirety.

1. Technical Field

The present disclosure relates to a multi-level inverter, and more particularly, to a multi-level inverter capable of performing a bypass operation without adding any separate module.

2. Description of the Related Art

A medium voltage inverter is an inverter having an input power whose root mean square (RMS) value is over 600V for a line-to-line voltage. The rating power capacity of the medium voltage inverter ranges from a few hundreds of kilowatts to a few tens of megawatts. Various medium voltage inverters are widely used in application fields including fans, pumps, and compressors. Among these medium voltage inverters, a cascaded multi-level inverter is frequently used, which generates an output phase voltage having three or more levels. The magnitude and number of levels of the output phase voltage generated from the cascaded multi-level inverter are determined according to the number of unit cells constituting the cascaded multi-level inverter.

Each phase of the cascaded multi-level inverter is formed by coupling a plurality of unit cells in series, and the three-phase output voltage of the inverter is determined by adding output voltages of unit cells constituting each phase of the inverter. If one of a plurality of unit cells included in a multi-level inverter is abnormal, the inverter can perform a bypass operation performed in a state in which an output is reduced. In the bypass operation, the abnormal unit cell is not used by short-circuiting an output terminal of the unit cell through a bypass switch, and only the other normal unit cells are used, thereby performing a normal operation of the inverter.

However, in an inverter having no bypass switch for controlling a bypass operation for each unit cell, a DC-link voltage increases due to rectification of an inverse-parallel diode of a power switch used in an abnormal unit cell. Therefore, the DC-link voltage exceeds the rating operating range of a DC-link capacitor. As a result, unit cells are damaged, and all operations of the inverter cannot be performed.

It is an aspect of some embodiments to provide a multi-level inverter capable of performing a bypass operation without adding any bypass switch for controlling a bypass operation for each unit cell.

It is an aspect of some embodiments to provide a multi-level inverter capable of performing an individual bypass operation according to the kind of an abnormal switch among a plurality of switches included in a unit cell.

The present disclosure is not limited to the above aspect and other aspects of the present disclosure will be clearly understood by those skilled in the art from the following description.

In accordance with one aspect of some embodiments, a multi-level inverter includes a first capacitor and a second capacitor coupled in series to each other, a plurality switches for generating a multi-level output voltage by using a voltage charged in the first capacitor and the second capacitor and a plurality of diodes respectively coupled in parallel to the plurality of switches, a first output terminal and a second output terminal for outputting the output voltage, and a controller for switching a state of each of the plurality of switches to an on or off state according to one of predetermined bypass modes, thereby interrupting the output of the output voltage through the first output terminal and the second output terminal.

FIG. 1 is a configuration diagram of a cascaded multi-level inverter.

FIG. 2 is a configuration diagram of a unit cell according to a conventional art.

FIG. 3 shows waveforms of control signals for controlling a plurality of diodes included in a unit cell to form a multi-level output voltage and magnitudes of the output voltage corresponding to the waveforms.

FIG. 4 is a configuration diagram of a unit cell according to an embodiment.

FIG. 5 shows a bypass operation of the unit cell in a first bypass mode according to an embodiment.

FIG. 6 shows a bypass operation of the unit cell in a second bypass mode according to an embodiment.

FIG. 7 shows a bypass operation of the unit cell in a third bypass mode according to an embodiment.

FIG. 8 is a flowchart illustrating a process in which a controller controls the unit cell according to an embodiment.

Hereinafter, disclosed embodiments will be described in detail with reference to the accompanying drawings. It should be understood that the present disclosure is not limited to the following embodiments, and that the embodiments are provided for illustrative purposes only. The scope of the disclosure should be defined only by the accompanying claims and equivalents thereof. In the drawings, like reference numerals designate identical or corresponding parts throughout the several views.

FIG. 1 is a configuration diagram of a cascaded multi-level inverter.

The cascaded multi-level inverter 101 shown in FIG. 1 is configured with unit cells a 1 , b 1 , c 1 , a 2 , b 2 , and c 2 in two stages, but the number of unit cells may vary depending on system requirements. Each of the unit cells a 1 , b 1 , c 1 , a 2 , b 2 , and c 2 has an independent single-phase inverter structure. As shown in FIG. 1 , the unit cells a 1 , b 1 , c 1 , a 2 , b 2 , and c 2 are coupled in series, thereby obtaining a high voltage.

The inverter 101 is supplied with, for example, a three-phase AC power whose root mean square (RMS) value is over 600V for a line-to-line voltage through a three-phase power source 105 . The three-phase AC power supplied by the three-phase power source 105 is input to a phase shift transformer 103 . The transformer 103 isolates the input three-phase AC power, and transforms the phase and magnitude of a voltage of the three-phase AC power to fit requirements of the unit cells a 1 , b 1 , c 1 , a 2 , b 2 , and c 2 . The transformer 103 improves the total harmonic distortion (THD) of the input three-phase AC power through phase shift. The transformer 103 includes a primary winding 10 and secondary windings 11 , 12 , 13 , 14 , 15 , and 16 having different phases.

The unit cells a 1 , b 1 , c 1 , a 2 , b 2 , and c 2 output voltages by using voltages output from the transformer 103 , respectively. The inverter 101 adds output voltages of unit cells corresponding to each phase among the unit cells a 1 , b 1 , c 1 , a 2 , b 2 , and c 2 , thereby outputting a final output voltage to be input to a three-phase machine 102 . Here, the three-phase machine 102 may be a high-voltage three-phase machine such as an induction machine or a synchronous machine.

The inverter 101 configured as shown in FIG. 1 outputs an output voltage of three phases, i.e., phases a, b, and c. For example, an output voltage of the phase a is a voltage obtained by adding output voltages of the unit cells a 1 and a 2 coupled in series. An output voltage of the phase b is a voltage obtained by adding output voltages of the unit cells b 1 and b 2 coupled in series. An output voltage of the phase c is a voltage obtained by adding output voltages of the unit cells c 1 and c 2 coupled in series.

The output voltages of the three phases, output from the inverter 101 , have the same magnitude but have a phase difference of 120 degrees. Thus, the number of unit cells constituting the inverter 101 varies, and the unit cells are differently controlled, so that it is possible to improve THDs, and voltage variations dv/dt of output voltages applied to the machine 102 .

FIG. 2 is a configuration diagram of a unit cell among the unit cells a 1 , b 1 , c 1 , a 2 , b 2 , and c 2 included in the inverter 101 shown in FIG. 1 according to a conventional art.

Referring to FIG. 2 , the unit cell includes a rectifier 201 , a smoother 202 , and an output voltage generator 203 .

The rectifier 201 is configured with six diodes as shown in FIG. 2 . The rectifier 201 receives a three-phase power output from the transformer 103 shown in FIG. 1 , and rectifies the input three-phase power to a DC power.

The DC power rectified by the rectifier 201 is transmitted to two capacitors, i.e., a first capacitor C 1 and a second capacitor C 2 coupled in series to each other. The first capacitor C 1 and the second capacitor C 2 have the same capacitance. Accordingly, the first capacitor C 1 and the second capacitor C 2 are charged with a voltage V dc having the same magnitude.

The output voltage generator 203 includes a plurality of diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , and D 8 . The diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , and D 8 constituting the output voltage generator 203 are coupled in parallel to corresponding switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 , respectively. A controller 205 outputs a control signal to switch the state of each of the switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 to an on or off state. Here, that the state of the switch is switched to the on state means that the switch is closed, and that the state of the switch is switched to the off state means that the switch is opened. The controller 205 controls an on or off operation of each of the switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 through the control signal, thereby generating a multi-level output voltage. The controller 205 outputs the generated output voltage through a first output terminal U and a second output terminal V.

An output voltage V UV of the unit cell, output through the first and second output terminals U and V of FIG. 2 is determined, as shown in Equation 1, by a pole voltage V U of the first output terminal U and a pole voltage V V of the second output terminal V.

V UV =V U −V V   Equation 1

Here, the pole voltage V U of the first output terminal U and the pole voltage V V of the second output terminal V are determined, as shown in Table 1, by complimentary on/off states of the switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 , which are switched by the controller 205 .

FIG. 3 shows waveforms of control signals for controlling a plurality of diodes included in a unit cell to form a multi-level output voltage and magnitudes of the output voltage corresponding to the waveforms. The waveforms of the control signals shown in FIG. 3 are obtained by using an in-phase disposition (IPD) modulation technique.

Referring to FIG. 3 , instruction voltages V m1 and V m2 with respect to both poles of the unit cell have the same frequency and magnitude but have a phase difference of 180 degrees. Also, carrier waves V cr1 and V cr2 with respect to both the poles of the unit cell having the same frequency and magnitude but have different offset values.

When the instruction voltages and the carrier waves are generated as shown in FIG. 3 , the controller 205 generates control signals for the switches S 1 and S 5 and the switches S 3 and S 7 at intersection points of the carrier wave V cr1 and the instruction voltages V m1 and V m2 , and generates control signals for the switches S 2 and S 6 and the switches S 4 and S 8 at intersection points of the carrier wave V cr2 and the instruction voltages V m1 and V m2 .

According to the generation of the control signals, the unit cell of FIG. 2 can generate an output voltage V uv having five levels 2V dc , V dc , 0, −V dc , and −2V dc as shown at the bottom end of FIG. 3 by using a pole voltage having three levels V dc , 0, and −V dc as shown in Table 1.

Meanwhile, when the output of a normal voltage from the unit cell of FIG. 2 is impossible due to abnormality of the unit cell, the output of a voltage from the unit cell was conventionally interrupted through a bypass switch 204 shown in FIG. 2 . That is, if the unit cell is abnormal, the controller 205 applies a bypass signal to the bypass switch 204 . Accordingly, the bypass switch 204 short-circuits the first output terminal U and the second output terminal V, so that the output voltage of the unit cell becomes 0V. The output of a voltage from the unit cell is interrupted by the above-described operation of the bypass switch 204 . The switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S respectively corresponding to the diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , and D 8 of the bypassed unit cell are turned off so as to prevent an arm short circuit.

The inverter according to the conventional art is to be provided with a bypass switch for each unit cell so as to interrupt the output of a voltage from a unit cell when the unit cell is abnormal. However, when the bypass switch is provided for each unit cell, the unit cell increases due to the disposition of the bypass switches configured with elements such as magnetic conductors (MC). Therefore, as the number of bypass switches disposed in the unit cell increases, the manufacturing cost of the inverter increases.

Some embodiments are conceived to solve this problem, and relates to a multi-level inverter capable of performing a bypass operation when a unit cell is abnormal, without using the bypass switch shown in FIG. 2 .

FIG. 4 is a configuration diagram of a unit cell according to an embodiment. For reference, the unit cell according to the embodiment may include the rectifier 201 shown in FIG. 2 . However, for convenience of illustration, the configuration of the rectifier is omitted in FIG. 4 .

Referring to FIG. 4 , the unit cell according to the embodiment includes a first capacitor C 1 , a second capacitor C 2 , first to eighth diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , and D 8 , first to eighth switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 , and a controller 401 .

In FIG. 4 , the first switch S 1 and the second switch S 2 are disposed between a first output terminal U and a connection point 41 of the first capacitor C 1 and the second capacitor C 2 . The first switch S 1 and the second switch S 2 are coupled in series to each other.

The third switch S 3 and the fourth switch S 4 are disposed between a second output terminal V and a connection point 42 of the first capacitor C 1 and the second capacitor C 2 . The third switch S 3 and the fourth switch S 4 are coupled in series to each other.

The fifth switch S 5 and the sixth switch S 6 are coupled in parallel to the first capacitor C 1 and the second capacitor C 2 . The fifth switch S 5 and the sixth switch S 6 are coupled in series to each other.

The seventh switch S 7 and the eighth switch S 8 are coupled in parallel to the first capacitor C 1 and the second capacitor C 2 . The seventh switch S 7 and the eighth switch S 8 are coupled in series to each other.

As shown in FIG. 4 , the fifth switch S 5 and the seventh switch S 7 are coupled to a positive (+) electrode of the DC-link voltage capacitor (first capacitor C 1 ), and the sixth switch S 6 and the eighth switch S 8 are coupled to a negative (−) electrode of the DC-link voltage capacitor (second capacitor C 2 ).

In the unit cell shown in FIG. 4 , functions of the first capacitor C 1 , the second capacitor C 2 , the first to eighth diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , and D 8 , and the first to eighth switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 and a process of generating an output voltage corresponding to a control signal of the controller 401 are the same as those in the conventional unit cell. However, unlike the conventional unit cell shown in FIG. 2 , the unit cell according to the embodiment is provided with no bypass switch as shown in FIG. 4 .

In the embodiment, the controller 401 switches, to on and off states, states of the first to eighth switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 respectively coupled in parallel to the first to eighth diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , and D 8 , according to one of predetermined bypass modes, so that it is possible to interrupt the output of an output voltage through the first output terminal U and the second output terminal V.

Hereinafter, first to third bypass modes according to an embodiment will be described with reference to FIGS. 5 to 7 .

FIG. 5 shows a bypass operation of the unit cell in a first bypass mode according to an embodiment.

In the first bypass mode according to the embodiment, the controller 401 , as shown in FIG. 5 , switches, to the on state, the states of only the fifth switch S 5 corresponding to the fifth diode D 5 and the seventh switch S 7 corresponding to the seventh diode D 7 , and switches, to the off state, the states of the switches S 1 to S 4 , S 6 , and S 8 respectively corresponding to the other diodes D 1 to D 4 , D 6 , and D 8 . Accordingly, current flows in a direction indicated by an arrow (solid line) when the direction of the current is a positive (+) direction, and flows in a direction indicated by an arrow (dotted line) when the direction of the current is a negative (−) direction, thereby interrupting the output of a voltage from the unit cell. The first bypass mode may be performed when the fifth diode D 5 , the seventh diode D 7 , the fifth switch S 5 , and the seventh switch S 7 are normally operated.

FIG. 6 shows a bypass operation of the unit cell in a second bypass mode according to an embodiment.

In the second bypass mode according to the embodiment, the controller 401 , as shown in FIG. 6 , switches, to the on state, the states of only the first switch S 1 , the second switch S 2 , the third switch S 3 , and the fourth switch S 4 , respectively corresponding to the first diode D 1 , the second diode D 2 , the third diode D 3 , and the fourth diode D 4 , and switches, to the off state, the states of the switches S 5 to S 8 respectively corresponding to the other diodes D 5 to D 8 . Accordingly, current flows in a direction indicated by an arrow (solid line) when the direction of the current is a positive (+) direction, and flows in a direction indicated by an arrow (dotted line) when the direction of the current is a negative (−) direction, thereby interrupting the output of a voltage from the unit cell. The second bypass mode may be performed when the first diode D 1 , the second diode D 2 , the third diode D 3 , the fourth diode D 4 , the first switch S 1 , the second switch S 2 , the third switch S 3 , and the fourth switch S 4 are normally operated.

FIG. 7 shows a bypass operation of the unit cell in a third bypass mode according to an embodiment.

In the third bypass mode according to the embodiment, the controller 401 , as shown in FIG. 6 , switches, to the on state, the states of only the sixth switch S 6 corresponding to the sixth diode D 6 and the eighth switch S 8 corresponding to the eighth diode D 8 , and switches, to the off state, the states of the switches S 1 to S 5 and S 7 respectively corresponding to the other diodes D 1 to D 5 and D 7 . Accordingly, current flows in a direction indicated by an arrow (solid line) when the direction of the current is a positive (+) direction, and flows in a direction indicated by an arrow (dotted line) when the direction of the current is a negative (−) direction, thereby interrupting the output of a voltage from the unit cell. The third bypass mode may be performed when the sixth diode D 6 , the eighth diode D 8 , the sixth switch S 6 , and the eighth switch S 8 are normally operated.

In the embodiment, the controller 401 may detect whether at least one of the first to eighth diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , and D 8 and the first to eighth switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 is abnormal. If it is detected that at least one of the first to eighth diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , and D 8 , and the first to eighth switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 is abnormal, the controller 401 determines a bypass mode to be applied to the unit cell according to the kind of an abnormal diode or switch. Then, the controller 401 switches states of predetermined switches to the on state and switches states of the other switches to the off state according to the determined bypass mode, so that the magnitude of an output voltage through the first output terminal U and the second output terminal V becomes 0V.

In the embodiment, when at least one of the first diode D 1 , the second diode D 2 , the third diode D 3 , the fourth diode D 4 , the first switch S 1 , the second switch S 2 , the third switch S 3 , and the fourth switch S 4 is abnormal, the controller 401 switches states of predetermined switches to the on state according to the first bypass mode or the third bypass mode, thereby interrupting the output of a voltage through the first output terminal U and the second output terminal V.

In the embodiment, when at least one of the fifth diode D 5 , the seventh diode D 7 , the fifth switch S 5 , and the seventh switch S 7 is abnormal, the controller 401 switches states of predetermined switches to the on state according to the second bypass mode or the third bypass mode, thereby interrupting the output of a voltage through the first output terminal U and the second output terminal V.

In the embodiment, when at least one of the sixth diode D 6 , the eighth diode D 8 , the sixth switch S 6 , and the eighth switch S 8 is abnormal, the controller 401 switches states of predetermined switches to the on state according to the first bypass mode or the second bypass mode, thereby interrupting the output of a voltage through the first output terminal U and the second output terminal V.

FIG. 8 is a flowchart illustrating a process in which the controller controls the unit cell according to an embodiment.

Referring to FIG. 8 , the controller 401 first detects whether a plurality of diodes or a plurality of switches corresponding to the respective diodes, included in the unit cell of the inverter, are abnormal ( 802 ). If it is determined that at least one of the plurality of diode and the plurality of switches corresponding to the respective diodes is abnormal, the controller 401 determines a bypass mode to be applied to the unit cell according to the kind of an abnormal diode or switch ( 804 ).

When at least one of the other diodes D 1 to D 4 , D 6 , and D 8 except the fifth diode D 5 and the seventh diode D 7 and the other switches S 1 to S 4 , S 6 , and S 8 except the fifth switch S 5 and the seventh switch S 7 is abnormal, the controller 401 interrupts the output of a voltage from the unit cell according to the first bypass mode ( 806 ).

When at least one of the other diodes D 5 to D 8 except the first diode D 1 , the second diode D 2 , the third diode D 3 , and the fourth diode D 4 and the other switches S 5 to S 8 except the first switch S 1 , the second switch S 2 , the third switch S 3 , and the fourth switch S 4 is abnormal, the controller 401 interrupts the output of a voltage from the unit cell according to the second bypass mode ( 808 ).

When at least one of the other diodes D 1 to D 5 and D 7 except the sixth diode D 6 and the eighth diode D 8 and the other switches S 1 to S 5 and S 7 except the sixth switch S 6 and the eighth switch S 8 is abnormal, the controller 401 interrupts the output of a voltage from the unit cell according to the third bypass mode ( 810 ).

Accordingly, in some embodiments, when one of switches or diodes included in the multi-level inverter is abnormal, the multi-level inverter performs a bypass operation according to one of the first to third bypass modes, thereby preventing the damage of a unit cell.

As described above, the multi-level inverter according to some embodiments can perform a bypass operation without adding any bypass switch for controlling a bypass operation for each unit cell.

Also, the multi-level inverter according to some embodiments can perform an individual bypass operation according to the kind of an abnormal switch among a plurality of switches included in a unit cell.

While certain embodiments have been described, it will be understood by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the disclosure defined by the appended claims.