Display device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-064514, filed Mar. 26, 2015, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a display device.

In a liquid crystal display device in a mode of electrically controlled birefringence (ECB) or the like, liquid crystal molecules are undesirably influenced by a lateral electric field due to a relationship between the polarities of adjacent pixels and the rubbing direction of an alignment film, and disclination of the alignment of the liquid crystal molecules occurs in an area in part. The disclination needs to be eliminated since it causes various display failures such as image lag, blurring, reduction in a contrast ratio and the like when an image is displayed.

Use of a light-shielding film or the like to block the light on a portion where the disclination occurs is the most dependable method, but a problem arises in that an area of an opening portion which contributes to the display is reduced as the light-shielding film is extended. Rubbing a pixel polarity in a direction in which no disclination occurs, applying a line-inversion drive scheme, and other methods for dealing with this problem are well known.

Recently, a display device has required a number of signal lines in accordance with the increase in pixels. For this reason, the display device has a problem that the energy consumption is increased.

FIG. 1 is a perspective view schematically showing a configuration of a liquid crystal display device DSP.

FIG. 2 is a schematic view showing a cross-section of the liquid crystal display panel DSP.

FIG. 3 is a diagram schematically showing an example of a pixel layout in the display area, and a configuration for writing video signals to respective pixels.

FIG. 4 is a table for explanation of an example of a method of writing the video signals to the liquid crystal display panel PNL of the pixel layout shown in FIG. 3 .

FIG. 5 is an illustration showing the polarities of the video signals output to each signal line by the writing method explained with reference to FIG. 4 .

FIG. 6 is an illustration showing an example of timing of writing the video signals to the respective sub-pixels of the pixel layout shown in FIG. 3 .

FIG. 7 is an illustration schematically showing a relationship between another pixel layout in the display area, and the polarities of the video signals written to the respective pixels.

FIG. 8 is a diagram schematically showing an example of another pixel layout in the display area, and a configuration for writing the video signals to the respective pixels.

FIG. 9 is a table for explanation of an example of a method of writing the video signals to the liquid crystal display panel PNL of the pixel layout shown in FIG. 8 .

FIG. 10 is an illustration showing a summary of the polarities of the video signals output to each signal line by the writing method explained with reference to FIG. 9 .

FIG. 11 is an illustration showing an example of timing of writing the video signals to the respective sub-pixels of the pixel layout shown in FIG. 8 .

FIG. 12 is an illustration schematically showing a relationship between yet another pixel layout in the display area, and the polarities of the video signals written to the respective pixels.

FIG. 13 is an illustration schematically showing a relationship between yet another pixel layout in the display area, and the polarities of the video signals written to the respective pixels.

FIG. 14 is an illustration schematically showing a relationship between yet another pixel layout in the display area, and polarities of video signals written to the respective pixels.

FIG. 15 is an illustration showing an example of timing of writing the video signals to the respective sub-pixels of the pixel layout shown in FIG. 14 .

FIG. 16 is an illustration for explanation of a relationship between the alignment direction AP 1 of the first alignment film AL 1 and the alignment direction AP 2 of the second alignment film AL 2 .

FIG. 17 shows experiment results and, more specifically, (A) shows a measurement result of the reflectivity (%) to the angle of rotation θ and (B) shows a measurement result of the contrast ratio to the angle of rotation θ.

FIG. 18 is a perspective view schematically showing another configuration of the liquid crystal display device DSP.

In general, according to one embodiment, a display device, includes: a first main pixel including a first sub-pixel, a second sub-pixel arranged in a first direction of the first sub-pixel, and a third sub-pixel arranged in a second direction of the first sub-pixel; a second main pixel including a fourth sub-pixel arranged in the first direction of the third sub-pixel, a fifth sub-pixel arranged in the second direction of the third sub-pixel, and a sixth sub-pixel arranged in the first direction of the fifth sub-pixel; a scanning line group including a plurality of scanning lines; a signal line group including a plurality of signal lines; and a display driver which produces video signals to be written to the respective sub-pixels of the first and second main pixels and supplies the video signals to the respective sub-pixels via the signal lines, any one of the first to third sub-pixels and any one of the fourth to sixth sub-pixels sharing one of the signal lines.

Embodiments will be described hereinafter with reference to the accompanying drawings. The disclosure is merely an example, and proper changes within the spirit of the invention, which are easily conceivable by a skilled person, are included in the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are schematically illustrated in the drawings, compared to the actual modes. However, the schematic illustration is merely exemplary, and adds no restrictions to the interpretation of the invention. In each drawing, like or similar elements disposed sequentially may not be denoted by reference numbers or symbols. Furthermore, in the specification and drawings, constituent elements having the same or similar functions as those described in connection with preceding drawings are denoted by like reference numerals and duplicated detailed explanations may be arbitrarily omitted.

In the embodiments, a liquid crystal display device is described as an example of the display device. The liquid crystal display device can be used in, for example, various types of equipment such as smartphones, tablet terminals, mobile telephone terminals, personal computers, TV receivers, in-car equipment and game consoles. The major configuration explained in the present embodiment can also be applied to a self-luminous display device comprising an organic electroluminescent display element, and the like, an electronic paper display device comprising a cataphoretic element, and the like, a display device employing micro-electromechanical systems (MEMS), or a display device employing electrochromism.

FIG. 1 is a perspective view schematically showing a configuration of a liquid crystal display device DSP.

The liquid crystal display device DSP comprises an active-matrix liquid crystal display panel PNL, a driving IC chip IC which drives the liquid crystal display panel PNL, a control module CM, a flexible printed-circuit board FPC and the like.

The liquid crystal display panel PNL includes an array substrate (first substrate) AR and a counter-substrate (second substrate) CT disposed to be opposed to the array substrate AR. The liquid crystal display panel PNL includes a display area DA in which an image is displayed and a frame-shaped non-display area NDA surrounding the display area DA. The liquid crystal display panel PNL includes a plurality of main pixels (or unit pixels) PX arrayed in a matrix in the display area DA. The driving IC chip IC is mounted on the array substrate AR. The flexible printed-circuit board FPC connects the liquid crystal display panel PNL with the control module CM.

For example, the liquid crystal display panel PNL is a reflective display panel having a reflective display function of displaying an image by selectively reflecting light incident from the display surface side, such as external light and auxiliary light on each of the main pixels PX. In the reflective liquid crystal display panel PNL, a front light unit may be disposed as an auxiliary light source, on a side opposed to the counter-substrate CT. The liquid crystal display panel PNL may be a transmissive display panel having a transmissive display function of displaying an image by selectively transmitting the light from a backlight unit disposed on a back surface side of the array substrate AR by each main pixel PX or a transreflective display panel having a transmissive display function and a reflective display function.

For example, the main pixel PX which is a minimum unit constituting a color image includes a sub-pixel PR which exhibits a red color, a sub-pixel PG which exhibits a green color, and a sub-pixel PB which exhibits a blue color, as explained later. The main pixel PX may further include sub-pixels of the other colors (for example, yellow, pale blue, pale red, substantially transparent, white and the like).

FIG. 2 is a schematic view showing a cross-section of the liquid crystal display panel DSP. The liquid crystal display device DSP comprising the reflective liquid crystal display panel PNL, in which one main pixel PX includes the sub-pixels PR, PG and PB, will be explained here.

The liquid crystal display device DSP comprises the array substrate AR, the counter-substrate CT, a liquid crystal layer LC, and an optical element OD.

The array substrate AR includes a first insulating substrate 10 , switching elements SW 1 to SW 3 , an interlayer insulating film 11 , pixel electrodes (reflecting electrodes) PE 1 to PE 3 , a first alignment film AL 1 and the like. The switching elements SW 1 to SW 3 are formed on a side of the first insulating substrate 10 , which is opposed to the counter-substrate CT. The switching element SW 1 is disposed on the sub-pixel PR, the switching element SW 2 is disposed on the sub-pixel PG, and the switching element SW 3 is disposed on the sub-pixel PB. The interlayer insulating film 11 covers the switching elements SW 1 to SW 3 and the first insulating substrate 11 . The pixel electrodes PE 1 to PE 3 are formed on a side of the interlayer insulating film 11 , which is opposed to the counter-substrate CT. Each of the pixel electrodes PE 1 to PE 3 includes a reflective layer formed of, for example, a metal material such as aluminum or silver, which has a light reflection property. The pixel electrodes PE 1 to PE 3 or reflective layers have substantially flat surfaces (specular surfaces). The pixel electrode PE 1 is disposed in the sub-pixel PR and electrically connected with the switching element SW 1 . The pixel electrode PE 2 is disposed in the sub-pixel PG and electrically connected with the switching element SW 2 . The pixel electrode PE 3 is disposed in the sub-pixel PB and electrically connected with the switching element SW 3 . The first alignment film AL 1 covers the pixel electrodes PE 1 to PE 3 and the interlayer insulating film 11 .

The counter-substrate CT includes a second insulating substrate 20 , a light-shielding layer BM, color filters CFR, CFG and CFB, an overcoat layer OC, a common electrode CE, a second alignment film AL 2 , and the like. The light-shielding layer BM is formed on a side of the second insulating substrate 20 , which is opposed to the array substrate AR. The color filters CFR, CFG and CFB are formed on a side of the second insulating substrate 20 , which is opposed to the array substrate AR, and partially overlap the light-shielding layer BM. The color filter CFR is a red color filter disposed in the sub-pixel PR and opposed to the pixel electrode PE 1 . The color filter CFG is a green color filter disposed in the sub-pixel PG and opposed to the pixel electrode PE 2 . The color filter CFB is a blue color filter disposed in the sub-pixel PB and opposed to the pixel electrode PE 3 . If the main pixel PX further includes a sub-pixel of the other color, a color filter of the corresponding color is disposed in the sub-pixel. For example, the main pixel PX may further include a color filter of yellow, pale blue or pale red or a substantially transparent or white color filter as a color filter of the other color different from red, green and blue. The color filters CF are disposed to correspond to the sub-pixels which exhibit the respective colors. The overcoat layer OC covers the color filters CF. The common electrode CE is formed on a side of the overcoat layer OC, which is opposed to the array substrate AR. The common electrode CE is disposed over the entire area of the main pixel PX and opposed to the pixel electrodes PE 1 to PE 3 . The common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second alignment film AL 2 covers the common electrode CE.

The array substrate AR and the counter-substrate CT are adhered to each other such that the first alignment film AL 1 and the second alignment film AL 2 are opposed to each other. The liquid crystal layer LC is held between the array substrate AR and the counter-substrate CT, and includes liquid crystal molecules LM located between the first alignment film AL 1 and the second alignment film AL 2 .

The optical element OD is disposed on a side opposite to a surface of the counter-substrate CT, which is in contact with the liquid crystal layer LC. The optical element OD includes, for example, a forward-scattering film FS, a retardation film RT, a polarizer PL and the like. The forward-scattering film FS is adhered to, for example, the second insulating substrate 20 . The forward-scattering film FS has a function of transmitting light incident from a specific direction (i.e., a light source LS side in the figure) and scattering light incident from the other specific direction, as shown in the figure. It is desirable to stack a plurality of forward-scattering films FS for the purpose of extending the range of diffusion, preventing rainbow hues and the like. The retardation film RT is stacked on the forward-scattering film FS. The retardation film RT is a quarter-wave plate. For example, the retardation film RT is constituted by stacking a quarter-wave plate and a half-wave plate so as to reduce a wavelength dependency and obtain a desired phase difference within a wavelength range used for color display. The polarizer PL is stacked on the retardation film RT. The forward-scattering film FS may not only be located at the position shown in the figure, but may also be stacked on the polarizer PL.

FIG. 3 is a diagram schematically showing an example of a pixel layout in the display area, and a configuration for writing video signals to respective pixels.

A part of the display area DA shown in the figure includes a scanning line group including a plurality of scanning lines G 1 to G 6 , a signal line group including a plurality of signal lines S 1 to S 6 , and a plurality of main pixels PX. The scanning lines G 1 to G 6 extend substantially along a second direction D 2 so as to be arranged in a first direction D 1 . The signal lines S 1 to S 6 extend substantially along the first direction D 1 so as to be arranged in the second direction D 2 . The first direction D 1 and the second direction D 2 are perpendicular to each other.

In the pixel layout shown in the figure, some main pixels in the display area DA, i.e., main pixels PX 11 to PX 13 and PX 21 to PX 23 are illustrated. The main pixels PX 11 to PX 13 , PX 21 to PX 23 and PX 31 to PX 33 are arranged in the first direction D 1 . The main pixels PX 11 , PX 21 and PX 31 are arranged in the second direction D 2 . Similarly, the main pixels PX 12 , PX 22 and PX 32 are arranged in the second direction D 2 , and the main pixels PX 13 , PX 23 and PX 33 are also arranged in the second direction D 2 .

When the main pixel PX 11 is noticed, the main pixel PX 11 includes a sub-pixel (first sub-pixel) PB 11 , a sub-pixel (second sub-pixel) PG 11 and a sub-pixel (third sub-pixel) PR 11 . The sub-pixel PG 11 and the sub-pixel PB 11 are arranged in the first direction D 1 . The sub-pixel PR 11 and the sub-pixel PB 11 are arranged in the second direction D 2 . The sub-pixel PB 11 comprises the switching element SW 1 and the pixel electrode PE 1 . The switching element SW 1 is electrically connected with the scanning line G 1 and the signal line S 1 . The pixel electrode PE 1 is electrically connected with the switching element SW 1 . The sub-pixel PG 11 comprises the switching element SW 2 and the pixel electrode PE 2 . The switching element SW 2 is electrically connected with the scanning line G 2 and the signal line S 2 . The pixel electrode PE 2 is electrically connected with the switching element SW 2 . The sub-pixel PR 11 comprises the switching element SW 3 and the pixel electrode PE 3 . The switching element SW 3 is electrically connected with the scanning line G 2 and the signal line S 3 . The pixel electrode PE 3 is electrically connected with the switching element SW 3 .

Each of the other main pixels also includes three sub-pixels. In the figure, PRn, PGn and PBn indicate a red sub-pixel, a green sub-pixel and a blue sub-pixel, respectively, in each main pixel PXn, where n indicates a positive integer. In the pixel layout shown in the figure, each of the sub-pixels is in a laterally elongated shape extending in the second direction D 2 .

When the main pixel PX 21 is noticed, the main pixel PX 21 includes a sub-pixel (fourth sub-pixel) PB 21 , a sub-pixel (fifth sub-pixel) PG 21 and a sub-pixel (sixth sub-pixel) PR 21 . The sub-pixel PB 21 and the sub-pixel PR 11 are arranged in the first direction D 1 . The sub-pixel PG 21 and the sub-pixel PR 11 are arranged in the second direction D 2 . The sub-pixel PR 21 and the sub-pixel PG 21 are arranged in the first direction D 1 . The switching element of the sub-pixel PB 21 is electrically connected with the scanning line G 3 , the signal line S 2 and the pixel electrode. Hereinafter, this connection state will simply be explained similarly to a phrase “the sub-pixel PB 21 is electrically connected with the scanning line G 3 and the signal line S 2 ”. The sub-pixel PG 21 is electrically connected with the scanning line G 1 and the signal line S 3 . The sub-pixel PR 21 is electrically connected with the scanning line G 2 and the signal line S 4 .

When the main pixel PX 31 is noticed, the main pixel PX 31 includes sub-pixels PB 31 , PG 31 and PR 31 . The sub-pixel PG 31 and the sub-pixel PB 31 are arranged in the first direction D 1 . The sub-pixel PR 31 and the sub-pixel PB 31 are arranged in the second direction D 2 . The sub-pixel PB 31 is electrically connected with the scanning line G 2 and the signal line S 5 . The sub-pixel PG 31 is electrically connected with the scanning line G 3 and the signal line S 4 . The sub-pixel PR 31 is electrically connected with the scanning line G 1 and the signal line S 5 .

The main pixels PX 12 , PX 22 and PX 32 arranged in the second direction D 2 are constituted similarly to the main pixels PX 11 , PX 21 and PX 31 . Similarly to this, the main pixels PX 13 , PX 23 and PX 33 are constituted similarly to the main pixels PX 11 , PX 21 and PX 31 .

A display driver DD supplies various signals to display images to the display area DA of this pixel layout. The display driver DD comprises a signal processor SP, a gate driver GD, a source driver SD and the like. The signal processor SP processes input signals from the outside and controls the gate driver GD, the source driver SD and the like. In addition, the signal processor SP produces a video signal which is to be written to each sub-pixel. The scanning lines G 1 to G 6 are connected to the gate driver GD. The gate driver GD sequentially outputs control signals to the scanning lines G 1 to G 6 , under control of the signal processor SP. The signal lines S 1 to S 6 are connected to the source driver SD. The source driver SD comprises output terminals Video ( 1 ) to Video ( 3 ) which output the video signals produced by the signal processor SP to the respective signal lines S 1 to S 6 .

More specifically, the line buffer LB is built in the source driver SD. In the source driver SD, the output terminals Video ( 1 ) to Video ( 3 ) are electrically connected with the line buffer LB and the signal processor SP. In addition, the output terminal Video ( 1 ) is electrically connected with the signal lines S 1 and S 3 , the output terminal Video ( 2 ) is electrically connected with the signal lines S 2 and S 4 , and the output terminal Video ( 3 ) is electrically connected with the signal line S 5 and a signal line S 7 (not shown). A switch SWA which is switched to be on (conductive state) or off (nonconductive state) in the same period is interposed between the signal line S 1 and the output terminal Video ( 1 ), between the signal line S 2 and the output terminal Video ( 2 ), and between the signal line S 5 and the output terminal Video ( 3 ). A switch SWB which is switched to be on (conductive state) or off (nonconductive state) in the same period is interposed between the signal line S 3 and the output terminal Video ( 1 ), between the signal line S 4 and the output terminal Video ( 2 ), and between the signal line S 7 and the output terminal Video ( 3 ). The switches SWA and SWB are controlled to be on and off by, for example, the signal processor SP.

The signal processor SP outputs some of the video signals to the output terminals Video ( 1 ) to Video ( 3 ) while outputting the other video signals to the line buffer LB. The line buffer LB temporarily stores the video signals input from the signal processor SP. For example, the signal processor SP produces video signals for one pixel line and outputs the video signals for one third pixel line to the output terminals Video ( 1 ) to Video ( 3 ) while outputting the video signals for remaining two third pixel lines to the line buffer LB and temporarily storing the video signals in the line buffer LB. For this reason, the line buffer LB may have a storage capacity to store video signals for at least two third pixel lines. Outputting the video signals will be explained later.

In this configuration, the polarities of the video signals output to each of the signal lines S 1 to S 6 , in one frame period, are not varied, and the polarities of the video signals output to adjacent signal lines are opposite. In the example illustrated, the polarities of the video signals output to the odd-numbered signal lines S 1 , S 3 and S 5 are positive (+) and the polarities of the video signals output to the even-numbered signal lines S 2 , S 4 and S 6 are negative (−), in a certain frame period. In one frame period subsequent to the frame period shown in the figure, polarities of the video signals output to the odd-numbered signal lines are negative (−), and polarities of the video signals output to the even-numbered signal lines are positive (+). In other words, the column-inversion drive scheme is applied to the present configuration.

In contrast, the polarities of the video signals written to the sub-pixels of the respective pixel lines are the same as each other, and the polarities of the video signals of the adjacent pixel lines are opposite to each other, in the frame period shown in the figure. In the example illustrated, the polarities of the video signals written to the sub-pixels of the odd-numbered pixel lines, for example, the sub-pixels PB 11 , PR 11 , PG 21 , PB 31 and PR 31 are positive (+), and the polarities of the video signals written to the sub-pixels of the even-numbered pixel lines, for example, the sub-pixels PG 11 , PB 21 , PR 21 , PG 31 and PB 41 are negative (−). In one frame period subsequent to the frame period shown in the figure, the polarities of the video signals of the odd-numbered pixel lines are negative (−), and the polarities of the video signals of the even-numbered pixel lines are positive (+). In other words, the polarity distribution equivalent to that of the line-inversion drive scheme can be obtained in the present configuration.

The positive polarity of the video signal indicates that the potential of the video signal written to the pixel electrode PE is high with respect to the potential of the common electrode CE, and the negative polarity of the video signal indicates that the potential of the video signal written to the pixel electrode PE is low with respect to the potential of the common electrode CE.

FIG. 4 is a table for explanation of an example of a method of writing the video signals to the liquid crystal display panel PNL of the pixel layout shown in FIG. 3 .

In the figure, column “Gate” indicates periods for causing the switching elements connected to the respective scanning lines to be conductive and writing the video signals via the switching elements (i.e., horizontal scanning periods in which the scanning lines G 1 to G 6 are selected, respectively). Column “input data” indicates the video signals supplied from the signal processor SP to the source driver SD. It should be noted that “Rn”, “Gn” and “Bn” represent the video signals written to the pixel electrodes of the sub-pixels PRn, PGn and PBn, respectively, and that the polarities of underlined video signals are different from those of non-underlined video signals. For example, the non-underlined video signals are assumed to have positive polarities and the underlined video signals are assumed to have negative polarities. In the present example, n is a positive integer. Column “line buffer” indicates the video signals temporarily stored in the line buffer LB, of the video signals of the input data. Column “display data” indicates the video signals supplied to the liquid crystal display panel PNL via the output terminals, of the video signals of the input data.

In the horizontal scanning period in which the scanning line G 1 is selected, the signal processor SP produces the video signals (R 11 , G 11 , B 11 , R 21 , G 21 , B 21 , R 31 , G 31 , B 31 , . . . ) corresponding to the main pixels PX 11 , PX 21 and PX 31 as the input data and supplies the video signals to the source driver SD. At this time, the signal processor SP supplies the video signals (B 11 , G 21 , R 31 , . . . ) to the liquid crystal display panel PNL while supplying the video signals (R 11 , G 11 , R 21 , B 21 , G 31 , B 31 , . . . ) to the line buffer LB. The video signals are thereby written to the sub-pixels PB 11 , PG 21 and PR 31 , respectively. The line buffer LB temporarily stores the video signals (R 11 , G 11 , R 21 , B 21 , G 31 , B 31 , . . . ).

In the horizontal scanning period in which the scanning line G 2 is selected, the source driver SD supplies the video signals (R 11 , G 11 , R 21 , B 31 , . . . ), of the video signals stored in the line buffer LB, to the liquid crystal display panel PNL. The video signals are thereby written to the sub-pixels PR 11 , PG 11 , PR 21 and PB 31 , respectively.

In the horizontal scanning period in which the scanning line G 3 is selected, the signal processor SP produces the video signals (R 12 , G 12 , B 12 , R 22 , G 22 , B 22 , R 32 , G 32 , B 32 , . . . ) corresponding to the main pixels PX 12 , PX 22 and PX 32 as the input data and supplies the video signals to the source driver SD. At this time, the signal processor SP supplies the video signals (R 12 , B 22 , G 32 , . . . ) to the liquid crystal display panel PNL while supplying the video signals (G 12 , B 12 , R 22 , G 22 , R 32 , B 32 , . . . ) to the line buffer LB. The line buffer LB temporarily stores the video signals (G 12 , B 12 , R 22 , G 22 , R 32 , B 32 , . . . ) from the signal processor SP after outputting the stored video signals (B 21 , G 31 , . . . ) to the liquid crystal display panel PNL. The video signals are thereby written to the sub-pixels PR 12 , PB 21 , PB 22 , PG 31 and PG 32 , respectively.

In the horizontal scanning period in which the scanning line G 4 is selected, the source driver SD supplies the video signals (G 12 , B 12 , G 22 , R 32 , . . . ), of the video signals stored in the line buffer LB, to the liquid crystal display panel PNL. The video signals are thereby written to the sub-pixels PG 12 , PB 12 , PG 22 and PR 32 , respectively.

In the horizontal scanning period in which the scanning line G 5 is selected, the signal processor SP produces the video signals (R 13 , G 13 , B 13 , R 23 , G 23 , B 23 , R 33 , G 33 , B 33 , . . . ) corresponding to the main pixels PX 13 , PX 23 and PX 33 as the input data and supplies the video signals to the source driver SD. At this time, the signal processor SP supplies the video signals (G 13 , R 23 , B 33 , . . . ) to the liquid crystal display panel PNL while supplying the video signals (R 13 , B 13 , G 23 , B 23 , R 33 , G 33 , . . . ) to the line buffer LB. The line buffer LB temporarily stores the video signals (R 13 , B 13 , G 23 , B 23 , R 33 , G 33 , . . . ) from the signal processor SP after outputting the stored video signals (R 22 , B 32 , . . . ) to the liquid crystal display panel PNL. The video signals are thereby written to the sub-pixels PG 13 , PR 22 , PR 23 , PB 32 and PB 33 , respectively.

In the horizontal scanning period in which the scanning line G 6 is selected, the source driver SD supplies the video signals (R 13 , B 13 , G 23 , B 23 , . . . ), of the video signals stored in the line buffer LB, to the liquid crystal display panel PNL. The video signals are thereby written to the sub-pixels PR 13 , PB 13 , PG 23 and PB 23 , respectively.

FIG. 5 is an illustration showing the polarities of the video signals output to each signal line by the writing method explained with reference to FIG. 4 .

In the horizontal scanning period in which the scanning line G 1 is selected, the video signal B 11 is output to the signal line S 1 , the video signal G 21 is output to the signal line S 3 , and the video signal R 31 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 2 is selected, the video signal G 11 is output to the signal line S 2 , the video signal R 11 is output to the signal line S 3 , the video signal R 21 is output to the signal line S 4 , and the video signal B 31 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 3 is selected, the video signal R 12 is output to the signal line S 1 , the video signal B 21 is output to the signal line S 2 , the video signal B 22 is output to the signal line S 3 , the video signal G 31 is output to the signal line S 4 , and the video signal G 32 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 4 is selected, the video signal B 12 is output to the signal line S 2 , the video signal G 12 is output to the signal line S 3 , the video signal G 22 is output to the signal line S 4 , and the video signal R 32 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 5 is selected, the video signal G 13 is output to the signal line S 1 , the video signal R 22 is output to the signal line S 2 , the video signal R 23 is output to the signal line S 3 , the video signal B 32 is output to the signal line S 4 , and the video signal B 33 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 6 is selected, the video signal R 13 is output to the signal line S 2 , the video signal B 13 is output to the signal line S 3 , the video signal B 23 is output to the signal line S 4 , and the video signal G 23 is output to the signal line S 5 .

When the polarities of the video signals output to the signal lines S 1 , S 3 and S 5 are noticed, all the polarities are the same and positive (+) in one frame period, in the example illustrated. In addition, when the polarities of the video signals output to the signal lines S 2 , S 4 and S 6 are noticed, all the polarities are the same and negative (−) in one frame period, in the example illustrated.

When the main pixel PX 11 is noticed, the video signal B 11 is written to the sub-pixel PB 11 in the horizontal scanning period in which the scanning line G 1 is selected, and the video signals G 11 and R 11 are written to the sub-pixels PG 11 and PR 11 , respectively, in the horizontal scanning period in which the scanning line G 2 is selected, as shown in the figure. In other words, the horizontal scanning periods for at least two pixel lines are required to write the video signals to all the sub-pixels constituting the main pixel PX 11 . In contrast, when the main pixel PX 22 is noticed, the video signal B 22 is written to the sub-pixel PR 22 in the horizontal scanning period in which the scanning line G 3 is selected, the video signals G 22 is written to the sub-pixels PG 22 in the horizontal scanning period in which the scanning line G 4 , and the video signal R 22 is written to the sub-pixel PR 22 in the horizontal scanning period in which the scanning line G 5 is selected. In other words, the horizontal scanning periods for at least three pixel lines are required to write the video signals to all the sub-pixels constituting the main pixel PX 22 .

FIG. 6 is an illustration showing an example of timing of writing the video signals to the respective sub-pixels of the pixel layout shown in FIG. 3 .

The horizontal scanning period 1 H(G 2 ) in which the scanning line G 2 is selected includes a first period P 11 and a second period P 12 subsequent to the first period P 11 . The horizontal scanning period 1 H(G 3 ) in which the scanning line G 3 is selected includes a third period P 13 and a fourth period P 14 subsequent to the third period P 13 . The first period P 11 and the third period P 13 are periods in which the switch SWA is conductive and the switch SWB is non-conductive. The second period P 12 and the fourth period P 14 are periods in which the switch SWB is conductive and the switch SWA is non-conductive.

In the first period P 11 , the output terminal Video ( 1 ) is electrically connected with the signal line S 1 , the output terminal Video ( 2 ) is electrically connected with the signal line S 2 , and the output terminal Video ( 3 ) is electrically connected with the signal line S 5 . A dummy video signal dmy output from the output terminal Video ( 1 ) is output to the signal line S 1 . The video signal G 11 output from the output terminal Video ( 2 ) is written to the sub-pixel PG 11 via the signal line S 2 . The video signal B 31 output from the output terminal Video ( 3 ) is written to the sub-pixel PB 31 via the signal line S 5 .

In the second period P 12 , the output terminal Video ( 1 ) is electrically connected with the signal line S 3 , the output terminal Video ( 2 ) is electrically connected with the signal line S 4 , and the output terminal Video ( 3 ) is electrically connected with the signal line S 7 . The video signal R 11 output from the output terminal Video ( 1 ) is written to the sub-pixel PR 11 via the signal line S 3 . The video signal R 21 output from the output terminal Video ( 2 ) is written to the sub-pixel PR 21 via the signal line S 4 . The video signal G 41 output from the output terminal Video ( 3 ) is written to the sub-pixel PG 41 via the signal line S 7 .

In the third period P 13 , similarly to the first period P 11 , the output terminal Video ( 1 ) is electrically connected with the signal line S 1 , the output terminal Video ( 2 ) is electrically connected with the signal line S 2 , and the output terminal Video ( 3 ) is electrically connected with the signal line S 5 . The video signal R 12 output from the output terminal Video ( 1 ) is written to the sub-pixel PR 12 via the signal line S 1 . The video signal B 21 output from the output terminal Video ( 2 ) is written to the sub-pixel PB 21 via the signal line S 2 . The video signal G 32 output from the output terminal Video ( 3 ) is written to the sub-pixel PG 32 via the signal line S 5 .

In the fourth period P 14 , similarly to the second period P 12 , the output terminal Video ( 1 ) is electrically connected with the signal line S 3 , the output terminal Video ( 2 ) is electrically connected with the signal line S 4 , and the output terminal Video ( 3 ) is electrically connected with the signal line S 7 . The video signal B 22 output from the output terminal Video ( 1 ) is written to the sub-pixel PB 22 via the signal line S 3 . The video signal G 31 output from the output terminal Video ( 2 ) is written to the sub-pixel PG 31 via the signal line S 4 . The video signal R 42 output from the output terminal Video ( 3 ) is written to a sub-pixel PR 52 via the signal line S 7 .

According to the present embodiment, one of the sub-pixels constituting one main pixel, and one of the sub-pixels constituting the other main pixel, of two main pixels arranged in the second direction D 2 , share the same signal line. For this reason, the number of the signal lines allocated to the two main pixels arranged in the second direction D 2 is smaller than the total number of the sub-pixels constituting the two main pixels. In other words, the number of the signal lines allocated to one main pixel PX is smaller than the total number of the sub-pixels constituting the main pixel PX. In the example shown in FIG. 3 , the signal lines S 1 to S 3 are arranged for totally six sub-pixels when two main pixels PX 11 and PX 21 arranged in the second direction D 2 are paired as a minimum unit of repetition. The signal line S 2 is electrically connected with the sub-pixel PG 11 constituting the main pixel PX 11 and the sub-pixel PB 21 constituting the main pixel PX 21 , and is shared by the sub-pixels PG 11 and PB 21 . In addition, the signal line S 3 is electrically connected with the sub-pixel PR 11 constituting the main pixel PX 11 and the sub-pixel PG 21 constituting the main pixel PX 21 , and is shared by the sub-pixels PR 11 and PG 21 . The sub-pixel PR 21 is electrically connected with the signal line S 4 , but the signal line S 4 is shared by the sub-pixel PR 21 and the sub-pixel PG 31 of the main pixel PX 31 , which is arranged with the sub-pixel PR 21 in the second direction D 2 , and is not included in the signal lines allocated to the main pixels PX 11 and PX 21 . Thus, three signal lines are allocated to every two main pixels, i.e., one and a half signal lines are allocated to each main pixel. Even if the number of the main pixels which should be disposed in the display area is increased, increase in the number of signal lines can be suppressed and the energy consumption can be reduced.

In addition, the polarities of the video signals output to each signal line are not varied in one frame period, and the polarities of the video signals of the signal lines adjacent in the second direction D 2 are opposite to each other. In other words, the column-inversion drive scheme is applied to the present embodiment. For this reason, the energy consumption can be reduced in comparison with application of the line-inversion drive scheme of supplying the video images having the polarities inverted in each one or more pixel lines for the same signal line.

In the above-explained example, two signal lines are connected to each output terminal Video via the switches and one horizontal scanning period is divided into two periods to output the video signals to each of the signal lines, but at least three signal lines may be connected to one output terminal Video via the switches and, in this case, one horizontal scanning period may be divided into a necessary number of periods to output the video signals to each of the signal lines.

Next, another configuration example of the present embodiment will be explained.

FIG. 7 is an illustration schematically showing a relationship between another pixel layout in the display area, and the polarities of the video signals written to the respective pixels.

Some main pixels in the display area are shown in the pixel layout illustrated in each of (A) to (C) in the figure, the main pixels PX 11 to PX 13 and PX 21 to PX 23 are arranged in the first direction D 1 , and the main pixels PX 11 and PX 21 , the main pixels PX 12 and PX 22 , and the main pixels PX 13 and PX 23 are arranged in the second direction D 2 .

In the pixel layout illustrated in (A), the main pixel PX 11 includes the sub-pixels PB 11 , PW 11 and PG 11 . The main pixel PX 21 includes the sub-pixels PR 21 , PB 21 and PW 21 . The main pixels PX 12 and PX 13 are also constituted similarly to the main pixel PX 11 , and the main pixels PX 22 and PX 23 are also constituted similarly to the main pixel PX 21 . In the figure, PRn, PGn, PBn and PWn indicate a red sub-pixel, a green sub-pixel, a blue sub-pixel and a sub-pixel of a fourth color (for example, white), respectively, in each main pixel PXn, where n indicates a positive integer. The other configuration examples to be explained below also have the same feature as this.

Two main pixels arranged in the second direction D 2 function as a pair of unit pixels and share sub-pixels of colors removed from the respective main pixels. In the example illustrated, the green sub-pixel PG 11 and the red sub-pixel PR 21 are shared in the unit pixel composed of the main pixels PX 11 and PX 21 .

In the main pixel PX 11 , the sub-pixel PB 11 is electrically connected with the scanning line G 1 and the signal line S 1 . The sub-pixel PW 11 is electrically connected with the scanning line G 2 and the signal line S 2 . The sub-pixel PG 11 is electrically connected with the scanning line G 2 and the signal line S 3 .

In the main pixel PX 21 , the sub-pixel PR 21 is electrically connected with the scanning line G 3 and the signal line S 2 . The sub-pixel PB 21 is electrically connected with the scanning line G 1 and the signal line S 3 . The sub-pixel PW 21 is electrically connected with the scanning line G 2 and the signal line S 4 . In the example illustrated, the signal line S 2 is shared by the sub-pixel PW 11 constituting the main pixel PX 11 and the sub-pixel PR 21 constituting the main pixel PX 21 . In addition, the signal line S 3 is shared by the sub-pixel PG 11 constituting the main pixel PX 11 and the sub-pixel PB 21 constituting the main pixel PX 21 .

Of the pixel lines composed of the sub-pixels arranged in the second direction D 2 , odd-numbered pixel lines are constituted similarly to the first pixel line, and even-numbered pixel lines are constituted similarly to the second pixel line. In one frame period shown in the figure, positive-polarity video signals (+) are supplied to the signal lines S 1 , S 3 , . . . and negative-polarity video signals (−) are supplied to the signal lines S 2 , S 4 , . . . . For this reason, the positive-polarity video signals (+) are written to the sub-pixels of the odd-numbered pixel lines and the negative-polarity video signals (−) are written to the sub-pixels of the even-numbered pixel lines.

It should be noted that processing of averaging the video signals is executed between the paired main pixels, in the configuration shown in the figure. For example, the signal processor SP shown in FIG. 3 executes averaging based on the video signal G 11 which should be written to the green sub-pixel PG 11 in the main pixel PX 11 and the video signal G 21 which should be written to the green sub-pixel in the main pixel PX 21 (but not included in the actual main pixel PX 21 ), and produces a corrected video signal. As the method of producing the corrected video signal for the averaging, calculating the signal as an arithmetic mean by multiplying the video signals G 11 and G 21 by a predetermined coefficient, calculating the signal as a geometric mean of the video signals C 11 and G 21 and the other methods, can be applied. The corrected video signal thus produced is supplied to the signal line S 3 and written to the sub-pixel PG 11 in the horizontal scanning period in which the scanning line G 2 is selected. Similarly to this, the signal processor SP executes averaging based on the video signal R 11 which should be written to the red sub-pixel in the main pixel PX 11 (but not included in the actual main pixel PX 11 ) and the video signal R 21 which should be written to the red sub-pixel PR 21 in the main pixel PX 21 , and writes the produced corrected video signal to the sub-pixel PR 21 .

The pixel layout illustrated in (B) is different from the pixel layout illustrated in (A) with respect to the sub-pixels included in each of the main pixels. That is, the main pixel PX 11 includes the sub-pixels PR 11 , PG 11 and PW 11 . The main pixel PX 21 includes the sub-pixels PB 21 , PR 21 and PG 21 . The main pixels PX 12 and PX 13 are also constituted similarly to the main pixel PX 11 , and the main pixels PX 22 and PX 23 are also constituted similarly to the main pixel PX 21 . In the example illustrated, the white sub-pixel PW 11 and the blue sub-pixel PB 21 are shared in the unit pixel composed of the main pixels PX 11 and PX 21 .

In the main pixel PX 11 , the sub-pixel PR 11 is electrically connected with the scanning line G 1 and the signal line S 1 . The sub-pixel PG 11 is electrically connected with the scanning line G 2 and the signal line S 2 . The sub-pixel PW 11 is electrically connected with the scanning line G 2 and the signal line S 3 .

In the main pixel PX 21 , the sub-pixel PB 21 is electrically connected with the scanning line G 3 and the signal line S 2 . The sub-pixel PR 21 is electrically connected with the scanning line G 1 and the signal line S 3 . The sub-pixel PG 21 is electrically connected with the scanning line G 2 and the signal line S 4 . In the example illustrated, the signal line S 2 is shared by the sub-pixel PG 11 constituting the main pixel PX 11 and the sub-pixel PB 21 constituting the main pixel PX 21 . The signal line S 3 is shared by the sub-pixel PW 11 constituting the main pixel PX 11 and the sub-pixel PR 21 constituting the main pixel PX 21 .

In the configuration shown in the figure, the processing of averaging the white and blue video signals is executed between the paired main pixels PX 11 and PX 21 .

The pixel layout illustrated in (C) is different from the pixel layout illustrated in (A) with respect to the sub-pixels included in each of the main pixels. That is, the main pixel PX 11 includes the sub-pixels PW 11 , PG 11 and PR 11 . The main pixel PX 21 includes the sub-pixels PB 21 , PW 21 and PG 21 . The main pixels PX 12 and PX 13 are also constituted similarly to the main pixel PX 11 , and the main pixels PX 22 and PX 23 are also constituted similarly to the main pixel PX 21 . In the example illustrated, the red sub-pixel PR 11 and the blue sub-pixel PB 21 are shared in the unit pixel composed of the main pixels PX 11 and PX 21 .

In the main pixel PX 11 , the sub-pixel PW 11 is electrically connected with the scanning line G 1 and the signal line S 1 . The sub-pixel PG 11 is electrically connected with the scanning line G 2 and the signal line S 2 . The sub-pixel PR 11 is electrically connected with the scanning line G 2 and the signal line S 3 .

In the main pixel PX 21 , the sub-pixel PB 21 is electrically connected with the scanning line G 3 and the signal line S 2 . The sub-pixel PW 21 is electrically connected with the scanning line G 1 and the signal line S 3 . The sub-pixel PG 21 is electrically connected with the scanning line G 2 and the signal line S 4 . In the example illustrated, the signal line S 2 is shared by the sub-pixel PG 11 constituting the main pixel PX 11 and the sub-pixel PB 21 constituting the main pixel PX 21 . The signal line S 3 is shared by the sub-pixel PR 11 constituting the main pixel PX 11 and the sub-pixel PW 21 constituting the main pixel PX 21 .

In the configuration shown in the figure, the processing of averaging the red and blue video signals is executed between the paired main pixels PX 11 and PX 21 .

In each of the configuration examples illustrated in (A) to (C), too, the same advantages as those of the above-described configuration examples can be obtained.

FIG. 8 is a diagram schematically showing an example of another pixel layout in the display area, and a configuration for writing the video signals to the respective pixels.

The example shown in FIG. 8 is different from the example shown in FIG. 3 with respect to the connection between the scanning lines and the signal lines in the respective sub-pixels. That is, in the main pixel PX 11 , the sub-pixel PB 11 is electrically connected with the scanning line G 1 and the signal line S 1 . The sub-pixel PG 11 is electrically connected with the scanning line G 2 and the signal line S 1 . The sub-pixel PR 11 is electrically connected with the scanning line G 1 and the signal line S 2 . In the main pixel PX 21 , the sub-pixel PB 21 is electrically connected with the scanning line G 2 and the signal line S 2 . The sub-pixel PG 21 is electrically connected with the scanning line G 1 and the signal line S 3 . The sub-pixel PR 21 is electrically connected with the scanning line G 2 and the signal line S 3 . In the main pixel PX 31 , the sub-pixel PB 31 is electrically connected with the scanning line G 1 and the signal line S 4 . The sub-pixel PG 31 is electrically connected with the scanning line G 2 and the signal line S 4 . The sub-pixel PR 31 is electrically connected with the scanning line G 1 and the signal line S 5 . The main pixels PX 12 and PX 13 are constituted similarly to the main pixel PX 11 , the main pixels PX 22 and PX 23 are constituted similarly to the main pixel PX 21 , and the main pixels PX 32 and PX 33 are constituted similarly to the main pixel PX 31 .

When the two main pixels PX 11 and PX 21 arranged in the second direction D 2 are noticed, the signal line S 1 is shared by the sub-pixels PB 11 and PG 11 constituting the main pixel PX 11 . In addition, the signal line S 2 is shared by the sub-pixel PR 11 constituting the main pixel PX 11 and the sub-pixel PB 21 constituting the main pixel PX 21 . The signal line S 3 is shared by the sub-pixels PG 21 and PR 21 constituting the main pixel PX 21 .

The display driver DD is constituted similarly to that in the example shown in FIG. 3 . The signal processor SP outputs some of the video signals to the output terminals Video ( 1 ) to Video ( 3 ) while outputting the other video signals to the line buffer LB. The line buffer LB temporarily stores the video signals input from the signal processor SP. For example, the signal processor SP produces video signals for one pixel line and outputs the video signals for a half pixel line to the output terminals Video ( 1 ) to Video ( 3 ) while outputting the video signals for a remaining half pixel line to the line buffer LB and temporarily storing the video signals in the line buffer LB. For this reason, the line buffer LB may have a storage capacity to store video signals for at least a half pixel line. Outputting the video signals will be explained later.

In this configuration, the polarities of the video signals output to each of the signal lines S 1 to S 6 , in one frame period, are not varied, and the polarities of the video signals output to adjacent signal lines are opposite. In the example illustrated, the polarities of the video signals output to the odd-numbered signal lines S 1 , S 3 and S 5 are negative (−) and the polarities of the video signals output to the even-numbered signal lines S 2 , S 4 and S 6 are positive (+), in a certain frame period. In one frame period subsequent to the frame period shown in the figure, the polarities of the video signals output to the odd-numbered signal lines are positive (+), and the polarities of the video signals output to the even-numbered signal lines are negative (−). In other words, the column-inversion drive scheme is applied to the present configuration.

In addition, in the frame period shown in the figure, the polarities of the video signals written to the sub-pixels arranged in the first direction D 1 are the same as each other, and the polarities of the video signals written to the sub-pixels arranged in the second directions D 2 are opposite to each other.

FIG. 9 is a table for explanation of an example of a method of writing the video signals to the liquid crystal display panel PNL of the pixel layout shown in FIG. 8 .

In the horizontal scanning period in which the scanning line G 1 is selected, the signal processor SP produces the video signals (R 11 , G 11 , B 11 , R 21 , G 21 , B 21 , R 31 , G 31 , B 31 , . . . ) corresponding to the main pixels PX 11 , PX 21 and PX 31 as the input data and supplies the video signals to the source driver SD. At this time, the signal processor SP supplies the video signals (R 11 , B 11 , G 21 , R 31 , B 31 , . . . ) to the liquid crystal display panel PNL while supplying the video signals (G 11 , R 21 , B 21 , G 31 , . . . ) to the line buffer LB. The video signals are thereby written to the sub-pixels PR 11 , PB 11 , PG 21 , PR 31 and PB 31 , respectively. The line buffer LB temporarily stores the video signals (G 11 , R 21 , B 21 , G 31 , . . . )

In the horizontal scanning period in which the scanning line G 2 is selected, the source driver SD supplies the video signals (G 11 , R 21 , B 21 , G 31 , . . . ) stored in the line buffer LB, to the liquid crystal display panel PNL. The video signals are thereby written to the sub-pixels PG 11 , PR 21 , PB 21 and PG 31 , respectively.

In the horizontal scanning period in which the scanning line G 3 is selected, the signal processor SP produces the video signals (R 12 , G 12 , B 12 , R 22 , G 22 , B 22 , R 32 , G 32 , B 32 , . . . ) corresponding to the main pixels PX 12 , PX 22 and PX 32 as the input data and supplies the video signals to the source driver SD. At this time, the signal processor SP supplies the video signals (R 12 , G 12 , B 22 , R 32 , G 32 , . . . ) to the liquid crystal display panel PNL while supplying the video signals (B 12 , R 22 , G 22 , B 32 , . . . ) to the line buffer LB. The video signals are thereby written to the sub-pixels PR 12 , PG 12 , PB 22 , PR 32 and PG 32 , respectively. The line buffer LB temporarily stores the video signals (B 12 , R 22 , G 22 , B 32 , . . . ).

In the horizontal scanning period in which the scanning line G 4 is selected, the source driver SD supplies the video signals (B 12 , R 22 , G 22 , B 32 , . . . ) stored in the line buffer LB, to the liquid crystal display panel PNL. The video signals are thereby written to the sub-pixels PB 12 , PR 22 , PG 22 and PB 32 , respectively.

In the horizontal scanning period in which the scanning line G 5 is selected, the signal processor SP produces the video signals (R 13 , G 13 , B 13 , R 23 , G 23 , B 23 , R 33 , G 33 , B 33 , . . . ) corresponding to the main pixels PX 13 , PX 23 and PX 33 as the input data and supplies the video signals to the source driver SD. At this time, the signal processor SP supplies the video signals (G 13 , B 13 , R 23 , G 33 , B 33 , . . . ) to the liquid crystal display panel PNL while supplying the video signals (R 13 , G 23 , B 23 , R 33 , . . . ) to the line buffer LB. The video signals are thereby written to the sub-pixels PG 13 , PB 13 , PR 23 , PG 33 and PB 33 , respectively. The line buffer LB temporarily stores the video signals (R 13 , G 23 , B 23 , R 33 , . . . ).

In the horizontal scanning period in which the scanning line G 6 is selected, the source driver SD supplies the video signals (R 13 , G 23 , B 23 , R 33 , . . . ) stored in the line buffer LB, to the liquid crystal display panel PNL. The video signals are thereby written to the sub-pixels PR 13 , PG 23 , PR 23 and PR 33 , respectively.

FIG. 10 is an illustration showing a summary of the polarities of the video signals output to each signal line by the writing method explained with reference to FIG. 9 .

In the horizontal scanning period in which the scanning line G 1 is selected, the video signal B 11 is output to the signal line S 1 , the video signal R 11 is output to the signal line S 2 , the video signal G 21 is output to the signal line S 3 , the video signal B 31 is output to the signal line S 4 , and the video signal R 31 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 2 is selected, the video signal G 11 is output to the signal line S 1 , the video signal B 21 is output to the signal line S 2 , the video signal R 21 is output to the signal line S 3 , the video signal G 31 is output to the signal line S 4 , and the video signal B 41 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 3 is selected, the video signal R 12 is output to the signal line S 1 , the video signal G 12 is output to the signal line S 2 , the video signal B 22 is output to the signal line S 3 , the video signal R 32 is output to the signal line S 4 , and the video signal G 32 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 4 is selected, the video signal B 12 is output to the signal line S 1 , the video signal R 22 is output to the signal line S 2 , the video signal G 22 is output to the signal line S 3 , the video signal B 32 is output to the signal line S 4 , and the video signal R 41 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 5 is selected, the video signal G 13 is output to the signal line S 1 , the video signal B 13 is output to the signal line S 2 , the video signal R 23 is output to the signal line S 3 , the video signal G 33 is output to the signal line S 4 , and the video signal B 33 is output to the signal line S 5 .

In the horizontal scanning period in which the scanning line G 6 is selected, the video signal R 13 is output to the signal line S 1 , the video signal G 23 is output to the signal line S 2 , the video signal B 23 is output to the signal line S 3 , the video signal R 33 is output to the signal line S 4 , and the video signal G 43 is output to the signal line S 5 .

When the polarities of the video signals output to the signal lines S 1 , S 3 and S 5 are noticed, all the polarities are the same and negative (−) in one frame period, in the example illustrated. When the polarities of the video signals output to the signal lines S 2 , S 4 and S 6 are noticed, all the polarities are the same and positive (+) in one frame period, in the example illustrated.

When the main pixel PX 11 is noticed, the video signals B 11 and R 11 are written to the sub-pixels PB 11 and PR 11 , respectively, in the horizontal scanning period in which the scanning line G 1 is selected, and the video signal G 11 is written to the sub-pixel PG 11 in the horizontal scanning period in which the scanning line G 2 is selected, as shown in the figure. When the main pixel PX 21 is noticed, the video signal G 21 is written to the sub-pixel PG 21 in the horizontal scanning period in which the scanning line G 1 is selected, and the video signals B 21 and R 21 are written to the sub-pixels PB 21 and PR 21 , respectively, in the horizontal scanning period in which the scanning line G 2 is selected. In other words, the horizontal scanning periods for at least two pixel lines are required to write the video signals to all the sub-pixels constituting each main pixel.

FIG. 11 is an illustration showing an example of timing of writing the video signals to the respective sub-pixels of the pixel layout shown in FIG. 8 .

The horizontal scanning period 1 H(G 1 ) in which the scanning line G 1 is selected includes a first period P 21 and a second period P 22 subsequent to the first period P 21 . The horizontal scanning period 1 H(G 2 ) in which the scanning line G 2 is selected includes a third period P 23 and a fourth period P 24 subsequent to the third period P 23 . The first period P 21 and the third period P 23 are periods in which the switch SWA is conductive and the switch SWB is non-conductive. The second period P 22 and the fourth period P 24 are periods in which the switch SWB is conductive and the switch SWA is non-conductive.

In the first period P 21 , the output terminal Video ( 1 ) is electrically connected with the signal line S 1 , the output terminal Video ( 2 ) is electrically connected with the signal line S 2 , and the output terminal Video ( 3 ) is electrically connected with the signal line S 5 . The video signal B 11 output from the output terminal Video ( 1 ) is written to the sub-pixel PB 11 via the signal line S 1 . The video signal R 11 output from the output terminal Video ( 2 ) is written to the sub-pixel PR 11 via the signal line S 2 . The video signal R 31 output from the output terminal Video ( 3 ) is written to the sub-pixel PR 31 via the signal line S 5 .

In the second period P 22 , the output terminal Video ( 1 ) is electrically connected with the signal line S 3 , and the output terminal Video ( 2 ) is electrically connected with the signal line S 4 . The video signal G 21 output from the output terminal Video ( 1 ) is written to the sub-pixel PG 21 via the signal line S 3 . The video signal B 31 output from the output terminal Video ( 2 ) is written to the sub-pixel PB 31 via the signal line S 4 .

In the third period P 23 , the video signal G 11 output from the output terminal Video ( 1 ) is written to the sub-pixel PG 11 via the signal line S 1 . The video signal B 21 output from the output terminal Video ( 2 ) is written to the sub-pixel PB 21 via the signal line S 2 . The video signal B 41 output from the output terminal Video ( 3 ) is written to the sub-pixel PB 41 via the signal line S 5 .

In the fourth period P 24 , the video signal R 21 output from the output terminal Video ( 1 ) is written to the sub-pixel PR 21 via the signal line S 3 . The video signal G 31 output from the output terminal Video ( 2 ) is written to the sub-pixel PG 31 via the signal line S 4 .

In this configuration example, too, one and a half signal lines are allocated to each main pixel and, even if the number of the main pixels which should be disposed in the display area is increased, increase in the number of signal lines can be suppressed and the energy consumption can be reduced. In addition, since the column-inversion drive scheme is applied, the energy consumption can be reduced in comparison with the application of the line-inversion drive scheme.

FIG. 12 is an illustration schematically showing a relationship between yet another pixel layout in the display area, and the polarities of the video signals written to the respective pixels.

In the pixel layout illustrated in (A), the main pixel PX 11 includes the sub-pixels PB 11 , PW 11 and PG 11 . The main pixel PX 21 includes the sub-pixels PR 21 , PB 21 and PW 21 . The main pixels PX 12 and PX 13 are also constituted similarly to the main pixel PX 11 , and the main pixels PX 22 and PX 23 are also constituted similarly to the main pixel PX 21 . Two main pixels arranged in the second direction D 2 function as a pair of unit pixels and share sub-pixels of colors removed from the respective main pixels. In the example illustrated, the green sub-pixel PG 11 and the red sub-pixel PR 21 are shared in the unit pixel composed of the main pixels PX 11 and PX 21 .

In the main pixel PX 11 , the sub-pixel PB 11 is electrically connected with the scanning line G 1 and the signal line S 1 . The sub-pixel PW 11 is electrically connected with the scanning line G 2 and the signal line S 1 . The sub-pixel PG 11 is electrically connected with the scanning line G 1 and the signal line S 2 .

In the main pixel PX 21 , the sub-pixel PR 21 is electrically connected with the scanning line G 2 and the signal line S 2 . The sub-pixel PB 21 is electrically connected with the scanning line G 1 and the signal line S 3 . The sub-pixel PW 21 is electrically connected with the scanning line G 2 and the signal line S 3 . In the example illustrated, the signal line S 1 is shared by the sub-pixels PB 11 and PW 11 constituting the main pixel PX 11 . In addition, the signal line S 2 is shared by the sub-pixel PG 11 constituting the main pixel PX 11 and the sub-pixel PR 21 constituting the main pixel PX 21 . In addition, the signal line S 3 is shared by the sub-pixels PB 21 and PW 21 constituting the main pixel PX 21 .

Of the pixel lines composed of the sub-pixels arranged in the second direction D 2 , odd-numbered pixel lines are constituted similarly to the first pixel line, and even-numbered pixel lines are constituted similarly to the second pixel line. In one frame period shown in the figure, positive-polarity video signals (+) are supplied to the signal lines S 1 , S 3 , . . . and negative-polarity video signals (−) are supplied to the signal lines S 2 , S 4 , . . . . In the configuration shown in the figure, the processing of averaging the red and green video signals is executed between the paired main pixels PX 11 and PX 21 .

In the pixel layout illustrated in (B), the main pixel PX 11 includes the sub-pixels PR 11 , PG 11 and PW 11 . The main pixel PX 21 includes the sub-pixels PB 21 , PR 21 and PG 21 . The main pixels PX 12 and PX 13 are also constituted similarly to the main pixel PX 11 , and the main pixels PX 22 and PX 23 are also constituted similarly to the main pixel PX 21 . In the example illustrated, the white sub-pixel PW 11 and the blue sub-pixel PB 21 are shared in the unit pixel composed of the main pixels PX 11 and PX 21 .

In the main pixel PX 11 , the sub-pixel PR 11 is electrically connected with the scanning line G 1 and the signal line S 1 . The sub-pixel PG 11 is electrically connected with the scanning line G 2 and the signal line S 1 . The sub-pixel PW 11 is electrically connected with the scanning line G 1 and the signal line S 2 .

In the main pixel PX 21 , the sub-pixel PB 21 is electrically connected with the scanning line G 2 and the signal line S 2 . The sub-pixel PR 21 is electrically connected with the scanning line G 1 and the signal line S 3 . The sub-pixel PG 21 is electrically connected with the scanning line G 2 and the signal line S 3 . In the example illustrated, the signal line S 1 is shared by the sub-pixels PR 11 and PG 11 constituting the main pixel PX 11 . In addition, the signal line S 2 is shared by the sub-pixel PW 11 constituting the main pixel PX 11 and the sub-pixel PB 21 constituting the main pixel PX 21 . The signal line S 3 is shared by the sub-pixels PR 21 and PG 21 constituting the main pixel PX 21 .

In the configuration shown in the figure, the processing of averaging the white and blue video signals is executed between the paired main pixels PX 11 and PX 21 .

In the pixel layout illustrated in (C), the main pixel PX 11 includes the sub-pixels PW 11 , PG 11 and PR 11 . The main pixel PX 21 includes the sub-pixels PB 21 , PW 21 and PG 21 . The main pixels PX 12 and PX 13 are also constituted similarly to the main pixel PX 11 , and the main pixels PX 22 and PX 23 are also constituted similarly to the main pixel PX 21 . In the example illustrated, the red sub-pixel PR 11 and the blue sub-pixel PB 21 are shared in the unit pixel composed of the main pixels PX 11 and PX 21 .

In the main pixel PX 11 , the sub-pixel PW 11 is electrically connected with the scanning line G 1 and the signal line S 1 . The sub-pixel PG 11 is electrically connected with the scanning line G 2 and the signal line S 1 . The sub-pixel PR 11 is electrically connected with the scanning line G 1 and the signal line S 2 .

In the main pixel PX 21 , the sub-pixel PB 21 is electrically connected with the scanning line G 2 and the signal line S 2 . The sub-pixel PW 21 is electrically connected with the scanning line G 1 and the signal line S 3 . The sub-pixel PG 21 is electrically connected with the scanning line G 2 and the signal line S 3 . In the example illustrated, the signal line S 1 is shared by the sub-pixels PW 11 and PG 11 constituting the main pixel PX 11 . In addition, the signal line S 2 is shared by the sub-pixel PR 11 constituting the main pixel PX 11 and the sub-pixel PB 21 constituting the main pixel PX 21 . The signal line S 3 is shared by the sub-pixels PW 21 and PG 21 constituting the main pixel PX 21 .

In the configuration shown in the figure, the processing of averaging the red and blue video signals is executed between the paired main pixels PX 11 and PX 21 .

In each of the configuration examples illustrated in (A) to (C), too, the same advantages as those of the above-described configuration examples can be obtained.

Next, yet another configuration example will be explained. In the configuration example explained below, the first direction D 1 and the second direction D 2 are different from those in the above-explained configuration examples, the first direction D 1 corresponds to a direction in which the signal lines S 1 to S 6 are arranged and the second direction D 2 corresponds to a direction in which the scanning lines G 1 to G 5 are arranged. In addition, each of the sub-pixels is in a longitudinally elongated shape extending in the second direction D 2 .

FIG. 13 is a diagram schematically showing an example of yet another pixel layout in the display area, and a configuration for writing the video signals to the respective pixels.

The main pixel PX 11 includes a sub-pixel (first sub-pixel) PB 11 , a sub-pixel (second sub-pixel) PR 11 and a sub-pixel (third sub-pixel) PG 11 . The sub-pixel PR 11 and the sub-pixel PB 11 are arranged in the first direction D 1 . The sub-pixel PG 11 and the sub-pixel PB 11 are arranged in the second direction D 2 . The sub-pixel PB 11 is electrically connected with the scanning line G 1 and the signal line S 1 . The sub-pixel PR 11 is electrically connected with the scanning line G 2 and the signal line S 3 . The sub-pixel PG 11 is electrically connected with the scanning line G 2 and the signal line S 2 .

The main pixel PX 12 includes a sub-pixel (fourth sub-pixel) PB 12 , a sub-pixel (fifth sub-pixel) PR 12 and a sub-pixel (sixth sub-pixel) PG 12 . The sub-pixel PB 12 and the sub-pixel PG 11 are arranged in the first direction D 1 . The sub-pixel PR 12 and the sub-pixel PG 11 are arranged in the second direction D 2 . The sub-pixel PG 12 and the sub-pixel PR 12 are arranged in the first direction D 1 . The sub-pixel PB 12 is electrically connected with the scanning line G 3 and the signal line S 2 . The sub-pixel PR 12 is electrically connected with the scanning line G 3 and the signal line S 1 . The sub-pixel PG 12 is electrically connected with the scanning line G 4 and the signal line S 3 .

The main pixel PX 13 includes the sub-pixels PB 13 , PR 13 and PG 13 . The sub-pixel PR 13 and the sub-pixel PB 13 are arranged in the first direction D 1 . The sub-pixel PG 13 and the sub-pixel PB 13 are arranged in the second direction D 2 . The sub-pixel PB 13 is electrically connected with the scanning line G 4 and the signal line S 2 . The sub-pixel PR 13 is electrically connected with the scanning line G 5 and the signal line S 2 . The sub-pixel PG 13 is electrically connected with the scanning line G 5 and the signal line S 1 .

The main pixels PX 21 , PX 22 and PX 23 are constituted similarly to the main pixels PX 11 , PX 12 and PX 13 , respectively.

When the two main pixels PX 11 and PX 12 arranged in the second direction D 2 are noticed, in the example illustrated, the signal line S 1 is shared by the sub-pixel PB 11 constituting the main pixel PX 11 and the sub-pixel PR 12 constituting the main pixel PX 12 . In addition, the signal line S 2 is shared by the sub-pixel PG 11 constituting the main pixel PX 11 and the sub-pixel PB 12 constituting the main pixel PX 12 . The signal line S 3 is shared by the sub-pixel PR 11 constituting the main pixel PX 11 and the sub-pixel PG 12 constituting the main pixel PX 12 .

The output terminal Video ( 1 ) is electrically connected with the signal lines S 1 and S 3 , the output terminal Video ( 2 ) is electrically connected with the signal lines S 2 and S 4 , the output terminal Video ( 3 ) is electrically connected with the signal line S 5 , and the output terminal Video ( 4 ) is electrically connected with the signal line S 6 . The switch SWA is interposed between the signal line S 1 and the output terminal Video ( 1 ), between the signal line S 2 and the output terminal Video ( 2 ), between the signal line S 5 and the output terminal Video ( 3 ), and between the signal line S 6 and the output terminal Video ( 4 ). The switch SWB is interposed between the signal line S 3 and the output terminal Video ( 1 ), and between the signal line S 4 and the output terminal Video ( 2 ).

The column-inversion drive scheme is applied to the present configuration and, in the example illustrated, the polarities of the video signals output to the odd-numbered signal lines S 1 , S 3 and S 5 are positive (+) and the polarities of the video signals output to the even-numbered signal lines S 2 , S 4 and S 6 are negative (−), in a certain frame period. In contrast, in the present configuration, the same polarity distribution as that of the line-inversion drive scheme can be obtained and, in the frame period shown in the figure, the polarities of the video signals written to the sub-pixels of the odd-numbered pixel lines are positive (+) and the polarities of the video signals written to the sub-pixels of the even-numbered pixel lines are negative (−).

In this configuration example, two signal lines are allocated to each main pixel and, even if the number of the main pixels which should be disposed in the display area is increased, increase in the number of signal lines can be suppressed and the energy consumption can be reduced. In addition, since the column-inversion drive scheme is applied, the energy consumption can be reduced in comparison with the application of the line-inversion drive scheme.

FIG. 14 is a diagram schematically showing an example of yet another pixel layout in the display area, and a configuration for writing the video signals to the respective pixels.

The main pixel PX 11 includes the sub-pixels PB 11 , PW 11 and PG 11 . The sub-pixel PW 11 and the sub-pixel PB 11 are arranged in the first direction D 1 . The sub-pixel PG 11 and the sub-pixel PB 11 are arranged in the second direction D 2 . The sub-pixel PB 11 is electrically connected with the scanning line G 1 and the signal line S 1 . The sub-pixel PW 11 is electrically connected with the scanning line G 2 and the signal line S 3 . The sub-pixel PG 11 is electrically connected with the scanning line G 2 and the signal line S 2 .

The main pixel PX 12 includes the sub-pixels PR 12 , PB 12 and PW 12 . The sub-pixel PR 12 and the sub-pixel PG 11 are arranged in the first direction D 1 . The sub-pixel PB 12 and the sub-pixel PG 11 are arranged in the second direction D 2 . The sub-pixel PW 12 and the sub-pixel PB 12 are arranged in the first direction D 1 . The sub-pixel PR 12 is electrically connected with the scanning line G 3 and the signal line S 2 . The sub-pixel PB 12 is electrically connected with the scanning line G 3 and the signal line S 1 . The sub-pixel PW 12 is electrically connected with the scanning line G 4 and the signal line S 3 .

The main pixel PX 13 includes the sub-pixels PB 13 , PW 13 and PG 13 . The sub-pixel PW 13 is arranged in the first direction D 1 of the sub-pixel PB 13 . The sub-pixel PG 13 is arranged in the second direction D 2 of the sub-pixel PB 13 . The sub-pixel PB 13 is electrically connected with the scanning line G 4 and the signal line S 2 . The sub-pixel PW 13 is electrically connected with the scanning line G 5 and the signal line S 2 . The sub-pixel PG 13 is electrically connected with the scanning line G 5 and the signal line S 1 .

The main pixels PX 21 to PX 23 and PX 31 to PX 33 are constituted similarly to the main pixels PX 11 to PX 13 .

When the two main pixels PX 11 and PX 12 arranged in the second direction D 2 are noticed, in the example illustrated, the signal line S 1 is shared by the sub-pixel PB 11 constituting the main pixel PX 11 and the sub-pixel PB 12 constituting the main pixel PX 12 . In addition, the signal line S 2 is shared by the sub-pixel PG 11 constituting the main pixel PX 11 and the sub-pixel PR 12 constituting the main pixel PX 12 . The signal line S 3 is shared by the sub-pixel PW 11 constituting the main pixel PX 11 and the sub-pixel PW 12 constituting the main pixel PX 12 .

The output terminal Video ( 1 ) is electrically connected with the signal lines S 1 and S 3 , the output terminal Video ( 2 ) is electrically connected with the signal lines S 2 and S 4 , the output terminal Video ( 3 ) is electrically connected with the signal lines S 5 and S 7 , and the output terminal Video ( 4 ) is electrically connected with the signal lines S 6 and S 8 . The switch SWA is interposed between the signal line S 1 and the output terminal Video ( 1 ), between the signal line S 2 and the output terminal Video ( 2 ), between the signal line S 5 and the output terminal Video ( 3 ), and between the signal line S 6 and the output terminal Video ( 4 ). The switch SWB is interposed between the signal line S 3 and the output terminal Video ( 1 ), between the signal line S 4 and the output terminal Video ( 2 ), between the signal line S 7 and the output terminal Video ( 3 ), and between the signal line S 8 and the output terminal Video ( 4 ).

The column-inversion drive scheme is applied to the present configuration and, in the example illustrated, the polarities of the video signals output to the odd-numbered signal lines S 1 , S 3 , S 5 and S 7 are positive (+) and the polarities of the video signals output to the even-numbered signal lines S 2 , S 4 , S 6 and S 8 are negative (−), in a certain frame period. In contrast, in the present configuration, the same polarity distribution as that of the line-inversion drive scheme can be obtained and, in the frame period shown in the figure, the polarities of the video signals written to the sub-pixels of the odd-numbered pixel lines are positive (+) and the polarities of the video signals written to the sub-pixels of the even-numbered pixel lines are negative (−).

Two main pixels arranged in the second direction D 2 function as a pair of unit pixels and share sub-pixels of colors removed from the respective main pixels. In the example illustrated, the green sub-pixel PG 11 and the red sub-pixel PR 12 are shared in the unit pixel composed of the main pixels PX 11 and PX 12 . In the configuration shown in the figure, the processing of averaging the red and green video signals is executed between the paired main pixels PX 11 and PX 21 .

FIG. 15 is an illustration showing an example of timing of writing the video signals to the respective sub-pixels of the pixel layout shown in FIG. 14 .

The horizontal scanning period 1 H(G 2 ) in which the scanning line G 2 is selected includes a first period P 31 and a second period P 32 subsequent to the first period P 31 . The horizontal scanning period 1 H(G 3 ) in which the scanning line G 3 is selected includes a third period P 33 and a fourth period P 34 subsequent to the third period P 33 .

In the first period P 31 , a dummy video signal dmy output from the output terminal Video ( 1 ) is output to the signal line S 1 . The video signal G 11 output from the output terminal Video ( 2 ) is written to the sub-pixel PG 11 via the signal line S 2 . The video signal W 21 output from the output terminal Video ( 3 ) is written to the sub-pixel PW 21 via the signal line S 5 . The video signal G 31 output from the output terminal Video ( 4 ) is written to the sub-pixel PG 31 via the signal line S 6 .

In the second period P 32 , the video signal W 11 output from the output terminal Video ( 1 ) is written to the sub-pixel PW 11 via the signal line S 3 . The video signal G 22 output from the output terminal Video ( 2 ) is written to the sub-pixel PG 22 via the signal line S 4 . The video signal W 31 output from the output terminal Video ( 3 ) is written to the sub-pixel PW 31 via the signal line S 7 . The video signal G 42 output from the output terminal Video ( 4 ) is written to the sub-pixel PG 42 via the signal line S 8 .

In the third period P 33 , the video signal B 12 output from the output terminal Video ( 1 ) is written to the sub-pixel PB 12 via the signal line S 1 . The video signal R 12 output from the output terminal Video ( 2 ) is written to the sub-pixel PR 12 via the signal line S 2 . The video signal B 32 output from the output terminal Video ( 3 ) is written to the sub-pixel PB 32 via the signal line S 5 . The video signal R 32 output from the output terminal Video ( 4 ) is written to the sub-pixel PB 32 via the signal line S 6 .

In the fourth period P 34 , the video signal B 22 output from the output terminal Video ( 1 ) is written to the sub-pixel PG 22 via the signal line S 3 . The video signal R 21 output from the output terminal Video ( 2 ) is written to the sub-pixel PR 21 via the signal line S 4 . The video signal B 42 output from the output terminal Video ( 3 ) is written to the sub-pixel PG 42 via the signal line S 7 .

In this configuration example, too, the same advantages as those of the configuration example shown in FIG. 13 can be obtained.

Next, an example of optimization of an alignment direction AP 1 of the first alignment film AL 1 and an alignment direction AP 2 of the second alignment film AL 2 on the reflective liquid crystal display panel PNL will be explained.

FIG. 16 is an illustration for explanation of a relationship between the alignment direction AP 1 of the first alignment film AL 1 and the alignment direction AP 2 of the second alignment film AL 2 . A shorter-side direction of the display device DSP is referred to as a first direction D 1 , a longer-side direction of the display device DSP is referred to as a second direction D 2 , and the first direction D 1 and the second direction D 2 are assumed to be orthogonal to each other. A clockwise angle between the first direction D 1 and the alignment direction AP 1 is represented by θ and a twist angle of the liquid crystal molecules defined by the alignment direction AP 1 and the alignment direction AP 2 is represented by θt. The driving IC chip IC is located on the negative side in the second direction D 2 . It is assumed that the main pixel PX 1 and the main pixel PX 2 are arranged in the first direction D 1 and the polarity of the main pixel PX 1 is opposite to the polarity of the main pixel PX 2 , in the display device DSP. Each of the main pixel PX 1 and the main pixel PX 2 includes the sub-pixels PR, PG, and PB arranged in the first direction D 1 .

In the display device DSP, the following experiment was conducted. That is, the reflectivity and the contrast ratio were measured in a situation that the light source LS was fixed on a positive side in the second direction D 2 shown in the figure, a light receiving portion RE was fixed on a negative side in the second direction D 2 shown in the figure, and the display device DSP was rotated clockwise in the X-Y plane defined by the first direction D 1 and the second direction D 2 . The twist angle θt was set at 70° and the angle θ corresponded to the angle of rotation set for rotation of the display device DSP. The measurement of the reflectivity and the contrast ratio was conducted within the range of the angle (or the angle of rotation) from 0 to 360°.

FIG. 17 shows experiment results and, more specifically, (A) shows a measurement result of the reflectivity (%) to the angle of rotation θ and (B) shows a measurement result of the contrast ratio to the angle of rotation θ. As shown in the figure, the angle of rotation at which a high reflectivity can be obtained does not necessarily correspond to the angle of rotation at which a high contrast ratio can be obtained. It was recognized based on the experiment results shown in the figure that the optical properties such as the reflectivity and the contrast ratio became preferable when the angle of rotation was greater than 150° and smaller than 180°. The angle of rotation θ was set at 158.5° as one of the conditions for optimizing the optical properties. In contrast, the column-inversion drive scheme in which the polarities of the main pixels adjacent in the first direction D 1 were different from each other was applied to the experiment. No display failure resulting from the disclination was recognized when the angle of rotation θ was set at 68.5°, but the display failure resulting from the disclination was recognized when the angle of rotation θ was set at 158.5°. In other words, the angle of rotation θ for optimizing the optical properties such as the reflectivity and the contrast ratio did not match the angle of rotation θ for suppressing the disclination.

In the present embodiment, a method of suppressing the disclination while setting the angle of rotation θ) (=158.5° for optimizing the optical properties will be reviewed. The disclination may often occur when the polarities of the pixels adjacent in the first direction D 1 are different from each other. For this reason, the disclination can be suppressed by applying the line-inversion drive scheme in which the polarities of the pixels arranged in the first direction D 1 are the same as each other. However, the line-inversion drive scheme has a problem in that the energy consumption is increased in comparison with the column-inversion drive scheme. In the present embodiment, as described above, the pixel layouts represented by those shown in FIG. 3 , FIG. 7 , FIG. 13 , FIG. 14 and the like are adopted and the pseudo-line-inversion drive scheme of arranging the polarities of the respective sub-pixels constituting the pixel lines is applied while substantially applying the column-inversion drive scheme. Since all the polarities of the sub-pixels constituting one pixel line thereby become the same as each other, an undesired lateral electric field between the adjacent sub-pixels can be suppressed and the disclination can also be suppressed. In other words, the display quality can be improved by optimizing the optical properties and suppressing the disclination. In addition, the energy consumption can be reduced by applying the column-inversion drive scheme to the embodiment.

FIG. 18 is a perspective view schematically showing another configuration of the liquid crystal display device DSP.

The liquid crystal display device DSP comprises an active-matrix liquid crystal display panel PNL, a driving IC chip IC which drives the liquid crystal display panel PNL, a backlight unit BL which illuminates the liquid crystal display panel PNL, a control module CM, flexible printed-circuit boards FPC 1 and FPC 2 , and the like.

The backlight unit BL is disposed on the back surface side of the liquid crystal display panel PNL. Various types of units are applicable as the backlight unit BL, but the detailed explanations of their structures are omitted. The flexible printed-circuit board FPC 1 connects the liquid crystal display panel PNL and the control module CM. The flexible printed-circuit board FPC 2 connects the backlight unit BL and the control module CM.

The liquid crystal display panel PNL is a transmissive display panel having a transmissive display function to display an image by selectively transmitting the light from the backlight unit BL by each main pixel PX or a transreflective display panel having the transmissive display function and the reflective display function. Any one of the above-explained examples can be applied as the layout of the sub-pixels included in each main pixel PX.

As described above, the present embodiment can provide the display device capable of improving the display quality and reducing the energy consumption.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.