Multi-gate and complementary varactors in FinFET process

This application is a continuation of U.S. patent application Ser. No. 13/801,089, entitled “Multi-Gate and Complementary Varactors in FinFET Process,” filed on Mar. 13, 2013, which application is incorporated herein by reference.

Varactors are commonly used in in various applications that require capacitors with variable capacitance values. Varactors are capacitors whole capacitance values change with the voltages applied on the capacitors. For example, in Voltage Controlled Oscillators (VCOs), varactors are widely used.

Varactors are commonly formed using Metal-Oxide-Semiconductor (MOS) devices. In a typical varactor, a gate of a MOS device is used as one capacitor plate of the varactor, and the source and drain of the MOS device are interconnected to form another capacitor plate of the varactor. The gate dielectric acts as the capacitor insulator. In the VCOs, low sensitivity and low KVCO (the gains of the VCOs) are typically needed, wherein the sensitivity is the ratio of the capacitance change to the change of the bias voltage applied on the gate.

For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1A, 1B, 1C, and 1D illustrate a perspective view and symbols of a varactor in accordance with some embodiments;

FIG. 1E illustrates C-V curves of a varactor in accordance with exemplary embodiments, wherein the C-V curves are compared to a C-V curve of a conventional varactor;

FIGS. 2A and 2B illustrate a perspective view and a top view, respectively, of a varactor in accordance with some embodiments, wherein the varactor includes two varactors, with the gates and the source/drain regions of the two varactors cross-connected;

FIGS. 3A and 3B illustrate a perspective view and a top view, respectively, of a varactor in accordance with some embodiments, wherein the varactor includes two varactors connected in parallel;

FIGS. 4A and 4B illustrate a perspective view and a top view, respectively, of a varactor in accordance with some embodiments, wherein the varactor includes two varactors connected in parallel, with the conductivity types of the source and drain regions of each of the two varactors being opposite to each other;

FIG. 5 illustrates the C-V curves of a plurality of varactors in accordance with some embodiments;

FIG. 6 illustrates the slopes of the capacitance of the plurality of varactors as functions of bias voltages; and

FIGS. 7 through 16 illustrate the perspective views of varactors in accordance with some exemplary embodiments.

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.

A varactor and the method of forming the same are provided in accordance with various exemplary embodiments. The variations and the operation of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 1A illustrates a perspective view of exemplary varactor 20 . In accordance with some embodiments, varactor 20 is formed based on a Fin Field-Effect Transistor (FinFET) structure, which includes semiconductor fin 22 . Fin 22 may be a top portion of semiconductor strip 23 , which is between opposite Shallow Trench Isolation (STI) regions 25 . Furthermore, semiconductor fin 22 is over the top surfaces of STI regions 25 . Gate dielectric 24 includes portions 24 A and 24 B, which are on the opposite sidewalls of fin 22 . Gate dielectric 24 may also include portion 24 C on a top surface of fin 22 . A portion of fin 22 overlapped by gate dielectric 24 forms the channel of the FinFET. Source and drain regions 26 are formed on the opposite sides of the channel, wherein one of the source and drain regions 26 is a source region, and the other one of source and drain regions 26 is a drain region. Throughout the description, the symbol “S/D” (as shown in FIG. 1A ) is used to indicate that the respective connected regions include a source region and a drain region.

Varactor 20 includes gates G 1 and G 2 . Gates G 1 and G 2 are physically separated from each other, and are electrically disconnected from each other. Accordingly, different voltages may be applied on gates G 1 and G 2 at the same time. In accordance with some embodiments, gates G 1 and G 2 are formed by forming a continuous gate, and etching a portion of the continuous gate directly over gate dielectric 24 . The sidewalls of gates G 1 and G 2 contact gate dielectric portions 24 A and 24 B, respectively. Gate G 1 forms first FinFET 20 A with fin 22 , wherein sidewall portion 24 A of gate dielectric 24 acts as the gate dielectric of the first FinFET 20 A, and source and drain regions 26 act as the source and drain regions of the first FinFET 20 A. Gate G 2 forms second FinFET 20 B with fin 22 , wherein sidewall portion 24 B of gate dielectric 24 acts as the gate dielectric of the second FinFET 20 B, and source and drain regions 26 also act as the source and drain regions of the second FinFET 20 B. In some embodiments, gates G 1 and G 2 do not include portions overlapping gate dielectric portion 24 C, and hence the first FinFET 20 A and the second FinFET 20 B are formed with the sidewalls portions of gate dielectric 24 , but not with top portion 24 C. In alternative embodiments, one or both gates G 1 and G 2 extend overlapping gate dielectric portion 24 C, and hence first FinFET 20 A and second FinFET 20 B are also formed with the top portion 24 C of gate dielectric 24 in addition to the sidewall portions.

The source and drain regions 26 are interconnected, for example, through contact plugs and metal lines in the overlying metal layers. The respective node is also denoted as “S/D.” Hence, FinFET 20 A forms a first varactor, and FinFET 20 B forms a second varactor. The first and the second varactors are connected in parallel to form varactor 20 .

FIG. 1B illustrates an equivalent circuit diagram of varactor 20 , wherein the first FinFET 20 A and second FinFET 20 B are illustrated as being connected in parallel. Capacitor 30 is the parasitic capacitor between gates G 1 and G 2 . In FIG. 1C , FinFETs 20 A and 20 B are represented by the symbols of varactor 20 A and 20 B. In FIG. 1D , the symbol of varactor 20 is illustrated, which is a three-terminal varactor, with gates G 1 and G 2 and source/drain S/D act as the three terminals.

FIG. 1E illustrates Capacitor-Voltage (C-V) curves 32 of varactor 20 ( FIG. 1A ), wherein the capacitance of varactor 20 is illustrated as a function of gate voltage Vctrl, which is the voltage applied on gate G 1 . A plurality of lines 32 are illustrated, wherein each of lines 32 is obtained by applying a voltage on gate G 2 . It is observed that when different voltages are applied on gate G 2 , the resulting C-V curves 32 are different from each other, and the higher the voltage on gate G 2 , the greater capacitance varactor 20 will have. FIG. 1E also illustrates line 34 , which is obtained from a conventional two-terminal varactor comprising a single gate, on which voltage Vctrl is applied. By comparing lines 32 with line 34 , it is observed that line 34 is steeper, indicating that the capacitance sensitivity of lines 32 are lower, wherein the capacitance sensitivity is the ratio of the change in capacitance to the change in gate voltage. Accordingly, the embodiments of the present disclosure have smaller capacitance sensitivities than conventional varactors.

FIGS. 2A and 2B illustrate a perspective view and a top view, respectively, of varactor 100 in accordance with some embodiments. Varactor 100 also includes gates G 1 and G 2 . Furthermore, varactor 100 includes fins 22 (including 22 A, 22 B, and 22 C). Fins 22 A and 22 B form FinFET 100 A with gate G 1 and gate dielectrics 124 A and 124 B, and fin 22 C forms FinFET 100 B with gate G 2 and gate dielectric 124 C. The source S 1 and drain D 1 of FinFET 100 A are interconnected, so that FinFET 100 A forms a varactor, which is also denoted as 100 A. The source S 2 and drain D 2 of FinFET 100 B are interconnected, so that FinFET 100 B forms a varactor, which is also denoted as 100 B. In addition, gate G 1 is connected to source S 2 and drain region D 2 to form one capacitor plate VAR_G of varactor 100 , and gate G 2 is connected to source S 1 and drain region D 1 to form the other capacitor plate VAR_S/D of varactor 100 .

Source and drain regions S 1 , S 2 , D 1 , and D 2 may be of the same conductivity type such as p-type or n-type. Each of varactors 100 A and 100 B may include any integer number of fins. In some embodiments, varactors 100 A and 100 B include different numbers of fins, as illustrated in FIGS. 2A and 2B . In alternative embodiments, varactors 100 A and 100 B include the same number of fins, wherein the fin number may be 1, 2, 3, 4, or more.

FIGS. 3A and 3B illustrate a perspective view and a top view, respectively, of varactor 200 . Varactor 200 also includes gates G 1 and G 2 . Furthermore, varactor 200 includes fins 22 (including 22 A, 22 B, and 22 C). Fins 22 A and 22 B form FinFET 200 A with gate G 1 and gate dielectrics 124 A and 124 B, and fin 22 C forms FinFET 200 B with gate G 2 and gate dielectric 124 C. The source S 1 and drain D 1 of FinFET 200 A are interconnected, so that FinFET 200 A forms a varactor, which is also denoted as 200 A. The source S 2 and drain D 2 of FinFET 200 B are interconnected, so that FinFET 200 B forms a varactor, which is also denoted as 200 B. In addition, gates G 1 and G 2 are interconnected to form one capacitor plate VAR_G of varactor 200 , and source S 1 and drain D 1 are connected to source S 2 and drain D 2 to form the other capacitor plate VAR_S/D of varactor 200 .

In some embodiments, source and drain regions S 1 , S 2 , D 1 , and D 2 are of the same conductivity type, which may be p-type or n-type. In alternative embodiments, source S 1 and drain D 1 may be of a conductivity type opposite to the conductivity type of source S 2 and drain D 2 . For example, source S 1 and drain D 1 may be of p-type, while source S 2 and drain D 2 may be of n-type. Alternatively, source S 1 and drain D 1 are of n-type, while source S 2 and drain D 2 are of p-type. Each of varactors 100 A and 100 B may include any integer number of fins. In some embodiments, varactors 100 A and 100 B include different numbers of fins, as illustrated in FIGS. 3A and 3B . In alternative embodiments, varactors 100 A and 100 B include the same number of fins, wherein the number may be 1, 2, 3, 4, or more.

FIGS. 4A and 4B illustrate a perspective view and a top view, respectively, of varactor 300 . Varactor 300 includes gates G 1 and G 2 that are interconnected to act as the capacitor plate VAR_G. Source S 1 and drain D 1 are connected to source S 2 and drain D 2 to form the other capacitor plate VAR_S/D of varactor 300 . These embodiments are similar to the embodiments in FIGS. 2A and 2B , except that source regions S 1 and S 2 are of the same conductivity type, which is opposite to the conductivity type of drain regions D 1 and D 2 . For example, source regions S 1 and S 2 may be of p-type, and drain regions D 1 and D 2 may be of n-type. Alternatively, source regions S 1 and S 2 may be of n-type, and drain regions D 1 and D 2 may be of p-type.

In accordance with some embodiments, as shown in the exemplary FIGS. 2A, 2B, 3A, 3B, 4A, and 4B , the size of the first varactor ( 100 A/ 200 A/ 300 A) is different from the size of the second varactor ( 100 B/ 200 B/ 300 B). This may be achieved, for example, by making the number of fins in the first varactor ( 100 A/ 200 A/ 300 A) to be different from the number of fins in the second varactor ( 100 B/ 200 B/ 300 B). With the numbers of fins in the two varactors being different from each other, the capacitance sensitivity of the respective varactor may be reduced. Furthermore, by adjusting the ratio of the numbers of fins in the two varactors, the capacitance sensitivity of the respective varactor may be adjusted to a desirable value. FIG. 5 illustrates the C-V curve of some exemplary varactors, wherein the capacitance of varactor 20 is illustrated as a function of bias voltage, which is the voltage applied on the two interconnected gates of the two varactors. The results may be obtained from the varactors having structures similar to what are shown in FIGS. 3A and 3B , wherein each of lines 36 A, 36 B, 36 C, and 36 D is generated from a varactor. Varactors 100 B/ 200 B/ 300 B and 100 A/ 200 A/ 300 A for generating each of lines 36 A, 36 B, 36 C, and 36 D include an n-type FinFET and a p-type FinFET, respectively. Lines 36 A, 36 B, 36 C, and 36 D are obtained from varactors that have different Fin Number Ratios (FNRs). FNR represents the ratio of the number of fins in varactor 100 B/ 200 B/ 300 B to the number of fins in the respective varactor 100 A/ 200 A/ 300 A ( FIGS. 3A and 3B ). In each of the varactors whose C-V curves are shown as lines 36 A, 36 B, 36 C, and 36 D, the total numbers of fins of varactors 100 B/ 200 B/ 300 B and 100 A/ 200 A/ 300 A is equal to 24. Line 36 A is obtained when the FNR is (1:0), and hence varactor 100 B/ 200 B/ 300 B includes 24 fins, and 100 A/ 200 A/ 300 A includes no fin, which means that no varactor is parallel connected to varactor 100 B/ 200 B/ 300 B. Lines 36 B, 36 C, and 36 D are obtained when the FNRs are adjusted to (2:1), (1:1), and (1:2), respectively. It is observed that with the change of FNR, the capacitance values are reduced, and the capacitance sensitivity is also reduced, as clearly observed from the less steep lines 36 B, 36 C, and 36 D. Furthermore, by comparing the capacitance values of lines 36 A, 36 B, and 36 C with line 36 A, it is observed that the actual capacitances of the varactors are proportional to the FNRs.

FIG. 6 illustrates the capacitance slope (calculated from FIG. 5 ) as a function of bias voltage, wherein the slope is the capacitance sensitivity. The slope is calculated as the ratio of the change in the capacitance to the change in bias voltage. It is clearly illustrated that with the FNR is reduced (with line 36 A having the highest FNR, and line 36 D having the lowest FNR), the capacitance sensitivity is also reduced.

In the above discussion, although FNRs equal to or smaller than 1 are used as examples, when FNRs are equal to or greater than 1, the same results may be obtained, wherein by enlarging the difference between the numbers of fins in the two interconnected varactors, the capacitance sensitivity of the resulting varactor may be reduced, regardless of which one of the interconnected varactors has more fins.

FIGS. 7 through 16 illustrate the variations of the varactors in accordance with the embodiments of the present disclosure. Please note that in each of FIGS. 7 through 16 , the conductivity types of the plurality of FinFETs may be the same as each other, or may be opposite to each other. The various components in FIGS. 7 through 15 such as the gate dielectrics (between gates and the respective fins) are not discussed in detail herein while they are illustrated.

FIG. 7 illustrates a one-finger-two-fin varactor 400 . Varactor 400 includes gates G 1 and G 2 that are aligned to a straight line, hence forming a finger. Fins 22 A and 22 B are parallel to each other, and form varactors 400 A and 400 B with gates G 1 and G 2 , respectively. The source and drain regions S/D of varactors 400 are interconnected, while gates G 1 and G 2 are disconnected from each other. In these embodiments, gate G 1 does not form any FinFET and any varactor with fin 22 B, and gate G 2 does not form any FinFET and any varactor with fin 22 A.

FIG. 8 illustrates one-finger-two-fin varactor 500 , which is similar to varactor 400 in FIG. 7 . In these embodiments, fins 22 A and 22 B are parallel to each other, and form varactors 500 A and 500 B with gates G 1 and G 2 , respectively. In addition, gate G 1 extends to contact a sidewall portion of gate dielectric 24 , and hence also forms a FinFET (which is also a varactor) with fin 22 B. The remaining portions are essentially the same as in FIG. 7 .

FIG. 9 illustrates varactor 600 , which is a one-finger-three-fin varactor including gates G 1 and G 2 that are aligned to a straight line, hence forming a finger. Fins 22 A and 22 B are parallel to each other, and form varactors 600 A with gate G 1 . Gate G 2 forms varactor 600 B with a sidewall portion of gate dielectric 24 . The source and drain regions of varactors 600 are interconnected, while gates G 1 and G 2 are physical disconnected from each other, and may be, or may not be, electrically disconnected from each other. In these embodiments, gate G 1 forms a FinFET (which is also a varactor) with fin 22 C, and gate G 2 does not form any FinFET and any varactor with fins 22 A and 22 B.

FIG. 10 illustrates a one-finger-three-fin varactor 700 , which includes gates G 1 and G 2 that are aligned to a straight line, hence forming a finger. Fins 22 A and 22 B are parallel to each other, and form varactor 700 A with gate G 1 . Fin 22 C forms varactor 700 B with gate G 2 . The source and drain regions of varactors 700 are interconnected, while gates G 1 and G 2 are physically and electrically disconnected from each other. In these embodiments, gate G 1 does not form any FinFET and any varactor with fin 22 C, and gate G 2 does not form any FinFET and any varactor with fins 22 A and 22 B.

FIG. 11 illustrates a two-finger-two-fin varactor 800 , which includes interconnected varactors 800 A, 800 B, and 800 C. Varactor 800 includes gates G 1 and G 2 A that are aligned to a straight line, hence forming a finger. Gate G 2 B forms another finger, which is not aligned to the same straight line that gates G 1 and G 2 A are aligned to. Gates G 2 A and G 2 B are interconnected to form gate G 2 of the respective varactor 800 . Gates G 1 , G 2 A, and G 2 B may be parallel to each other. Fins 22 A and 22 B are parallel to each other, and form varactor 800 C with gate G 2 B. Fin 22 A further forms varactor 800 A with gate G 1 . Fin 22 B further forms varactor 800 B with gate G 2 A. The source and drain regions of varactors 800 A, 800 B, and 800 C are interconnected as node S/D, while gates G 1 and G 2 are disconnected from each other.

FIG. 12 illustrates a two-finger-two-fin varactor 900 , which includes interconnected varactors 900 A, 900 B, 900 C, and 900 D. FIG. 12 is similar to FIG. 11 , except that each of gates G 1 and G 2 includes two physically separated and electrically interconnected gates, which form varactors with fins 22 A and 22 B.

FIG. 13 also illustrates a two-finger-two-fin varactor 1000 , which includes interconnected varactors 1000 A, 1000 B, and 1000 C. Varactor 1000 is similar to the varactor in FIG. 11 , except that gate G 1 extends to the sidewall of gate dielectric 24 to form another varactor. Besides, gate G 1 also forms a FinFET (which is also a varactor) with the sidewalls and the top surface of fin 22 A. Gate G 2 forms a varactor with a sidewall portion of gate dielectric 24 .

FIG. 14 illustrates a three-gate varactor 1100 , which includes interconnected varactors 1100 A, 1100 B, and 1100 C. Varactor 1100 is also a two-finger-two-fin varactor. In accordance with some embodiments, gates G 1 and G 2 form one finger. Gate G 3 forms another finger. Gates G 1 , G 2 , and G 3 are physically and electrically disconnected from each other, so that different voltages may be applied on gates G 1 , G 2 , and G 3 at the same time. The respective varactor 1100 is hence a four-terminal varactor.

FIG. 15 illustrates a four-gate varactor 1200 , which includes interconnected varactors 1200 A, 1200 B, 1200 C, and 1200 D. These embodiments are similar to the embodiments in FIG. 14 , except that gate G 1 of varactor 1200 includes portions in two fingers. The gates of varactors 1200 A, 1200 B, 1200 C, and 1200 D are physically disconnected from each other. The gates of varactors 1200 A and 1200 C are interconnected to form gate G 1 . The gate G 2 of varactor 1200 B and gate G 3 of varactor 1200 D are electrically disconnected from gates G 1 , and are electrically disconnected from each other.

FIG. 16 illustrates a three-gate varactor 1300 , which includes interconnected varactors 1300 A, 1300 B, and 1300 C including gates G 1 , G 2 , and G 3 , respectively. These embodiments are similar to the embodiments in FIG. 14 , except that gate G 1 of varactor 1300 extends to the sidewall of gate dielectric 24 to form another varactor.

In accordance with embodiments of the present disclosure, by forming varactors that include multiple gates and/or multiple fins, the capacitance sensitivity of the varactors may be reduced. In addition, better Q factor may be achieved. The embodiments of the present disclosure are compatible with FinFET formation processes, and there is no additional process steps required.

In accordance with some embodiments, a varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.

In accordance with other embodiments, a varactor includes a first semiconductor fin, and a gate dielectric, which includes a first sidewall portion on a first sidewall of the first semiconductor fin, and a second sidewall portion on a second sidewall of the first semiconductor fin. The varactor further includes a first gate in contact with the first sidewall portion of the gate dielectric, and a second gate in contact with the second sidewall portion of the gate dielectric. The first gate, the first sidewall portion of the gate dielectric, and the first sidewall of the first semiconductor fin form portions of a first varactor. The second gate is physically disconnected from the first gate. The second gate, the second sidewall portion of the gate dielectric, and the second sidewall of the first semiconductor fin form portions of a second varactor. A source and a drain region are on opposite ends of the gate dielectric, wherein the source and the drain regions are interconnected to form the first varactor and the second varactor.

In accordance with yet other embodiments, a varactor includes a first FinFET and a second FinFET connected to the first FinFET to form the varactor. The first FinFET includes a plurality of semiconductor fins, a first gate over the plurality of semiconductor fins, and a first source and a first drain comprising end portions of the plurality of semiconductor fins. The first source is electrically connected to the first drain. The second FinFET includes at least one semiconductor fin, a second gate over the at least one semiconductor fin, and a second source and a second drain comprising end portions of the at least one semiconductor fin. The second source is electrically connected to the second drain. A total number of fins in the first FinFET is greater than a total number of fins in the second FinFET.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.