Power converter

1. Technical Field

The present disclosure relates to a power converter for converting power.

2. Description of the Related Art

Japanese Unexamined Patent Application Publication No. 2014-209841 discloses an inverter device including an inverter and a clamper.

In the related art, it is desirable to reduce common-mode noise.

In one general aspect, the techniques disclosed here feature a power converter including first through sixth switching elements, first through tenth diodes, first through fourth capacitors, and a controller. A second end of the first switching element and a first end of the second switching element are connected to each other at a first node. A second end of the third switching element and a first end of the fourth switching element are connected to each other at a second node. A first end of the first switching element and a first end of the third switching element are connected to each other at a third node. A second end of the second switching element and a second end of the fourth switching element are connected to each other at a fourth node. A second end of the fifth switching element and the first node are connected to each other at a fifth node. A second end of the sixth switching element and the second node are connected to each other at a sixth node. A first end of the fifth switching element and a first end of the sixth switching element are connected to each other. An input voltage is input between the third node and the fourth node. The controller controls ON/OFF states of the first through sixth switching elements to convert the input voltage into an output voltage. The output voltage is output from between the fifth node and the sixth node. The first through fourth diodes are connected inversely in parallel with the first through fourth switching elements, respectively. The fifth diode is connected in parallel with the fifth switching element. The sixth diode is connected in parallel with the sixth switching element. The first through fourth capacitors are connected in parallel with the first through fourth switching elements, respectively. The seventh diode is connected in series with the first capacitor and is connected inversely in parallel with the first switching element. The eighth diode is connected in series with the second capacitor and is connected in parallel with the second switching element. The ninth diode is connected in series with the third capacitor and is connected inversely in parallel with the third switching element. The tenth diode is connected in series with the fourth capacitor and is connected in parallel with the fourth switching element.

According to an embodiment of the present disclosure, it is possible to reduce common-mode noise.

Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and/or advantages may be individually obtained by the various embodiments and features of the specification and drawings, which need not all be provided in order to obtain one or more of such benefits and/or advantages.

FIG. 1 is a circuit diagram of the schematic configuration of a power converter according to an embodiment;

FIG. 2 is a timing chart illustrating a switching operation in this embodiment;

FIG. 3 illustrates a state in which a common-mode voltage is generated;

FIG. 4 illustrates a state in which a common-mode voltage is generated; and

FIG. 5 is a circuit diagram of the schematic configuration of a power converter, which is a modified example of this embodiment.

An embodiment of the present disclosure will be described below with reference to the accompanying drawings.

The viewpoints of the present inventor will first be discussed below.

The operation of an output-clamp inverter device is different from that of the other types of inverter devices. Accordingly, in the output-clamp inverter device, common-mode noise is more likely to occur.

In particular, due to a variation in the timing at which switching elements are turned OFF, common-mode components are generated in the output U phase and W phase of the inverter of the inverter device. This causes the occurrence of radio-frequency electromagnetic noise.

Noise may be reduced by, for example, connecting a capacitor in parallel with a switching element and by decreasing the switching speed of the switching element.

That is, if the switching speed is decreased by the provision of a capacitor, radio-frequency components contained in a pulsating voltage are decreased. It is thus possible to reduce noise which conducts to the outside of the inverter device.

On the other hand, however, if the switching speed is decreased, switching loss is increased, which impairs the efficiency. Additionally, a longer dead time is required, which also impairs the controllability of the inverter device.

In view of the above-described viewpoints, the present inventor has conceived the configuration of an embodiment of the present disclosure.

Embodiment

FIG. 1 is a circuit diagram of the schematic configuration of a power converter 1000 according to an embodiment.

The power converter 1000 of this embodiment has a function of converting a direct current (DC) voltage into an alternating current (AC) voltage, for example.

The power converter 1000 includes an inverter 2 and a clamper 5 .

More specifically, the power converter 1000 includes first through sixth switching elements Q 1 through Q 6 , first through tenth diodes D 1 through D 10 , first through fourth capacitors C 1 through C 4 , and a controller 6 .

A second end (for example, an emitter terminal) of the first switching element Q 1 and a first end (for example, a collector terminal) of the second switching element Q 2 are connected to each other at a first node a 1 .

A second end (for example, an emitter terminal) of the third switching element Q 3 and a first end (for example, a collector terminal) of the fourth switching element Q 4 are connected to each other at a second node a 2 .

A first end (for example, a collector terminal) of the first switching element Q 1 and a first end (for example, a collector terminal) of the third switching element Q 3 are connected to each other at a third node a 3 .

A second end (for example, an emitter terminal) of the second switching element Q 2 and a second end (for example, an emitter terminal) of the fourth switching element Q 4 are connected to each other at a fourth node a 4 .

A second end (for example, an emitter terminal) of the fifth switching element Q 5 and the first node al are connected to each other at a fifth node a 5 .

A second end (for example, an emitter terminal) of the sixth switching element Q 6 and the second node a 2 are connected to each other at a sixth node a 6 .

A first end (for example, a collector terminal) of the fifth switching element Q 5 and a first end (for example, a collector terminal) of the sixth switching element Q 6 are connected to each other.

An input voltage is input between the third and fourth nodes a 3 and a 4 .

The controller 6 controls the ON/OFF states of the first through sixth switching elements Q 1 through Q 6 to convert the input voltage into an output voltage. The input voltage is converted into an output voltage by a control of the ON/OFF states of the first through sixth switching elements Q 1 through Q 6 .

The output voltage is output from between the fifth and sixth nodes a 5 and a 6 .

The first through fourth diodes D 1 through D 4 are connected inversely in parallel with the first through fourth switching elements Q 1 through Q 4 , respectively.

The fifth diode D 5 is connected in parallel with the fifth switching element Q 5 .

The sixth diode D 6 is connected in parallel with the sixth switching element Q 6 .

The first through fourth capacitors C 1 through C 4 are connected in parallel with the first through fourth switching elements Q 1 through Q 4 , respectively.

The seventh diode D 7 is connected in series with the first capacitor C 1 and is connected inversely in parallel with the first switching element Q 1 .

The eighth diode D 8 is connected in series with the second capacitor C 2 and is connected in parallel with the second switching element Q 2 .

The ninth diode D 9 is connected in series with the third capacitor C 3 and is connected inversely in parallel with the third switching element Q 3 .

The tenth diode D 10 is connected in series with the fourth capacitor C 4 and is connected in parallel with the fourth switching element Q 4 .

With the above-described configuration, it is possible to reduce common-mode noise while an increase in the switching loss is being suppressed.

The term “being connected inversely in parallel with” means that predetermined two elements are connected in parallel with each other, but their conducting directions are opposite.

The above-described input voltage is, for example, a DC voltage. The input voltage may be supplied from a DC voltage source 3 .

The above-described output voltage is, for example, an AC voltage. The output voltage may be supplied to a load 4 .

FIG. 2 is a timing chart illustrating a switching operation in this embodiment.

A period Tp 1 is a period for which the first and fourth switching elements Q 1 and Q 4 are ON and the fifth switching element Q 5 is OFF.

A period Tp 2 is a period for which the first and fourth switching elements Q 1 and Q 4 are OFF and the fifth switching element Q 5 is ON.

A period Tn 1 is a period for which the second and third switching elements Q 2 and Q 3 are ON and the sixth switching element Q 6 is OFF.

A period Tn 2 is a period for which the second and third switching elements Q 2 and Q 3 are OFF and the sixth switching element Q 6 is ON.

The controller 6 performs control so that, during a certain period Tp, the second and third switching elements Q 2 and Q 3 will be OFF and the sixth switching element Q 6 will be ON. During this period Tp, the controller 6 alternately repeats the periods Tp 1 and Tp 2 while modulating the length of the period Tp 1 .

The controller 6 also performs control so that, during another certain period Tn, the first and fourth switching elements Q 1 and Q 4 will be OFF and the fifth switching element Q 5 will be ON. During this period Tn, the controller 6 alternately repeats the periods Tn 1 and Tn 2 while modulating the length of the period Tn 1 .

According to the above-described switching operation, a DC voltage, which is the input voltage, is converted into an AC voltage, which is the output voltage.

As described above, in the power converter 1000 , the switching elements to be ON are changed according to the polarity of the output AC voltage.

When the output voltage is at a positive polarity, the first and fourth switching elements Q 1 and Q 4 and the fifth switching element Q 5 are complementarily switched with the provision of a dead time. During this time period, the second and third switching elements Q 2 and Q 3 are maintained in the OFF state, while the sixth switching element Q 6 is maintained in the ON state.

When the output voltage is at a negative polarity, the second and third switching elements Q 2 and Q 3 and the sixth switching element Q 6 are complementarily switched with the provision of a dead time. During this time period, the first and fourth switching elements Q 1 and Q 4 are maintained in the OFF state, while the fifth switching element Q 5 is maintained in the ON state.

The controller 6 may create control pulses on the basis of a triangle-wave-and-sine-wave control technique, as shown in FIG. 2 .

According to the above-described pulse width modulation (PWM) control, the controller 6 changes (switches) the ON/OFF states of the first through fourth switching elements Q 1 through Q 4 of the inverter 2 and the fifth and sixth switching elements Q 5 and Q 6 of the clamper 5 .

With this switching operation, the controller 6 is able to apply a current or a voltage which approximates to an AC waveform to, for example, the load 4 .

PWM control performed by the controller 6 may be implemented by software control or by an analog circuit using a comparator. The controller 6 may be constituted by, for example, a processor (such as a central processing unit (CPU) or a micro-processing unit (MPU)) and a memory. In this case, the processor may perform a control method disclosed in an embodiment of the present disclosure by reading and executing a program stored in the memory.

FIG. 3 illustrates a state in which a common-mode voltage is generated.

The state shown in FIG. 3 is a state where there is no variation in the characteristics of switching elements (that is, the state under ideal conditions).

FIG. 3( a ) illustrates a voltage state at the first node 1 a and that at the second node a 2 when the first and fourth switching elements Q 1 and Q 4 are being turned OFF.

FIG. 3( b ) illustrates the voltage state of common-mode noise corresponding to the voltage states shown in FIG. 3( a ) .

Immediately before the state in which the first and fourth switching elements Q 1 and Q 4 are turned OFF (that is, the first and fourth switching elements Q 1 and Q 4 are ON), a current flows in a path constituted by the positive electrode of the DC voltage source 3 , the first switching element Q 1 , a first reactor L 1 , the load 4 , a second reactor L 2 , the fourth switching element Q 4 , and the negative electrode of the DC voltage source 3 in this order.

At a time t 11 shown in FIG. 3 , the transition of the U phase and the W phase starts, that is, the first and fourth switching elements Q 1 and Q 4 start being turned OFF. Then, the first and second reactors L 1 and L 2 serve as current supply sources, and parasitic capacitance in the first through fourth switching elements Q 1 through Q 4 is charged and discharged. As a result, the voltage at the first node al drops and the voltage at the second node a 2 rises.

At a time t 12 shown in FIG. 3 , the first node al and the second node a 2 are at the same potential. Then, the fifth diode D 5 conducts. As a result, the current in the first and second reactors L 1 and L 2 flows in a path constituted by the first reactor L 1 , the load 4 , the second reactor L 2 , the sixth switching element Q 6 , and the fifth diode D 5 in this order.

After the lapse of a dead time after the first and fourth switching elements Q 1 and Q 4 have started being turned OFF, the fifth switching element Q 5 is turned ON. Then, the current in the first and second reactors L 1 and L 2 flows in a path constituted by the first reactor L 1 , the load 4 , the second reactor L 2 , the sixth switching element Q 6 , and the fifth switching element Q 5 in this order. Then, the switching operation has been completed.

In this manner, as shown in FIG. 3 , the instant that the first and second nodes al and a 2 are at the same potential, the clamper 5 (fifth switching element Q 5 ) is turned ON. Accordingly, the common-mode voltage does not fluctuate. That is, if the operation is performed under the ideal conditions, the common-mode voltage at the timing at which the first and second nodes a 1 and a 2 are at the same potential is 0.

FIG. 4 illustrates a state in which a common-mode voltage is generated.

The state shown in FIG. 4 is a state where there is a variation in the characteristics of switching elements (that is, the conditions are not ideal).

FIG. 4( a ) illustrates a voltage state at the first node 1 a and that at the second node a 2 when the first and fourth switching elements Q 1 and Q 4 are being turned OFF.

FIG. 4( b ) illustrates the voltage state of common-mode noise corresponding to the voltage states shown in FIG. 4( a ) .

At a time t 21 shown in FIG. 4 , the transition of the W phase starts.

At a time t 22 shown in FIG. 4 , the transition of the U phase starts.

That is, since there is a variation in the characteristics of switching elements, there is a predetermined time difference in the transition timing between the U phase and the W phase.

At a time t 23 shown in FIG. 4 , the clamper 5 is turned ON with a common-mode voltage.

From a time t 23 to a time t 24 , the voltage gradually attenuates because of the parasitic capacitance.

With the above-described switching operation, a common-mode voltage is generated, as shown in FIG. 4( b ) .

In this manner, due to a variation in the characteristics of switching elements, a common-mode voltage is generated.

The power converter 1000 is effective only for suppressing single-polarity common-mode noise.

For example, if the common-mode voltage at the load 4 is higher than that at the DC voltage source 3 , the seventh through tenth diodes D 7 through D 10 are changed to the conducting state, and the capacitors C 1 through C 4 serve to suppress noise.

If the common-mode voltage at the load 4 is lower than that at the DC voltage source 3 , a reverse voltage is applied to the seventh through tenth diodes D 7 through D 10 , which makes it difficult for a current to flow.

For example, if the output voltage is at a positive polarity, the first and fourth switching elements Q 1 and Q 4 are switched ON.

The capacitor C 1 including parasitic capacitance connected in parallel with the first switching element Q 1 is charged, while the capacitor C 2 including parasitic capacitance connected in parallel with the second switching element Q 2 is discharged. As a result, the first switching element Q 1 has been turned OFF.

In this case, a reverse voltage is being applied to the seventh and eighth diodes D 7 and D 8 . Accordingly, the charging and discharging of the first and second capacitors C 1 and C 2 does not contribute to the switching operation.

Accordingly, the switching speed is not influenced by the first and second capacitors C 1 and C 2 , that is, the switching speed is not decreased.

As described above, the power converter 1000 is effective for suppressing the occurrence of common-mode noise caused by a variation in the characteristics of components. That is, it is possible to suppress noise without delaying the switching time. Thus, conduction noise can be reduced without increasing switching loss or impairing the controllability.

In the above-described embodiment, as the switching elements, transistors, for example, insulated gate bipolar transistors (IGBTs), may be used.

The power converter 1000 may include the first reactor L 1 and the second reactor L 2 .

In this case, as shown in FIG. 1 , the first reactor L 1 may be disposed between the fifth node a 5 and the output side (load 4 ).

As shown in FIG. 1 , the second reactor L 2 may be disposed between the sixth node a 6 and the output side (load 4 ).

By the provision of the first and second reactors L 1 and L 2 , the current is less likely to change.

The controller 6 may change a state of the fourth switching element Q 4 from an ON state to an OFF state, at a timing which shifted by a predetermined time from a timing at which the first switching element Q 1 is changed from an ON state to an OFF state.

The controller 6 may also change a state of the third switching element Q 3 from an ON state to an OFF state, at a timing which shifted by a predetermined time from a timing at which the second switching element Q 2 is changed from an ON state to an OFF state.

With the above-described configuration, a variation in the timing at which the switching elements are turned OFF can be controlled. It is thus possible to control the polarity of common-mode noise.

The controller 6 may include a drive signal generator and a signal delayer.

The drive signal generator generates first through fourth drive signals for controlling the ON/OFF states of the first through fourth switching elements Q 1 through Q 4 , respectively.

The signal delayer delays at least one of the first through fourth drive signals so as to generate a lag of the above-described predetermined time.

As described above, it is possible to control a variation in the timing at which the switching elements are turned OFF with a simple configuration.

FIG. 5 is a circuit diagram of the schematic configuration of a power converter 1100 , which is a modified example of the above-described embodiment.

In the power converter 1100 , the controller 6 includes a drive signal generator 10 and first and second signal delayers 8 and 9 .

The drive signal generator 10 generates first through sixth drive signals for controlling the ON/OFF states of the first through sixth switching elements Q 1 through Q 6 , respectively.

The first and second signal delayers 8 and 9 add a predetermined delay time to the signals output from the drive signal generator 10 .

The first and second signal delayers 8 and 9 may be implemented by software control or by an analog circuit.

With the above-described configuration, the waveform shape of a common-mode voltage which is determined by the characteristics of components can be controlled in accordance with the delay time added by the first and second signal delayers 8 and 9 .

That is, it is possible to control the polarity of common-mode noise produced during the switching operation by using the first and second signal delayers 8 and 9 .

For example, the first signal delayer 8 may delay the timing at which the first switching element Q 1 is turned OFF to be later than that at which the fourth switching element Q 4 is turned OFF. In this case, only a positive common-mode voltage is generated.

Conversely, the first signal delayer 8 may hasten the timing at which the first switching element Q 1 is turned OFF to be earlier than that at which the fourth switching element Q 4 is turned OFF. In this case, only a negative common-mode voltage is generated.

The operation of the second signal delayer 9 is similar to that of the first signal delayer 8 , and a detailed explanation thereof will thus be omitted.

With the above-described configuration, it is possible to control a variation in the timing at which switching elements are turned OFF. This makes it possible to fix the polarity of a common-mode voltage at a desired polarity. For example, the controller 6 may perform control so that the common-mode voltage at the load 4 will be higher than that at the DC voltage source 3 . Then, the seventh through tenth diodes D 7 through D 10 are changed to the conducting state, and the capacitors C 1 through C 4 serve to suppress noise.

As shown in FIG. 5 , the controller 6 may include an amplifier circuit for amplifying a control signal (drive signal) output from the drive signal generator 10 to a predetermined voltage.

In the above-described embodiment of the present invention, the “connection between two elements” (e.g., one element connects to another element) may mean, not only a direct connection, but also an electrical connection and a connection in which an element (e.g., a wiring, a resistor, and the like, which do not impair the functions of the embodiments) is inserted therebetween.

The power converter according to an embodiment of the present disclosure may be used in, for example, a power conditioner and a rotor driving inverter.

While the present disclosure has been described with respect to exemplary embodiments thereof, it will be apparent to those skilled in the art that the disclosure may be modified in numerous ways and may assume many embodiments other than those specifically described above. Accordingly, it is intended by the appended claims to cover all modifications of the disclosure that fall within the true spirit and scope of the disclosure.