Semiconductor device and manufacturing method thereof

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-049850, filed Mar. 12, 2015, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a semiconductor device and a manufacturing method of the semiconductor device.

In recent years, as semiconductor devices have been miniaturized, internal wirings in these devices have also been miniaturized. As the wirings have become smaller, a narrow line effect in which scattering effects caused by interfacial and grain boundaries in copper wirings of the related art begins to predominate, and wiring resistance consequently increases appreciably.

For this reason, wirings in the semiconductor devices according to the related art often fail to satisfy device specifications and/or meet performance targets. Therefore, it is preferable to use a material which is hardly affected by narrow line effects. However, since materials in which narrow line effects are hardly apparent generally have a high bulk specific resistance, when the same material is used for a wide wiring as used for narrow wiring, the wide wiring will have a high resistance and overall device performance may not be substantially improved.

FIGS. 1A and 1B are diagrams which show an example of a configuration of a semiconductor device according to a first embodiment.

FIGS. 2A and 2B to FIGS. 6A and 6B depict processes in a manufacturing method of the semiconductor device according to the first embodiment.

FIGS. 7A and 7B to FIGS. 9A and 9B depict processes in a manufacturing method of a semiconductor device according to a second embodiment.

FIGS. 10A and 10B are diagrams which show an example of a configuration of a semiconductor device according to a third embodiment.

FIG. 11 is a cross-sectional view which shows another example of the cross-section of the semiconductor device, focused on an area Z of FIG. 10A .

FIG. 12 is a diagram which shows an example of a configuration of wirings according to a fourth embodiment.

FIGS. 13A to 13D depict processes in a manufacturing method of a semiconductor device according to the fourth embodiment.

FIGS. 14A to 14D depict additional processes in a manufacturing method of the semiconductor device according to the fourth embodiment.

FIGS. 15A to 15D depict additional processes in a manufacturing method of the semiconductor device according to the fourth embodiment.

FIGS. 16A to 16D depict additional processes in a manufacturing method of the semiconductor device according to the fourth embodiment.

FIGS. 17A to 17D depict additional processes in a manufacturing method of the semiconductor device according to the fourth embodiment.

FIGS. 18A and 18B are diagrams which explain the process of a manufacturing method of the semiconductor device according to the fourth embodiment.

FIGS. 19A and 19B are diagrams which show the process of a manufacturing method of the semiconductor device according to the fourth embodiment.

In general, according to one embodiment, a semiconductor device includes a first wiring comprising a first conductive material on a semiconductor layer, a second wiring comprising the first conductive material on the semiconductor layer, a third wiring comprising a second conductive material different from the first conductive material, and an insulation film on the semiconductor layer between the first wiring and the second wiring and between the second wiring and the third wiring. The second wiring is provided on at least two sides of the third wiring, and a mean free path of free electrons in the first conductive material is shorter than a mean free path of free electrons in the second conductive material, or the first conductive material shows quantized conduction and the second conductive material does not show quantized conduction. The first wiring, the second wiring, the third wiring, and the insulation film are in one wiring layer provided on the semiconductor layer.

Hereinafter, example embodiments are described with reference to the drawings.

First Embodiment

FIGS. 1A and 1B depict a semiconductor according to a first embodiment. FIG. 1A is a plan view which shows a top of the semiconductor device 100 . FIG. 1B is a cross-sectional view taken along line X-X of FIG. 1A .

As shown in FIGS. 1A and 1B , the semiconductor device 100 includes a semiconductor substrate S 1 , a semiconductor layer S 2 , a first wiring L 1 , a second wiring L 2 , a third wiring L 3 , an insulation film IN, a first insulation film IN 1 , and a second insulation film IN 2 .

The semiconductor substrate S 1 is, for example, a silicon substrate.

The semiconductor layer S 2 is provided on the semiconductor substrate S 1 . The semiconductor layer S 2 is a device layer in which components of a semiconductor device element, such as a MOS transistor, are provided.

The first wiring L 1 is provided on the semiconductor layer S 2 . The first wiring L 1 is formed of a first conductive material.

The first wiring L 1 is arranged in a memory cell area A 1 of, for example, a NAND-type flash memory.

In addition, the insulation film IN is provided on the semiconductor layer S 2 . The insulation film IN is provided between adjacent first wirings L 1 .

The second wiring L 2 is provided on the semiconductor layer S 2 . The second wiring L 2 is also formed of first conductive material.

Here, for example, as shown in FIGS. 1A and 1B , the second wiring L 2 is provided to surround a periphery of the second insulation film IN 2 on the semiconductor layer S 2 .

The third wiring L 3 is provided to extend in a first direction D 1 on the semiconductor layer S 2 . The third wiring L 3 has a line width W 3 (a width in a second direction D 2 orthogonal to the first direction D 1 ) greater than a line width W 1 (a width in the second direction D 2 ) of the first wiring L 1 . The third wiring L 3 comprises a second conductive material that is different from the first conductive material.

The second wiring L 2 is provided on both sides of the third wiring L 3 in the second direction D 2 and the also the first direction D 1 , and the third wiring L 3 is between different portions of the second wirings L 2 . Here, as shown in FIGS. 1A and 1B , the third wiring L 3 is surrounded by the second wirings L 2 on the semiconductor layer S 2 in a D 1 -D 2 plane.

The second wiring L 2 and the third wiring L 3 are disposed, for example, in a peripheral circuit region A 2 of a NAND-type flash memory.

The first insulation film IN 1 is provided on the semiconductor layer S 2 . The first insulation film IN 1 is between the first wiring L 1 and the second wiring L 2 in the second direction D 2 .

The second insulation film IN 2 is provided on the semiconductor layer S 2 . The second insulation film IN 2 is between the second wiring L 2 and the third wiring L 3 so as to be adjacent to and to surround the periphery of the third wiring L 3 .

The second insulation film IN 2 is provided to surround the third wiring L 3 on the semiconductor layer S 2 , that is, in a D 1 -D 2 plane. In a particular example, the second insulation film IN 2 may surround the periphery of the third wiring L 3 with a constant width from a side surface of the third wiring L 3 —that is, the distance from the third wiring L 3 to the second wiring L 2 may be a fixed distance.

The first wiring L 1 , the second wiring L 2 , the third wiring L 3 , the first insulation film IN 1 , and the second insulation film IN 2 are provided in a wiring layer Y on the semiconductor layer S 2 ( FIG. 1B ).

Here, an electrical conductivity of the first conductive material results from free, mobile electrons. The first conductive material is a material which has an electrical conduction mechanism due to free electrons whose mean free path is shorter than a mean free path of free electrons in the second conductive material, or the first conductive material is a material which exhibits quantized conduction.

First, a second metal such as one of Cu and Al, or a second alloy which includes the second metal as a main component is selected as a material for the second conductive material. The second conductive material has a low bulk specific resistance.

In this case, the first conductive material, which is a material having an electrical conduction mechanism due to free electrons whose mean free path is shorter than the mean free path of electrons in the second conductive material, is, for example, a first metal such as any one of Rh, Mo, A 1 (though Al should be used as the first metal only when the second conductive material is Cu), Ru, Cd, W, Ir, Zn, Ga, Pt, Pd, Nb, In, Co, Ni, Cr, Tc, Os, Ta, Fe, Sn, Tl, and Re; or a first alloy which includes the first metal as a main component; or a silicide of the first metal or the first alloy. In particular, W, Mo, and Ru are materials which are hardly affected by a narrow line effect and also have low bulk specific resistances. According to the narrow line effect, resistivity increases as a result of electron scattering at grain boundaries and/or interfacial.

A first conductive material which exhibits quantized conduction is graphene.

In this manner, the semiconductor device 100 has a wiring material (the first conductive material), which is not significantly affected by the narrow line effect, to narrow wiring (e.g., the first wiring L 1 ) which might be susceptible to the narrow line effect, and has a wiring material (the second conductive material) having a low specific resistance for a wide wiring (e.g., the third wiring L 3 ).

Accordingly, the semiconductor device 100 may obtain improved electrical characteristics.

Here, an example of a manufacturing method of the semiconductor device 100 will be described. FIGS. 2A to 6B are diagrams which show processes in the manufacturing method of the semiconductor device 100 according to the first embodiment. FIGS. 2A, 3A, 4A, 5A, and 6A are top views focused on a region in a periphery of line X-X (see FIG. 1A ). FIGS. 2B, 3B, 4B, 5B, and 6B are sectional views which show a cross-section of the semiconductor device 100 taken along line X-X of FIG. 1A at points in the manufacturing method.

First, as one example, a conductive film made from the first conductive material is formed on the semiconductor layer S 2 . Thereafter, using, for example, a lithography technique and a reactive ion etching (RIE) method, the conductive film is selectively etched to produce the first wiring L 1 and the second wiring L 2 as depicted. An additive process rather than a subtractive process maybe adopted for formation of the first wiring L 1 and the second wiring L 2 . Accordingly, the first wiring L 1 containing the first conductive material and the second wiring L 2 containing the first conductive material are formed on the semiconductor layer S 2 ( FIGS. 2A and 2B ).

Next, an insulation film 101 is formed on the semiconductor layer S 2 in which the first wiring L 1 and the second wiring L 2 have been formed, using, for example, a chemical vapor deposition (CVD) method ( FIGS. 3A and 3B ).

Then, the insulation film 101 is anisotropically etched by a reactive ion etching (RIE) method. Here, the insulation film 101 is etched until a surface of the semiconductor layer S 2 of a region in which the third wiring L 3 is to be formed is exposed.

Accordingly, both the first insulation film IN 1 positioned between the first wiring L 1 and the second wiring L 2 and the second insulation film IN 2 adjacent to the second wiring L 2 are formed on the semiconductor layer S 2 ( FIGS. 4A and 4B ). At this time, the insulation film IN between the adjacent first wirings L 1 is also formed.

A width of an opening 110 (see FIG. 4A ) in the second insulation film IN 2 in a second direction is the same as a width W 3 of the third wiring L 3 .

Then, the second conductive material (for example, Cu or Al) described above is deposited on the semiconductor layer S 2 so as to be embedded in or fill the opening 110 of the second insulation film IN 2 to form a conductive film 102 ( FIGS. 5A and 5B ).

Next, for example, planarization is performed to remove the overfill portions of the conductive film 102 on the first and the second insulation films IN 1 and IN 2 and the first and the second wirings L 1 and L 2 using a chemical mechanical polishing (CMP) method. Here, since the CMP processing is controlled by a processing time, an upper portion of the first and the second insulation films IN 1 and IN 2 and the first and the second wirings L 1 and L 2 may be partially removed,—that is, the CMP process need not be stopped exactly at the original upper surface of the insulation films IN, IN 1 , IN 2 , or the first wiring L 1 and second wiring L 2 , but rather the substrate may be over polished to some extent with portions of these elements being removed.

Accordingly, the third wiring L 3 which has a line width W 3 greater than a line width W 1 of the first wiring L 1 is formed on the semiconductor layer S 2 ( FIGS. 6A and 6B ). At this time, as shown in FIGS. 6A and 6B , the second insulation film IN 2 is between the second wiring L 2 and the third wiring L 3 and adjacent to the third wiring L 3 so as to surround the third wiring L 3 in a D 1 -D 2 plane.

Through the processes described above, the semiconductor device 100 shown in FIGS. 1A and 1B is formed.

The CMP processing may be finished when the upper portions of the first and the second insulation films IN 1 and IN 2 and the first and the second wirings L 1 and L 2 are first exposed. In this case, an upper portion of the opening 110 of the second insulation film IN 2 is wider than a bottom of the opening. That is, a width of an upper portion of the third wiring L 3 may be wider than a width of a lower portion of the third wiring L 3 . Accordingly, it is possible to reduce resistance of the third wiring L 3 .

Here, in the related art, for example, two or more lithography processes would be required so as to use two different types of wiring materials for a narrow wiring and a wide wiring within the same wiring layer. For this reason, one would expect a decrease in device yield due to poor alignment of the multiple lithography steps or additional handling associated with the extra processing steps, which would result in higher device costs due to lower yield and additional processing steps.

On the other hand, in a manufacturing method of a semiconductor device according to the present embodiment, as described above, a separate lithography process for the third wiring L 3 is omitted. Therefore, manufacturing costs are reduced. Furthermore, the third wiring L 3 is formed by self-aligned process with respect to the patterns of the first and the second wirings L 1 and L 2 . Therefore, alignment accuracy and the yield may be expected to be improved.

As described above, by the semiconductor device according to the first embodiment, it is possible to obtain improved electrical characteristics.

In particular, by the manufacturing method of a semiconductor device according to the first embodiment, it is possible to improve yield while reducing manufacturing costs.

Second Embodiment

In a second embodiment, another example of a manufacturing method of a semiconductor device will be described. A semiconductor device according to the second embodiment has substantially the same configuration as the semiconductor device 100 according to the first embodiment except for a detailed configuration (wiring structure) of the first and the second wirings. That is, a configuration of the semiconductor device according to the second embodiment is the same as that of FIGS. 1A and 1B in the first embodiment except for the detailed configuration (wiring structure) of the first and the second wirings.

Here, FIGS. 7A to 9B are diagrams which show examples of processes in the manufacturing method of the semiconductor device according to the second embodiment. In FIGS. 7A to 9B , the same reference numerals as in FIGS. 1A to 6B show the same elements as depicted in the first embodiment. FIGS. 7A, 8A , and 9 A show top views which show tops of processes in the manufacturing method of a semiconductor device. FIGS. 7B, 8B , and 9 B are sectional views which show cross-sections of the semiconductor device (taken along line X-X of FIG. 1A ) during the manufacturing process.

First, a conductive film 103 made of the first conductive material is formed on the semiconductor layer S 2 . Thereafter, a mask film 104 made from SiO 2 , SiN, Si, or the like is formed on the conductive film 103 . Then, resist films 105 a and 105 b are selectively formed on the mask film 104 using a lithography technique ( FIGS. 7A and 7B ).

Then, the resist films 105 a and 105 b are used as a mask, and the conductive film 103 and the mask film 104 are anisotropically etched by, for example, the RIE method or the like. Thereafter, the remaining resist films 105 a and 105 b are removed. Accordingly, the first wiring L 1 and the second wiring L 2 are formed ( FIGS. 8A and 8B ).

Here, as shown in FIGS. 8A and 8B , the first wiring L 1 has a stacked structure (wiring structure) which includes a first layer L 1 a of the first conductive material and a second layer (mask film L 1 b ) stacked on the first layer L 1 a that is a material different from the first conductive material.

The second wiring L 2 also has a stacked structure the same as the first wiring L 1 . That is, the second wiring L 2 has a stacked structure (wiring structure) which includes a first layer L 2 a of the first conductive material and a second layer (mask film) L 2 b of the material different from the first conductive material.

The second layers L 1 b and L 2 b are, for example, silicon films, silicon oxide films, or silicon nitride films.

Next, for example, in a similar manner as the process shown in FIGS. 3A and 3B , an insulation film is formed on the semiconductor layer S 2 using a CVD method. Then, the insulation film is anisotropically etched by a RIE method or the like.

Accordingly, in a similar manner as the process shown in FIGS. 4A and 4B , both the first insulation film IN 1 positioned between the first wiring L 1 and the second wiring L 2 and the second insulation film IN 2 adjacent to the second wiring L 2 are formed on the semiconductor layer S 2 . At this time, an insulation film IN is also formed between the first adjacent wirings L 1 .

Next, in a similar manner as the process shown in FIGS. 5A and 5B , the second conductive material is deposited on the semiconductor layer S 2 so as to be embedded in the opening 110 of the second insulation film IN 2 to form the conductive film 102 .

Then, for example, planarization is performed to remove the conductive film 102 disposed above the first and the second insulation films IN 1 and IN 2 and the first and the second wirings L 1 and L 2 is removed by using a CMP method.

Accordingly, the third wiring L 3 which has a line width W 3 greater than a line width W 1 of the first wiring L 1 and includes the second conductive material different from the first conductive material is formed on the semiconductor layer S 2 ( FIGS. 9A and 9B ). Thus, similar to the semiconductor device 100 shown in FIGS. 1A and 1B , the second insulation film IN 2 is arranged between the second wiring L 2 and the third wiring L 3 to be adjacent to the third wiring L 3 so as to surround the periphery of the third wiring L 3 .

Through the above processes, the semiconductor device according to the second embodiment is formed.

In the semiconductor device according to the second embodiment, the first and the second wirings L 1 and L 2 have a stacked structure which includes a first layer having the first conductive material and a second layer stacked on the first layer and having a material different from the first conductive material.

Then, a metal exposed after planarization by the CMP method is a first type (the second wiring L 3 ) and a level of difficulty of the CMP processing on a wide wiring is lowered by the manufacturing method of the semiconductor device according to the second embodiment.

In addition, leakage characteristics between the wirings affected by a residue or contamination left after the CMP processing on the exposed narrow wiring material are also improved in the second embodiment.

The other configurations and manufacturing methods of the semiconductor device are the substantially the same as in the first embodiment.

That is, by the semiconductor device according to the second embodiment, in the same manner as the first embodiment, it is possible to obtain improved electrical characteristics.

In particular, by the manufacturing method of the semiconductor device according to the second embodiment, it is possible to improve device yield while reducing manufacturing costs.

Third Embodiment

In a third embodiment, another example of a semiconductor device will be described. The semiconductor device according to the third embodiment has a configuration the same as the semiconductor device 100 according to the first embodiment, except for arrangements and configurations of the first and the second wirings and a contact wiring. That is, the semiconductor device according to the third embodiment has the same configuration as in FIGS. 1A and 1B according to the first embodiment, except for the arrangements and configurations of the first and the second wirings and the contact wiring.

FIGS. 10A and 10B are diagrams which show an example of a configuration of a semiconductor device 300 according to the third embodiment. In FIGS. 10A and 10B , the same reference numerals as in FIGS. 1A and 1B show configurations the same as in the first embodiment. FIG. 10A is a top view of the semiconductor device 300 . In addition, FIG. 10B is a sectional view which shows an example of a cross-section of the semiconductor device 300 focused on a region Z in FIG. 10A . In addition, FIG. 11 is a sectional view which shows another example of the cross-section of the semiconductor device 300 focused on the region Z of FIG. 10A .

As shown in FIGS. 10A and 10B , the semiconductor device 300 includes the semiconductor substrate S 1 , the semiconductor layer S 2 , the first wiring L 1 , the second wiring L 2 , the third wiring L 3 , the insulation film IN, the first insulation film IN 1 , and the second insulation film IN 2 .

The first wiring L 1 , the second wiring L 2 , the third wiring L 3 , the first insulation film IN 1 , and the second insulation film IN 2 are provided in one wiring layer Y provided on the semiconductor layer S 2 .

Here, the second wiring L 2 is intermittently provided so as to surround the periphery of the second insulation film IN 2 on the semiconductor layer S 2 . That is, the second wiring L 2 does not fully encircle the third wiring L 3 in a D 1 -D 2 plane and the second wiring L 2 is not a closed loop surrounding the third wiring L 3 .

That is, in the third embodiment, an end portion of the first wiring L 1 is adjacent to an end portion of the third wiring L 3 through the second insulation film IN 2 (not through the first insulation film IN 1 and the second wiring L 2 ) (the region Z of FIGS. 10A and 10B ).

Then, a contact wiring C is provided in the semiconductor layer S 2 below the wiring layer Y. An upper portion of the contact wiring C is electrically connected to an end portion of the first wiring L 1 and an end portion of the third wiring L 3 . Accordingly, the first wiring L 1 and the third wiring L 3 are electrically connected via at least contact wiring C.

As shown in FIG. 11 , the contact wiring C is provided in a semiconductor layer S 3 above the wiring layer Y so as to be electrically connected to the first wiring L 1 and the third wiring L 3 ( FIG. 11 ).

A structure of the semiconductor device 300 shown in FIGS. 10 A and 10 B and FIG. 11 reduces the number of wiring levels required in semiconductor device 300 as compared to other semiconductor devices, and thereby improves device yield which would otherwise be reduced due to contact failure or the like. Additionally, resistance due to extension of wiring length (i.e., additionally device wiring due to additional wiring level(s)) may be reduced.

The other characteristics and manufacturing methods of the semiconductor device 300 having a configuration as described above are substantially the same as characteristics of the semiconductor device 100 according to the first embodiment.

That is, by the semiconductor device according to the third embodiment, it is possible to obtain improved electrical characteristics.

In particular, by the manufacturing method of the semiconductor device according to the third embodiment, it is possible to improve the yield while reducing manufacturing costs.

Fourth Embodiment

In a fourth embodiment, another example of a semiconductor device will be described. A configuration of the semiconductor device according to the fourth embodiment is substantially the same as that of the semiconductor device 100 according to the first embodiment, except for arrangements and configurations of the second (L 2 ) and the third (L 3 ) wirings and the second insulation film IN 2 . That is, the configuration of the semiconductor device according to the fourth embodiment is the same as in FIGS. 1A and 1B of the first embodiment, except for the arrangements and configurations of the second and the third wirings and the second insulation film.

FIG. 12 is a diagram which shows an example of a configuration of the second (L 2 ) and the third (L 3 ) wirings and the second insulation film IN 2 of the semiconductor device according to the fourth embodiment. In FIG. 12 , reference numerals the same as in FIGS. 1A and 1B represent the same elements as in the first embodiment.

As shown in FIG. 12 , the second wiring L 2 is intermittently provided on the semiconductor layer S 2 in parallel with a first direction D 1 along which the third wiring L 3 extends.

Accordingly, a metal region in the second insulation film IN 2 is reduced, whereby leakage characteristics are improved.

Here, a second width WL 3 b (along second direction D 2 ) of a region of the third wiring L 3 corresponding to a position at which the second wiring L 2 is not present (that is, at a position along first direction D 1 that is between adjacent portions of the second wirings L 2 ) becomes greater than a first width WL 3 a (along second direction D 2 ) of a region corresponding to a position at which the second wiring L 2 is present along the first direction D 1 .

Accordingly, as compared to a case where a width of the third wiring L 3 is fixed to the first width WL 3 a , it is possible to reduce wiring resistance of the third wiring L 3 .

The other configurations of the semiconductor device according to the fourth embodiment are substantially the same as that of the semiconductor device according to the first embodiment.

Here, an example of the manufacturing method of a semiconductor device which has a configuration of the fourth embodiment will be described. FIGS. 13A to 17D are diagrams depicting processes in the manufacturing method of the semiconductor device according to the fourth embodiment. FIGS. 13A, 14A, 15A, 16A, and 17A are top views of the semiconductor device. FIGS. 13B, 14B, 15B, 16B, and 17B are sectional views which depict cross-sections of the semiconductor device taken along line X 1 -X 1 (see FIG. 13A ) during the manufacturing process. FIGS. 13C, 14C, 15C, 16C, and 17C are sectional views which depict cross-sections of the semiconductor device taken along line X 2 -X 2 (see FIG. 13A ) during the manufacturing process. FIGS. 13D, 14D, 15D, 16D, and 17D are sectional views which depict cross-sections of the semiconductor device taken long line X 3 -X 3 (see FIG. 13A ) during the manufacturing process.

In the manufacturing process of the semiconductor device according to the fourth embodiment, a conductive film (not shown) that is made from the first conductive material is formed on the semiconductor layer S 2 . Thereafter, the conductive film is selectively etched using, for example, a lithography technique and a RIE method. Accordingly, the first wiring L 1 (not specifically depicted) formed of the first conductive material and the second wiring L 2 formed of the first conductive material are disposed on the semiconductor layer S 2 ( FIGS. 13A to 13D ).

In the example of FIGS. 13A to 13D , a plurality of second wirings L 2 (which may be referred to as a plurality of portions of the second wiring L 2 ) are arranged in the first direction D 1 and the second direction D 2 on the semiconductor layer S 2 (that is, for example, rows and columns).

Next, the insulation film 101 is formed on the semiconductor layer S 2 ( FIGS. 14A to 14D ) by using a CVD method. The insulation film 101 has an opening 101 a which is between a particular adjacent pair of rows of the plurality of second wirings L 2 in the second direction D 2 .

Here, FIGS. 18A to 19B are diagrams for explaining processes of the manufacturing method of the semiconductor device shown in FIGS. 14A to 14D . FIG. 18A is a top view which corresponds to FIG. 14A . FIG. 18B is a top view which shows an enlarged region Z 1 of FIG. 18A . FIG. 19A is a top view which corresponds to FIG. 14B . FIG. 19B is a top view which shows an enlarged region Z 2 of FIG. 19A .

As shown in FIGS. 18A to 19B , the insulation film 101 is formed by the CVD method in a generally conformal manner, such that a film thickness of the insulation film 101 in a side surface of the second wiring L 2 becomes a thickness t. Furthermore, a film thickness of the insulation film 101 in a vicinity of an edge L 2 x of the upper portion of the second wiring L 2 becomes a thickness t in a circular arc shape around the edge L 2 x . Thus, the width of opening 101 a can be controlled by reference to the spacing (in the second direction D 2 ) between a particular pair of adjacent rows of the second wirings L 2 , the height of the second wirings L 2 (in a direction orthogonal to the D 1 -D 2 plane), and the deposited film thickness t of the insulating film 101 .

Then, the insulation film 101 is anisotropically etched by the RIE method or the like. Here, the insulation film 101 is etched until a surface of the semiconductor layer S 2 of a region on which the third wiring L 3 is to be formed is exposed.

Accordingly, both the first insulation film IN 1 (not shown) positioned between the first wiring L 1 and the second wiring L 2 and the second insulation film IN 2 adjacent to the second wiring L 2 are formed on the semiconductor layer S 2 ( FIGS. 15A to 15D ).

A width of the opening 110 of the second insulation film IN 2 in the second direction D 2 corresponding to the region in which the third wiring L 3 is formed is the same as a width W 3 of the third wiring L 3 .

Next, the second conductive material (for example, Cu or Al) is deposited on the semiconductor layer S 2 so as to be embedded in or fill the opening 110 of the second insulation film IN 2 to form the conductive film 102 ( FIGS. 16A to 16D ).

Then, planarization is performed until the conductive film 102 above the first and the second insulation films IN 1 and IN 2 and the first and the second wirings L 1 and L 2 is removed by using a CMP method. Here, since the CMP processing is controlled by a processing time, an upper portion of the first and the second insulation films IN 1 and IN 2 and the first and the second wirings L 1 and L 2 may be partially removed in the planarization process.

Accordingly, the third wiring L 3 which has the line width W 3 greater than the line width W 1 of the first wiring L 1 and contains the second conductive material different from the first conductive material is formed on the semiconductor layer S 2 ( FIGS. 17A to 17D ).

As shown in FIGS. 17A to 17D , the second wiring L 2 is intermittently provided on the semiconductor layer S 2 in parallel with the first direction D 1 in which the third wiring L 3 extends. Accordingly, as described above, a metal region in the second insulation film IN 2 is reduced, whereby leakage characteristics are improved.

Furthermore, a second width ( FIG. 17D and FIG. 12 , W 3 Lb) of the third wiring L 3 at a position along the second direction D 2 at which the second wiring L 2 is not present is greater than a first width ( FIG. 17C and FIG. 12 , W 3 La) at a position along the second direction D 2 at which the second wiring L 2 is present.

Accordingly, as described above, compared to a case when a width of the third wiring L 3 is fixed at the first width WL 3 a , it is possible to reduce wiring resistance of the third wiring L 3 .

Through the above processes, the semiconductor device according to the fourth embodiment is completed.

That is, by the semiconductor device according to the fourth embodiment, it is possible to obtain improved electrical characteristics.

In particular, by the manufacturing method of the semiconductor device according to the fourth embodiment, it is possible to improve the yield while reducing manufacturing costs.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.