Driving circuit for full-color organic light-emitting diode pixel and driving method of the driving circuit

This application is the National Stage of PCT/CN2015/094183filed on Nov. 10, 2015, which claims priority under 35 U.S.C. § 119 of Chinese Application No. 201510243720.5 filed on May 13, 2015, the disclosure of which is incorporated by reference.

The present disclosure relates to the technical field of organic light-emitting diode pixel display, and particularly to a driving circuit for a full-color organic light-emitting diode pixel and a driving method of the driving circuit.

Organic light emitting diodes AMOLEDs have currently become a hotspot in plate display research. As compared with a liquid crystal display, OLED has advantageous of low power consumption, low production cost, self-luminescent, wide viewing angle and rapid response, etc.

A traditional AMOLED display mainly comprises a substrate and OLED pixel units manufactured on the substrate, each of the OLED pixel units comprises a structure of an OLED pixel per se and a driving circuit for the OLED pixel, and the driving circuit drives the OLED pixel to emit light according to signals on a corresponding gate line and a corresponding data line. FIG. 1 illustrates a schematic structural diagram of an OLED pixel in the prior art. As shown in FIG. 1 , the structure of the OLED pixel comprises an anode electrode and a cathode electrode disposed oppositely and a light-emitting thin film layer sandwiched between the anode electrode and the cathode electrode, the light-emitting thin film layer comprises a hole injection layer (HIL), a hole transport layer (HTL), an organic light-emitting material layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL) in sequence along a direction from the anode electrode to the cathode electrode. The OLED pixel is a current driving type light-emitting device, when a driving current flows from the anode electrode to the cathode electrode of the structure of the OLED structure, holes and electrons are combined at the organic light-emitting material layer to release energy, uminescent molecules in the organic light-emitting material layer transit to an excited state from a ground state when being excited, and the molecules in the excited state form photons in the radiative transition from the excited state back to the ground state, thereby luminance phenomenon is generated.

FIG. 2 illustrates a schematic diagram of pixel arrangement of an AMOLED display in the prior art. As shown in FIG. 2 , three adjacent OLED pixels in a row are a red pixel, a green pixel and a blue pixel, color display can be achieved by color mixing of the red pixel, the green pixel and the blue pixel, Gate represents a gate line and Data represents a data line in FIG. 2 . However, each specific OLED pixel can only display one of three primary colors and only functions as a functional unit in the color display. In other words, the AMOLED display as shown in FIG. 2 fails to really achieve full-color display on a pixel level.

Therefore, there is a need for an OLED pixel structure and an AMOLED display corresponding thereto which are capable of really achieving extreme full-color display.

In order to solve the above technical problem, the present disclosure proposes a driving circuit for a full-color OLED pixel and a driving method of the driving circuit, which can achieve full-color display by the full-color OLED pixel by reading data signals for at least two color thin film layers stacked in sequence and controlling the at least two color thin film layers to emit light concurrently.

According to one aspect of the present disclosure, there is provided a driving circuit for a full-color OLED pixel. The full-color OLED pixel comprises at least two color thin film layers stacked and insulating layers arranged between any two adjacent thin film layers. The driving circuit comprises at least two driving sub-circuits, the at least two driving sub-circuits share a data line and a light-emitting control terminal, and each of the driving sub-circuits is connected to a scanning control terminal corresponding thereto and is configured to drive the color thin film layer corresponding thereto. The at least two driving sub-circuits read data signals on the data line in sequence under the control of the respective scanning control terminals, and drive the respective color thin film layers to emit light concurrently under the control of the light-emitting control terminal.

According to one embodiment of the present disclosure, the at least two color thin film layers comprise a first color thin film layer, a second color thin film layer and a third color thin film layer, and the at least two driving sub-circuits comprise a first driving sub-circuit connected to a first scanning control terminal, the data line and the light-emitting control terminal and configured to drive the first color thin film layer; a second driving sub-circuit connected to a second scanning control terminal, the data line and the light-emitting control terminal and configured to drive the second color thin film layer; and a third driving sub-circuit connected to a third scanning control terminal, the data line and the light-emitting control terminal and configured to drive the third color thin film layer.

The first driving sub-circuit, the second driving sub-circuit and the third driving sub-circuit read the data signals on the data line in sequence under the control of the first scanning control terminal, the second scanning control terminal and the third scanning control terminal; and the first driving sub-circuit, the second driving sub-circuit and the third driving sub-circuit drive the first color thin film layer, the second color thin film layer and the third color thin film layer respectively to emit light concurrently under the control of the light-emitting control terminal.

According to one embodiment of the present disclosure, each of the driving sub-circuits comprises a data-reading module for reading and storing a data signal on the data line, and a light-emitting driving module for driving a color thin film layer corresponding thereto to emit light.

According to one embodiment of the present disclosure, the data-reading module is further configured to store a threshold voltage of a driving transistor in the light-emitting driving module, and the data-reading module comprises a first switching transistor having a gate connected to the first scanning control terminal, a first electrode connected to the data line and a second electrode connected to a second electrode of the driving transistor; a second switching transistor having a gate connected to the first scanning control terminal and a second electrode connected to a first electrode of the driving transistor; a capacitor having a first electrode connected to a first electrode of the second switching transistor and a second electrode connected to a first level supply terminal.

According to one embodiment of the present disclosure, the light-emitting driving module comprises: a third switching transistor having a gate connected to the light-emitting control terminal, a first electrode connected to the first level supply terminal, and a second electrode connected to the first electrode of the driving transistor and the second electrode of the second switching transistor; a fourth switching transistor having a gate connected to the light-emitting control terminal, a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to a first electrode of the color thin film layer corresponding thereto; and the driving transistor having a gate connected to the first electrode of the capacitor.

According to one embodiment of the present disclosure, the at least two driving sub-circuits further share a resetting control terminal, and each of the driving sub-circuits further comprises a resetting module for resetting the data-reading module in the driving sub-circuit to its initial state under the control of the resetting control terminal.

According to one embodiment of the present disclosure, the resetting module comprises a fifth switching transistor having a gate connected to the resetting control terminal, a first electrode connected to the first electrode of the capacitor and the gate of the driving transistor, and a second electrode connected to a second level supply terminal.

According to another aspect of the present disclosure, there is further provided a driving method of a driving circuit of a full-color OLED pixel, the full-color OLED pixel comprises at least two color thin film layers stacked and insulating layers arranged between any two adjacent thin film layers. The driving circuit comprises at least two driving sub-circuits, the at least two driving sub-circuits share a data line and a light-emitting control terminal, and each of the driving sub-circuits is connected to a scanning control terminal corresponding thereto and is configured to drive the color thin film layer corresponding thereto. The driving method comprises: during a data-reading period, the at least two driving sub-circuits reading data signals on the data line in sequence under the control of the respective scanning control terminals; during a light-emitting period, the at least two driving sub-circuits driving the respective color thin film layers respectively to emit light concurrently under the control of the light-emitting control terminal.

According to one embodiment of the present disclosure, after the light-emitting period or before the data-reading period, the driving method further comprises: during a resetting period, resetting each of the at least two driving sub-circuit to its initial state.

According to one embodiment of the present disclosure, the at least two color thin film layers comprise a first color thin film layer, a second color thin film layer and a third color thin film layer, and the at least two driving sub-circuits comprise a first driving sub-circuit, a second driving sub-circuit and a third driving sub-circuit, the first driving sub-circuit is connected to a first scanning control terminal, the data line and the light-emitting control terminal, the second driving sub-circuit is connected to a second scanning control terminal, the data line and the light-emitting control terminal, and the third driving sub-circuit is connected to a third scanning control terminal, the data line and the light-emitting control terminal.

The at least two driving sub-circuits reading data signals on the data line in sequence under the control of the respective scanning control terminals during a data-reading period comprises: during a first data-reading period, the first driving sub-circuit reading and storing a first data signal on the data line under the control of the first scanning control terminal; during a second data-reading period, the second driving sub-circuit reading and storing a second data signal on the data line under the control of the second scanning control terminal; and during a third data-reading period, the third driving sub-circuit reading and storing a third data signal on the data line under the control of the third scanning control terminal.

The at least two driving sub-circuits driving the respective color thin film layers to emit light concurrently under the control of the light-emitting control terminal during a light-emitting period comprises: during the light-emitting period, the first driving sub-circuit, the second driving sub-circuit and the third driving sub-circuit drive the first color thin film layer, the second color thin film layer and the third color thin film layer respectively to emit light concurrently under the control of the light-emitting control terminal.

According to one embodiment of the present disclosure, during the first data-reading period, the first scanning control terminal is at a low level, the second scanning control terminal and the third scanning control terminal are at a high level, and the light-emitting control terminal is at a high level; during the second data-reading period, the second scanning control terminal is at a low level, the first scanning control terminal and the third scanning control terminal are at a high level, and the light-emitting control terminal is at a high level; during the third data-reading period, the third scanning control terminal is at a low level, the first scanning control terminal and the second scanning control terminal are at a high level, and the light-emitting control terminal is at a high level; during the light-emitting period, the first scanning control terminal, the second scanning control terminal and the third scanning control terminal are at a high level, and the light-emitting control terminal is at a low level.

According to one embodiment of the present disclosure, the at least two driving sub-circuits further share a resetting control terminal, the resetting control terminal is at a low level during a resetting period and is at a high level during the data-reading period and the light-emitting period. During the resetting period, the respective scanning control terminals and the light-emitting control terminal are at a high level.

According to one embodiment of the present disclosure, each of the driving sub-circuits comprises a data-reading module and a light-emitting driving module. The data-reading module comprises: a first switching transistor having a gate connected to the first scanning control terminal, a first electrode connected to the data line and a second electrode connected to a second electrode of a driving transistor in the light-emitting driving module; a second switching transistor having a gate connected to the first scanning control terminal and a second electrode connected to a first electrode of the driving transistor; a capacitor having a first electrode connected to a first electrode of the second switching transistor and a second electrode connected to a first level supply terminal. The light-emitting driving module comprises: a third switching transistor having a gate connected to the light-emitting control terminal, a first electrode connected to the first level supply terminal, and a second electrode connected to the first electrode of the driving transistor and the second electrode of the second switching transistor; a fourth switching transistor having a gate connected to the light-emitting control terminal, a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to a first electrode of the color thin film layer corresponding thereto; and the driving transistor having a gate connected to the first electrode of the capacitor.

According to one embodiment of the present disclosure, the driving sub-circuits share a resetting control terminal, and each of the driving sub-circuits further comprises a resetting module for resetting the data-reading module to its initial state. The resetting module comprises a fifth switching transistor having a gate connected to the resetting control terminal, a first electrode connected to the first electrode of the capacitor and the gate of the driving transistor, and a second electrode connected to a second level supply terminal.

According to one embodiment of the present disclosure, the at least two color thin film layers comprise a first color thin film layer, a second color thin film layer and a third color thin film layer, and the at least two driving sub-circuits comprise a first driving sub-circuit, a second driving sub-circuit and a third driving sub-circuit, the first driving sub-circuit is connected to a first scanning control terminal, the data line and the light-emitting control terminal, the second driving sub-circuit is connected to a second scanning control terminal, the data line and the light-emitting control terminal, and a third driving sub-circuit is connected to a third scanning control terminal, the data line and the light-emitting control terminal.

The at least two driving sub-circuits reading data signals on the data line in sequence under the control of the respective scanning control terminals during a data-reading period comprises: during a first data-reading period, the first scanning control terminal is at a low level, the second scanning control terminal and the third scanning control terminal are at a high level, and the light-emitting control terminal is at a high level, a data signal on the data line is a first data signal, the first switching transistor and the second switching transistor in the first driving sub-circuit are turned on, the driving transistor in the first driving sub-circuit is turned on such that the capacitor stores the first data signal and the threshold voltage of the driving transistor; during the second data-reading period, the second scanning control terminal is at a low level, the first scanning control terminal and the third scanning control terminal are at a high level, and the light-emitting control terminal is at a high level, a data signal on the data line is a second data signal, such that the capacitor in the second driving sub-circuit stores the second data signal and the threshold voltage of the driving transistor in the second driving sub-circuit, the capacitor in the first driving sub-circuit keeps the voltage across its two electrodes unchanged; during the third data-reading period, the third scanning control terminal is at a low level, the first scanning control terminal and the second scanning control terminal are at a high level, and the light-emitting control terminal is at a high level, a data signal on the data line is a third data signal, such that the capacitor in the third driving sub-circuit stores the third data signal and the threshold voltage of the driving transistor in the third driving sub-circuit, the capacitor in the first driving sub-circuit keeps the voltage across its two electrodes unchanged and the capacitor in the second driving sub-circuit keeps the voltage across its two electrodes unchanged.

The at least two sub-circuits driving the respective color thin film layers to emit light concurrently under the control of the light-emitting control terminal during a light-emitting period comprises: during the light-emitting period, the first scanning control terminal, the second scanning control terminal and the third scanning control terminal are at a high level, and the light-emitting control terminal is at a low level, the driving transistor in the first driving sub-circuit is turned on and drives the first color thin film layer to emit light, the driving transistor in the second driving sub-circuit is turned on and drives the second color thin film layer to emit light, and the driving transistor in the third driving sub-circuit is turned on and drives the third color thin film layer to emit light.

According to one embodiment of the present disclosure, during the resetting period, the respective scanning control terminals and the light-emitting control terminal are at a high level, the resetting control terminal is at a low level, the fifth switching transistor in the resetting module of each of the driving sub-circuits is turned on, such that a voltage of the first electrode of the capacitor in each of the driving sub-circuits is reset to a voltage at the second level supply terminal.

According to one embodiment of the present disclosure, for each of the driving sub-circuits, during the data-reading period corresponding thereto, a first current origins from the data line, flows through the first switching transistor, the driving transistor and the second switching transistor in sequence, and arrives at the first electrode of the capacitor in the driving sub-circuit; and during the light-emitting period, a second current origins from the first level supply terminal, flows through the third switching transistor, the driving transistor and the fourth switching transistor in sequence, and arrives at the first electrode of the color thin film layer corresponding to the driving sub-circuit.

According to one embodiment of the present disclosure, for each of the driving sub-circuits, during the data-reading period corresponding thereto, the first current flows from the second electrode of the driving transistor to the first electrode of the driving transistor, during the light-emitting period, the second current flows from the first electrode of the driving transistor to the second electrode of the driving transistor; and for each of the driving sub-circuits, during the light-emitting period, the color thin film layer corresponding thereto is driven to emit light by the data voltage corresponding thereto and the threshold voltage of the driving transistor corresponding thereto stored by the capacitor in the driving sub-circuit, so as to compensate for effect of drift of the threshold voltage of the driving transistor on luminance of the color thin film layer.

According to one embodiment of the present disclosure, the first level supply terminal is a high level supply terminal, the second level supply terminal is a low level supply terminal; and for each of the color thin film layers, the first electrode is an anode, and the second electrode is a cathode and is connected to the second level supply terminal.

According to another aspect of the present disclosure, there is further provided a substrate array comprising an array of full-color OLED pixels, each of the full-color OLED pixels comprises the driving circuit for the full-color OLED pixel described above.

According to yet another aspect of the present disclosure, there is further provided a full-color OLED display comprising the substrate array described above.

Other features and advantageous of the present disclosure will be illustrated in the following specification, and will partially become apparent from the specification or be obtained by implementing the present disclosure. The object and other advantageous of the present disclosure can be achieved and acquired by structures specifically proposed in the specification, claims and the accompanying drawings.

The above and other objects, features and advantageous of the present disclosure will be apparent from the detailed descriptions on the embodiments of the present disclosure in connection with the accompanying drawings. The accompanying drawings are used to provide further understandings to the embodiments of the present disclosure and constitute a part of the specification, and are used to explain the present disclosure together with the embodiments of the present disclosure rather than constituting limitations to the present disclosure. In the accompanying drawings, same reference signs generally represent same components or steps.

FIG. 1 illustrates a schematic structural diagram of an OLED pixel in the prior art;

FIG. 2 illustrates a schematic diagram of pixel arrangement of an AMOLED display in the prior art;

FIG. 3 illustrates an exemplary structural block diagram of a full-color OLED pixel according to one embodiment of the present disclosure;

FIG. 4 illustrates a detailed structural block diagram of the full-color OLED pixel as shown in FIG. 3 ;

FIG. 5 and FIG. 6 illustrate arrangement of the full-color OLED pixel and a driving circuit for the full-color OLED pixel according to one embodiment of the present disclosure;

FIG. 7 illustrates a schematic structural block diagram of a driving circuit of the full-color OLED pixel according to one embodiment of the present disclosure;

FIG. 8 illustrates a detailed structural block diagram of a driving circuit of the full-color OLED pixel according to a first embodiment of the present disclosure;

FIG. 9 illustrates a schematic circuit diagram of the driving circuit of the full-color OLED pixel as shown in FIG. 8 according to the first embodiment of the present disclosure;

FIG. 10 illustrates a detailed structural block diagram of a driving circuit of the full-color OLED pixel according to a second embodiment of the present disclosure;

FIG. 11 illustrates a schematic circuit diagram of the driving circuit of the full-color OLED pixel as shown in FIG. 10 according to the second embodiment of the present disclosure;

FIG. 12 illustrates a schematic flowchart of an operation method of the driving circuit of the full-color OLED pixel according to the first embodiment of the present disclosure;

FIG. 13 illustrates a schematic flowchart of an operation method of the driving circuit of the full-color OLED pixel according to the second embodiment of the present disclosure;

FIG. 14 illustrates a signal sequence diagram of the driving circuit of the full-color OLED pixel according to the first embodiment of the present disclosure;

FIG. 15 illustrates a schematic operation diagram of the driving circuit of the full-color OLED pixel during a first data-reading period according to the first embodiment of the present disclosure;

FIG. 16 illustrates a schematic operation diagram of the driving circuit of the full-color OLED pixel during a second data-reading period according to the first embodiment of the present disclosure;

FIG. 17 illustrates a schematic operation diagram of the driving circuit of the full-color OLED pixel during a third data-reading period according to the first embodiment of the present disclosure;

FIG. 18 illustrates a schematic operation diagram of the driving circuit of the full-color OLED pixel during a light-emitting period according to the first embodiment of the present disclosure;

FIG. 19 illustrates a signal sequence diagram of the driving circuit of the full-color OLED pixel according to the second embodiment of the present disclosure; and

FIG. 20 illustrates a schematic operation diagram of the driving circuit of the full-color OLED pixel according to the second embodiment of the present disclosure.

In order to make the object, the technical solutions and the advantageous of the embodiments of the present disclosure apparent, the embodiments of the present disclosure will be described below in detail taken in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described exemplary embodiments are only some but not all of the embodiments of the present disclosure. Other embodiments obtained by those skilled in the art based on the described embodiments without paying inventive labor shall belong to the scope sought for protection in the present disclosure.

Here, it should be noted that, in the accompanying drawings, same reference signs represent components having substantially same or similar structures or functions and repeated description thereof will be omitted.

According to embodiments of the present disclosure, an OLED pixel structure comprising at least two color display thin film layers stacked is proposed. Particularly, a full-color OLED pixel according to the embodiments of the present disclosure comprises at least two thin film layers stacked and insulating layers arranged between any two adjacent thin film layers. In order to achieve full-color display of the full-color OLED pixel, the at least two film layers and the insulating layers are transparent layers.

FIG. 3 is an exemplary structural block diagram of the full-color OLED pixel of the embodiments of the present disclosure.

As shown in FIG. 3 , the full-color OLED pixel comprises three color thin film layers stacked and insulating layers arranged between any two adjacent color thin film layers. Particularly, the full-color OLED pixel shown in FIG. 3 comprises a first color thin film layer Color 1 , an insulating layer Ins 1 , a second color thin film layer Color 2 , an insulating layer Ins 2 , and a third color thin film layer Color 3 in a stack order. The first color thin film layer Color 1 is configured to emit light having a first color, the second color thin film layer Color 2 is configured to emit light having a second color, and the third color thin film layer Color 3 is configured to emit light having a third color. For example, the first color thin film layer Color 1 , the second color thin film layer Color 2 and the third color thin film layer Color 3 may be a combination of a red thin film layer, a green thin film layer and a blue thin film layer in any order.

Furthermore, as shown in FIG. 3 , the three color thin film layers and the insulating layers of the full-color OLED pixel are transparent layers.

FIG. 4 illustrates a detailed structural block diagram of the full-color OLED pixel as shown in FIG. 3 .

As shown in FIG. 4 , each of the first color thin film layer Color 1 , the second color thin film layer Color 2 and the third color thin film layer Color 3 comprises an electron injection layer (EIL), an electron transport layer (ETL), an emitting material layer (EML), a hole transport layer (HTL) and a hole injection layer (HIL).

Furthermore, each of the first color thin film layer Color 1 , the second color thin film layer Color 2 and the third color thin film layer Color 3 further comprises a cathode electrode (Cathode) and an anode electrode (Anode). The cathode electrode may be a metal negative electrode, and the anode electrode may be an Indium Tin Oxide (ITO) electrode.

For each of the first color thin film layer Color 1 , the second color thin film layer Color 2 and the third color thin film layer Color 3 , the luminance of the color thin film layer can be controlled by controlling a current flowing from the anode electrode to the cathode electrode thereof according to the data voltage corresponding thereto. Any combination of the first color, the second color and the third color can be achieved by controlling the luminance of each of the color thin film layers in the full-color OLED pixel structure separately since each of the color thin film layers and each of the insulating layers are transparent layers. In case that the first color, the second color and the third color are three primary colors, the full-color display can be achieved. Therefore, each of the color thin film layers functions as a display functional layer of the full-color OLED pixel.

FIG. 5 and FIG. 6 illustrate arrangement of the full-color OLED pixel and a driving circuit for the full-color OLED pixel according to one embodiment of the present disclosure.

As shown in FIG. 5 , the driving circuit for the full-color OLED pixel is arranged on the full-color OLED pixel, and size of the full-color OLED pixel can be set according to size of the driving circuit for the full-color OLED pixel.

As shown in FIG. 6 , the driving circuit for the full-color OLED pixel can supply a driving current for each of the color thin film layers of the full-color OLED pixel. Based on such arrangement, a driving circuit for a plurality of color thin film layers of a full-color OLED pixel can be formed on the full-color OLED pixel and can supply a driving current for an anode electrode of each of the color thin film layers separately, and thus a real full-color display of the full-color OLED pixel can be achieved. In FIG. 6 , the driving circuit is illustrated as three parts Cst 1 , Cst 2 and Cst 3 which supply driving currents for the anode electrodes of the three color thin film layers respectively. However, the present application is not so limited, and the driving circuit may be a whole circuit instead of being formed by three separate parts.

According to one embodiment of the present application, the driving circuit for the full-color OLED pixel comprises at least two driving sub-circuits connected to a same data line and a same light-emitting control terminal, and each of the driving sub-circuits is connected to a scanning control terminal corresponding thereto and is configured to drive the color thin film layer corresponding thereto. The at least two driving sub-circuits read data signals on the data line in sequence under the control of the respective scanning control terminals, and drive the respective color thin film layers to emit light concurrently under the control of the light-emitting control terminal.

Description will be given below by taking that the first, the second and the third color thin film layers correspond to three primary colors respectively as an example. Herein, the three primary colors may be red-green-blue three primary colors, but the present application is not so limited.

FIG. 7 illustrates a schematic structural block diagram of the driving circuit for the full-color OLED pixel according to one embodiment of the present disclosure.

As shown in FIG. 7 , the driving circuit for the full-color OLED pixel comprises a first driving sub-circuit 701 , a second driving sub-circuit 702 and a third driving sub-circuit 703 . Furthermore, the driving circuit for the full-color OLED pixel is further connected to a data line DATA, three scanning control terminals SCAN 1 -SCAN 3 and a light-emitting control terminal EM.

The first driving sub-circuit 701 is connected to a first scanning control terminal SCAN 1 , the data line DATA and the light-emitting control terminal EM, and is configured to drive the first color thin film layer.

The second driving sub-circuit 702 is connected to a second scanning control terminal SCAN 2 , the data line DATA and the light-emitting control terminal EM, and is configured to drive the second color thin film layer.

The third driving sub-circuit 703 is connected to a third scanning control terminal SCAN 3 , the data line DATA and the light-emitting control terminal EM, and is configured to drive the third color thin film layer.

The first driving sub-circuit 701 , the second driving sub-circuit 702 and the third driving sub-circuit 703 read the data signals on the data line DATA in sequence under the control of a first scanning control signal at the first scanning control terminal SCAN 1 , a second scanning control signal at the second scanning control terminal SCAN 2 and a third scanning control signal at the third scanning control terminal SCAN 3 .

The first driving sub-circuit 701 , the second driving sub-circuit 702 and the third driving sub-circuit 703 drive the first color thin film layer, the second color thin film layer and the third color thin film layer respectively to emit light concurrently under the control of a light-emitting control signal at the light-emitting control terminal EM.

FIG. 8 illustrates a detailed structural block diagram of a driving circuit for the full-color OLED pixel according to a first embodiment of the present disclosure.

As shown in FIG. 8 , the first driving sub-circuit 701 comprises a data-reading module 801 and a light-emitting driving module 802 ; the second driving sub-circuit 702 comprises a data-reading module 803 and a light-emitting driving module 804 ; and the third driving sub-circuit 703 comprises a data-reading module 805 and a light-emitting driving module 806 .

The data-reading modules 801 , 803 and 805 read and store data signals on the data line DATA respectively. Particularly, the data-reading module 801 is connected to the first scanning control terminal SCAN 1 and the data line DATA, and read and store a data signal on the data line DATA under the control of the first scanning control terminal SCAN 1 ; the data-reading module 803 is connected to the second scanning control terminal SCAN 2 and the data line DATA, and read and store a data signal on the data line DATA under the control of the second scanning control terminal SCAN 2 ; and the data-reading module 805 is connected to the third scanning control terminal SCAN 3 and the data line DATA, and read and store a data signal on the data line DATA under the control of the third scanning control terminal SCAN 3 .

The light-emitting driving modules 802 , 804 and 806 drive the first, the second and the third color thin film layers to emit light respectively. Particularly, the light-emitting driving modules 802 , 804 and 806 are all connected to the light-emitting control terminal EM, and drive the first, the second and the third color thin film layers respectively to emit light concurrently under the control of the light-emitting control terminal EM.

FIG. 9 illustrates a schematic circuit diagram of the driving circuit for the full-color OLED pixel as shown in FIG. 8 according to the first embodiment of the present disclosure. The circuit configuration and operation of the driving circuit for the full-color OLED pixel will be described below by taking the first driving sub-circuit 701 as an example.

In the accompanying drawings, for sake of simple illustration, the first color thin film layer is illustrated as OLED 1 , the second color thin film layer is illustrated as OLED 2 and the third color thin film layer is illustrated as OLED 3 .

As shown in FIG. 9 , the first driving sub-circuit 701 comprises a first switching transistor T 1 , a second switching transistor T 2 , a third switching transistor T 3 , a fourth switching transistor T 4 , a first driving transistor DT 1 and a first capacitor C 1 . The first switching transistor T 1 , the second switching transistor T 2 and the first capacitor C 1 constitute the data-reading module 801 ; the third switching transistor T 3 , the fourth switching transistor T 4 and the first driving transistor DT 1 constitute the light-emitting driving module 802 .

In the data-reading module 801 , the first switching transistor T 1 has a gate connected to the first scanning control terminal SCAN 1 , a first electrode connected to the data line DATA and a second electrode connected to a second electrode of the first driving transistor DT 1 ; the second switching transistor T 2 has a gate connected to the first scanning control terminal SCAN 1 , a first electrode connected to a first electrode a 1 of the first capacitor C 1 and a second electrode connected to a first electrode of the first driving transistor DT 1 ; the first capacitor C 1 has a second electrode b 1 connected to a first level supply terminal VDD. For example, the first level supply terminal VDD is a high level supply terminal.

When the first scanning control signal at the first scanning control terminal SCAN 1 is at an active control level, the first switching transistor T 1 is turned on such that a data signal on the data line DATA is applied to the second electrode of the first driving transistor DT 1 ; and the second switching transistor T 2 is turned on such that the gate and the first electrode of the first driving transistor DT 1 are connected.

When the first scanning control terminal SCAN 1 is at an active control level, a reverse-charging current (that is, discharging current) of the first capacitor C 1 origins from the data line DATA, flows through the first switching transistor T 1 , the first driving transistor DT 1 and the second switching transistor T 2 in sequence, and arrives at the first electrode a 1 of the first capacitor C 1 .

Taking that the first driving transistor DT 1 is a P type transistor as an example, a threshold voltage of the P type transistor has a negative value, a voltage at the gate is lower than a voltage at the source and a gate-source voltage of the P type transistor is lower than the threshold voltage thereof. In other words, an absolute value of the gate-source voltage of the P type transistor is higher than an absolute value of the threshold voltage thereof.

Specifically, the threshold voltage V th1 of the first driving transistor DT 1 has a negative value, and the first electrode of the first driving transistor DT 1 is a drain and the second electrode of the first driving transistor DT 1 is a source.

Until the absolute value of the gate-source voltage V GS of the first driving transistor DT 1 is equal to the absolute value of the threshold voltage V th1 of the first driving transistor DT 1 , the first capacitor C 1 keeps to be charged reversely (discharged). Then, the first driving transistor D 1 is turned off such that no reverse-charging current of the first capacitor C 1 flows. That is,

| V GS |=|V G −V S |=|V G −V Data |=|V th1 |,

where |•| represents sign of taking an absolute value. After removing sign of the absolute value, it can be obtained that: V Data −V G =−V th1 . Therefore, V G =V Data +V th1 .

At this time, voltage difference across the two electrodes of the first capacitor C 1 is V dd −V G =V dd −V Data −V th1 , where V th1 <0, V dd is a first level at the first level supply terminal VDD, V Data is a data voltage on the data line DATA.

Therefore, not only the data voltage V Data on the data line DATA but also the threshold voltage V th1 of the first driving transistor DT 1 is held in the first capacitor C 1 .

In the light-emitting driving module 802 , the third switching transistor T 3 has a gate connected to the light-emitting control terminal EM, a first electrode connected to the first level supply terminal VDD, and a second electrode connected to the first electrode of the first driving transistor DT 1 and the second electrode of the second switching transistor T 2 ; the fourth switching transistor T 4 has a gate connected to the light-emitting control terminal EM, a first electrode connected to the second electrode of the first driving transistor DT 1 , and a second electrode connected to an anode electrode of the first color thin film layer; and the first driving transistor DT 1 has a gate connected to the first electrode a 1 of the first capacitor C 1 .

When the first scanning control signal at the first scanning control terminal SCAN 1 is at an inactive control level and the light-emitting control signal at the light-emitting control terminal EM is at an active control level, the third switching transistor T 3 is turned on such that the first level V dd at the first level supply terminal VDD is applied to the first electrode of the first driving transistor DT 1 ; and the fourth switching transistor T 4 is turned on. At this time, the voltage at the gate of the first driving transistor DT 1 is V G =V Data +V th1 due to the voltage holding effect of the first capacitor C 1 . Therefore, When the first scanning control terminal SCAN 1 is at an inactive control level and the light-emitting control terminal EM is at an active control level, the third switching transistor T 3 , the first driving transistor DT 1 and the fourth switching transistor T 4 are all turned on, a light-emitting driving current origins from the first level supply terminal VDD, flows through the third switching transistor T 3 , the first driving transistor DT 1 and the fourth switching transistor T 4 , and arrives at the anode electrode of the first color thin film layer. At this time, the first electrode of the first driving transistor DT 1 is a source and the second electrode of the first driving transistor DT 1 is a drain.

The driving current flowing into the anode electrode of the first color thin film layer can be represented as:

It can be seen that the driving current flowing into the anode electrode of the first color thin film layer is irrelevant to the threshold voltage V th1 of the first driving transistor DT 1 . In other words, not only the full-color display of the full-color OLED pixel can be achieved but also disadvantageous effect due to drift of the threshold voltage of the driving transistor can be removed by the driving circuit for the full-color OLED pixel according to the embodiments of the present disclosure.

In FIG. 9 , the cathode electrodes of the first, the second and the third color thin film layers are all grounded, but the present disclosure is not so limited. The cathode electrodes of the first, the second and the third color thin film layers can be connected to a second level supply terminal VSS together. In case that the first level supply terminal VDD is a high level supply terminal, the second level supply terminal VSS is a low level supply terminal.

On the other hand, in order that display of each frame of image is not effected by display of its previous frame of image, that is, by the data voltage V Data stored in the first capacitor C 1 during the process of display of the previous frame, a resetting module can also be incorporated into each of the driving sub-circuits in the driving circuit for the full-color OLED pixel as shown in FIG. 8 so as to reset the data-reading module to its initial state.

FIG. 10 illustrates a detailed structural block diagram of a driving circuit of the full-color OLED pixel according to a second embodiment of the present disclosure.

As shown in FIG. 10 , the first driving sub-circuit 701 comprises a data-reading module 801 , a light-emitting driving module 802 and a resetting module 901 ; the second driving sub-circuit 702 comprises a data-reading module 803 , a light-emitting driving module 804 and a resetting module 902 ; and the third driving sub-circuit 703 comprises a data-reading module 805 , a light-emitting driving module 806 and a resetting module 903 .

The configuration and operation of the data-reading modules 801 , 803 and 805 in the second embodiment of the present disclosure are same as those of the data-reading modules 801 , 803 and 805 in the first embodiment of the present disclosure, and detailed description is no repeated herein.

The configuration and operation of the light-emitting driving modules 802 , 804 and 806 in the second embodiment of the present disclosure are same as those of the light-emitting driving modules 802 , 804 and 806 in the first embodiment of the present disclosure, and detailed description is no repeated herein.

FIG. 11 illustrates a schematic circuit diagram of the driving circuit for the full-color OLED pixel as shown in FIG. 10 according to the second embodiment of the present disclosure. The circuit configuration and operation of the driving circuit for the full-color OLED pixel will be described below by taking the first driving sub-circuit 701 as an example.

As shown in FIG. 11 , the first driving sub-circuit 701 comprises a first switching transistor T 1 , a second switching transistor T 2 , a third switching transistor T 3 , a fourth switching transistor T 4 , a fifth switching transistor T 5 , a first driving transistor DT 1 and a first capacitor C 1 . The first switching transistor T 1 , the second switching transistor T 2 and the first capacitor C 1 constitute the data-reading module 801 ; the third switching transistor T 3 , the fourth switching transistor T 4 and the first driving transistor DT 1 constitute the light-emitting driving module 802 ; and the fifth switching transistor T 5 constitutes the resetting module 901 .

The configuration and operation of the data-reading module 801 in the second embodiment of the present disclosure are same as those of the data-reading module 801 in the first embodiment of the present disclosure, and detailed description is no repeated herein.

The configuration and operation of the light-emitting driving module 802 in the second embodiment of the present disclosure are same as those of the light-emitting driving module 802 in the first embodiment of the present disclosure, and detailed description is no repeated herein.

In the resetting module 901 , the fifth switching transistor T 5 has a gate connected to a resetting control terminal RST, a first electrode connected to the first electrode a 1 of the first capacitor C 1 and the gate of the first driving transistor DT 1 , and a second electrode connected to the second level supply terminal VSS.

When the resetting control signal at the resetting control terminal RST is at an active control level, the fifth switching transistor T 5 is turned on, and the first capacitor C 1 is charged such that the voltage difference across the two electrodes of the first capacitor C 1 is equal to difference between the voltage at the first level supply terminal VDD and the voltage at the second level supply terminal VSS.

Although the first to fifth switching transistors T 1 -T 5 and the driving transistor DT 1 are illustrated as P type transistors in the circuit structure in FIG. 9 and FIG. 11 , the embodiments of the present disclosure are not so limited. It should be understood that each of the first to fifth switching transistors T 1 -T 5 and the driving transistor DT 1 may be an N type transistor or a P type transistor in the embodiments of the present disclosure. In case that the first and second switching transistors T 1 and T 2 share the first scanning control terminal SCAN 1 , it should be ensured that the first and second switching transistors T 1 and T 2 are transistors having a same type; in case that the third and fourth switching transistors T 3 and T 4 share the light-emitting control terminal EM, it should be ensured that the third and fourth switching transistors T 3 and T 4 are transistors having a same type.

As an example, the first and second switching transistors T 1 and T 2 are N type switching transistors, the third and fourth switching transistors T 3 and T 4 are P type switching transistors, and the fifth switching transistor is an N type switching transistor. At this time, the active control level of the first scanning control signal at the first scanning control terminal SCAN 1 is a high level, and the active control level of the light-emitting control signal at the light-emitting control terminal EM is a low level, and the active control level of the resetting control signal at the resetting control terminal RST is a high level.

As another example, the first and second switching transistors T 1 and T 2 are N type switching transistors, the third and fourth switching transistors T 3 and T 4 are N type switching transistors, and the fifth switching transistor is a P type switching transistor. At this time, the active control level of the first scanning control signal at the first scanning control terminal SCAN 1 is a high level, and the active control level of the light-emitting control signal at the light-emitting control terminal EM is a high level, and the active control level of the resetting control signal at the resetting control terminal RST is a low level.

As another example, the first driving transistor DT 1 is an N type driving transistor. It is easily understood by those skilled in the art that the connection relationship of the first capacitor C 1 , the fifth switching transistor T 5 , the first switching transistor T 1 and the second switching transistor T 2 may be adjusted accordingly.

As another example, the first to fifth switching transistors T 1 -T 5 are all N type switching transistors, and the first driving transistor is an N type or a P type driving transistor. At this time, the active control levels of the control signals at the first scanning control terminal SCAN 1 , the light-emitting control terminal EM and the resetting control terminal RST are all a high level.

Operation of the driving circuit for the full-color OLED pixel according to the embodiments of the present disclosure may comprise at least two data-reading periods and one light-emitting period. During the at least two data-reading periods, the at least two driving sub-circuits read and store data signals on the data line in sequence, and during each of the data-reading periods, only one of the driving sub-circuits reads and stores a data signal on the data line; during the light-emitting period, the at least two sub-circuits drive the at least two color thin film layers respectively to emit light concurrently.

Operation of the driving circuit for the full-color OLED pixel according to the first embodiment of the present disclosure will be described below with reference to FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 and FIG. 16 .

FIG. 12 illustrates a schematic flowchart of an operation method of the driving circuit of the full-color OLED pixel according to the first embodiment of the present disclosure.

During a first data-reading period, the first driving sub-circuit reads and stores a first data signal on the data line.

During a second data-reading period, the second driving sub-circuit reads and stores a second data signal on the data line.

During a third data-reading period, the third driving sub-circuit reads and stores a third data signal on the data line.

During a light-emitting period, the first driving sub-circuit, the second driving sub-circuit and the third driving sub-circuit drive the first color thin film layer, the second color thin film layer and the third color thin film layer respectively to emit light concurrently.

As shown in FIG. 10 , the driving circuit for the full-color OLED pixel according to the second embodiment of the present disclosure comprises a resetting module which can reset all of the first driving sub-circuit, the second driving sub-circuit and the third driving sub-circuit to their initial state after the light-emitting period or before the data-reading period.

FIG. 13 illustrates a schematic flowchart of an operation method of the driving circuit of the full-color OLED pixel according to the second embodiment of the present disclosure.

During a resetting period, the first driving sub-circuit, the second driving sub-circuit and the third driving sub-circuit are all reset to their initial state.

During a first data-reading period, the first driving sub-circuit reads and stores a first data signal on the data line.

During a second data-reading period, the second driving sub-circuit reads and stores a second data signal on the data line.

During a third data-reading period, the third driving sub-circuit reads and stores a third data signal on the data line.

During a light-emitting period, the first driving sub-circuit, the second driving sub-circuit and the third driving sub-circuit drive the first color thin film layer, the second color thin film layer and the third color thin film layer respectively to emit light concurrently.

FIG. 14 illustrates a signal sequence diagram of the driving circuit of the full-color OLED pixel according to the first embodiment of the present disclosure.

During the first data-reading period (1), the first scanning control signal at the first scanning control terminal SCAN 1 is at a low level, the second scanning control signal at the second scanning control terminal SCAN 2 and the third scanning control signal at the third scanning control terminal SCAN 3 are at a high level, and the light-emitting control signal at the light-emitting control terminal EM is at a high level.

As shown in FIG. 15 , during the first data-reading period, since the first scanning control signal at the first scanning control terminal SCAN 1 is at a low level, the first switching transistor T 1 is turned on such that the data voltage V 1 on the data line DATA is applied to the second electrode of the first driving transistor DT 1 ; and the second switching transistor T 2 is turned on such that the gate and the first electrode of the first driving transistor DT 1 are connected. At this time, the discharging current i 1 of the first capacitor C 1 origins from the data line DATA, flows through the first switching transistor T 1 , the first driving transistor DT 1 and the second switching transistor T 2 in sequence, and arrives at the first electrode a 1 of the first capacitor C 1 . Specifically, the discharging current i 1 flows from the second electrode of the first driving transistor DT 1 to the first electrode of the first driving transistor DT 1 , and arrives at the first electrode a 1 of the first capacitor C 1 via the second switching transistor T 2 .

At the end of the first data-reading period, as described above, the voltage at the first electrode a 1 of the first capacitor C 1 is V 1 +V th1 and the absolute value of the gate-source voltage of the first driving transistor DT 1 is equal to the absolute value of the threshold voltage of the first driving transistor DT 1 at this time, such that the first driving transistor DT 1 is turned off. Accordingly, the first data voltage V 1 on the data line DATA and the threshold voltage V th1 of the first driving transistor DT 1 are stored in the first capacitor C 1 .

During the first data-reading period, the second driving sub-circuit 702 and the third driving sub-circuit 703 do not operate.

During the second data-reading period (2), the second scanning control signal at the second scanning control terminal SCAN 2 is at a low level, the first scanning control signal at the first scanning control terminal SCAN 1 and the third scanning control signal at the third scanning control terminal SCAN 3 are at a high level, and the light-emitting control signal at the light-emitting control terminal EM is at a high level.

As shown in FIG. 16 , during the second data-reading period, since the second scanning control signal at the second scanning control terminal SCAN 2 is at a low level, the twenty-first switching transistor T 21 is turned on such that the data voltage V 2 on the data line DATA is applied to the second electrode of the second driving transistor DT 2 ; and the twenty-second switching transistor T 22 is turned on such that the gate and the first electrode of the second driving transistor DT 2 are connected. At this time, the discharging current i 2 of the second capacitor C 2 origins from the data line DATA, flows through the twenty-first switching transistor T 21 , the second driving transistor DT 2 and the twenty-second switching transistor T 22 in sequence, and arrives at the first electrode a 2 of the second capacitor C 2 .

At the end of the second data-reading period, the voltage at the first electrode a 2 of the second capacitor C 2 is V 2 +V th2 and the absolute value of the gate-source voltage of the second driving transistor DT 2 is equal to the absolute value of the threshold voltage of the second driving transistor DT 2 at this time, such that the second driving transistor DT 2 is turned off. Accordingly, the second data voltage V 2 on the data line DATA and the threshold voltage V th2 of the second driving transistor DT 2 are stored in the second capacitor C 2 .

During the second data-reading period, the first driving sub-circuit 701 and the third driving sub-circuit 703 do not operate, and the first capacitor C 1 in the first driving sub-circuit 701 keeps the voltage across the two electrodes thereof unchanged.

During the third data-reading period (3), the third scanning control signal at the third scanning control terminal SCAN 3 is at a low level, the first scanning control signal at the first scanning control terminal SCAN 1 and the second scanning control signal at the second scanning control terminal SCAN 2 are at a high level, and the light-emitting control signal at the light-emitting control terminal EM is at a high level.

As shown in FIG. 17 , during the third data-reading period, since the third scanning control signal at the third scanning control terminal SCAN 3 is at a low level, the thirty-first switching transistor T 31 is turned on such that the data voltage V 3 on the data line DATA is applied to the second electrode of the third driving transistor DT 3 ; and the thirty-second switching transistor T 32 is turned on such that the gate and the first electrode of the third driving transistor DT 3 are connected. At this time, the discharging current i 3 of the third capacitor C 3 origins from the data line DATA, flows through the thirty-first switching transistor T 31 , the third driving transistor DT 3 and the thirty-second switching transistor T 32 in sequence, and arrives at the first electrode a 3 of the third capacitor C 3 .

At the end of the third data-reading period, the voltage at the first electrode a 3 of the third capacitor C 3 is V 3 +V th3 and the absolute value of the gate-source voltage of the third driving transistor DT 3 is equal to the absolute value of the threshold voltage of the third driving transistor DT 3 at this time, such that the third driving transistor DT 3 is turned off. Accordingly, the third data voltage V 3 on the data line DATA and the threshold voltage V th3 of the third driving transistor DT 3 are stored in the third capacitor C 3 .

During the third data-reading period, the first driving sub-circuit 701 and the second driving sub-circuit 702 do not operate, and each of the first capacitor C 1 in the first driving sub-circuit 701 and the second capacitor C 2 in the second driving sub-circuit 702 keeps the voltage across the two electrodes thereof unchanged.

During the light-emitting period (4), the first scanning control signal at the first scanning control terminal SCAN 1 , the second scanning control signal at the second scanning control terminal SCAN 2 and the third scanning control signal at the third scanning control terminal SCAN 3 are at a high level, and the light-emitting control signal at the light-emitting control terminal EM is at a low level.

As shown in FIG. 18 , during the light-emitting period, since the light-emitting control signal at the light-emitting control terminal EM is at a low level, the third switching transistor T 3 is turned on such that the first level Vdd at the first level supply terminal VDD is applied to the first electrode of the first driving transistor DT 1 , and the fourth switching transistor T 4 is turned on; similarly, the twenty-third switching transistor T 23 is turned on such that the first level Vdd at the first level supply terminal VDD is applied to the first electrode of the second driving transistor DT 2 , and the twenty-fourth switching transistor T 24 is turned on; similarly, the thirty-third switching transistor T 33 is turned on such that the first level Vdd at the first level supply terminal VDD is applied to the first electrode of the third driving transistor DT 3 , and the thirty-fourth switching transistor T 34 is turned on.

At this time, the voltage at the gate of the first driving transistor DT 1 is V G1 =V 1 +V th1 due to the voltage holding effect of the first capacitor C 1 ; the voltage at the gate of the second driving transistor DT 2 is V G2 =V 2 +V th2 due to the voltage holding effect of the second capacitor C 2 ; and the voltage at the gate of the third driving transistor DT 3 is V G3 =V 3 +V th3 due to the voltage holding effect of the third capacitor C 3 . V th1 is a threshold voltage of the first driving transistor DT 1 , V th2 is a threshold voltage of the second driving transistor DT 2 , and V th3 is a threshold voltage of the third driving transistor DT 3 .

At this time, the light-emitting driving current of the first color thin film layer origins from the first level supply terminal VDD, flows through the third switching transistor T 3 , the first driving transistor DT 1 and the fourth switching transistor T 4 , and arrives at the anode electrode of the first color thin film layer. Specifically, the light-emitting driving current of the first color thin film layer flows from the first electrode of the first driving transistor DT 1 to the second electrode of the first driving transistor DT 1 . During this period, the first color thin film layer is driven to emit light by the data voltage V 1 and the threshold voltage V th1 of the first driving transistor DT 1 stored in the first capacitor C 1 , such that effect of drift of the threshold voltage of the first driving transistor DT 1 on the luminance of the first color thin film layer is compensated.

Similarly, the light-emitting driving current of the second color thin film layer origins from the first level supply terminal VDD, flows through the twenty-third switching transistor T 23 , the second driving transistor DT 2 and the twenty-fourth switching transistor T 24 , and arrives at the anode electrode of the second color thin film layer; the light-emitting driving current of the third color thin film layer origins from the first level supply terminal VDD, flows through the thirty-third switching transistor T 33 , the third driving transistor DT 3 and the thirty-fourth switching transistor T 34 , and arrives at the anode electrode of the third color thin film layer.

The current flowing into the anode electrode of the first color thin film layer can be represented as:

The current flowing into the anode electrode of the second color thin film layer can be represented as:

The current flowing into the anode electrode of the third color thin film layer can be represented as:

It can be seen that the current flowing into the anode electrode of the first color thin film layer is irrelevant to the threshold voltage V th1 of the first driving transistor DT 1 , the current flowing into the anode electrode of the second color thin film layer is irrelevant to the threshold voltage V th2 of the second driving transistor DT 2 , and the current flowing into the anode electrode of the third color thin film layer is irrelevant to the threshold voltage V th3 of the third driving transistor DT 3 . In other words, not only the full-color display of the full-color OLED pixel can be achieved but also disadvantageous effect due to drift of the threshold voltage of the driving transistor can be removed by the driving circuit for the full-color OLED pixel according to the embodiments of the present disclosure.

FIG. 19 illustrates a signal sequence diagram of the driving circuit of the full-color OLED pixel according to the second embodiment of the present disclosure.

During a resetting period (1), the first scanning control signal at the first scanning control terminal SCAN 1 , the second scanning control signal at the second scanning control terminal SCAN 2 and the third scanning control signal at the third scanning control terminal SCAN 3 are at a high level, the light-emitting control signal at the light-emitting control terminal EM is at a high level, and the resetting control signal at the resetting control terminal RST is at a low level.

As shown in FIG. 20 , during the resetting period, the fifth switching transistor T 5 , the twenty-fifth switching transistor T 25 and the thirty-fifth switching transistor T 35 are turned on so as to charge the first capacitor C 1 , the second capacitor C 2 and the third capacitor C 3 respectively, such that the voltage across the two electrodes of each of the first capacitor C 1 , the second capacitor C 2 and the third capacitor C 3 is equal to difference between the voltage of the first level supply terminal VDD and the voltage of the second level supply terminal VSS.

During a first data-reading period (2), the first scanning control signal at the first scanning control terminal SCAN 1 is at a low level, the second scanning control signal at the second scanning control terminal SCAN 2 and the third scanning control signal at the third scanning control terminal SCAN 3 are at a high level, the light-emitting control signal at the light-emitting control terminal EM is at a high level, and the resetting control signal at the resetting control terminal RST is at a high level.

During a second data-reading period (3), the second scanning control signal at the second scanning control terminal SCAN 2 is at a low level, the first scanning control signal at the first scanning control terminal SCAN 1 and the third scanning control signal at the third scanning control terminal SCAN 3 are at a high level, the light-emitting control signal at the light-emitting control terminal EM is at a high level, and the resetting control signal at the resetting control terminal RST is at a high level.

During a third data-reading period (4), the third scanning control signal at the third scanning control terminal SCAN 3 is at a low level, the first scanning control signal at the first scanning control terminal SCAN 1 and the second scanning control signal at the second scanning control terminal SCAN 2 are at a high level, the light-emitting control signal at the light-emitting control terminal EM is at a high level, and the resetting control signal at the resetting control terminal RST is at a high level.

During a light-emitting period (5), the first scanning control signal at the first scanning control terminal SCAN 1 , the second scanning control signal at the second scanning control terminal SCAN 2 and the third scanning control signal at the third scanning control terminal SCAN 3 are at a high level, the light-emitting control signal at the light-emitting control terminal EM is at a low level, and the resetting control signal at the resetting control terminal RST is at a high level.

Operations of the driving circuit for the full-color OLED pixel according to the second embodiment of the present disclosure in the first data-reading period, the second data-reading period, the third data-reading period and light-emitting period are same as those of the driving circuit for the full-color OLED pixel according to the first embodiment of the present disclosure in the first data-reading period, the second data-reading period, the third data-reading period and light-emitting period, and detailed description is no repeated herein.

According to the embodiments of the present disclosure, there is further provided a substrate array comprising an array of full-color OLED pixels, each of the full-color OLED pixels comprises the pixel structure of the full-color OLED pixel and the driving circuit for the full-color OLED pixel according to the embodiments of the present disclosure.

According to the embodiments of the present disclosure, there is further provided a full-color AMOLED display comprising an array of pixels each of which being constituted by the pixel structure of the full-color OLED pixel and the driving circuit for the full-color OLED pixel according to the embodiments of the present disclosure.

According to the embodiments of the present disclosure, in a stacked AMOLED pixel structure, at least two color thin film layers are stacked and share a common cathode electrode, such that any mixture of three primary display colors can be displayed by every pixel, thus achieving extreme full-color display on the pixel level and improving display effect of the AMOLED display.

In addition, as compared to the AMOLED pixel structure in the art, data transmission for three color thin film layers can be implemented by one data line and data reading can be implemented in sequence for the three color thin film layers according to three scanning control signals. Taking a row of N pixels as an example, the AMOLED display in the art requires one scanning control line and 3N data lines, whereas the full-color AMOLED display according to the embodiments of the present disclosure only requires N data lines and 3 scanning control lines. Therefore, with the driving circuit for the full-color AMOLED display according to the embodiments of the present disclosure, area of the driving circuit can be reduced significantly due to reduced number of the data lines, and thereby pitches among the full-color OLED pixels can be reduced, which is beneficial for resolution improvement of the full-color OLED display.

Various embodiments of the present disclosure have been described in detail. However, those skilled in the art should understand that various variations and improvements can be made without departing from the spirit and scope of the embodiments of the present disclosure, which should be considered as falling within the protection scope of the embodiments of the present disclosure.

This application claims priority to a Chinese Patent Application No. 201510243720.5, filed on May 13, 2015 in the China's State Intellectual Property Office, the disclosure of which is incorporated by reference herein as a whole.