Nonvolatile memory device

The present application claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2015-0148412 filed in the Korean Intellectual Property Office on Oct. 26, 2015, which is herein incorporated by reference in its entirety.

1. Technical Field

Various embodiments generally relate to a semiconductor memory device and more particularly, to a nonvolatile memory device.

2. Related Art

Semiconductor memory devices may be realized using semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs) and indium phosphide (InP). Semiconductor memory devices are generally classified into volatile and nonvolatile memory devices.

A volatile memory device does not retain stored data when its power supply is turned off. Examples of volatile memory devices include SRAM (static RAM), DRAM (dynamic RAM) and SDRAM (synchronous DRAM) devices. A nonvolatile memory device retains stored data even when its power supply is turned off. Examples of nonvolatile memory devices include ROM (read only memory), PROM (programmable ROM), EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM), flash memory, PRAM (phase change RAM), MRAM (magnetoresistive RAM), RRAM (resistive RAM), and FRAM (ferroelectric RAM) devices.

In an embodiment, a nonvolatile memory device may include a plurality of memory blocks each including a drain select line, word lines and a source select line, and a pass transistor stage including a plurality of pass transistors formed in series in an active region and suitable for transferring word line voltages to a memory block selected among the memory blocks, in response to a block select signal, wherein the pass transistors each share a drain with a first adjacent pass transistor at one side while sharing a source with a second adjacent pass transistor at the other, and wherein a pair of pass transistors which share the source transfer word line driving signals from drains thereof to a pair of word lines which are included in different memory blocks among the memory blocks, through the source.

FIG. 1 is a block diagram illustrating a nonvolatile memory device, according to an embodiment of the invention.

FIG. 2 is a circuit diagram illustrating a memory block included in the memory cell array shown in FIG. 1 , according to an embodiment of the invention.

FIG. 3 is a perspective view illustrating a portion of the memory cell array shown in FIG. 1 , according to an embodiment of the invention.

FIG. 4 is a block diagram schematically illustrating a configuration of the row decoder shown in FIG. 1 , according to an embodiment of the invention.

FIG. 5 is a diagram schematically illustrating the layout pattern of the pass transistor stages shown in FIG. 4 , according to an embodiment of the invention.

FIG. 6 is a diagram illustrating pass transistors disposed in a first active region ACT 1 shown in FIG. 5 and the layout structure of wiring lines associated therewith, according to an embodiment of the invention.

FIGS. 7 to 9 are diagrams illustrating various layout patterns of driving signal lines, according to an embodiment of the invention.

FIG. 10 is a diagram illustrating the relationship between the word lines of a first memory block MB 1 and the word lines of a second memory block MB 2 , according to an embodiment of the invention.

FIGS. 11 and 12 are diagrams illustrating bias application states in the case where the memory cell MC 31 of the second memory block MB 2 in FIG. 10 is programmed, according to an embodiment of the invention.

FIG. 13 is a diagram illustrating the relationship between the word lines of a first memory block MB 1 and the word lines of a second memory block MB 2 , according to an embodiment of the invention.

FIG. 14 is a diagram illustrating a bias application state in the case where the memory cell MC 31 of the second memory block MB 2 in FIG. 13 is programmed, according to an embodiment of the invention.

FIG. 15 is a block diagram schematically a memory system including a nonvolatile memory device, according to an embodiment of the invention.

FIG. 16 is a block diagram schematically illustrating a computing system including a nonvolatile memory device, according to an embodiment of the invention.

Hereinafter, various embodiments of the present invention are described with reference to the accompanying drawings.

Referring to FIG. 1 a nonvolatile memory device 100 is provided, according to an embodiment of the invention. The nonvolatile memory device 100 may include a memory cell array 110 , a row decoder 120 , a page buffer 130 , an input/output buffer 140 , a control logic 150 , and a voltage generator 160 .

The memory cell array 110 may be coupled to the row decoder 120 through a plurality of word lines WL. The memory cell array 110 may also be coupled to the row decoder 120 through one or more drain select and source select lines DSL, SSL, hereinafter also referred to generally as select lines DSL, SSL. The memory cell array 110 may be coupled to the page buffer 130 through a plurality of bit lines BL.

The memory cell array 110 may include a plurality of memory blocks. Each of the plurality of memory blocks may correspond to an erase unit. Each of the memory blocks may include a plurality of cell strings. A cell string is group of memory cells coupled in series. Memory cells included in one cell string may be selected by the same select transistor.

The row decoder 120 may select a memory block of the memory cell array 110 in response to an address ADD. The row decoder 120 may select a word line WL of a selected memory block in response to an address ADD. The row decoder 120 may transfer a driving signal from the voltage generator 160 , to a selected word line WL of a selected memory block. The row decoder 120 may transfer a driving signal from the voltage generator 160 to the select lines DSL, SSL. In particular, for example, a high voltage driving signal may be provided to a selected word line WL of a selected memory block. For transferring a high voltage driving signal, the row decoder 120 may include one or more pass transistors that may be or comprise high voltage transistors.

According to an embodiment, the footprint of the row decoder 120 i.e. the area occupied by the row decoder 120 , may be reduced through modification in the positioning or layout structure of the pass transistors.

The page buffer 130 may operate as a write driver or a sense amplifier depending on the operation modes of the nonvolatile memory device. In a program operation, the page buffer 130 may transfer a voltage corresponding to data to be programmed, to a bit line BL of the memory cell array 110 . In a read operation, the page buffer 130 senses data stored in a selected memory cell, through a bit line BL, and may transfer the sensed data to the input/output buffer 140 . In an erase operation, the page buffer 130 may float bit lines BL of the memory cell array 110 .

In a program operation, the input/output buffer 140 may transfer data inputted from an external device, to the page buffer 130 . In a read operation, the input/output buffer 140 may output data provided from the page buffer 130 , to an external device. The input/output buffer 140 may transfer an address ADD or a command CMD to the row decoder 120 or the control logic 150 .

The control logic 150 may control the page buffer 130 and the voltage generator 160 for accessing selected memory cells in response to a command CMD transferred from the input/output buffer 140 .

The voltage generator 160 may generate a voltage S to be supplied to a selected word line WL, under the control of the control logic 150 . Different level voltages may be generated by the voltage generator as may be needed. The voltage generator 160 may generate one or more voltages to be supplied to one or more word lines at a time. The voltage generator 160 may generate a voltage to be supplied to a bulk in which memory cells are formed, for example, a well region, under the control of the control logic 150 . Examples, of word line voltages S to be supplied to respective word lines WL may include a program voltage Vpgm, a pass voltage Vpass, a selected read voltage Vrd and/or an unselected read voltage Vread. The voltage generator 160 may generate select signals DS, SS which may provided to the select lines DSL and SSL, respectively, in a read and/or a program operation. For example, the first select signal DS may be a control signal for selecting a cell string, while the second select signal SS may be a ground select signal.

Referring now to FIG. 2 a circuit diagram for the memory block MB included in the memory cell array 110 of FIG. 1 is provided.

FIG. 2 illustrates, as an example, that the memory cell array 110 may be a three-dimensional memory cell array. However, it is noted that the memory cell array 110 may be provided as a two-dimensional memory cell array.

The memory block MB may include a plurality of cell strings CS 11 , CS 12 , CS 21 and CS 22 . Each of the plurality of cell strings CS 11 , CS 12 , CS 21 and CS 22 may include a drain select transistor DST, a source select transistor SST and a plurality of memory cells DC and MC 00 to MC 47 which may be disposed perpendicularly with respect to the main surface of a substrate (not shown). For example, the various parts of each cell string may be stacked in a vertical orientation. In each of the cell strings CS 11 , CS 12 , CS 21 and CS 22 , the memory cells DC and MC 00 to MC 47 may be coupled in series between the drain select transistor DST and the source select transistor SST. Among the memory cells DC and MC 00 to MC 47 , the memory cells MC 00 to MC 47 may represent main memory cells that are used for storing valid data. The memory cell DC may represent a dummy memory cell not used for storing valid data. For example, a dummy memory cell may store dummy data.

The gates of the source select transistors SST of the plurality of cell strings CS 11 , CS 12 , CS 21 and CS 22 may be coupled in common to a source select line SSL. One of the ends of the source select transistors SST may be coupled to the main memory cells MC 47 , and the other of the ends may be couple to a common source line CSL.

The gates of the drain select transistors DST of the cell strings CS 11 and CS 12 may be coupled to a drain select line DSL 1 . Similarly, the gates of the drain select transistors DST of the cell strings CS 21 and CS 22 may be coupled to a drain select line DSL 2 .

One of the ends of the drain select transistors DST of the cell strings CS 11 and CS 21 may be coupled to a bit line BL 1 , while the other of the ends may be coupled to the dummy memory cells DC. One of the ends of the drain select transistors DST of the cell strings CS 12 and CS 22 may be coupled to a bit line BL 2 , while the other of the ends may be coupled to the dummy memory cells DC.

For facilitating explanation, in the following descriptions, row, column and height directions are defined.

The direction in which the drain select lines DSL 1 , DSL 2 extend may be a row direction RD. Hence, for example, the cell strings CS 11 and CS 12 may be arranged in the row direction RD, and may form a first row. Or, also for example, the cell strings CS 21 and CS 22 may be arranged in the row direction RD, and may form a second row.

The direction in which the bit lines BL 1 , BL 2 extend may be a column direction CD. Hence, for example, the cell strings CS 11 and CS 21 may be arranged in the column direction CD, and may form a first column while the cell strings CS 12 and CS 22 may be arranged in the column direction CD, and may form a second column.

A direction from the source select transistors SST to the drain select transistors DST may be a height direction VD.

The memory cells DC and MC 00 to MC 47 may form a three-dimensional structure as they are arranged in the column direction CD and the row direction RD and are stacked in the height direction VD. Main memory cells MC of the same height may be coupled in common to one word line WL. Main memory cells MC of different heights may be coupled to different corresponding word lines WL. Similarly, the dummy memory cells DC of the same height may be coupled in common to one dummy word line DWL.

Drain select transistors DST of the same row may be coupled in common to one drain select line DSL 1 or DSL 2 , while drain select transistors DST of different rows may be coupled to different, corresponding drain select lines DSL 1 and DSL 2 . Drain select transistors DST of the same column may be coupled in common to one bit line BL 1 or BL 2 , while drain select transistors DST of different columns may be coupled to different, corresponding bit lines BL 1 and BL 2 .

FIG. 2 shows, as an example, that the memory block MB may include 4 cell strings CS 11 , CS 12 , CS 21 and CS 22 . However, it is noted that the number of cell strings of the memory block MB is not limited to such an example, and two or more cell strings may be provided in the column direction CD or the row direction RD.

Further, FIG. 2 shows, as an example, that the source select transistors SST are coupled in common to one source select line SSL. However, it is to be noted that, similarly to the drain select transistors DST, the structure of the memory block MB may be changed and applied such that source select transistors SST of the same row are coupled in common to one source select line and source select transistors SST of different rows are coupled to different source select lines, respectively.

Furthermore, FIG. 2 shows as an example that one drain select transistor DST and one source select transistor SST may be provided in each cell string. However, it is to be noted that two or more drain select transistors or two or more source select transistors may be provided in each cell string.

Moreover, FIG. 2 shows as an example that one dummy memory cell DC and 48 main memory cells MC 00 to MC 47 are included in each cell string. However, it is to be noted that one or more main memory cells may be included in each cell string and no dummy memory cell or two or more dummy memory cells may be included in each cell string.

FIG. 3 is a perspective view of a portion of the memory cell array 110 shown in FIG. 1 .

Referring to FIG. 3 , the memory cell array 110 may include a plurality of channels 11 extending perpendicularly, for example, protrude, from a substrate 10 , a plurality of select lines DSL and SSL and a plurality of word lines DWL and WL stacked along the channels 11 , and bit lines BL which are electrically coupled with the channels 11 .

The bottom ends of the channels 11 may be electrically coupled to the substrate 10 . The top ends of the channels 11 may be electrically coupled to the bit lines BL by the medium of bit line contacts (not shown). The bit lines BL may extend in the column direction CD. Each of the bit lines BL may be coupled in common to the channels 11 of different memory blocks MB.

The memory cell array 110 may be included in a semiconductor memory device that further may include memory layers (not shown) provided between the channels 11 and the word lines DWL and WL, for example, a NAND flash memory device or a resistive memory device.

The select lines DSL and SSL may include source select lines SSL that are adjacent to the substrate 10 and drain select lines DSL that are adjacent to the bit lines BL. The word lines DWL and WL may include main word lines WL and dummy word lines DWL disposed between the source select lines SSL and the drain select lines DSL.

The select lines DSL and SSL and the word lines DWL and WL may be electrically coupled, for example, with metal lines (not shown) by the medium of contact plugs (not shown). In order to provide pads that are brought into contact with the contact plugs, the select lines DSL, SSL and the word lines DWL, WL may be stacked in the form of a pyramid such that the edges of the select lines DSL, SSL and the word lines DWL, WL may be exposed in the form of a stair. The exposed edges of the select lines DSL, SSL and the word lines DWL, WL may be referred to as a slimming region.

The drain select lines DSL may have the form of a line extending in a direction crossing with the bit lines BL. For example, the bit lines BL may extend in the column direction CD, while the drain select lines DSL may extend in the row direction RD.

The word lines DWL, WL and the source select lines SSL may be cut by a wide cutting part 12 formed in the row direction RD, and may be divided into the memory blocks MB.

The word line voltages S generated by the voltage generator 160 as described above with reference to FIG. 1 may be transferred to the word lines DWL, WL. The word line voltages S may include a program voltage Vpgm, an unselected read voltage Vread, a read voltage Vrd, a pass voltage Vpass and a verify voltage Vfy. The unselected read voltage Vread may be a voltage provided to an unselected word line in a read operation. The read voltage Vrd may be a voltage provided to a selected word line in a read operation.

The program voltage Vpgm, the pass voltage Vpass or the unselected read voltage Vread may correspond to a relatively high voltage. Therefore, pass transistors capable of withstanding a high voltage may be included in the row decoder 120 described above with reference to FIG. 1 .

A high voltage transistor forming a pass transistor may have a longer channel than a low voltage transistor, for withstanding a high voltage, that is, for preventing a punch-through between its source and drain. Also, a high voltage transistor may have a thicker gate oxide layer than a low voltage transistor, for withstanding the high voltage, that is, for withstanding a high potential difference between its gate and its drain and/or its gate and its source. In other words, a high voltage transistor may need a wider chip area than a low voltage transistor.

For this reason, even through the size of a memory cell may shrink through fine processing, it is not easy to decrease the size of a pass transistor for providing a high voltage. The exemplary embodiment provides a technology capable of decreasing the footprint of pass transistors by changing their layout.

FIG. 4 is a block diagram schematically illustrating the configuration of the row decoder 120 shown in FIG. 1 .

FIG. 4 shows the row decoder 120 from the viewpoint of operations of memory blocks MB 1 to MB 4 , and illustrates, as an example, that the row decoder 120 may have a structure for driving the 4 memory blocks MB 1 to MB 4 .

Referring to FIG. 4 , the row decoder 120 may include an SI decoder 121 , a block decoder 122 , and a plurality of pass transistor stages 123 A to 123 D.

The SI decoder 121 may output word line driving signals DPSA, SA<00:15>, SA<32:47> and SD<16:31> to global word lines GWL_A and GWL_D in the case where an inputted block address corresponds to the first memory block MB 1 . The SI decoder 121 may output word line driving signals DPSA, SA<00:15>, SA<32:47> and SC<16:31> to global word lines GWL_A and GWL_C in the case where an inputted block address corresponds to the second memory block MB 2 . The SI decoder 121 may output word line driving signals DPSB, SB<00:15>, SB<32:47> and SC<16:31> to global word lines GWL_B and GWL_C in the case where an inputted block address corresponds to the third memory block MB 3 . The SI decoder 121 may output word line driving signals DPSB, SB<00:15>, SB<32:47> and SD<16:31> to global word lines GWL_B and GWL_D in the case where an inputted block address corresponds to the fourth memory block MB 4 .

The block decoder 122 may enable one of a plurality of block select signals BLKWL 1 to BLKWL 4 in response to a block address. One pass transistor stage among the pass transistor stages 123 A to 123 D may be driven by an enabled block select signal BLKWL.

The pass transistor stages 123 A to 123 D may include first to fourth pass transistor stages 123 A to 123 D driven in response to the block select signals BLKWL 1 to BLKWL 4 , respectively.

The first pass transistor stage 123 A may include a plurality of pass transistors driven in response to the first block select signal BLKWL 1 . The drains of the pass transistors included in the first pass transistor stage 123 A may be respectively electrically coupled to the global word lines GWL_A and GWL_D, and the sources of the pass transistors included in the first pass transistor stage 123 A may be respectively electrically coupled to word lines (not shown) of the first memory block MB 1 .

In the case where the first memory block MB 1 is selected, the first block select signal BLKWL 1 may be enabled by the block decoder 122 , and the word line driving signals DPSA, SA<00:15>, SA<32:47> and SD<16:31> may be provided from the SI decoder 121 to the global word lines GWL_A and GWL_D. The pass transistors of the first pass transistor stage 123 A may be turned on in response to the enabled first block select signal BLKWL 1 , and may transfer the word line driving signals DPSA, SA<00:15>, SA<32:47> and SD<16:31> to the word lines of the first memory block MB 1 .

The second pass transistor stage 123 B may include a plurality of pass transistors driven in response to the second block select signal BLKWL 2 . The drains of the pass transistors included in the second pass transistor stage 123 B may be electrically coupled to the global word lines GWL_A and GWL_C, respectively, and the sources of the pass transistors included in the second pass transistor stage 123 B may be electrically coupled to word lines (not shown) of the second memory block MB 2 , respectively.

In the case where the second memory block MB 2 is selected, the second block select signal BLKWL 2 may be enabled by the block decoder 122 , and the word line driving signals DPSA, SA<00:15>, SA<32:47> and SC<16:31> may be provided from the SI decoder 121 to the global word lines GWL_A and GWL_C. The pass transistors of the second pass transistor stage 123 B may be turned on in response to the enabled second block select signal BLKWL 2 , and may transfer the word line driving signals DPSA, SA<00:15>, SA<32:47> and SC<16:31> to the word lines of the second memory block MB 2 .

The third pass transistor stage 123 C may include a plurality of pass transistors driven in response to the third block select signal BLKWL 3 . The drains of the pass transistors included in the third pass transistor stage 123 C may be electrically coupled to the global word lines GWL_B and GWL_C, respectively. The sources of the pass transistors included in the third pass transistor stage 123 C may be electrically coupled to word lines (not shown) of the third memory block MB 3 , respectively.

In the case where the third memory block MB 3 is selected, the third block select signal BLKWL 3 may be enabled by the block decoder 122 , and the word line driving signals DPSB, SB<00:15>, SB<32:47> and SC<16:31> may be provided from the SI decoder 121 to the global word lines GWL_B and GWL_C. The pass transistors of the third pass transistor stage 123 C may be turned on in response to the enabled third block select signal BLKWL 3 , and may transfer the word line driving signals DPSB, SB<00:15>, SB<32:47> and SC<16:31> to the word lines of the third memory block MB 3 .

The fourth pass transistor stage 123 D may include a plurality of pass transistors driven in response to the fourth block select signal BLKWL 4 . The drains of the pass transistors included in the fourth pass transistor stage 123 D may be electrically coupled to the global word lines GWL_B and GWL_D, respectively. The sources of the pass transistors included in the fourth pass transistor stage 123 D may be electrically coupled to word lines (not shown) of the fourth memory block MB 4 , respectively.

In the case where the fourth memory block MB 4 is selected, the fourth block select signal BLKWL 4 may be enabled by the block decoder 122 , and the word line driving signals DPSB, SB<00:15>, SB<32:47> and SD<16:31> may be provided from the SI decoder 121 to the global word lines GWL_B and GWL_D. The pass transistors of the fourth pass transistor stage 123 D may be turned on in response to the enabled fourth block select signal BLKWL 4 , and may transfer the word line driving signals DPSB, SB<00:15>, SB<32:47> and SD<16:31> to the word lines of the fourth memory block MB 4 .

As will be described below with reference to FIGS. 5 to 9 , a plurality of pass transistors may be formed in each active region. The pass transistors formed in each active region may be coupled in series while pass transistors adjacent to each other may share a source or a drain.

Further, the pass transistors formed in each active region may be disposed in such a manner that pass transistors to be driven by the same block select signal BLKWL are not adjacent to each other and pass transistors to be driven by different block select signals BLKWL are adjacent to each other. Accordingly, a pair of pass transistors to be driven by different block select signals BLKWL may share one drain, and a pair of pass transistors to be driven by different block select signals BLKWL may share one source.

In FIG. 4 , it is illustrated that the word line driving signals DPSA, SA<00:15>, SA<32:47>, DPSB, SB<00:15>, SB<32:47>, SC<16:31> and SD<16:31> may be each provided in common to the drains of a pair of pass transistors to be driven by different block select signals BLKWL. This means that each pair of pass transistors to be driven by different block select signals BLKWL may share one drain.

In FIG. 4 , lines designated by the reference symbols L 1 and L 2 represent that each pair of pass transistors to be driven by different block select signals BLKWL may share a source. In particular, it is noted that the lines L 1 and L 2 may not be physical coupling elements such as wiring lines but may represent electrically coupled states of pass transistors sharing sources.

According to an embodiment, an inactive region may be reduced by forming a plurality of pass transistors in each active region, which reduces the effective area of the pass transistors. Therefore, the chip size of memory devices may decrease. Such technical characteristics will be described below in detail with reference to FIGS. 5 to 9 .

FIG. 5 is a diagram schematically illustrating the layout pattern of the pass transistors included in the pass transistor stages 123 A to 123 D shown in FIG. 4 .

Referring to FIG. 5 , the plurality of memory blocks MB 1 to MB 4 may be arranged in the column direction CD.

As described above with reference to FIGS. 2 and 3 , in each of the memory blocks MB 1 to MB 4 , one or more cell strings including the drain select transistors DST, the plurality of memory cells DC and MC 00 to MC 47 and the source select transistors SST disposed three-dimensionally may be formed. In addition, in each of the memory blocks MB 1 to MB 4 , the drain select lines DSL, a plurality of word lines DWL and WL 00 to WL 47 and the source select lines SSL coupled to the gates of the drain select transistors DST, the plurality of memory cells DC and MC 00 to MC 47 and the source select transistors SST and stacked in the height direction VD, may be formed.

A plurality of first active regions ACT 1 to ACTm (m is an integer equal to or greater than 2) extending in the column direction CD may be formed on one side of the memory blocks MB 1 to MB 4 . For example, the first active regions ACT 1 to ACTm may have a line shape extending in the column direction CD.

The first active regions ACT 1 to ACTm as substrate portions surrounded by an isolation layer may be arranged in the row direction RD perpendicular to the column direction CD.

For example, four sources S and three drains D may be alternately disposed in the column direction CD in each of the first active regions ACT 1 to ACTm. Gates G 1 to G 12 may be disposed between drains D and sources S that are adjacent to each other in the column direction CD. While FIG. 5 shows, as an example, that four sources S and three drains D are alternately disposed in each of the first active regions ACT 1 to ACTm, it is to be noted that three or more sources S and two or more drains D may be provided to be alternately disposed in each of the first active regions ACT 1 to ACTm.

The gates G 1 to G 6 may traverse side by side the first active regions ACT 1 to ACTk in the row direction RD, and the gates G 7 to G 12 may traverse side by side the first active regions ACTk+1 to ACTm in the row direction RD.

Different block select signals BLKWL may be inputted to gates which are adjacent to each other in the column direction CD. For example, the first block select signal BLKWL 1 may be inputted to the gate G 2 , and the second block select signal BLKWL 2 may be inputted to the gates G 1 and G 3 which are adjacent to the gate G 2 in the column direction CD.

In the pass transistor stages 123 A to 123 D, second active regions ACTm+1 and ACTm+2 having a different shape from the first active regions ACT 1 to ACTm may be additionally formed. Unlike the first active regions ACT 1 to ACTm, in each of the second active regions ACTm+1 and ACTm+2, one drain D and two sources S may be formed. While FIG. 5 shows as an example that two sources S and one drain D are formed in each of the second active regions ACTm+1 and ACTm+2, it is to be noted that one source S and one drain D may be formed in each of the second active regions ACTm+1 and ACTm+2.

Gates G 13 and G 14 may be disposed between the drain D and the sources S that are formed in the second active region ACTm+1, and gates G 15 and G 16 may be disposed between the drain D and the sources S that are formed in the second active region ACTm+2. The gates G 13 and G 14 may traverse side by side the second active region ACTm+1 in the row direction RD. The gates G 15 and G 16 may traverse side by side the second active region ACTm+2 In the row direction RD.

Different block select signals BLKWL may be inputted to two gates G that traverse each of the second active regions ACTm+1 and ACTm+2. For example, the first block select signal BLKWL 1 may be inputted to one gate G 13 of the gates G 13 and G 14 that traverse the second active region ACTm+1, and the second block select signal BLKWL 2 may be inputted to the other gate G 14 . Further, the third block select signal BLKWL 3 may be inputted to one gate G 15 of the gates G 15 and G 16 that traverse the second active region ACTm+2, and the fourth block select signal BLKWL 4 may be inputted to the other gate G 16 .

The gates G 2 , G 7 , G 9 and G 13 to which the first block select signal BLKWL 1 may be inputted to construct pass transistors TR 1 for transferring word line driving signals to the first memory block MB 1 , along with the sources S and the drains D disposed on both ends thereof. The gates G 1 , G 3 , G 8 and G 14 to which the second block select signal BLKWL 2 may be inputted to construct pass transistors TR 2 for transferring word line driving signals to the second memory block MB 2 , along with the sources S and the drains D disposed on both ends thereof. The gates G 4 , G 6 , G 11 and G 15 to which the third block select signal BLKWL 3 may be inputted to construct pass transistors TR 3 for transferring word line driving signals to the third memory block MB 3 , along with the sources S and the drains D disposed on both ends thereof. The gates G 5 , G 10 , G 12 and G 16 to which the fourth block select signal BLKWL 4 may be inputted to construct pass transistors TR 4 for transferring word line driving signals to the fourth memory block MB 4 , along with the sources S and the drains D disposed on both ends thereof.

In the pass transistors disposed in the first active regions ACT 1 to ACTm, pass transistors disposed at inner parts of the first active regions ACT 1 to ACTm may share sources S with pass transistors disposed adjacent to them. Also, pass transistors disposed at both ends of the first active regions ACT 1 to ACTm may not share sources S with pass transistors disposed adjacent to them. The pass transistors disposed in the second active regions ACTm+1 and ACTm+2 may not share sources S with pass transistors disposed adjacent to them.

Pass transistors that do not share sources S with other pass transistors, such as the pass transistors disposed at both ends of the first active regions ACT 1 to ACTm and the pass transistors disposed in the second active regions ACTm+1 and ACTm+2, may be electrically coupled to the word lines of 2 or 3 memory cells adjacent to the drain select transistors DST, and may individually transfer word line driving signals to the 2 or 3 memory cells adjacent to the drain select transistors DST.

FIG. 6 is a diagram illustrating the layout structure of wiring lines associated with the pass transistors disposed in the first active region ACT 1 of FIG. 5 .

The wiring lines associated with the pass transistors disposed in the remaining first active regions ACT 2 to ACTm may have a similar layout structure to the structure shown in FIG. 6 .

Referring to FIG. 6 , a plurality of pass transistors TR 2 _ 1 , TR 1 , TR 2 _ 2 , TR 3 _ 1 , TR 4 and TR 3 _ 2 may be disposed in the first active region ACT 1 . The pass transistors TR 2 _ 1 , TR 1 , TR 2 _ 2 , TR 3 _ 1 , TR 4 and TR 3 _ 2 may be coupled in series so that adjacent pass transistors may share one of a source S and a drain D. Accordingly, the sources S and the drains D of adjacent pass transistors may have an opposite disposition.

In two pass transistors which share a drain D or a source S, different block select signals BLKWL may be inputted to their respective gates G. For example, in the pass transistors TR 2 _ 1 and TR 1 that share a drain D 1 , the second block select signal BLKWL 2 may be inputted to the gate G 1 of the pass transistors TR 2 _ 1 , while the first block select signal BLKWL 1 may be inputted to the gate G 2 of the pass transistor TR 1 . Similarly, in the pass transistors TR 1 and TR 2 _ 2 which share a source S 2 , the first block select signal BLKWL 1 may be inputted to the gate G 2 of the pass transistors TR 1 , while the second block select signal BLKWL 2 may be inputted to the gate G 3 of the pass transistor TR 2 _ 2 .

The global word lines GWL_A, GWL_D and GWL_B extending in the column direction CD may be formed in a metal layer lying over the gates G 1 to G 6 . The global word lines GWL_A, GWL_D and GWL_B may transfer the word line driving signals SA<15>, SD<31> and SB<15> provided from the SI decoder 121 (see FIG. 4 ) in the column direction CD.

The global word line GWL_A may be electrically coupled to the common drain D 1 of the pass transistors TR 2 _ 1 and TR 1 through a contact plug CNT 1 , and may provide the word line driving signal SA<15> to the common drain D 1 . The global word line GWL_D may be electrically coupled to a common drain D 2 of the pass transistors TR 2 _ 2 and TR 3 _ 1 through a contact plug CNT 2 , and may provide the word line driving signal SD<31> to the common drain D 2 . The global word line GWL_B may be electrically coupled to a common drain D 3 of the pass transistors TR 4 and TR 3 _ 2 through a contact plug CNT 3 , and may provide the word line driving signal SB<15> to the common drain D 3 .

The common source S 2 of the pass transistors TR 1 and TR 2 _ 2 may be electrically coupled to the word line WL 15 of the first memory block MB 1 and the word line WL 31 of the second memory block MB 2 through driving signal lines LWL_V 1 , LWL_H 1 and LWL_H 2 . The pass transistor TR 1 may transfer the word line driving signal SA<15> inputted to the drain D 1 thereof, to the word line WL 15 of the first memory block MB 1 and the word line WL 31 of the second memory block MB 2 , through the source S 2 and the driving signal lines LWL_V 1 , LWL_H 1 and LWL_H 2 , in response to the first block select signal BLKWL 1 . The pass transistor TR 2 _ 2 may transfer the word line driving signal SD<31> inputted to the drain D 2 thereof, to the word line WL 15 of the first memory block MB 1 and the word line WL 31 of the second memory block MB 2 , through the source S 2 and the driving signal lines LWL_V 1 , LWL_H 1 and LWL_H 2 , in response to the second block select signal BLKWL 2 .

Similarly, a common source S 3 of the pass transistors TR 3 _ 1 and TR 4 may be electrically coupled to the word line WL 31 of the third memory block MB 3 and the word line WL 15 of the fourth memory block MB 4 through driving signal lines LWL_V 2 , LWL_H 3 and LWL_H 4 . The pass transistor TR 3 _ 1 may transfer the word line driving signal SD<31> inputted to the drain D 2 thereof, to the word line WL 31 of the third memory block MB 3 and the word line WL 15 of the fourth memory block MB 4 , through the source S 3 and the driving signal lines LWL_V 2 , LWL_H 3 and LWL_H 4 , in response to the third block select signal BLKWL 3 . The pass transistor TR 4 may transfer the word line driving signal SB<15> inputted to the drain D 3 thereof, to the word line WL 31 of the third memory block MB 3 and the word line WL 15 of the fourth memory block MB 4 , through the source S 3 and the driving signal lines LWL_V 2 , LWL_H 3 and LWL_H 4 , in response to the fourth block select signal BLKWL 4 .

In word lines WL of memory blocks MB which are electrically coupled to each of the common sources S 2 and S 3 , the word line WL of one memory block MB and the word line WL of the other memory block MB may be different from each other in their stack positions. For example, in the word line WL 15 of the first memory block MB 1 and the word line WL 31 of the second memory block MB 2 which are electrically coupled to the common source S 2 , the word line WL 15 of the first memory block MB 1 may be disposed in a higher layer than the word line WL 31 of the second memory block MB 2 . Similarly, in the word line WL 31 of the third memory block MB 3 and the word line WL 15 of the fourth memory block MB 4 which are electrically coupled to the common source S 3 , the word line WL 31 of the third memory block MB 3 may be disposed in a lower layer than the word line WL 15 of the fourth memory block MB 4 .

Since word lines of memory blocks which are coupled in common to one common source may be disposed in different layers, word line driving signals may be applied to the respective memory blocks in different patterns. Accordingly, word line driving signals (word line voltages) may be provided such that a disturbance does not occur in one memory block while a program operation is performed in another memory block. These features will be described later in more detail with reference to FIGS. 10 to 12 .

The pass transistors TR 2 _ 1 and TR 3 _ 2 which are positioned at both ends of the first active region ACT 1 may not share sources S with other pass transistors due to a positional issue. Each of the pass transistors TR 2 _ 1 and TR 3 _ 2 which are positioned at both ends of the first active region ACT 1 may be electrically coupled to one of the word lines of memory blocks, and may individually transfer a word line driving signal to the one word line.

For example, the source S 1 of the pass transistor TR 2 _ 1 may be electrically coupled to the word line WL 15 of the second memory block MB 2 through driving signal lines LWL_V 3 and LWL_H 5 , and the pass transistors TR 2 _ 1 may transfer the word line driving signal SA<15> inputted to the drain D 1 thereof, to the word line WL 15 of the second memory block MB 2 , through the source S 1 and the driving signal lines LWL_V 3 and LWL_H 5 , in response to the second block select signal BLKWL 2 .

Similarly, a source S 4 of the pass transistor TR 3 _ 2 may be electrically coupled to the word line WL 15 of the third memory block MB 3 through driving signal lines LWL_V 4 and LWL_H 6 , and the pass transistors TR 3 _ 2 may transfer the word line driving signal SB<15> inputted to the drain D 3 thereof, to the word line WL 15 of the third memory block MB 3 , through the source S 4 and the driving signal lines LWL_V 4 and LWL_H 6 , in response to the third block select signal BLKWL 3 .

Pass transistors that do not share sources S with other pass transistors, such as the pass transistors TR 2 _ 1 and TR 3 _ 2 , may be electrically coupled to the word lines of 2 or 3 memory cells adjacent to the drain select transistors DST, and may individually transfer word line driving signals to these memory cells. This will be described in more detail later with reference to FIGS. 13 and 14 .

The driving signal lines LWL_V 1 to LWL_V 4 and LWL_H 1 to LWL_H 6 may be electrically coupled between the sources S 1 to S 4 of the pass transistors TR 2 _ 1 , TR 1 , TR 2 _ 2 , TR 3 _ 1 , TR 4 and TR 3 _ 2 and the memory blocks MB 1 to MB 4 , and may transfer the word line driving signals SA<15>, SD<31> and SB<15> provided to the sources S 1 to S 4 of the pass transistors TR 2 _ 1 , TR 1 , TR 2 _ 2 , TR 3 _ 1 , TR 4 and TR 3 _ 2 , to the memory blocks MB 1 to MB 4 .

The driving signal lines LWL_V 1 to LWL_V 4 and LWL_H 1 to LWL_H 6 may include, for example, first signal lines LWL_V 1 to LWL_V 4 for transferring the word line driving signals SA<15>, SD<31> and SB<15> in the column direction CD, and second signal lines LWL_H 1 to LWL_H 6 for transferring the word line driving signals SA<15>, SD<31> and SB<15> in the row direction RD.

The first signal lines LWL_V 1 to LWL_V 4 may be formed in the same metal layer as the global word lines GWL_A, GWL_D and GWL_B, and may be electrically coupled to the sources S 1 to S 4 through metal contacts CNT 4 to CNT 7 . The second signal lines LWL_H 1 to LWL_H 6 may be formed, for example, in a metal layer lying under the first signal lines LWL_V 1 to LWL_V 4 , and may be electrically coupled to the first signal lines LWL_V 1 to LWL_V 4 and the word lines of the memory blocks MB through metal contacts (not shown).

While FIG. 6 shows as an example that the first signal lines LWL_V 1 to LWL_V 4 are formed in the same metal layer as the global word lines GWL_A, GWL_D and GWL_B and the second signal lines LWL_H 1 to LWL_H 6 are formed in a metal layer lying under the global word lines GWL_A, GWL_D and GWL_B, it is noted that the structures of the driving signal lines LWL_V 1 to LWL_V 4 and LWL_H 1 to LWL_H 6 may be changed and applied such that the first signal lines LWL_V 1 to LWL_V 4 are formed in a layer different from the global word lines GWL_A, GWL_D and GWL_B or the second signal lines LWL_H 1 to LWL_H 6 are formed in a metal layer lying over the first signal lines LWL_V 1 to LWL_V 4 .

A first signal line LWL_V may be electrically coupled to each of the common sources S 2 and S 3 which are shared by adjacent pass transistors. For example, the first signal line LWL_V 1 may be electrically coupled to the common source S 2 , and the first signal line LWL_V 2 may be electrically coupled to the common source S 3 . Therefore, the number of first signal lines LWL_V may be decreased compared to a structure in which pass transistors do not share sources and thus it is necessary to couple first signal lines LWL_V individually to the sources of the pass transistors.

The layout structure of the driving signal lines LWL_V and LWL_H may be changed into various shapes, and replaceable embodiments will be described below with reference to FIGS. 7 to 9 .

FIGS. 7 to 9 are diagrams illustrating various layout patterns of driving signal lines LWL_V and LWL_H.

In the following descriptions to be made with reference to FIGS. 7 to 9 , repeated descriptions for configurations already described above with reference to FIGS. 5 and 6 will be omitted.

Referring to FIG. 7 , first signal lines LWL_V of driving signal lines LWL_V and LWL_H may be disposed on the first active regions ACT 1 to ACTm in such a way as to overlap with the first active regions ACT 1 to ACTm. The first signal lines LWL_V may be individually coupled to corresponding sources S of edge pass transistors TR_EU 1 to TR_EUm and TR_ED 1 to TR_EDm which are positioned at both ends of the first active regions ACT 1 to ACTm. The first signal lines LWL_V coupled to the sources S of the edge pass transistors TR_EU 1 to TR_EUm and TR_ED 1 to TR_EDm each may be electrically coupled to one of the word lines of the memory blocks MB through a second signal line LWL_H.

The edge pass transistors TR_EU 1 to TR_EUm and TR_ED 1 to TR_EDm each may be electrically coupled to one of the word lines DWL, WL 00 and WL 01 of the outermost main memory cell MC 00 adjoining the drain select transistor DST, which is susceptible to a disturbance and the memory cells DC and MC 01 adjacent thereto, and may provide word line driving signals individually to the word lines DWL, WL 00 and WL 01 of the memory cells DC, MC 00 and MC 01 .

Similarly to the edge pass transistors TR_EU 1 to TR_EUm and TR_ED 1 to TR_EDm, each of the pass transistors disposed in the second active regions ACTm+1 and ACTm+2 of FIG. 5 may be electrically coupled to one of the word lines DWL, WL 00 and WL 01 of the memory cells DC, MC 00 and MC 01 .

Referring to FIG. 8 , the edge pass transistors TR_EU 1 to TR_EUm and TR_ED 1 to TR_EDm which are positioned at both ends of the first active regions ACT 1 to ACTm may be paired so that each pair of edge pass transistors may be driven by different block select signals BLKWL. Each pair of edge pass transistors may be electrically coupled to a first signal line LWL_V. Each of the first signal lines LWL_V may be electrically coupled to a pair of word lines which are included in different memory blocks MB, through two second signal lines LWL_H. For example, a first edge pass transistor TR_EU 1 to be driven by the third block select signal BLKWL 3 and a (k+1)th edge pass transistor TR_EUk+1 to be driven by the fourth block select signal BLKWL 4 may be paired with each other and may be electrically coupled to a first signal line LWL_V. The first signal line LWL_V may be electrically coupled to a word line included in the third memory block MB 3 and a word line included in the fourth memory block MB 4 , through two second signal lines LWL_H.

Therefore, since it may be sufficient to form only a first signal line LWL_V for two edge pass transistors, the number of first signal lines LWL_V may be decreased. Accordingly, since the space/distance between first signal lines LWL_V may be widened, interference between the first signal lines LWL_V may be reduced.

Referring to FIG. 9 , some of the first signal lines LWL_V of driving signal lines LWL_V and LWL_H may be disposed on, instead of the first active regions ACT 1 to ACTm, a slimming region SR. As described above with reference to FIG. 3 , the slimming region SR may be a region where the edge portions of the drain select lines DSL, the word lines DWL and WL and the source select lines SSL of the memory blocks MB may be exposed in the form of a stair.

According to the embodiment shown in FIG. 9 , since some of the first signal lines LWL_V may be disposed on the slimming region SR, the number of first signal lines LWL_V disposed on the first active regions ACT 1 to ACTm may be decreased. Accordingly, since the space/distance between first signal lines LWL_V may be widened, interference between the first signal lines LWL_V may be reduced.

FIG. 10 illustrates a relationship between the word lines of the first and second memory blocks MB 1 , MB 2 .

In the circuit diagram shown on the left side of FIG. 10 , there are illustrated only one cell string for each of the first and second memory blocks MB 1 , MB 2 . The cell strings of each of the first and second memory blocks MB 1 , MB 2 may be coupled to the same bit line BL.

In the table shown on the right side of FIG. 10 , word lines DWL, WL of the left column may be the word lines of the first memory block MB 1 , and word lines DWL, WL of the right column may be the word lines of the second memory block MB 2 . Further, word lines DWL, WL given in the same row may be a pair of word lines coupled in common to one of the sources of pass transistor stages and may be provided with the same word line driving signal.

Referring to FIG. 10 , the word lines DWL and WL 00 to WL 47 of the first memory block MB 1 and the word lines DWL and WL 00 to WL 47 of the second memory block MB 2 may be paired in a one-to-one basis, and each pair of word lines may be coupled in common to one of the sources of the pass transistor stages and be provided with the same word line driving signal.

For example, the word line WL 00 of the first memory block MB 1 and the word line WL 31 of the second memory block MB 2 may be paired with each other and coupled in common to one source of the pass transistor stages. The same word line driving signal may be transferred to the word lines WL 00 and WL 31 from two pass transistors which share the source.

In particular, in order to prevent the outermost main memory cell MC 00 adjoining the drain select transistor DST, which may be susceptible to a disturbance, from being programmed in an undesired manner, each of the word lines DWL, WL 00 and WL 01 coupled to the outermost main memory cell MC 00 and the adjacent memory cells DC and MC 01 of the first memory block MB 1 may be paired with one of the word lines WL 02 to WL 47 of the second memory block MB 2 , that is one of the remaining word lines other than the word lines DWL, WL 00 and WL 01 of the second memory block MB 2 . Each pair of word lines may be transferred with the same word line driving signal from the pass transistor stages. For example, the word lines DWL, WL 00 and WL 01 of the first memory block MB 1 may be paired with the word lines WL 06 , WL 31 and WL 11 of the second memory block MB 2 , respectively. Respective pairs of word lines may be transferred with the same word line driving signals from the pass transistor stages.

Accordingly, in the case where the main memory cell MC 31 of the second memory block MB 2 is programmed and a program voltage is transferred to the outermost main word line WL 00 of the first memory block MB 1 which is provided with the same word line driving signal as the main word line WL 31 of the second memory block MB 2 , a program prohibition bias may be applied to the word lines DWL, WL 01 of the unselected memory block MB 1 which are adjacent to the main word line WL 00 so that the main memory cell MC 00 of the unselected memory block MB 1 may not be programmed.

FIGS. 11 and 12 are diagrams illustrating bias application states in the case where the memory cell MC 31 of the second memory block MB 2 in FIG. 10 is programmed.

Referring to FIG. 11 , in the case where the main memory cell MC 31 of the second memory block MB 2 is programmed, a ground voltage of 0V may be applied to the bit line BL, and a power supply voltage VCC may be applied to the drain select line DSL of the selected memory block MB 2 . Further, the ground voltage of 0V may be applied to the drain select line DSL of the unselected memory block MB 1 and the common source lines CSL of the memory blocks MB 1 , MB 2 .

A program voltage VPGM as a word line driving signal may be applied to the main word line WL 31 of the second memory block MB 2 and the main word line WL 00 of the first memory block MB 1 which are coupled in common to a source of the pass transistor stages. A first pass voltage VPASS 1 as a word line driving signal, lower than the program voltage VPGM, may be applied to the word lines WL 02 to WL 47 of the first memory block MB 1 and word lines of the second memory block MB 2 which are coupled in common to sources of the pass transistor stages. A second pass voltage VPASS 2 as a word line driving signal, lower than the program voltage VPGM and higher than the first pass voltage VPASS 1 , may be applied to the word lines DWL and WL 01 of the first memory block MB 1 and the word lines WL 06 and WL 11 of the second memory block MB 2 which are coupled in common to sources of the pass transistor stages. For example, the program voltage VPGM may be 18V, the first pass voltage VPASS 1 may be 9V, and the second pass voltage VPASS 2 may be 10V.

Accordingly, since the second pass voltage VPASS 2 and the program voltage VPGM higher than the first pass voltage VPASS 1 may be coupled to the channels of the memory cells DC, MC 00 and MC 01 of the first memory block MB 1 , potential differences between the boosted channel voltages of the memory cells DC, MC 00 and MC 01 of the first memory block MB 1 and the program voltage VPGM applied to the word line WL 00 of the first memory block MB 1 may be smaller than a potential difference necessary for F−N tunneling. In this way, the outermost main memory cell MC 00 of the first memory block MB 1 may be prevented to be programmed unintentionally.

Referring to FIG. 12 , a decoupling voltage VLOCAL as a word line driving signal may be applied to the word lines DWL and WL 01 of the first memory block MB 1 and the word lines WL 06 and WL 11 of the second memory block MB 2 which are coupled in common to sources of the pass transistor stages. For example, the decoupling voltage VLOCAL may be 0V.

Accordingly, as the memory cells DC and MC 01 of the first memory block MB 1 are turned off, the channel portion of the main memory cell MC 00 of the first memory block MB 1 may be electrically decoupled from the other channel portions and may become a floating state. Hence, the program voltage VPGM applied to the word line WL 00 of the first memory block MB 1 may be coupled to the channel of the memory cell MC 00 of the first memory block MB 1 . Therefore, a potential difference between the voltage of the word line WL 00 of the first memory block MB 1 and the boosted channel voltage of the memory cell MC 00 of the first memory block MB 1 may be smaller than a potential difference necessary for F−N tunneling, whereby the outermost main memory cell MC 00 of the first memory block MB 1 may be prevented to be programmed in an unintentional manner.

FIG. 13 illustrates a relationship between the word lines of the memory block MB 1 and the word lines of the memory block MB 2 .

For example, in the table of FIG. 13 , word lines DWL and WL of the left column may be the word lines of the first memory block MB 1 , and word lines DWL and WL of the right column may be the word lines of the second memory block MB 2 . Further, word lines DWL and WL given in the same row may be a pair of word lines that are coupled in common to one of the sources of pass transistor stages and may be provided with the same word line driving signal.

Referring to FIG. 13 , for preventing occurrence of a phenomenon that the outermost main memory cells MC 00 adjoining the drain select transistors DST, which are susceptible to a disturbance, are programmed in an unintentional manner, the word lines DWL, WL 00 and WL 01 of the outermost main memory cells MC 00 and the adjacent memory cells DC and MC 01 included in the first and second memory blocks MB 1 and MB 2 may be respectively coupled to pass transistors which do not share sources, among the pass transistors of the pass transistor stages, and may be individually provided with word line driving signals from the pass transistor stages.

Each of the word lines DWL, WL 00 and WL 01 of the outermost main memory cells MC 00 and the adjacent memory cells DC and MC 01 may be electrically coupled to one of, for example, the edge pass transistors positioned at both ends of the first active regions ACT 1 to ACTm or the pass transistors formed in the second active regions ACTm+1 and ACTm+2 shown in FIG. 5 , and may be provided with a word line driving signal from one of the edge pass transistors or the pass transistors formed in the second active regions ACTm+1 and ACTm+2.

Meanwhile, the other word lines WL 02 to WL 47 excluding the word lines DWL, WL 00 and WL 01 of the outermost main memory cells MC 00 and the adjacent memory cells DC and MC 01 may be paired so that each pair may include word lines belonging to different memory blocks MB. Each pair of word lines may be coupled in common to a source of the pass transistor stages, and may be transferred with a word line driving signal from two pass transistors sharing the source.

FIG. 14 illustrates a bias application state in the case where the memory cell MC 31 of the second memory block MB 2 in FIG. 13 is programmed.

Referring to FIG. 14 , in the case where the main memory cell MC 31 of the second memory block MB 2 is programmed, a ground voltage of 0V may be applied to the bit line BL, and a power supply voltage VCC may be applied to the drain select line DSL of the selected memory block MB 2 . Further, the ground voltage of 0V may be applied to the drain select line DSL of the unselected memory block MB 1 and the common source lines CSL of the memory blocks MB 1 and MB 2 .

A program voltage VPGM as a word line driving signal may be applied to the main word line WL 31 of the second memory block MB 2 and a word line of the first memory block MB 1 which are coupled in common to a source of the pass transistor stages. A first pass voltage VPASS 1 as a word line driving signal may be applied to the remaining word lines DWL, WL 00 to WL 30 and WL 32 to WL 47 of the second memory block MB 2 .

Further, the first pass voltage VPASS 1 as a word line driving signal may be applied to remaining word lines of the first memory block MB 1 other than the word line which may be coupled to the same source as the main word line WL 31 of the second memory block MB 2 , among the word lines DWL and WL 00 to WL 47 of the first memory block MB 1 .

Since the word lines DWL, WL 00 and WL 01 of the first memory block MB 1 may be electrically decoupled from the word lines of the second memory block MB 2 , the first pass voltage VPASS 1 may be applied to the word lines DWL, WL 00 and WL 01 of the first memory block MB 1 regardless of word line driving signals applied to the word lines of the second memory block MB 2 , whereby it is possible to prevent the main memory cell MC 00 of the first memory block MB 1 to be programmed in an unintentional manner.

FIG. 15 is a block diagram schematically illustrating a memory system 600 including a nonvolatile memory device 620 , according to an embodiment of the invention.

The memory system 600 may also include a memory controller 610 . The memory controller 610 may control the nonvolatile memory device 620 . By the combination of the nonvolatile memory device 620 and the memory controller 610 , a memory card or a solid state disk (SSD) may be provided. An SRAM 611 may be used as the working memory of a central processing unit (CPU) 612 . A host interface 613 may include the data exchange protocol of a host which may be coupled with the memory system 600 .

An error correction code (ECC) block 614 may detect and correct an error included in the data read out from the nonvolatile memory device 620 .

A memory interface 615 may interface with the nonvolatile memory device 620 . The CPU 612 may perform general control operations for data exchange of the memory controller 610 .

Although not shown, it should become apparent to a person skilled in the art that the memory system 600 may further be provided with a ROM which stores code data for interfacing with the host. The nonvolatile memory device 620 may be provided as a multi-chip package constructed by a plurality of flash memory chips.

The memory system 600 may be used as a storage medium of high reliability having a low probability of an error occurring. In particular, the aforementioned semiconductor memory device may be provided for a memory system such as a solid state disk (SSD). In this case, the memory controller 610 may communicate with an external device (for example, the host) through one of various interface protocols such as a USB (universal serial bus) protocol, an MMC (multimedia card) protocol, a PCI-E (peripheral component interconnection express) protocol, an SATA (serial advanced technology attachment) protocol, a PATA (parallel advanced technology attachment) protocol, an SCSI (small computer system interface) protocol, an ESDI (enhanced small disk interface) protocol and an IDE (integrated device electronics) protocol.

FIG. 16 is a block diagram schematically illustrating a computing system including a nonvolatile memory device in according to an embodiment.

Referring to FIG. 16 , a computing system 700 in according to an embodiment may include a microprocessor (or CPU) 720 , a RAM 730 , a user interface 740 , a modem 750 such as a baseband chipset, and a memory system 710 , which are electrically coupled to a system bus 760 . In the case where the computing system 700 in according to the embodiment is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system 700 may be additionally provided. Although not shown in the drawing, it should become apparent to a person skilled in the art that the computing system 700 may further comprise an application chipset, a camera image processor (CIS), a mobile DRAM, and so on. The memory system 710 may be configured, for example, as an SSD (solid state drive/disk) which uses a nonvolatile memory to store data. Or also as an example, the memory system 710 may be provided as a fusion flash memory (for example, a OneNAND flash memory).

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the nonvolatile memory device described herein should not be limited based on the described embodiments. Many other embodiments and variations thereof may be envisaged by those skilled in the art to which the invention pertains without departing from the scope and spirit of the invention as defined by the appended claims.