Resistive memory and measurement system thereof

This application claims priority of Taiwan Patent Application No. 104105250, filed on Feb. 16, 2015, the entirety of which is incorporated by reference herein.

The invention relates to a non-volatile memory, and more particularly to a resistive memory and a measurement system thereof.

Generally, memory units used in computers comprise volatile memories and non-volatile memories. The non-volatile memories comprise read-only memories (ROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and flash memories. The volatile memories comprise dynamic random access memories (DRAMs) and static random access memories (SRAMs).

New kinds of volatile memory comprise ferroelectric memory, Phase-change memory, Magnetoresistive Random Access Memory (MRAM) and Resistive Random Access Memory (RRAM). The RRAMs are used widely, as they possess such favorable advantages as having a simple structure, low cost, high speed, and low power consumption.

In accordance with an embodiment, a measurement system comprises a testing machine and a resistive memory. The testing machine provides a row address, a column address, a word voltage, a bit voltage and a source voltage. The resistive memory comprises a row controller, a column controller, and a first storage cell. The row controller is coupled to a plurality of word lines and transmits the word voltage to a first word line among the word lines according to the row address. The column controller is coupled to a plurality of bit lines and transmits the bit voltage to a first bit line among the bit lines according to the column address. The first storage cell comprises at least one transistor and at least one variable resistor. A gate of the transistor is coupled to the first word line. A source of the transistor is coupled to a source line. The variable resistor is couple between the first bit line and a drain of the transistor. The source line receives the source voltage. In a specific period, the testing machine provides a write voltage to change the state of the variable resistor. The testing machine maintains the level of the write voltage and measures the current flowing through the variable resistor in a maintaining period. When the current flowing through the variable resistor does not arrive at a pre-determined value, the testing machine increases the write voltage.

In accordance with another embodiment, a resistive memory receives a row address, a column address, a word voltage, a bit voltage, and a source voltage and comprises a row controller, a column controller, and a first storage cell. The row controller is coupled to a plurality of word lines and transmits the word voltage to a first word line among the word lines according to the row address. The column controller is coupled to a plurality of bit line and transmits the bit voltage to a first bit line among the bit lines according to the column address. The first storage cell comprises at least one transistor and at least one variable resistor. A gate of the transistor is coupled to the first word line. A source of the transistor is coupled to a source line. The variable resistor is coupled between the first bit line and a drain of the transistor. The source line receives the source voltage. In a specific period, the resistive memory receives a write voltage to change the state of the variable resistor. The level of the write voltage is maintained in a maintaining period. When the current flowing through the variable resistor does not arrive at a pre-determined value, the level of the write voltage received by the resistive memory is increased.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of an exemplary embodiment of a measurement system, according to various aspects of the present disclosure;

FIGS. 2A and 2B are schematic diagrams of exemplary embodiments of a storage cell, according to various aspects of the present disclosure;

FIG. 3 is a schematic diagram illustrating the relationship between a bit voltage and the current flowing through a variable resistor when a specific period is a forming period;

FIG. 4 is a schematic diagram illustrating the relationship between a bit voltage and the current flowing through a variable resistor when a specific period is a set period; and

FIG. 5 is a schematic diagram illustrating the relationship between a source voltage and the current flowing through a variable resistor when the specific period is a reset period.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 is a schematic diagram of an exemplary embodiment of a measurement system, according to various aspects of the present disclosure. The measurement system 100 comprises a testing machine 110 and a resistive RAM (RRAM) 120 . The testing machine 110 is configured to determine whether the resistive RAM 120 can access data normally. In this embodiment, the testing machine 110 provides a word voltage V WL , a bit voltage V BL , a source voltage V SL , a row address ADS R and a column address ADS C . In one embodiment, the row address ADS R and the column address ADS C are parallel data.

The resistive RAM 120 comprises a row controller 121 , a column controller 122 , a source controller 123 , and storage cells CL 11 ˜CL mn . The row controller 121 is coupled to the bit lines WL 1 ˜WL m and transmits the word voltage V WL to one of the bit lines WL 1 ˜WL m . In other embodiments, the row controller 121 can provide the word voltage V WL to 2 or more bit lines.

In this embodiment, the row controller 121 comprises a word-line logic controller 124 and a row decoder 125 . The word-line logic controller 124 receives the word voltage V WL and provides the word voltage V WL to the row decoder 125 . The row decoder 125 decodes the row address ADS R and outputs the word voltage V WL to at least one of the bit lines WL 1 ˜WL m according the decoded result. Furthermore, the column controller 122 is coupled to the bit lines BL 1 ˜BL n and transmits the bit voltage V BL to one of the bit lines BL 1 ˜BL n according to the column address ADS C . In other embodiments, the column controller 122 may provide the bit voltage V BL to 2 or more bit lines. In this embodiment, the column controller 122 comprises a bit-line logic controller 126 and a column decoder 127 . The bit-line logic controller 125 receives the bit voltage V BL and provides the bit voltage V BL to the column decoder 127 . The column decoder 127 decodes the column address ADS C and outputs the bit voltage V BL to at least of the bit lines BL 1 ˜BL n according to the decoded result.

Each of the storage cells CL 11 ˜CL mn is coupled to a corresponding word line, a corresponding bit line, and a corresponding source line to receive the word voltage V WL , the bit voltage V BL , and the source voltage V SL . Taking the storage cell CL 11 as an example, the storage cell CL 11 is coupled to the word line WL 1 , the bit line BL 1 , and the source line SL 1 . In another embodiment, the word line WL 1 comprises two sub-word lines (not shown), and the bit line BL 1 may comprise two sub-bit lines (not shown). Therefore, the storage cell CL 11 may be coupled to two sub-word lines and/or two sub-bit lines.

In this embodiment, the storage cells, such as CL 11 ˜CL mn arranged in the same row are coupled to the same source line. For example, the storage cells CL 11 ˜CL mi are coupled to the source line SL 1 , and the storage cells CL 1n ˜CL mn are coupled to the source line SL n . In some embodiments, different storage cells are coupled to different source lines. The invention does not limit the arrangement of the storage cells. In one embodiment, the storage cells CL 11 ˜CL mn are arranged in an array. In particular, the source controller 123 receives the source voltage V SL and provides the source voltage V SL to the source lines SL 1 ˜SL n . In this embodiment, the source controller 123 provides the source voltage V SL to the storage cells CL 11 ˜CL mn via the source lines SL 1 ˜SL n . In some embodiments, the source controller 123 only utilizes a single source line to provide the source voltage V SL to the storage cells CL 11 ˜CL mn .

FIG. 2A is a schematic diagram of an exemplary embodiment of a storage cell, according to various aspects of the present disclosure. Since the structures of the storage cells CL 11 ˜CL mn are the same, the storage cell CL 11 is given as an example. As shown in FIG. 2A , the storage cell CL 11 comprises a transistor 210 and a variable resistor 220 . The storage cell CL 11 operates at a high resistance state (HRS) or at a low resistance state (LRS) according to the word voltage V WL , the bit voltage V BL , and the source voltage V SL to represent that the storage cell CL 11 stores data “0” or data “1”. The gate of the transistor 210 is coupled to the word line WL 1 to receive the word voltage V WL . The source of the transistor 210 is coupled to the source line SL 1 to receive the source voltage V sL . The variable resistor 220 is coupled between the bit line BL 1 and the drain of the transistor 210 and receives the bit voltage V BL . The testing machine 110 controls the word voltage V WL , the bit voltage V BL , and the source voltage V sL to control the state of the variable resistor 220 .

FIG. 2B is a schematic diagram of another exemplary embodiment of the storage cell, according to various aspects of the present disclosure. The storage cell CL 1 shown in FIG. 2B comprises transistors 230 and 250 and variable resistors 240 and 260 . The gate of the transistor 230 is coupled to the word line WL 1A . The source of the transistor 230 is coupled to the source line SL 1 . The variable resistor 240 is coupled between the drain of the transistor 230 and the bit line BL 1A . The gate of the transistor 250 is coupled to the word line WL 1B . The source of the transistor 250 is coupled to the source line SL 1 . The variable resistor 260 is coupled between the drain of the transistor 250 and the bit line BL 1B .

In FIG. 2 , the transistors 230 and 250 are coupled to the same source line SL 1 , but the disclosure is not limited thereto. In another embodiment, the transistors 230 and 250 are coupled to different source lines. In some embodiments, the variable resistors 240 and 260 are coupled to the same bit line. In this embodiment, the testing machine 110 controls the voltage levels of the word lines WL 1A and WL 1B , the bit lines BL 1A and BL 1B , and the source line SL 1 to control the state of the variable resistors 240 and 260 such that the storage cell CL 11 stores the corresponding data.

For example, when the variable resistor 240 is at a LRS and the variable resistor 260 is at a HRS, it means that the storage cell CL 11 stores data “0” or data “1”. When the variable resistor 240 is at the HRS and the variable resistor 260 is at the LRS, it means that the storage cell CL 11 stores the data “1” or the data “0”. In another embodiment, when the variable resistors 240 and 260 are at the LRS, it means that the storage cell CL 11 stores the data “0” or the data “1”. When the variable resistors 240 and 260 are at the HRS, it means that the storage cell CL 11 stores the data “1” or the data “0”.

In this embodiment, the testing machine 110 provides a write voltage to change the state of the variable resistor 220 in a specific period and maintains the write voltage to measure the current flowing through the variable resistor 220 in a maintaining period. When the current flowing through the variable resistor 220 is less than a pre-determined value, the testing machine 110 increases the write voltage and provides the increased write voltage to the storage cell CL 11 .

The invention does not limit the specific period. In one embodiment, the specific period is a forming period, a reset period, or a set period. When the specific period is the forming period, the testing machine 110 utilizes the word voltage V WL , the bit voltage V BL , and the source voltage V SL to set the state of the variable resistor 220 at a LRS. During this period, the bit voltage V BL is higher than the source voltage V SL . When the testing machine 110 tests the storage cell CL 11 in the forming period, the write voltage is the bit voltage V BL . The testing machine 110 increases the bit voltage V BL and measures the current flowing through the variable resistor 220 .

When the specific period is the reset period, the testing machine 110 similarly utilizes the word voltage V WL , the bit voltage V BL , and the source voltage V SL to set the state of the variable resistor 220 from the LRS to a HRS. During this period, the bit voltage V BL is less than the source voltage V SL . When the testing machine 110 tests the storage cell CL 11 in the reset period, the write voltage is the source voltage V SL . The testing machine 110 increases the source voltage V SL and measures the current flowing through the variable resistor 220 .

When the specific period is the set period, the testing machine 110 utilizes the word voltage V WL , the bit voltage V BL , and the source voltage V SL to set the state of the variable resistor 220 from the HRS to the LRS. During this period, the bit voltage V BL is higher than the source voltage V SL . When the testing machine 110 tests the storage cell CL 11 in the set period, the write voltage is the bit voltage V BL . The testing machine 110 increases the bit voltage V BL and measures the current flowing through the variable resistor 220 .

FIG. 3 is a schematic diagram illustrating the relationship between the bit voltage V BL and the current flowing through the variable resistor 220 when the specific period is the forming period. The curve 310 represents the current flowing through the variable resistor 220 . The curve 320 represents the level of the bit voltage V BL . The testing machine 110 stepwise adjusts the bit voltage V BL of the bit line BL 1 in the forming period 300 to change the state of the variable resistor 220 . At this time, the testing machine 110 maintains the level of the source voltage V SL and provides a forming voltage to serve as the word voltage V WL .

In this embodiment, the testing machine 110 provides the bit voltage V BL to the storage cell CL 11 . The testing machine 110 maintains the level of the bit voltage V BL and measures the current flowing through the variable resistor 220 . When the current flowing through the variable resistor 220 does not arrive at a pre-determined value I M1 , the testing machine 110 increases the level of the bit voltage V BL until the current flowing through the variable resistor 220 arrives at the pre-determined value I M1 .

For example, the testing machine 110 sets the bit voltage V BL at the level VF 1 and measures the current flowing through the variable resistor 220 . Since the current flowing through the variable resistor 220 is less than the pre-determined value I M1 , the testing machine 110 increases the level of the bit voltage V BL . In this embodiment, the testing machine 110 increases the level of the bit voltage V BL from the level VF 1 to the level VF 2 and maintains the bit voltage V BL at the level VF 2 in the maintaining period 302 . Next, the testing machine 110 measures the current flowing through the variable resistor 220 again. Since the current flowing through the variable resistor 220 is still less than the pre-determined value I M1 , the testing machine 110 increases the level of the bit voltage V BL again until the current flowing through the variable resistor 220 is higher than the pre-determined value I M1 . As shown in FIG. 3 , when the bit voltage V BL is at the level VFn, the current flowing through the variable resistor 220 is higher than the pre-determined value I M1 . Therefore, the testing machine 110 stops providing the bit voltage V BL . In other embodiments, when the current flowing through the variable resistor 220 is higher than the pre-determined value I M1 , the testing machine 110 maintains the level of the bit voltage V BL at a fixed level, such as VFn.

The invention does not limit the relationship between the maintaining periods 301 ˜ 303 . In one embodiment, the durations of the maintaining periods 301 ˜ 303 are the same. In another embodiment, the durations of the maintaining periods 301 ˜ 303 are gradually increased. For example, the duration of the maintaining period 301 is less than the duration of the maintaining period 302 , and the duration of the maintaining period 302 is less than the duration of the maintaining period 303 . In other embodiments, the difference between the levels VF 1 and VF 2 is equal to or less than the difference between the levels VF 2 and VF 3 .

As shown in FIG. 3 , before time point t 1 , since the variable resistor 220 is not at the LRS yet, the current flowing through the variable resistor 220 is approximately 0. Therefore, the testing machine 110 gradually increases the bit voltage V BL . At time point t 1 , since the variable resistor 220 is at the LRS, the current flowing through the variable resistor 220 is quickly increased to the pre-determined value I M1 . In this embodiment, the current flowing through the variable resistor 220 does not linearly increase as the bit voltage V BL increases. The current flowing through the variable resistor 220 suddenly increases when the variable resistor 220 is at the LRS, such as time point t 1 .

FIG. 4 is a schematic diagram illustrating the relationship between the bit voltage V BL and the current flowing through the variable resistor 220 when the specific period is the set period. The curve 410 represents the current flowing through the variable resistor 220 . The curve 420 represents the level of the bit voltage V BL . In one embodiment, the maintaining periods (e.g. 401 - 403 in FIG. 4 ) when the bit voltage V BL is maintained is less than the maintaining periods (e.g. 301 - 303 in FIG. 3 ) when the bit voltage V BL is maintained. In another embodiment, the difference between the levels VS 1 and VS 2 shown in FIG. 4 may be less than the difference between the levels VF 1 and VF 2 shown in FIG. 3 . In other embodiments, the pre-determined value I M2 shown in FIG. 4 may be less than the pre-determined value I M1 shown in FIG. 3 . Additionally, the level VS 1 shown in FIG. 4 may be equal to the level VF 1 shown in FIG. 3 .

FIG. 5 is a schematic diagram illustrating the relationship between the source voltage V SL and the current flowing through the variable resistor 220 when the specific period is the reset period. The curve 510 represents the current flowing through the variable resistor 220 . The curve 520 represents the level of the source voltage V SL . The testing machine 110 maintains the level of the bit voltage V BL and gradually increases the source voltage V SL of the source line SL 1 in the reset period 500 such that the state of the variable resistor 220 is changed from the LRS to the HRS. At this time, the testing machine 110 provides a reset voltage to serve as the word voltage V WL .

In this embodiment, the testing machine 110 provides the source voltage V SL to the storage cell. The testing machine 110 maintains the level of the source voltage V SL and measures the current flowing through the variable resistor 220 . When the current flowing through the variable resistor 220 does not arrive at a pre-determined value I M3 , the testing machine 110 increases the level of the source voltage V SL until the current flowing through the variable resistor 220 arrives at the pre-determined value I M3 .

The invention does not limit when the testing machine 110 gradually increases the corresponding voltage. For example, the testing machine 110 gradually increases the bit voltage V BL or the source voltage V SL in at least one of the forming period, the reset period, and the set period. In one embodiment, the testing machine 110 gradually increases the bit voltage V BL only in the forming period. In this case, the testing machine 110 does not gradually increase the bit voltage V BL or the source voltage V SL in the reset period and the set period.

In another embodiment, the testing machine 110 gradually increases the bit voltage V BL in the forming period and the set period. In this case, the durations of the maintaining periods (e.g. 301 - 303 ) in the forming period may be longer than the durations of the maintaining periods (e.g. 401 - 403 ) in the set period. Additionally, the increased degree of the bit voltage V BL in the forming period may be greater than the increased degree of the bit voltage V BL in the set period.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.