Current-mode logic latch circuit

The present invention relates to a latch circuit, and more particularly to a current-mode logic latch circuit.

Generally, the applications of high-speed latches and flip-flops are widespread. In designing digital circuits, high-speed latches and flip-flops are widely used for sampling and storing/holding data. For example, a current-mode logic latch circuit (also referred hereinafter as a latch circuit) is widely-used because the differential architecture of the latch circuit can increase the operating speed and reject the common mode noise. Since the trends of designing circuits are toward miniaturization and high frequency application, it is important for the latch circuit to accurately sample and latch input signals.

The present invention provides a latch circuit for reducing the influence of the instantaneous switching between the clock signals.

An embodiment of the present invention provides a latch circuit. The latch circuit includes a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees apart. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, and providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit regenerates and holds the differential output signal.

Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.

The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

FIG. 1 is a schematic circuit diagram of a current-mode logic latch circuit;

FIG. 2A is a schematic circuit block diagram illustrating a current-mode logic latch circuit according to an embodiment of the present invention;

FIG. 2B is a schematic circuit diagram illustrating the current-mode logic latch circuit with the circuitry architecture of FIG. 2A ;

FIG. 3 is a schematic timing waveform diagram illustrating an ideal differential input signal, the differential input signal processed by the latch circuit of FIG. 1 and the differential input signal processed by the current-mode logic latch circuit of FIG. 2B ; and

FIG. 4 is a schematic timing waveform diagram illustrating an ideal differential output signal, the differential output signal generated by the latch circuit of FIG. 1 and the differential output signal generated by the current-mode logic latch circuit of FIG. 2B .

FIG. 1 is a schematic circuit diagram of a current-mode logic latch circuit. The current-mode logic latch circuit 10 includes plural transistors (switch elements) M 1 , M 2 , M 3 , M 4 , M 5 , M 6 and M 7 . A resistor Rd 1 is connected between a supply voltage Vdd and the drain terminal of the transistor M 1 . A resistor Rd 2 is connected between the supply voltage Vdd and the drain terminal of the transistor M 2 . In this embodiment, the resistance of the resistor Rd 1 and the resistance of the resistor Rd 2 are equal.

The transistors M 1 and M 2 have a differential configuration, and are cross-coupled to the transistors M 3 and M 4 . The drain terminal of the transistor M 1 is connected with the drain terminal of the transistor M 4 and the gate terminal of the transistor M 3 . The drain terminal of the transistor M 2 is connected with the drain terminal of the transistor M 3 and the gate terminal of the transistor M 4 .

In FIG. 1 , a sampling circuit is defined by the transistors M 1 and M 2 collaboratively, and a holding circuit is defined by the transistors M 3 and M 4 collaboratively. The transistor M 5 receives a first clock signal Vclk, and the transistor M 6 receives a second clock signal Vclk′. The phase difference between the first clock signal Vclk and the second clock signal Vclk′ is equal to 180 degrees. According to the first clock signal Vclk and the second clock signal Vclk′, the latch circuit 10 is selectively operated in a sampling mode or a holding mode. Moreover, the transistor M 7 is used as a current source for providing a stable discharge current Iss. Moreover, a first input node Sin 1 and a second input node Sin 2 receive a first input signal and a second complementary differential input signal, respectively. The first input signal and the second input signal are collaboratively formed as a differential input signal Vin.

In case that the first clock signal Vclk is in a high level state (that is Vclk=1), the transistor M 5 is turned on. Under this circumstance, the discharge current Iss from the transistor M 7 completely flows through the sampling circuit. Meanwhile, the latch circuit 10 is operated in the sampling mode. In the sampling mode, the transistors M 1 and M 2 of the sampling circuit sense and track the differential input signal Vin.

In case that the first clock signal Vclk is in a low level state (that is Vclk=0) and the second clock signal Vclk′ is in a high level state (that is, Vclk′=1), the transistor M 6 is turned on. Under this circumstance, the discharge current Iss from the transistor M 7 completely flows through the holding circuit. Meanwhile, the latch circuit 10 is operated in the holding mode. In the holding mode, the holding circuit (that is, the transistors M 3 and M 4 ) samples the outputs of the sampling circuit (that is, the transistors M 1 and M 2 ).

In this context, the differential input signal Vin is defined as a voltage difference between the voltage of the first input node Sin 1 and the voltage of the second input node Sin 2 . If the voltage of the first input node Sin 1 is higher than the voltage of the second input node Sin 2 , the differential input signal Vin is a positive voltage. If the voltage of the first input node Sin 1 is lower than the voltage of the second input node Sin 2 , the differential input signal Vin is a negative voltage. The voltage difference between a first output node Sout 1 of the latch circuit and a second output node Sout 2 of the latch circuit is defined as a differential output voltage Vout.

Hereinafter, the operations of the latch circuit 10 in the sampling mode and the holding mode will be illustrated by referring to the following two situations. In the first situation, the differential input signal Vin has the positive voltage (that is, the voltage of the first input node Sin 1 is higher than the voltage of the second input node Sin 2 ). In the second situation, the differential input signal Vin has the negative voltage (that is, the voltage of the first input node Sin 1 is lower than the voltage of the second input node Sin 2 ). Moreover, the symbol “ON” indicates that the transistor is turned on, the symbol “OFF” indicates that the transistor is turned off, the symbol “H” indicates that the logic level is 1 (that is, the high voltage level), and the symbol “L” indicates that the logic level is 0 (that is, the low voltage level).

Firstly, the first situation will be described. Table 1 shows the relationship between the voltages of the nodes and the on/off statuses of the transistors of the sampling circuit in the sampling mode when the differential input signal Vin has the positive voltage.

Since the voltage of the first input node Sin 1 is higher, the transistor M 1 is turned on. Under this circumstance, the discharge current Iss flows through the transistor M 1 . Consequently, the voltage of the drain terminal of the transistor M 1 (that is, the first output node Sout 1 ) drops from the higher voltage level (Vdd) to the lower voltage level (Vdd−Iss×Rd). On the other hand, since the voltage of the second input node Sin 2 is lower, the transistor M 2 is turned off. Under this circumstance, no current flows through the transistor M 2 . Consequently, the voltage of the second output node Sout 2 connected with the drain terminal of the transistor M 2 is maintained at the high voltage level (Vdd).

After the sampling circuit samples the differential input signal Vin and generates voltages at the first output node Sout 1 and the second output node Sout 2 , the sampling circuit maintains/tracks the data of the previous stage. Then, the second clock signal Vclk′ is switched to the high level state, so that the latch circuit 10 is in the holding mode. Table 2 shows the relationship between the voltages of the nodes and the on/off statuses of the transistors of the holding circuit in the holding mode when the differential input signal Vin has the positive voltage.

In the beginning of the holding mode, the voltage of the first output node Sout 1 has the lower voltage level (Vdd−Iss×Rd), and the voltage of the second output node Sout 2 has the higher voltage level (Vdd). Since the gate terminal of the transistor M 3 is connected with the first output node Sout 1 , the transistor M 3 is turned off. At the same time, the voltage of the second output node Sout 2 is maintained at the higher voltage level (Vdd). Moreover, since the gate terminal of the transistor M 4 is connected with the second output node Sout 2 , the transistor M 4 is turned on. Consequently, the voltage of the first output node Sout 1 is maintained at the lower voltage level (Vdd−Iss×Rd).

Secondly, the second situation will be described. Table 3 shows the relationship between the voltages of the nodes and the on/off statuses of the transistors of the sampling circuit in the sampling mode when the differential input signal Vin has the negative voltage.

Since the voltage of the first input node Sin 1 is lower, the transistor M 1 is turned off. Under this circumstance, no current flows through the transistor M 1 . Consequently, the voltage of the drain terminal of the transistor M 1 (that is, the first output node Sout 1 ) is maintained at the higher voltage level (Vdd). On the other hand, since the voltage of the second input node Sin 2 is higher, the transistor M 2 is turned on. Under this circumstance, the discharge current Iss flows through the transistor M 2 . Consequently, the voltage of the drain terminal of the transistor M 2 (that is, the second output node Sout 2 ) drops from the higher voltage level (Vdd) to the lower voltage level (Vdd−Iss×Rd).

After the sampling circuit samples the differential input signal Vin and generates voltages at the first output node Sout 1 and the second output node Sout 2 , the sampling circuit tracks the data of the previous stage (that is the tracking period). Then, the second clock signal Vclk′ is switched to the high level state, so that the latch circuit 10 is in the holding mode. Table 4 shows the relationship between the voltages of the nodes and the on/off statuses of the transistors of the holding circuit in the holding mode when the differential input signal Vin has the negative voltage.

In the beginning of the holding mode, the voltage of the first output node Sout 1 has higher voltage level (Vdd), and the voltage of the second output node Sout 2 has the lower voltage level (Vdd−Iss×Rd). Since the gate terminal of the transistor M 3 is connected with the first output node Sout 1 , the transistor M 3 is turned on. At the same time, the voltage of the second output node Sout 2 is maintained at the lower voltage level (Vdd−Iss×Rd). Moreover, since the gate terminal of the transistor M 4 is connected with the second output node Sout 2 , the transistor M 4 is turned off. Consequently, the voltage of the first output node Sout 1 is maintained at the higher voltage level (Vdd).

However, the operations of the latch circuit 10 are adversely affected by the gate-source capacitance c 1 between the node S 1 and the first input node Sin 1 and the gate-source capacitance C 2 between the node S 1 and the second input node Sin 2 . When the transistor M 1 is turned off, a bypass current possibly flows through the gate-source capacitance c 1 between the node S 1 and the first input node Sin 1 . Consequently, the voltage of the first input node Sin 1 is influenced. Similarly, even if the transistor M 2 is turned off, a bypass current possibly flows through the gate-source capacitance c 2 between the node S 1 and the second input node Sin 2 . Consequently, the voltage of the second input node Sin 2 is influenced. In other words, the differential input signal Vin is interfered.

As mentioned above, the instantaneous switching between the clock signals Vclk and Vclk′ has a coupling influence on the first input node Sin 1 and the second input node Sin 2 , and thus the differential input signal Vin sampled by the sampling circuit is interfered. For example, kick back noise is generated. Due to the kick back noise, the differential output signal Vout latched and generated by the latch circuit 10 is subjected to deviation. If the voltage of the differential input signal Vin is decreased and the switching frequency of the clock signals Vclk and Vclk′ is increased, the deviation of the differential output signal Vout is more serious.

FIG. 2A is a schematic circuit block diagram illustrating a current-mode logic latch circuit according to an embodiment of the present invention. As shown in FIG. 2A , the latch circuit 20 includes a sampling circuit 21 a , a holding circuit 21 b , a current generating circuit 23 , a clock receiving circuit 27 and a symmetric replica circuit 25 (symmetric circuit). The current generating circuit 23 further includes a source circuit 23 a and a mirroring circuit 23 b . The symmetric replica circuit 25 and the clock receiving circuit 27 are connected with a ground voltage Vss. The symmetric replica circuit 25 is continuously turned on. Consequently, the source circuit 23 a and a mirroring circuit 23 b are based on the same reference voltage (Vref).

The sampling circuit 21 a and the holding circuit 21 b are connected with each other, and connected with a supply voltage Vdd. The sampling circuit 21 a receives a differential input signal Vin. The holding circuit 21 b generates a differential output signal Vout.

The source circuit 23 a and the mirroring circuit 23 b of the current generating circuit 23 receive a bias voltage Vbias. A mirror current in the mirroring circuit 23 b is determined by referring to a source current in the source circuit 23 a . The design of the source circuit 23 a and the mirroring circuit 23 b do not have to be completely identical, and the person having ordinary skill in the art is able to modify the design of the source circuit 23 a and the mirroring circuit 23 b . Typically, the source current is smaller than the mirror current by a factor of N, which can be equal or 0.5, 0.1 . . . or 0.05. The source circuit 23 a is electrically connected with the symmetric replica circuit 25 . The mirroring circuit 23 b is electrically connected with the sampling circuit 21 a , the holding circuit 21 b and the clock receiving circuit 27 .

FIG. 2B is a schematic circuit diagram illustrating the current-mode logic latch circuit with the circuitry architecture of FIG. 2A . As shown in FIG. 2B , the latch circuit 30 includes a sampling circuit 31 a , a holding circuit 31 b , a current generating circuit 33 , a clock receiving circuit 37 and a symmetric replica circuit 35 . The sampling circuit 31 a is operated in a sampling mode, and the holding circuit 31 b is operated in a holding mode. In addition, some parasitic capacitors Ca, Cb may exist in the latch circuit.

The sampling circuit 31 a includes transistors M 1 and M 2 for receiving the differential input signal Vin. The holding circuit 31 b includes transistors M 3 and M 4 . The operations of the sampling circuit 31 a and the holding circuit 31 b are similar to those of the latch circuit 10 of FIG. 1 , and are not redundantly described herein.

The current generating circuit 33 includes a source circuit 33 a and a mirroring circuit 33 b . The source circuit 33 a is used for generating the source current having a current value of 1/N×Iss. The mirroring circuit 33 b generates the mirror current having a current value of Iss. In the latch circuit 30 , the current generating circuit 33 is not directly connected with the ground voltage Vss. Instead, the mirroring circuit 33 b of the current generating circuit 33 is connected between the sampling circuit 31 a , the holding circuit 31 b and the clock receiving circuit 37 .

The source circuit 33 a includes a transistor M 9 . The drain terminal and the gate terminal of the transistor M 9 are connected with each other, and receive a bias voltage Vbias. The mirroring circuit 33 b includes transistors M 7 and M 8 . The transistor M 7 is electrically connected with the sampling circuit 31 a . Moreover, according to the bias voltage Vbias, the transistor M 7 is turned on, and a first mirror current is generated. The transistor M 8 is electrically connected with the holding circuit 31 b . According to the bias voltage Vbias, the transistor M 8 is turned on, and a second mirror current is generated. The current value (Iss) of the first mirror current and the second mirror current are substantially equal to multiple of the current value (1/N×Iss) of the source current.

The clock receiving circuit 37 includes transistors M 5 and M 6 . In case that the first clock signal Vclk is in the high level state, the transistor M 5 is turned on, and the transistor M 6 is turned off. Meanwhile, the first mirror current is used as the discharge current Iss. The discharge current Iss flows from the supply voltage Vdd to the ground voltage source Vss through the sampling circuit 31 a , the transistor M 7 and the transistor M 5 . Under this circumstance, the latch circuit 30 is in the sampling mode.

In case that the second clock signal Vclk′ is in the high level state, the transistor M 5 is turned off, and the transistor M 6 is turned on. Meanwhile, the second mirror current is used as the discharge current Iss. The discharge current Iss flows from the supply voltage Vdd to the ground voltage Vss through the holding circuit 31 b , the transistor M 8 and the transistor M 6 . Under this circumstance, the latch circuit 30 is in the holding mode.

The symmetric replica circuit 35 is connected between the source circuit 33 a and the ground voltage Vss. By means of the transistor of the symmetric replica circuit 35 , operation of the transistors M 9 , M 7 and M 8 are based on the same reference voltage (Vref). That is, voltage of the nodes S 3 , S 4 , and S 5 can be maintained at the reference voltage (Vref). Consequently, the symmetric current mirror configuration is formed. As shown in FIG. 2B , the symmetric replica circuit 35 includes a transistor M 10 . The drain terminal of the transistor M 10 is electrically connected with the source terminal of the transistor M 9 . The gate terminal of the transistor M 10 is electrically connected with the supply voltage Vdd. The source terminal of the transistor M 10 is electrically connected with the ground voltage Vss. Consequently, the transistor M 10 is continuously turned on, and the voltage of node S 5 is equal to the reference voltage (Vref).

Because the transistor M 10 is always turned on, operation of the source circuit 33 a is consistently based on the voltage difference between the drain terminal and the source terminal of the transistor M 10 . Because the transistors M 5 and M 6 are alternately turned on, operation of the mirroring circuit 33 b is either based on the voltage difference between the drain terminal and the source terminal of the transistor M 5 or that of the transistor M 6 . Thus, the voltage of nodes S 3 and S 4 are alternately equal to the reference voltage (Vref).

When the latch circuit 30 is in the sampling mode, the transistor M 5 is turned on and the transistor M 6 is turned off. Consequentially, the voltage of node S 3 is equal to the reference voltage (Vref). Under this circumstance, the operation of the mirroring circuit 33 b is based on the voltage difference of the drain terminal and the source terminal of the transistor M 5 when the latch circuit 30 is in the sampling mode.

On the other hand, when the latch circuit 30 is in the holding mode, the transistor M 5 is turned off and the transistor M 6 is turned on. Consequentially, the voltage of node S 4 is equal to the reference voltage (Vref). Under this circumstance, the operation of the mirroring circuit 33 b is based on the voltage difference between the drain terminal and the source terminal of the transistor M 6 when the latch circuit 30 is in the holding mode.

Therefore, in the latch circuit 30 , operation of the source circuit 33 a and the mirroring circuit 33 b are both based on the same reference voltage (Vref), that is, a voltage difference between a drain terminal and a source terminal of a conducted transistor.

In this embodiment, the clock receiving circuit 37 is not directly connected with the sampling circuit 31 a and the holding circuit 31 b . Instead, the clock receiving circuit 37 is indirectly connected with the sampling circuit 31 a and the holding circuit 31 b through the mirroring circuit 33 b . In other words, the mirroring circuit 33 b is used for providing the shielding and isolating efficacy. Consequently, the influence of the instantaneous switching between the clock signals Vclk and Vclk′ on the differential input signal Vin will be minimized. By means of the transistor M 7 , the coupling influence of the first clock signal Vclk on the transistors M 1 and M 2 of the sampling circuit 31 a is minimized. By means of the transistor M 8 , the coupling influence of the second clock signal Vclk′ on the transistors M 3 and M 4 of the holding circuit 31 b is minimized.

FIG. 3 is a schematic timing waveform diagram illustrating an ideal differential input signal, the differential input signal processed by the latch circuit of FIG. 1 and the differential input signal processed by the current-mode logic latches circuits of FIG. 2B . In the drawings, the dotted regions indicate that the clock signal Vclk/Vclk′ is switched from the high level state to the low level state or switched from the low level state to the high level state. It is found that the instantaneous switching results in the kick back noise of the differential input signal Vin.

At the time points T 1 , T 2 , T 3 and T 4 , the differential input signal Vin is in the low level state. At the time point T 1 , the voltage of the ideal differential input signal Vin_ideal is 675 mV (segment C 1 ). The instantaneous switching of the clock signal Vclk/Vclk′ may result in the kick back noise. For example, at the time point T 1 , the voltage of the differential input signal processed by the latch circuit 10 of FIG. 1 fluctuates between 695 mV and 640 mV (segment C 11 ). That is, the fluctuation voltage range of the differential input signal Vin for the latch circuit 10 is about 45 mV. Moreover, at the time point T 1 , the voltage of the differential input signal processed by the latch circuit 30 of FIG. 2B fluctuates between 684 mV and 668 mV (segment C 21 ). That is, the fluctuation voltage range of the differential input signal Vin for the latch circuit 30 is about 16 mV.

At the time points T 2 , T 3 and T 4 , the voltage of the ideal differential input signal Vin_ideal remains at 675 mV (segments C 2 , C 3 and C 4 ). Meanwhile, the fluctuation voltage range of the differential input signal Vin for the latch circuit 10 is about 50 mV (segments C 12 , C 13 and C 14 ). At the time points T 2 , T 3 and T 4 , the fluctuation voltage range of the differential input signal Vin for the latch circuit 30 is about 15 mV (segments C 22 , C 23 and C 24 ). When compared with the influence of the instantaneous switching of the clock signal Vclk/Vclk′ on the differential input signal Vin of the latch circuit 10 , the influence of the instantaneous switching of the clock signal Vclk/Vclk′ on the differential input signal Vin of the latch circuit 30 is largely reduced. In other words, the circuitry of FIG. 2B is capable of reducing the influence of the instantaneous switching of the clock signal Vclk/Vclk′ on the low voltage level of the differential input signal Vin by using the current generating circuit to reduce the influence of the clock receiving circuit.

At the time points T 5 , T 6 and T 7 , the differential input signal Vin is in the high level state. At the time point T 5 , the voltage of the ideal differential input signal Vin_ideal is 720 mV (segment C 5 ).

The instantaneous switching of the clock signal Vclk/Vclk′ result in the kick back noise. For example, at the time point T 5 , the voltage of the differential input signal Vin for the latch circuit 10 fluctuates between 690 mV and 730 mV (segment C 15 ). That is, at the time point T 5 , the fluctuation voltage range of the differential input signal Vin for the latch circuit 10 is about 40 mV. Moreover, at the time point T 5 , the voltage of the differential input signal for the latch circuit 30 fluctuates between 710 mV and 722 mV (segment C 25 ). That is, the fluctuation voltage range of the differential input signal Vin for the latch circuit 30 is about 12 mV. In other words, the latch circuit 30 can reduce the influence of the instantaneous switching of the clock signal Vclk/Vclk′ on the differential input signal Vin.

At the time points T 6 and T 7 , the voltage of the ideal differential input signal Vin_ideal remains at 720 mV (segments C 6 and C 7 ). Meanwhile, the fluctuation voltage range of the differential input signal Vin for the latch circuit 10 is about 30 mV (segments C 16 and C 17 ). At the time points T 6 and T 7 , the fluctuation voltage range of the differential input signal Vin for the latch circuit 30 is about 15 mV (segments C 26 and C 27 ).

When compared with the influence of the instantaneous switching of the clock signal Vclk/Vclk′ on the differential input signal Vin of the latch circuit 10 , the influence of the instantaneous switching of the clock signal Vclk/Vclk′ on the differential input signal Vin of the latch circuit 30 is largely reduced. In other words, the circuitry of FIG. 2B is capable of reducing the influence of the instantaneous switching of the clock signal Vclk/Vclk′ on the high voltage level of the differential input signal Vin by using the current generating circuit to reduce the influence of the clock receiving circuit.

FIG. 4 is a schematic timing waveform diagram illustrating an ideal differential output signal, the differential output signal generated by the latch circuit of FIG. 1 and the differential output signal generated by the latch circuit of FIG. 2B . The waveform shown in FIG. 4 is obtained by a sampling flip-flop which is built as a pair of back-to-back latches with opposite sampling clock phase connections.

In the time interval d 1 , the voltage of the ideal differential output signal Vout_ideal is higher than 0V. That is, the logic level of the ideal differential output signal Vout_ideal is 1. In the time interval d 1 , the voltage of the differential output signal Vout for the latch circuit 10 is lower than 0V. That is, the logic level of the differential output signal Vout is “0”. In the time interval d 1 , the voltage of the differential output signal Vout for the latch circuit 30 is higher than 0V. That is, the logic level of the differential output signal Vout is “1”. That is, in the time interval d 1 , the latch circuit 10 erroneously generates the logic level of the differential output signal Vout, but the latch circuit 30 accurately generates the logic level of the differential output signal Vout. Similarly, in the time intervals d 2 , d 3 and d 4 , the latch circuit 10 also erroneously generates the logic level of the differential output signal Vout, but the latch circuit 30 accurately generates the logic level of the differential output signal Vout.

In the time interval d 5 , the voltage of the ideal differential output signal Vout_ideal is lower than 0V. That is, the logic level of the ideal differential output signal Vout_ideal is “0”. In the time interval d 5 , the voltage of the differential output signal Vout for the latch circuit 10 is higher than 0V. That is, the logic level of the differential output signal Vout is “1”. In the time interval d 5 , the voltage of the differential output signal Vout for the latch circuit 30 is lower than 0V. That is, the logic level of the differential output signal Vout is “0”. That is, in the time interval d 5 , the latch circuit 10 erroneously generates the logic level of the differential output signal Vout, but the latch circuit 30 accurately generates the logic level of the differential output signal Vout. Similarly, in the time interval d 6 , the latch circuit 10 also erroneously generates the logic level of the differential output signal Vout, but the latch circuit 30 accurately generates the logic level of the differential output signal Vout. According to the result of FIG. 4 , it is found that the differential output signal Vout generated by the latch circuit 30 has enhanced accuracy.

Moreover, if the switching rate of the differential output signal Vout is increased, the possibility of causing erroneous judgment by the latch circuit 10 increases. As mentioned above, the differential output signal Vout is outputted from the latch circuit. Consequently, the latch circuit 30 is suitably used for latching the differential input signal Vin with smaller amplitude and higher frequency (e.g., 14 Gigabit/sec).

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.