Charge pump circuit capable of reducing reverse currents

This non-provisional application claims priority of U.S. provisional application U.S. 62/100,485, filed on Jan. 7, 2015, included herein by reference in its entirety.

1. Field of the Invention

This invention relates to a charge pump circuit, and more particularly, a charge pump circuit that is capable of reducing reverse currents.

2. Description of the Prior Art

Due to requirements of low power for electronic devices, the power specification of integrated circuits (IC) is re-designed to work in a low voltage environment for reducing power consumption. For example, the IC power specification that used to be 5V before is now reduced to 3.3V or even lower than 2V. Although lower voltages are supplied to reduce power consumption, greater voltages are still needed in some situations. For example, flash memory may require a greater voltage for programming or erasing. The greater voltage is usually supplied by a charge pump circuit.

The charge pump circuits of the prior art are usually controlled by complementary clock signals. However, since the clock signals are not perfect square waves, switches of the charge pump circuits may be turned on or turned off unpredictably during transitions of voltage levels of the clock signals. In this case, unwanted reverse currents may be produced, which further increase power consumption. Therefore, how to reduce the reverse current of the charge pump circuit has become an issue to be resolved.

One embodiment of the present invention discloses a charge pump unit. The charge pump unit includes a first capacitor, a second capacitor, a first N-type metal oxide semiconductor (NMOS) transistor, a second NMOS, a first P-type metal oxide semiconductor (PMOS) transistor, and a second PMOS transistor. The first capacitor has a first terminal and a second terminal. The first terminal of the first capacitor is for receiving a first clock signal. The second capacitor has a first terminal and a second terminal. The first terminal of the second capacitor is for receiving a second clock signal.

The first NMOS transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first NMOS transistor is for receiving a first input voltage, the second terminal of the first NMOS transistor is coupled to the second terminal of the first capacitor, and the control terminal of the first NMOS transistor is coupled to the second terminal of the second capacitor. The first PMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal of first PMOS transistor is coupled to the second terminal of the first NMOS transistor, the second terminal of the first PMOS transistor is for outputting a first output voltage, and the control terminal of the first PMOS transistor is coupled to the control terminal of the first NMOS transistor. The second NMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal second NMOS transistor is for receiving a second input voltage, the second terminal of the second NMOS transistor is coupled to the second terminal of the second capacitor, and the control terminal of the second NMOS transistor is coupled to the second terminal of the first capacitor. The second PMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second PMOS transistor is coupled to the second terminal of the second NMOS transistor, the second terminal of the second PMOS transistor is for outputting a second output voltage, and the control terminal of the second PMOS transistor is coupled to the control terminal of the second NMOS transistor.

In addition, the first clock signal and the second clock signal transit at different time points. A rising edge of the first clock signal leads a respective falling edge of the second clock signal.

Another embodiment of the present invention discloses a charge pump circuit. The charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit includes a first capacitor, a second capacitor, a first N-type metal oxide semiconductor (NMOS) transistor, a second NMOS, a first P-type metal oxide semiconductor (PMOS) transistor, and a second PMOS transistor.

The first capacitor has a first terminal and a second terminal. The first terminal of the first capacitor is for receiving a first clock signal. The second capacitor has a first terminal and a second terminal. The first terminal of the second capacitor is for receiving a second clock signal.

The first NMOS transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first NMOS transistor is for receiving a first input voltage, the second terminal of the first NMOS transistor is coupled to the second terminal of the first capacitor, and the control terminal of the first NMOS transistor is coupled to the second terminal of the second capacitor. The first PMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal of first PMOS transistor is coupled to the second terminal of the first NMOS transistor, the second terminal of the first PMOS transistor is for outputting a first output voltage, and the control terminal of the first PMOS transistor is coupled to the control terminal of the first NMOS transistor. The second NMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal second NMOS transistor is for receiving a second input voltage, the second terminal of the second NMOS transistor is coupled to the second terminal of the second capacitor, and the control terminal of the second NMOS transistor is coupled to the second terminal of the first capacitor. The second PMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second PMOS transistor is coupled to the second terminal of the second NMOS transistor, the second terminal of the second PMOS transistor is for outputting a second output voltage, and the control terminal of the second PMOS transistor is coupled to the control terminal of the second NMOS transistor.

The second charge pump unit includes a third capacitor, a fourth capacitor, a third NMOS transistor, a fourth NMOS, a third PMOS transistor, and a fourth PMOS transistor.

The third capacitor has a first terminal and a second terminal. The first terminal of the third capacitor is for receiving a third clock signal. The fourth capacitor has a first terminal and a second terminal. The first terminal of the fourth capacitor is for receiving a fourth clock signal.

The third NMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the third NMOS transistor is coupled to the second terminal of the first PMOS transistor, the second terminal of the third NMOS transistor is coupled to the second terminal of the third capacitor, and the control terminal of the third NMOS transistor is coupled to the second terminal of the fourth capacitor. The third PMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the third PMOS is coupled to the second terminal of the third NMOS transistor, and the control terminal of the third PMOS is coupled to the control terminal of the third NMOS transistor. The fourth NMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the fourth NMOS transistor is coupled to the second terminal of the second PMOS transistor, the second terminal of the fourth NMOS transistor is coupled to the second terminal of the fourth capacitor, and the control terminal of the fourth NMOS transistor is coupled to the second terminal of the third capacitor. The fourth PMOS transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the fourth PMOS transistor is coupled to the second terminal of the fourth NMOS transistor, and the control terminal of the fourth PMOS transistor is coupled to the control terminal of the fourth NMOS transistor.

In addition, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal transit at different time points. A falling edge of the second clock signal lags a respective rising edge of the first clock signal and leads a respective rising edge of the fourth clock signal. The rising edge of the fourth clock signal leads a respective falling edge of the third clock signal.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 shows a charge pump unit according to one embodiment of the present invention.

FIG. 2 shows the operational timing of the charge pump unit in FIG. 1 according to one embodiment of the present invention.

FIG. 3 shows clock generator of the charge pump unit in FIG. 1 according to one embodiment of the present invention.

FIG. 4 shows a charge pump circuit according to one embodiment of the present invention.

FIG. 5 shows the operational timing of the charge pump circuit in FIG. 4 according to one embodiment of the present invention.

FIG. 6 shows clock generators of the charge pump circuit in FIG. 4 according to one embodiment of the present invention.

FIG. 7 shows a charge pump circuit according to another embodiment of the present invention.

FIG. 8 shows the operational timing of the charge pump circuit in FIG. 7 according to one embodiment of the present invention.

FIG. 9 shows clock generators of the charge pump circuit in FIG. 7 according to one embodiment of the present invention.

FIG. 1 shows a charge pump unit 10 according to one embodiment of the present invention. The charge pump unit 10 includes a first capacitor C 1 , a second capacitor C 2 , a first N-type metal oxide semiconductor (NMOS) transistor N 1 , a first P-type metal oxide semiconductor (PMOS) transistor P 1 , a second NMOS transistor N 2 , and a second PMOS transistor P 2 .

The first capacitor C 1 has a first terminal and a second terminal NA 1 . The first terminal of the first capacitor C 1 is for receiving a first clock signal CLKA 1 . The second capacitor C 2 has a first terminal and a second terminal NB 1 . The first terminal of the second capacitor C 2 is for receiving a second clock signal CLKB 1 . In some embodiments of the present invention, the first capacitor C 1 can be composed of a metal oxide semiconductor transistor. For example, the first terminal of the first capacitor C 1 can be the source, the drain and the body of the metal oxide semiconductor transistor while the second terminal NA 1 of the first capacitor C 1 can be the gate of the metal oxide semiconductor transistor. Similarly, the second capacitor C 2 can also be composed of a metal oxide semiconductor transistor.

The first NMOS transistor N 1 has a first terminal, a second terminal and a control terminal. The first terminal of the first NMOS transistor N 1 is for receiving a first input voltage VI 1 , the second terminal of the first NMOS transistor N 1 is coupled to the second terminal NA 1 of the first capacitor C 1 , and the control terminal of the first NMOS transistor N 1 is coupled to the second terminal NB 1 of the second capacitor C 2 . The first PMOS transistor P 1 has a first terminal, a second terminal and a control terminal. The first terminal of the first PMOS transistor P 1 is coupled to the second terminal of the first NMOS transistor N 1 , the second terminal of the first PMOS transistor P 1 is for outputting a first output voltage VO 1 , and the control terminal of the first PMOS transistor P 1 is coupled to the control terminal of the first NMOS transistor N 1 .

The second NMOS transistor N 2 has a first terminal, a second terminal and a control terminal. The first terminal of the second NMOS transistor N 2 is for receiving a second input voltage VI 2 , the second terminal of the second NMOS transistor N 2 is coupled to the second terminal NB 1 of the second capacitor C 2 , and the control terminal of the second NMOS transistor N 2 is coupled to the second terminal NA 1 of the first capacitor C 1 . The second PMOS transistor P 2 has a first terminal, a second terminal and a control terminal. The first terminal of the second PMOS transistor P 2 is coupled to the second terminal of the second NMOS transistor N 2 , the second terminal of the second PMOS transistor P 2 is for outputting a second output voltage VO 2 , and the control terminal of the second PMOS transistor P 2 is coupled to the control terminal of the second NMOS transistor N 2 . The first input voltage VI 1 and the second input voltage VI 2 can be substantially equal to a high voltage VDD.

In order to prevent the charge pump unit 10 from generating reverse currents, the first clock signal CLKA 1 and the second clock signal CLKB 1 are designed to turn on the NMOS transistors and PMOS transistors in a predetermined order. FIG. 2 shows the operational timing diagram of the charge pump unit 10 according to one embodiment of the present invention.

In FIG. 2 , the first clock signal CLKA 1 and the second clock signal CLKB 1 transit at different time points.

Furthermore, a rising edge REA 1 of the first clock signal CLKA 1 leads a respective falling edge FEB 1 of the second clock signal CLKB 1 . During a first time period T 1 before the rising edge REA 1 of the first clock signal CLKA 1 , the first clock signal CLKA 1 is at the low voltage GND and the second clock signal CLKB 1 is at the high voltage VDD. In this case, the voltage level of the second terminal NB 1 of the second capacitor C 2 remains around VI 2 +VDD due to the previous operations. Therefore, the first NMOS transistor N 1 is turned on, and the first PMOS transistor P 1 is turned off. Thus, the voltage level of the second terminal NA 1 of the first capacitor C 1 is kept the same as the first input voltage VI 1 . The second NMOS transistor N 2 is turned off, and the second PMOS transistor P 2 is turned on. In the first time period T 1 , the second output voltage VO 2 outputted from the second PMOS transistor P 2 is around VI 2 +VDD.

During a second time period T 2 between the rising edge REA 1 of the first clock signal CLKA 1 and the falling edge FEB 1 of the second clock signal CLKB 1 , the first clock signal CLKA 1 is at the high voltage VDD and the second clock signal CLKB 1 is at the high voltage VDD. The voltage level of the second terminal NA 1 of the capacitor C 1 is coupled to VI 1 +VDD instantly. Since the voltage level of the second terminal NB 1 of the second capacitor C 2 remains around VI 2 +VDD, the first NMOS transistor N 1 and the second NMOS transistor N 2 are both turned on. The first PMOS transistor P 1 and the second PMOS transistor P 2 are both turned off. Thus, reverse currents generated at the outputs of the charge pump unit 10 due to the second clock CLKB 1 changing to low voltage GND before the first clock CLKA 1 changing to high voltage VDD in prior art can be avoided. In addition, although the first capacitor C 1 may be discharged through the first NMOS transistor N 1 unwantedly, the voltage drops are rather small and will not cause any significant effect because the second time period T 2 is rather short and the voltage of the second terminal of the first capacitor C 1 is not affecting the output voltage directly due to the turning off of the first PMOS transistor P 1 .

During a third time period T 3 after the falling edge FEB 1 of the second clock signal CLKB 1 , the first clock signal CLKA 1 is at the high voltage VDD and the second clock signal CLKB 1 is at the low voltage GND. The voltage level of the second terminal NB 1 of the second capacitor C 2 is coupled to VI 2 while the voltage level of the second terminal NA 1 of the first capacitor C 1 remains at VI 1 +VDD. Therefore, the first NMOS transistor N 1 is turned off and the first PMOS transistor P 1 is turned on. Consequently, first output voltage VO 1 outputted from the second terminal of the first PMOS P 1 is about VI 1 +VDD. Also, the second NMOS transistor N 2 is turned on and the second PMOS transistor P 2 is turned off so that the voltage level of the second terminal NB 1 of the second capacitor C 2 is kept at VI 2 by the second NMOS transistor N 2 .

Similarly, the second PMOS transistor P 2 can be used to output the second output voltage VO 2 , which is greater than the second input voltage VI 2 . In this case, to prevent reverse currents, a rising edge REB 1 of the second clock signal CLKB 1 leads a respective falling edge FEA 1 of the first clock signal CLKA 1 .

During a fourth time period T 4 between the rising edge REB 1 of the second clock signal CLKB 1 and the falling edge FEA 1 of the first clock signal CLKA 1 , the first clock signal CLKA 1 is at the high voltage VDD and the second clock signal CLKB 1 is at the high voltage VDD. In this case, the voltage level of the second terminal NB 1 of the capacitor C 2 is coupled to VI 2 +VDD instantly. Since the voltage level of the second terminal NA 1 of the first capacitor C 1 remains around VI 1 +VDD due to the operations in the time period T 3 , the second NMOS transistor N 2 and the first NMOS transistor N 1 are turned on. Also, the first PMOS transistor P 1 and the second PMOS transistor P 2 are turned off. Thus, reverse currents generated at the outputs of the charge pump unit 10 due to the first clock CLKA 1 changing to low voltage GND before the second clock CLKB 1 changing to high voltage VDD in prior art can be avoided.

During a fifth time period T 5 after the falling edge FEA 1 of the first clock signal CLKA 1 , the first clock signal CLKA 1 is at the low voltage GND and the second clock signal CLKB 1 is at the high voltage VDD. Therefore, the voltage level of the second terminal NA 1 of the first capacitor C 1 is coupled to VI 1 while the voltage level of the second terminal NB 1 of the second capacitor C 2 remains at VI 2 +VDD. Therefore, the second NMOS transistor N 2 is turned off and the second PMOS transistor P 2 is turned on. Consequently, the second terminal of the second PMOS P 2 can output the second output voltage VO 2 , which is about VI 2 +VDD. Also, the first NMOS transistor N 1 is turned on and the first PMOS transistor P 1 is turned off so that the voltage level of the second terminal NA 1 of the first capacitor C 1 is kept at VI 1 .

Therefore, the charge pump unit 10 can generate voltages greater than its input voltages while no reverse current is generated.

FIG. 3 shows a clock generator 12 according to one embodiment of the present invention. The clock generator 12 can generate the first clock signal CLKA 1 and the second clock signal CLKB 1 according to a reference clock CLK 0 . The clock generator 12 includes a first inverter INV 1 , a first NAND gate G 1 , a first delay circuit D 1 , a second NAND gate G 2 , and a second delay circuit D 2 .

The first inverter INV 1 has an input terminal and an output terminal. The input terminal of the first inverter INV 1 is for receiving a reference clock signal CLK 0 . The first NAND gate G 1 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first NAND gate G 1 is for receiving the reference clock signal CLK 0 . The first delay circuit D 1 has an input terminal and an output terminal. The input terminal of the first delay circuit D 1 is coupled to the output terminal of the first NAND gate G 1 , and an output terminal of the first delay circuit D 1 is for outputting the first clock signal CLKA 1 . The second NAND gate G 2 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second NAND gate G 2 is coupled to the output terminal of the first inverter INV 1 , the second input terminal of the second NAND gate G 2 is coupled to the output terminal of the first delay circuit D 1 . The second delay circuit D 2 has an input terminal and an output terminal. The input terminal of the second delay circuit D 2 is coupled to the output terminal of the second NAND gate G 2 , and the output terminal of the second delay circuit D 2 is coupled to the second input terminal of the first NAND gate G 1 and is for outputting the second clock signal CLKB 1 .

In some embodiments of the present invention, the first delay circuit D 1 and the second delay circuit D 2 can output signals by delaying their input signals. In the embodiment of FIG. 3 , the function of delaying input signals can be done by using inverters. In FIG. 3 , the first delay circuit D 1 includes a second inverter INV 2 and a third inverter INV 3 . The second inverter has an input terminal and an output terminal. The input terminal of the second inverter INV 2 is coupled to the input terminal of the first delay circuit D 1 . The third inverter INV 3 has an input terminal and an output terminal. The input terminal of the third inverter INV 3 is coupled to the output terminal of the second inverter INV 2 , and the output terminal of the third inverter INV 3 is coupled to the output terminal of the first delay circuit D 1 .

Similarly, the second delay circuit D 2 includes a fourth inverter INV 4 and a fifth inverter INV 5 . The fourth inverter INV 4 has an input terminal and an output terminal. The input terminal of the fourth inverter INV 4 is coupled to input terminal of the second delay circuit D 2 . The fifth inverter INV 5 has an input terminal and an output terminal. The input terminal of the fifth inverter INV 5 is coupled to the output terminal of the fourth inverter INV 4 , and the output terminal of the fifth inverter INV 5 is coupled to the output terminal of the second delay circuit D 2 .

In some embodiments of the present invention, a plurality of charge pump units can be combined together for generating even higher output voltages. FIG. 4 shows a charge pump circuit 200 according to one embodiment of the present invention. The charge pump circuit 200 includes the first charge pump unit 10 and a second charge pump unit 20 .

The second charge pump unit 20 has a similar structure as the first charge pump unit 10 . The second charge pump unit 20 includes a third capacitor C 3 , a fourth capacitor C 4 , a third NMOS transistor N 3 , a third PMOS transistor P 3 , a fourth NMOS transistor N 4 , and a fourth PMOS transistor P 4 .

The third capacitor C 3 has a first terminal and a second terminal NA 2 . The first terminal of the third capacitor C 3 is for receiving a third clock signal CLKA 2 . The fourth capacitor C 4 has a first terminal and a second terminal NB 2 . The first terminal of the fourth capacitor C 4 is for receiving a fourth clock signal CLKB 2 .

The third NMOS transistor N 3 has a first terminal, a second terminal and a control terminal. The first terminal of the third NMOS transistor N 3 is coupled to the second terminal of the first PMOS transistor P 1 , the second terminal of the third NMOS transistor N 3 is coupled to the second terminal NA 2 of the third capacitor C 3 , and the control terminal of the third NMOS transistor N 3 is coupled to the second terminal NB 2 of the fourth capacitor C 4 . The third PMOS transistor P 3 has a first terminal, a second terminal and a control terminal. The first terminal of the third PMOS transistor P 3 is coupled to the second terminal of the third NMOS transistor N 3 , and the control terminal of the third PMOS transistor P 3 is coupled to the control terminal of the third NMOS transistor N 3 .

The fourth NMOS transistor N 4 has a first terminal, a second terminal and a control terminal. The first terminal of the fourth NMOS transistor N 4 is coupled to the second terminal of the second PMOS transistor P 2 , the second terminal of the fourth NMOS transistor N 4 is coupled to the second terminal NB 2 of the fourth capacitor C 4 , and the control terminal of the fourth NMOS transistor N 4 is coupled to the second terminal NA 2 of the third capacitor C 3 . The fourth PMOS transistor P 4 has a first terminal, a second terminal and a control terminal. The first terminal of the fourth PMOS transistor P 4 is coupled to the second terminal of the fourth NMOS transistor N 4 , and the control terminal of the fourth PMOS transistor P 4 is coupled to the control terminal of the fourth NMOS transistor N 4 .

FIG. 5 shows the operational timing diagram of charge pump circuit 200 according to one embodiment of the present invention.

In FIG. 5 , the first clock signal CLKA 1 , the second clock signal CLKB 1 , the third clock signal CLKA 2 , and the fourth clock signal CLKB 2 transit at different time points.

Generally, in the first time period T 1 in FIG. 5 , the second terminal NA 1 of the first capacitor C 1 can be charged to the first input voltage VI 1 through the first NMOS transistor N 1 , the second terminal NA 2 of the third capacitor C 3 can output the high voltage of VI 1 +2VDD through the third PMOS transistor P 3 , and the second terminal NB 2 of the fourth capacitor C 4 can be charged to VI 2 +VDD from the second terminal NB 1 of the second capacitor C 2 through the second PMOS transistor P 2 and the fourth NMOS transistor N 4 . Also, in the fifth time period T 5 in FIG. 5 , the second terminal NB 1 of the second capacitor C 2 can be charged to the second input voltage VI 2 through the second NMOS transistor N 2 , the second terminal NB 2 of the fourth capacitor C 4 can output the high voltage of VI 2 +2VDD through the fourth PMOS transistor P 4 , and the second terminal NA 2 of the third capacitor C 3 can be charged to VI 1 +VDD from the second terminal NA 1 of the first capacitor C 1 through the first PMOS transistor P 1 and the third NMOS transistor N 3 .

However, to prevent the charge pump circuit 200 from generating reverse current, transitions of different clock signals CLKA 1 , CLKA 2 , CLKB 1 , and CLKB 2 are separated. That is, a falling edge FEB 1 of the second clock signal CLKB 1 lags a respective rising edge REA 1 of the first clock signal CLKA 1 and leads a respective rising edge REB 2 of the fourth clock signal CLKB 2 . Also, the rising edge REB 2 of the fourth clock signal CLKB 2 leads a respective falling edge FEA 2 of the third clock signal CLKA 2 . Consequently, there are three more time periods T 2 , T 3 and T 4 between the first time period T 1 and the fifth time period T 5 .

In FIG. 5 , during the first time period T 1 before the rising edge REA 1 of the first clock signal CLKA 1 , the first clock signal CLKA 1 is at a low voltage GND, the second clock signal CLKB 1 is at the high voltage VDD, the third clock signal CLKA 2 is at the high voltage VDD, and the fourth clock signal CLKB 2 is at the low voltage GND. In this case, the voltage level of the second terminal NB 1 of the second capacitor C 2 remains around VI 2 +VDD and the voltage level of the second terminal NA 2 of the third capacitor C 3 remains around VI 1 +2VDD due to the previous operations. Therefore, the first NMOS transistor N 1 is turned on, and the first PMOS transistor P 1 is turned off. Thus, the voltage level of the second terminal NA 1 of the first capacitor C 1 is kept same as the first input voltage VI 1 , which turns off the second NMOS transistor N 2 and turns on the second PMOS transistor P 2 . Also, the third NMOS transistor N 3 and fourth PMOS transistor P 4 are turned off. The fourth NMOS transistor N 4 and the third PMOS transistor P 3 are turned on. Consequently, the voltage of the second terminal NB 2 of the fourth capacitor C 4 is at the same voltage as the voltage of the second terminal NB 1 of the second capacitor C 2 , that is, VI 2 +VDD. Furthermore, the third PMOS transistor P 3 can output the voltage of the second terminal NA 2 of the third capacitor, which is at VI 1 +2VDD.

During the second time period T 2 between the rising edge REA 1 of the first clock signal CLKA 1 and the falling edge FEB 1 of the second clock signal CLKB 1 , the first clock signal CLKA 1 is at the high voltage VDD, the second clock signal CLKB 1 is at the high voltage VDD, the third clock signal CLKA 2 is at the high voltage VDD, and the fourth clock signal CLKB 2 is at the low voltage GND. The third NMOS transistor N 3 and fourth PMOS transistor P 4 remain turned off. The fourth NMOS transistor N 4 and the third PMOS transistor P 3 remain turned on. The voltage level of the second terminal NA 1 of the capacitor C 1 is coupled to VI 1 +VDD instantly. Since the voltage level of the second terminal NB 1 of the second capacitor C 2 remains around VI 2 +VDD, the first NMOS transistor N 1 and the second NMOS transistor N 2 are both turned on. Also, the first PMOS transistor P 1 and the second PMOS transistor P 2 are turned off. Therefore, no reverse current will be generated between the fourth capacitor C 4 and the second capacitor C 2 or between the first capacitor C 1 and the third capacitor C 3 . Although the first capacitor C 1 may be discharged through the first NMOS transistor N 1 unwantedly, the voltage drops are rather small and will not cause any significant effect because the second time period T 2 is rather short and the voltage of the second terminal of the first capacitor C 1 is not affecting the output voltage directly due to the turned-off the first PMOS transistor P 1 . In addition, this voltage drop may only happen to the first charge pump unit 10 , and can be prevented by the clock signals in the following charge pump units.

During the third time period T 3 between the falling edge FEB 1 of the second clock signal CLKB 1 and the rising edge REB 2 of the fourth clock signal CLKB 2 , the first clock signal CLKA 1 is at the high voltage VDD, the second clock signal CLKB 1 is at the low voltage GND, the third clock signal CLKA 2 is at the high voltage VDD, and the fourth clock signal CLKB 2 is at the low voltage GND. Therefore, the voltage level of the second terminal NB 1 of the second capacitor C 2 is coupled to VI 2 while the voltage level of the second terminal NA 1 of the first capacitor C 1 remains at VDD+VI 1 . The first NMOS transistor N 1 is turned off and the first PMOS transistor P 1 is turned on. In this case, the second terminal of the first PMOS P 1 can output the voltage of the second terminal NA 1 of the first capacitor, that is, VI 1 +VDD. Also, although the voltage level of the second terminal NB 2 of the fourth capacitor C 4 may be higher than the voltage level of the second terminal NB 1 of the second capacitor C 2 due to previous operations, no reverse current will be generated since the second PMOS transistor P 2 remains turned off.

During the fourth time period T 4 between the rising edge REB 2 of the fourth clock signal CLKB 2 and the falling edge FEA 2 of the third clock signal CLKA 2 , the first clock signal CLKA 1 is at the high voltage VDD, the second clock signal CLKB 1 is at the low voltage GND, the third clock signal CLKA 2 is at the high voltage VDD, and the fourth clock signal CLKB 2 is at the high voltage VDD. The voltage level of the second terminal NB 2 of the fourth capacitor C 4 is coupled to VI 2 +2VDD instantly. Since the voltage level of the second terminal NA 2 of the third capacitor C 3 remains around VI 1 +2VDD, the third NMOS transistor N 3 and the fourth NMOS transistor N 4 are turned on. The third PMOS transistor P 3 and the fourth PMOS transistor P 4 are turned off. Although the second terminal of the third capacitor C 3 may be discharged through the first PMOS transistor P 1 and the third NMOS transistor N 3 , the voltage level of the second terminal of the third capacitor C 3 will not be outputted due to the turned off third PMOS transistor P 3 . Also the voltage level of the second terminal of the third capacitor C 3 will finally be adjusted to VI 1 +VDD in the next time period T 5 so the voltage drop of the third capacitor C 3 can be ignored. Meanwhile, since the second PMOS transistor P 2 remains turned off, no reverse current will be generated between the second capacitor C 2 and the fourth capacitor C 4 .

During the fifth time period T 5 after the falling edge FEA 2 of the third clock signal CLKA 2 , the first clock signal CLKA 1 is at the high voltage VDD, the second clock signal CLKB 1 is at the low voltage GND, the third clock signal CLKA 2 is at the low voltage GND, and the fourth clock signal CLKB 2 is at the high voltage VDD. Therefore, the voltage level of the second terminal NA 2 of the third capacitor C 3 is coupled to around VI 1 +VDD while the voltage level of the second terminal NB 2 of the fourth capacitor C 4 remains at VI 2 +2VDD. The third NMOS transistor N 3 is turned on and the third PMOS transistor P 3 is turned off. The turned-on third NMOS transistor N 3 and the turned-on first PMOS transistor P 1 can further maintain the voltage level of the second terminal NA 2 of the third capacitor C 3 to be same as the voltage level of the second terminal NA 1 of the first capacitor C 1 , that is VI 1 +VDD. Also, the fourth PMOS P 4 is turned on and the fourth NMOS N 4 is turned off. Therefore, the second terminal of the fourth PMOS P 4 can output a voltage higher than the second input voltage VI 2 , that is, VI 2 +2VDD.

In some embodiments of the present invention, the periods of the clock signals CLKA 1 , CLKB 1 , CLKA 2 , and CLKB 2 can be 10 ns to 20 ns, and the time periods T 2 , T 3 , and T 4 between falling edges and rising edges can be shorter than 1 ns but long enough to turn on or turn off the transistors.

According to the aforesaid clock signals CLKA 1 , CLKB 1 , CLKA 2 , and CLKB 2 , the charge pump circuit 200 can output voltages higher than its input voltages and reduce reverse currents. Therefore, the unnecessary power consumption of the charge pump circuit 200 can be saved.

In addition, the second charge pump unit 20 can also output a high voltage from the third PMOS P 3 . In this case, to prevent the reverse current, the similar timing can be applied. That is, in FIG. 5 , a falling edge FEA 1 of the first clock signal CLKA 1 lags a respective rising edge REB 1 of the second clock signal CLKB 1 and leads a respective rising edge REA 2 of the third clock signal CLKA 2 . The rising edge REA 2 of the third clock signal CLKA 2 leads a respective falling edge FEB 2 of the fourth clock signal CLKB 2 . Consequently, the charge pump circuit 200 can output the voltage VI 1 +2VDD and VI 2 +2VDD from the third PMOS P 3 and the fourth PMOS transistor P 4 respectively and alternately.

In some embodiments, the charge pump circuit 200 may include clock generators to produce the desired clock signals. In FIG. 5 , the fourth clock signal CLKB 2 can be produced by delaying the first clock signal CLKA 1 by the time periods T 2 and T 3 . That is, the fourth clock signal CLKB 2 can be generated by delaying the first clock signal CLKA 1 with a simple delay circuit. Similarly, the third clock signal CLKA 2 can also be generated by delaying the second clock signal CLKB 1 properly in some embodiments of the present invention. However, by using simple delay circuits to generate all the clock signals, the duty cycles of the clock signals may be different from each other. Furthermore, the difference of duty cycles of the clock signals may increase when the number of clock signals increases.

FIG. 6 shows the clock generator 12 and a clock generator 22 according to one embodiment of the present invention. The clock generator 12 can generate the first clock signal CLKA 1 and the second clock signal CLKB 1 according to a reference clock CLK 0 , and the clock generator 22 can generate the third clock signal CLKA 2 and the fourth clock signal CLKB 2 according to the first clock signal CLKA 1 and the second clock signal CLKB 1 . The clock generator 22 includes a third NAND gate G 3 , a third delay circuit D 3 , a fourth NAND gate G 4 , and a fourth delay circuit D 4 . According to the clock generators 12 and 22 , the difference of duty cycles of clock signals can be avoided.

The third NAND gate G 3 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the third NAND gate G 3 is coupled to the output terminal of the first delay circuit D 1 for receiving the first clock signal CLKA 1 . The third delay circuit D 3 has an input terminal and an output terminal. The input terminal of the third delay circuit D 3 is coupled to the output terminal of the third NAND gate G 3 , and an output terminal is for outputting the fourth clock signal CLKB 2 .

The fourth NAND gate G 4 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the fourth NAND gate G 4 is coupled to the output terminal of the second delay circuit D 2 for receiving the second clock signal CLKB 1 , the second input terminal of the fourth NAND gate G 4 is coupled to the output terminal of the third delay circuit D 3 . The fourth delay circuit D 4 has an input terminal and an output terminal. The input terminal of the fourth delay circuit D 4 is coupled to the output terminal of the fourth NAND gate G 4 , and the output terminal of the fourth delay circuit D 4 is coupled to the second input terminal of the third NAND gate G 3 and is for outputting the third clock signal CLKA 2 .

In some embodiments of the present invention, the charge pump circuit 200 may include more charge pump units so that the output voltages of the charge pump circuit can be pumped to even higher voltage levels. FIG. 7 shows a charge pump circuit 300 according to one embodiment of the present invention. The charge pump circuit 300 includes the first charge pump unit 10 , the second charge pump unit 20 , and a third charge pump unit 30 .

The third charge pump unit 30 has a similar structure as the first charge pump unit 10 . The third charge pump unit 30 includes a fifth capacitor C 5 , a sixth capacitor C 6 , a fifth NMOS transistor N 5 , a fifth PMOS transistor P 5 , a sixth NMOS transistor N 6 , and a sixth PMOS transistor P 6 .

The fifth capacitor C 5 has a first terminal and a second terminal NA 3 . The first terminal of the fifth capacitor C 5 is for receiving a fifth clock signal CLKA 3 . The sixth capacitor C 6 has a first terminal and a second terminal NB 3 . The first terminal of the sixth capacitor C 6 is for receiving a sixth clock signal CLKB 3 .

The fifth NMOS transistor N 5 has a first terminal, a second terminal and a control terminal. The first terminal of the fifth NMOS transistor N 5 is coupled to the second terminal of the third PMOS transistor P 3 , the second terminal of the fifth NMOS transistor N 5 is coupled to the second terminal NA 3 of the fifth capacitor C 5 , and the control terminal of the fifth NMOS transistor N 5 is coupled to the second terminal NB 3 of the sixth capacitor C 6 . The fifth PMOS transistor P 5 has a first terminal, a second terminal and a control terminal. The first terminal of the fifth PMOS transistor P 5 is coupled to the second terminal of the fifth NMOS transistor N 5 , and the control terminal of the fifth PMOS transistor P 5 is coupled to the control terminal of the fifth NMOS transistor N 5 .

The sixth NMOS transistor N 6 has a first terminal, a second terminal and a control terminal. The first terminal of the sixth NMOS transistor N 6 is coupled to the second terminal of the fourth PMOS transistor P 4 , the second terminal of the sixth NMOS transistor N 6 is coupled to the second terminal NB 3 of the sixth capacitor C 6 , and the control terminal of the sixth NMOS transistor N 6 is coupled to the second terminal NA 3 of the fifth capacitor C 5 . The sixth PMOS transistor P 6 has a first terminal, a second terminal and a control terminal. The first terminal of the sixth PMOS transistor P 6 is coupled to the second terminal of the sixth NMOS transistor N 6 , and the control terminal of the sixth PMOS transistor P 6 is coupled to the control terminal of the sixth NMOS transistor N 6 .

The third charge pump unit 30 and the second charge pump unit 20 have the same operational principles. Namely, the third charge pump unit 30 can receive voltages (ex., VI 1 +2VDD and VI 2 +2VDD) from the second charge pump unit 20 through the fifth NMOS transistor N 5 and the sixth NMOS transistor N 6 , and outputs higher voltages (ex., VI 1 +3VDD and VI 2 +3VDD). FIG. 8 shows the operational timing diagram of charge pump circuit according to one embodiment of the present invention.

In FIG. 8 , the first clock signal CLKA 1 , the second clock signal CLKB 1 , the third clock signal CLKA 2 , the fourth clock signal CLKB 2 , the fifth clock signal CLKA 3 , and the sixth clock signal CLKB 3 transit at different time points.

To prevent the charge pump circuit 300 from generating reverse current, a falling edge FEB 1 of the second clock signal CLKB 1 lags a respective rising edge REA 1 of the first clock signal CLKA 1 and leads a respective rising edge REB 2 of the fourth clock signal CLKB 2 . Also, the rising edge REB 2 of the fourth clock signal CLKB 2 leads a respective falling edge FEA 2 of the third clock signal CLKA 2 . Furthermore, a rising edge REA 3 of the fifth clock signal CLKA 3 lags the respective falling edge FEA 2 of the third clock signal CLKA 2 and leads a respective falling edge FEB 3 of the sixth clock signal CLKB 3 .

Also, in FIG. 8 , the falling edge FEAT of the first clock signal CLKA 1 lags a respective rising edge REB 1 of the second clock signal CLKB 1 and leads a respective rising edge REA 3 of the third clock signal CLKA 2 . The rising edge REA 2 of the third clock signal CLKA 2 leads a respective falling edge FEB 2 of the fourth clock signal CLKB 2 . A rising edge REB 3 of the sixth clock signal CLKB 3 lags the respective falling edge FEB 2 of the fourth clock signal CLKB 2 and leads a respective falling edge FEA 3 of the fifth clock signal CLKA 3 .

Consequently, the charge pump circuit 300 can output the voltages VI 1 +3VDD and VI 2 +3VDD from the fifth PMOS P 5 and the sixth PMOS transistor P 6 respectively and alternately. Also, the charge pump circuit 300 can reduce reverse currents according to the well-arranged clock signals.

In FIG. 8 , the fourth clock signal CLKB 2 can be produced by delaying the first clock signal CLKA 1 by the time periods T 2 and T 3 . That is, the fourth clock signal CLKB 2 can be generated by delaying the first clock signal CLKA 1 with a simple delay circuit. Similarly, the third clock signal CLKA 2 can be generated by delaying the second clock signal CLKB 1 properly in some embodiments of the present invention. Also, the fifth clock signal CLKA 3 and the sixth clock signal CLKB 3 can be generated by delaying the first clock signal CLKA 1 , the second clock signal CLKB 1 , or the third clock signal CLKA 2 , and/or the fourth clock signal CLKB 2 properly in some embodiments of the present invention. However, by using simple delay circuits to generate all the clock signals, the duty cycles of the clock signals may be different from each other. Furthermore, the difference of duty cycles of the clock signals may increase when the number of clock signals increases.

FIG. 9 further shows the clock generator 12 , the clock generator 22 , and a clock generator 32 according to one embodiment of the present invention. The clock generator 12 can generate the first clock signal CLKA 1 and the second clock signal CLKB 1 according to a reference clock CLK 0 , the clock generator 22 can generate the third clock signal CLKA 2 and the fourth clock signal CLKB 2 according to the first clock signal CLKA 1 and the second clock signal CLKB 1 , and the clock generator 32 can generate the fifth clock signal CLKA 3 and the sixth clock signal CLKB 3 according to the third clock signal CLKA 2 and the fourth clock signal CLKB 2 . The clock generator 32 and the clock generator 22 have same structure. That is, the clock generator 32 includes a fifth NAND gate G 5 , a fifth delay circuit D 5 , a sixth NAND gate G 6 , and a sixth delay circuit D 6 . By using the clock generators 12 , 22 and 32 , the difference of duty cycles of the clock signals can be avoided.

The fifth NAND gate G 5 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the fifth NAND gate G 5 is coupled to the output terminal of the third delay circuit D 3 for receiving the fourth clock signal CLKB 2 . The fifth delay circuit D 5 has an input terminal and an output terminal. The input terminal of the fifth delay circuit D 5 is coupled to the output terminal of the fifth NAND gate G 5 , and an output terminal is for outputting the fifth clock signal CLKA 3 .

The sixth NAND gate G 6 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the sixth NAND gate G 6 is coupled to the output terminal of the fourth delay circuit D 4 for receiving the third clock signal CLKA 2 , the second input terminal of the sixth NAND gate G 6 is coupled to the output terminal of the fifth delay circuit D 5 . The sixth delay circuit D 6 has an input terminal and an output terminal. The input terminal of the sixth delay circuit D 6 is coupled to the output terminal of the sixth NAND gate G 6 , and the output terminal of the sixth delay circuit D 6 is coupled to the second input terminal of the fifth NAND gate G 5 and is for outputting the sixth clock signal CLKB 3 .

With the clock generator circuits 12 , 22 , and 32 , the first to sixth clock signals CLKA 1 to CLKB 3 can be generated according to the reference clock signal CLK 0 . In some embodiments of the present invention, the charge pump circuits may include a plurality number of charge pump units for generating desired high voltages. With the increasing numbers of the charge pump units, the corresponding clock signals can easily generated by including a corresponding number of clock generators of similar structures. Therefore, the flexible design of the charge pump circuit can fit the system requirements even more easily.

In summary, according to the embodiments of the present invention, the charge pump units and the charge pump circuits can generate high voltages for system requirements and reduce the reverse currents according to the well-arranged clock signals. Therefore, the unnecessary power consumption can be saved. Also, the flexible design of the charge pump circuits can fit the system requirements even more easily.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.