Multi-ported static random access memory

This Application claims priority of China Patent Application No. CN201510890908.9, filed on Dec. 4, 2015, the entirety of which is incorporated by reference herein.

The present invention relates to a static random access memory (SRAM), especially relates to storage cells of SRAM.

Static random access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry (e.g., cross-coupled CMOS inverters) to store each bit. How to efficiently access an SRAM is an important topic in the field.

A static random access memory in accordance with an exemplary embodiment of the disclosure includes a first bistable cell, a first bit line, a first complementary bit line, a first word line and a second word line. The first bistable cell has a first access terminal, a second access terminal, a first access switch and a second access switch. The first access switch is controlled by the first word line to couple the first access terminal to the first bit line. The second access switch is controlled by the second word line to couple the second access terminal to the first complementary bit line. The first access switch and the second access switch are controlled separately. Thus, the access efficiency of the SRAM is considerably improved.

In comparison with conventional techniques, the bistable cells of the disclosure use less number of transistors for multiple read operations or multiple write operations, making maximum utilization of storage space and more efficient.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1A depicts a static random access memory (SRAM) 100 in accordance with an exemplary embodiment of the disclosure;

FIG. 1B depicts a word line control module 102 for the SRAM 100 in accordance with an exemplary embodiment of the disclosure, which especially focuses on the control of the word lines WL 11 and WL 12 corresponding to the bistable cell BC 1 and the control of the word lines WL 21 and WL 22 corresponding to the bistable cell BC 2 ;

FIG. 1C shows waveforms for operating the SRAM 100 shown in FIG. 1A and FIG. 1B ;

FIG. 2A shows an SRAM 200 with each storage cell having eight transistors;

FIG. 2B depicts a word line control module 202 for the SRAM 200 in accordance with an exemplary embodiment of the disclosure;

FIG. 2C shows waveforms for operating the SRAM 200 of FIG. 2A and FIG. 2B ; and

FIG. 3 shows another way to implement an eight-transistor storage cell.

The following description shows exemplary embodiments carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1A depicts a static random access memory (SRAM) 100 in accordance with an exemplary embodiment of the disclosure. FIG. 1A shows two bistable cells BC 1 and BC 2 sharing a pair of bit line and complementary bit line BL and BLB in a storage array to help understand the structure of the SRAM 100 .

The bistable cell BC 1 /BC 2 is implemented by a pair of cross-coupled complementary metal oxide semiconductor (CMOS) inverters (coupled to a power source VDD and a ground terminal GND). A sense amplifier SA 1 is coupled to the bit line BL to get data READ 1 from the bit line BL. A sense amplifier SA 2 is coupled to the complementary bit line BLB to get data READ 2 from the complementary bit line BLB. When the write enable signal WREN is enabled, write data DATAIN is coupled to the bit line BL and the complementary bit line BLB by the write circuit Write_C to be written to the enabled bistable cell.

The bistable cell BC 1 has two access terminals N 11 and N 12 which respectively correspond to two access switches SW 11 and SW 12 that are controlled by two separate word lines WL 11 and WL 12 . The access switch SW 11 is operative to couple the access terminal N 11 to the bit line BL. The access switch SW 12 is operative to couple the access terminal N 12 to the complementary bit line BLB. The bistable cell BC 2 has two access terminals N 21 and N 22 which respectively correspond to two access switches SW 21 and SW 22 that are controlled by two separate word lines WL 21 and WL 22 . The access switch SW 21 is operative to couple the access terminal N 21 to the bit line BL. The access switch SW 22 is operative to couple the access terminal N 22 to the complementary bit line BLB. When the word lines WL 11 and WL 22 are enabled and the word lines WL 12 and WL 21 are disabled, data stored in the bistable cell BC 1 is conveyed to the sense amplifier SA 1 by the bit line BL to be read as data READ 1 and data stored in the bistable cell BC 2 is conveyed to the sense amplifier SA 2 by the complementary bit line BLB to be read as data READ 2 . When the word lines WL 12 and WL 21 are enabled and the word lines WL 11 and WL 22 are disabled, data stored in the bistable cell BC 1 is conveyed to the sense amplifier SA 2 by the complementary bit line BLB to be read as data READ 2 and data stored in the bistable cell BC 2 is conveyed to the sense amplifier SA 1 by the bit line BL to be read as data READ 1 . In write operations, the write enable signal WREN is enabled, the bistable cell BC 1 and the bistable cell BC 2 are written separately. To write the bistable cell BC 1 , the word lines WL 11 and WL 12 are controlled to close (turn on) the access switch SW 11 and SW 12 . Thus, the write data DATAIN coupled to the bit line BL and the complementary bit line BLB via the write circuit Write_C is further coupled to the bistable cell BC 1 . To write the bistable cell BC 2 , the word lines WL 21 and WL 22 are controlled to close the access switch SW 21 and SW 22 . Thus, the write data DATAIN coupled to the bit line BL and the complementary bit line BLB via the write circuit Write_C is coupled to the bistable cell BC 2 . The write circuit Write_C has two transistors, one inverter and one latch circuit. The bistable cell BC 1 /BC 2 has six transistors and achieves one write operation or two read operations at the same time even though only two transistors of the six transistors are access switches.

FIG. 1B depicts a word line control module 102 for the SRAM 100 in accordance with an exemplary embodiment of the disclosure, which especially focuses on the control of the word lines WL 11 and WL 12 corresponding to the bistable cell BC 1 and the control of the word lines WL 21 and WL 22 corresponding to the bistable cell BC 2 . There is a decoder 104 which is operated according to a clock signal CLK to generate decoded signals S 11 , S 12 , S 21 and S 22 based on address signals addrA and addrB. The decoder 104 includes decoding units DEC 11 , DEC 12 , DEC 21 and DEC 22 . Inverters INV 11 and INV 12 are coupled in series to couple the decoded signal S 11 to the word line WL 11 . Inverter INV 13 has an input terminal coupled to the write enable signal WREN and has an output terminal. A NAND gate G 11 has a first input terminal coupled to the decoded signal S 11 , a second input terminal coupled to the write enable signal WREN, and an output terminal. A NAND gate G 12 has a first input terminal coupled to the output terminal of the inverter INV 13 , a second input terminal coupled to the decoded signal S 12 , and an output terminal. A NAND gate G 13 has a first input terminal coupled to the output terminal of the NAND gate G 11 , a second input terminal coupled to the output of the NAND gate G 12 , and an output terminal coupled to the word line WL 12 . The inverters INV 21 and INV 22 are connected in series to couple the decoded signal S 21 to the word line WL 21 . An inverter INV 23 has an input terminal coupled to the write enable signal WREN, and has an output terminal. A NAND gate G 21 has a first input terminal coupled to the decoded output S 21 , a second input terminal coupled to the write enable signal WREN, and an output terminal. A NAND gate G 22 has a first input terminal coupled to the output terminal of the inverter INV 23 , a second input terminal coupled to the decoded output S 22 , and an output terminal. A NAND gate G 23 has a first input terminal coupled to the output terminal of the NAND gate G 21 , a second input terminal coupled to the output terminal of the NAND gate G 22 , and an output terminal coupled to the word line WL 22 . When it is indicated by the address signal addrA to write the write data DATAIN to the bistable cell BC 1 , the decoder 104 asserts the decoded signal S 11 and, with the enabled write enable signal WREN, the word lines WL 11 and WL 12 are enabled. When it is indicated by the address signal addrA to write the write data DATAIN into the bistable cell BC 2 , the decoder 104 asserts the decoded signal S 21 and, with the enabled write enable signal WREN, the word lines WL 21 and WL 22 are enabled. In read operations, the write enable signal WREN is disabled. When it is indicated by the address signal addrA to read the bistable cell BC 1 , the decoder 104 asserts the decoded signal S 11 to enable the word line WL 11 to couple the bit line BL to the bistable cell BC 1 . At the same time, the word line WL 12 is not affected by the word line WL 11 . When it is indicated by the address signal addrA to read the bistable cell BC 2 , the decoder 104 asserts the decoded signal S 21 to enable the word line WL 21 to couple the bit line BL to the bistable cell BC 2 . At the same time, the word line WL 22 is not affected by the word line WL 21 . When it is indicated by the address signal addrB to read the bistable cell BC 1 , the decoder 104 asserts the decoded signal S 12 to enable the word line WL 12 to couple the complementary bit line BLB to the bistable cell BC 1 . When it is indicated by the address signal addrB to read the bistable cell BC 2 , the decoder 104 asserts the decoded signal S 22 to enable the word line WL 22 to couple the complementary bit line BLB to the bistable cell BC 2 .

FIG. 1C shows waveforms for operating the SRAM 100 shown in FIG. 1A and FIG. 1B . As shown, when the write enable signal WREN is enabled, the SRAM 100 writes the write data DATAIN to the bistable cell BC 1 indicated by the address signal addrA and thereby the word lines WL 11 and WL 12 are enabled to couple the bit line BL and the complementary bit line BLB to the bistable cell BC 1 . Thus, the write data DATAIN is successfully written to the bistable cell BC 1 . As for the read operations on the SRAM 100 , the write enable signal WREN is disabled. Because the address signal addrA indicates the bistable cell BC 1 , the word line WL 11 is enabled to couple the bit line BL to the bistable cell BC 1 . Thus, the data stored in the bistable cell BC 1 is conveyed to the sense amplified SA 1 and obtained as data READ 1 . Because the address signal addrB indicates the bistable cell BC 2 , the word line WL 22 is enabled to couple the complementary bit line BLB to the bistable cell BC 2 . Thus, the data stored in the bistable cell BC 2 is conveyed to the sense amplified SA 2 and obtained as data READ 2 . As shown in FIG. 1C , the bistable cell BC 1 and the bistable cell BC 2 are read at the same time.

In addition to such six-transistor (6T) SRAM shown in FIGS. 1A, 1B and 1C , an eight-transistor (8T) SRAM is based on the same concept.

FIG. 2A shows an SRAM 200 with each storage cell having eight transistors. Each storage cell relates to two pairs of bit line and complementary bit line. To help understand the structure of SRAM 200 , the following discussion is focused on the four bistable cells BC 1 , BC 2 , BC 3 and BC 4 that share a first pair of bit line and complementary bit line (BL 1 and BL 1 B) and a second pair of bit line and complementary bit line (BL 2 and BL 2 B).

Each of the bistable cells BC 1 to BC 4 is implemented by a pair of cross-coupled CMOS inverters. Each bistable cell (any of BC 1 to BC 4 ) corresponds to four access switches and up to four word lines (referring to the word lines WL 11 , WL 12 , WL 13 and WL 14 corresponding to the bistable cell BC 1 , the word lines WL 21 , WL 22 , WL 23 and WL 24 corresponding to the bistable cell BC 2 , the word lines WL 31 , WL 32 , WL 33 and WL 34 corresponding to the bistable cell BC 3 , and the word lines WL 41 , WL 42 , WL 43 and WL 44 corresponding to the bistable cell BC 4 ). The following discussion is about the bistable cell BC 1 , to help understand the operations on a bistable cell. An access switch SW 11 is controlled according to word line WL 11 to couple the access terminal N 11 to the bit line BL 1 . An access switch SW 12 is controlled according to word line WL 12 to couple the access terminal N 12 to the complementary bit line BL 1 B. An access switch SW 13 is controlled according to word line WL 13 to couple the access terminal N 11 to the bit line BL 2 . An access switch SW 14 is controlled according to word line WL 14 to couple the access terminal N 12 to the complementary bit line BL 2 B. The other bistable cells are in the similar structure. The connection between a bistable cell, e.g. BC 1 . and the bit line BL 1 , the connection between the bistable cell (BC 1 ) and the complementary bit line BL 1 B, the connection between the bistable cell (BC 1 ) and the bit line BL 2 , and the connection between the bistable cell (BC 1 ) and the complementary bit line BL 2 B are controlled separately. A sense amplifier SA 1 is coupled to the bit line BL 1 to get data READ 1 from the bit line BL 1 . A sense amplifier SA 2 is coupled to the complementary bit line BL 1 B to get data READ 2 from the complementary bit line BL 1 B. A sense amplifier SA 3 is coupled to the bit line BL 2 to get data READ 3 from the bit line BL 2 . A sense amplifier SA 4 is coupled to the complementary bit line BL 2 B to get data READ 4 from the complementary bit line BL 2 B. At the same time, there may be up to four bits read from the bit line BL 1 , the complementary bit line BL 1 B, the bit line BL 2 and the complementary bit line BL 2 B. As for write operations, there may be up to two bits to be written to two storage cells at the same time through the two pairs of bit line and complementary bit line BL 1 and BL 1 B and BL 2 and BL 2 B. To write data to the SRAM 200 , the write enable signal WREN is enabled. As shown, the write data DATAIN 1 is coupled to the bit line BL 1 and the complementary bit line BL 1 B through the write circuit and then written to an enabled bistable cell, and the write data DATAIN 2 is coupled to the bit line BL 2 and the complementary bit line BL 2 B through the write circuit and then written to another enabled bistable cell. The write circuit similar to that shown in FIG. 1A is repeated here.

In summary, when reading the bistable cell BC 1 , only one access switch between the access switches SW 11 , SW 12 , SW 13 and SW 14 is close. Thus, three lines between the bit line BL 1 , the complementary bit line BL 1 B, the bit line BL 2 and the complementary bit line BL 2 B, and not connected to the bistable cell BC 1 may be separately coupled to other three bistable cells for data reading. When writing the write data DATAIN 1 to the bistable cell BC 1 through the bit line BL 1 and the complementary bit line BL 1 B, the word lines WL 11 and WL 12 close the access switches SW 11 and SW 12 and the word lines WL 13 and WL 14 open the access switches SW 13 and SW 14 . Thus, the bit line BL 2 and the complementary bit line BL 2 B can be used in writing data to another bistable cell to store the write data DATAIN 2 . Because one inverter has two transistors, the 8T bistable cell BC 1 /BC 2 only provides four transistors as access switches. Even though, two write operations or four read operations at the same time are achieved.

FIG. 2B depicts a word line control module 202 for the SRAM 200 in accordance with an exemplary embodiment of the disclosure. The control architecture for each pair of bit line and complementary bit line coupled to a bistable cell is similar to that shown in FIG. 1B . For simplicity, FIG. 2B focuses on a word line control structure 204 including decoding units DEC 11 . . . DEC 14 and logic gates for the bistable cell BC 1 and a word line control structure 206 including decoding units DEC 41 . . . DEC 44 and logic gates for the bistable cell BC 4 . The word line control of the bistable cells BC 2 and BC 3 not shown in FIG. 2C is similar to that for the bistable cell BC 1 or BC 4 .

To control the word lines WL 11 , WL 12 , WL 13 and WL 14 of the bistable cell BC 1 , the decoder including decoding units DEC 11 , DEC 12 , DEC 13 and DEC 14 generates decoded signals S 11 , S 12 , S 13 and S 14 based on the address signals addrA, addrB, addrC and addrD. When the address signal addrA indicates the bistable cell BC 1 and the write enable signal WREN is enabled, the decoder asserts the decoded signal S 11 to enable the word lines WL 11 and WL 12 both and the write data DATAIN 1 is written to the bistable cell BC 1 through the bit line BL 1 and the complementary bit line BL 1 B. At the same time, the address signal addrC can indicate the bistable cell BC 3 to drive the word line control structure of the bistable cell BC 3 to enable the word lines WL 33 and WL 34 and thereby the write data DATAIN 2 is written to the bistable cell BC 3 through the bit line BL 2 and the complementary bit line BL 2 B. In read operations, the write enable signal WREN is disabled and the four access switches of the same bistable cell are separately controlled. The different address signals addrA, addrB, addrC and addrD may indicate the different bistable cells BC 1 , BC 2 , BC 3 and BC 4 . The word line control module 202 enables the words lines WL 11 , WL 22 , WL 33 and WL 44 . The data READ 1 , READ 2 , READ 3 and READ 4 in the bistable cells BC 1 , BC 2 , BC 3 and BC 4 may be conveyed to the sense amplifiers SA 1 , SA 2 , SA 3 and SA 4 via the bit line BL 1 , the complementary bit line BL 1 B, the bit line BL 2 and the complementary bit line BL 2 B, respectively.

FIG. 2C shows waveforms for operating the SRAM 200 of FIG. 2A and FIG. 2B . When the write enable signal WREN is enabled, the SRAM 200 writes the write data DATAIN 1 and DATAIN 2 to the bistable cell BC 1 indicated by the address signal addrA and the bistable cell BC 3 indicated by the address signal addrC, respectively. Thus, the word lines WL 11 and WL 12 of the bistable cell BC 1 are enabled and the word lines WL 33 and WL 34 of the bistable cell BC 3 are enabled. The bit line BL 1 and the complementary bit line BL 1 B are coupled to the bistable cell BC 1 to write the write data DATAIN 1 to the bistable cell BC 1 , and the bit line BL 2 and the complementary bit line BL 2 B are coupled to the bistable cell BC 3 to write the write data DATAIN 2 to the bistable cell BC 3 . The write enable signal WREN is disabled for reading the SRAM 200 . When the address signal addrA indicates the bistable cell BC 1 , the word line WL 11 is enabled and the bit line BL 1 is coupled to the bistable cell BC 1 and the data stored in the bistable cell BC 1 is conveyed to the sense amplifier SA 1 by the bit line BL 1 to be read as data READ 1 . When the address signal addrB indicates the bistable cell BC 2 , the word line WL 22 is enabled and the complementary bit line BL 1 B is coupled to the bistable cell BC 2 and the data stored in the bistable cell BC 2 is conveyed to the sense amplifier SA 2 by the complementary bit line BL 1 B to be read as data READ 2 . When the address signal addrC indicates the bistable cell BC 3 , the word line WL 33 is enabled and the bit line BL 2 is coupled to the bistable cell BC 3 and the data stored in the bistable cell BC 3 is conveyed to the sense amplifier SA 3 by the bit line BL 2 to be read as data READ 3 . When the address signal addrD indicates the bistable cell BC 4 , the word line WL 44 is enabled and the complementary bit line BL 2 B is coupled to the bistable cell BC 4 and the data stored in the bistable cell BC 4 is conveyed to the sense amplifier SA 4 by the complementary bit line BL 2 B to be read as data READ 4 . FIG. 2C shows that the bistable cells BC 1 , BC 2 , BC 3 and BC 4 are read at the same time.

FIG. 3 shows another way to implement an eight-transistor storage cell. Referring to SRAM 300 shown in FIG. 3 , the separate control on the bit line and the complementary bit line is performed on only one bit line and complementary bit line pair of the bistable cell BC 1 . An access switch SW 11 is controlled by a word line WL 11 to couple the bistable cell BC 1 to a bit line BL 1 and an access switch SW 12 is controlled by a word line WL 12 to couple the bistable cell BC 1 to a complementary bit line BL 1 B. Two access switches SW 13 and SW 14 both are controlled by a word line WL 13 to couple the bistable cell BC 1 to a bit line BL 2 and a complementary bit line BL 2 B. A sense amplifier SA 1 is coupled the bit line BL 1 to get data READ 1 from the bit line BL 1 . A sense amplifier SA 2 is coupled the complementary bit line BL 1 B to get data READ 2 from the complementary bit line BL 1 B. A sense amplifier SA 3 is coupled the bit line BL 2 and the complementary bit line BL 2 B both to get data READ 3 . As shown, one bit is read from the bit line BL 1 , one bit is read from the complementary bit line BL 1 B and one bit is read from the bit line BL 2 and the complementary bit line BL 2 B at the same time. During write operations, up to two bits can be written to the SRAM 300 by the two pairs of bit line and complementary bit line BL 1 and BL 1 B and BL 2 and BL 2 B at the same time. To write data to the SRAM 300 , the write enable signal WREN is enabled. The write data DATAIN 1 is written to an enabled bistable cell through the bit line BL 1 and the complementary bit line BL 1 B while the write data DATAIN 2 is written to another enabled bistable cell through the bit line BL 2 and the complementary bit line BL 2 B. The write circuit similar to that shown in FIG. 1A is not repeated here.

A bistable cell with separately controlled bit line and complementary bit line is within the scope of the invention.

While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.