Output circuit and integrated circuit

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-013485, filed on Jan. 27, 2015, the entire contents of which are incorporated herein by reference.

The embodiments discussed herein are directed to an output circuit and an integrated circuit.

An input-output circuit capable of eliminating ringing by cooperation of an input circuit and an acceleration circuit has been known (see Patent Literature 1). Data lines outside a chip connected to an I/O terminal are doubly driven by two transistors, facilitating potential drop of a node. After a predetermined time passes, when level of the node is determined to be L logic, H logic is outputted from the input circuit, and thereby transistors of the acceleration circuit turn off. Data lines outside the chip connected to the I/O terminal are singly driven by one output transistor, and thus potential variations of the node become gradual, avoiding waveform distortion such as ringing.

There has been known a data output circuit having a transmission line driving unit which drives a transmission line according to input data, and a data transition detection unit which detects a transition of input data or a transition of output data of the transmission line driving unit (see Patent Literature 2). For a predetermined period since the data transition detection unit detected a transition of data, driving capability of the transmission line driving unit is enhanced.

Patent Literature 1: Japanese Laid-open Patent Publication No. 6-104725

Patent Literature 2: Japanese Laid-open Patent Publication No. 11-239049

Double driving by two transistors enables fast driving. However, when driving capability is enhanced, an impedance mismatch occurs, and an overshoot or an undershoot of output voltage occurs, making it not possible to transmit a desired signal.

An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

Further, an output circuit has: a first driver circuit, to which a voltage of an input terminal is inputted, configured to output a voltage to an output terminal; a comparison circuit configured to compare a first reference voltage with a voltage of the output terminal at a time of rising of the voltage of the output terminal, and compare a second reference voltage different from the first reference voltage with the voltage of the output terminal at a time of falling of the voltage of the output terminal; and a second driver circuit, to which the voltage of the input terminal is inputted, configured to output a voltage to the output terminal and become an off state according to a comparison result of the comparison circuit.

The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.

FIG. 1 is a circuit diagram illustrating a configuration example of an output circuit according to a first embodiment;

FIG. 2A is a diagram illustrating a voltage waveform of an output terminal;

FIG. 2B is a voltage waveform for explaining operation of a hysteresis comparison circuit;

FIG. 3A is a circuit diagram illustrating a configuration example of the hysteresis comparison circuit of FIG. 1 ;

FIG. 3B is a circuit diagram illustrating a configuration example of a comparison circuit of FIG. 3A ;

FIG. 3C is a circuit diagram illustrating a configuration example of a first selector of FIG. 1 ;

FIG. 4 is a timing chart for explaining operation of the output circuit of FIG. 1 ;

FIG. 5 is a circuit diagram illustrating a configuration example of an output circuit according to a second embodiment;

FIG. 6A is a voltage waveform diagram for explaining operation of the output circuit of FIG. 5 ;

FIG. 6B is a voltage waveform diagram at the time of rising of an output terminal after control of driving;

FIG. 7 is a circuit diagram illustrating a configuration example of an output circuit according to a third embodiment;

FIG. 8A is a circuit diagram illustrating a configuration example of a selector of FIG. 7 ;

FIGS. 8B and 8C are circuit diagrams illustrating configuration examples of a measurement circuit of FIG. 7 ;

FIG. 9 is a diagram illustrating a voltage waveform at the time of rising of an output terminal;

FIG. 10 is a flowchart illustrating a processing example in which the output circuit controls the number of parallel connections of p-channel field effect transistors;

FIG. 11 is a timing chart illustrating a processing example of the output circuit;

FIG. 12 is a flowchart illustrating a processing example in which the output circuit controls the number of parallel connections of n-channel field effect transistors;

FIG. 13 is a timing chart illustrating a processing example of the output circuit;

FIG. 14 is a circuit diagram illustrating a configuration example of an output circuit according to a fourth embodiment;

FIG. 15 is a voltage waveform diagram of an output terminal;

FIG. 16 is a timing chart for explaining operation of p-channel field effect transistors;

FIG. 17 is a timing chart for explaining operation of n-channel field effect transistors;

FIG. 18 is a circuit diagram illustrating a configuration example of an output circuit according to a fifth embodiment;

FIG. 19A is a circuit diagram illustrating a configuration example of a part of a selector of FIG. 18 ;

FIGS. 19B and 19C are circuit diagrams illustrating configuration examples of a measurement circuit of FIG. 18 ;

FIG. 20A is a circuit diagram illustrating a configuration example of another part of the selector of FIG. 18 ;

FIGS. 20B and 20C are diagrams illustrating the measurement circuit;

FIG. 21A is a voltage waveform diagram of an output terminal;

FIG. 21B is a diagram illustrating a voltage waveform at the time of rising of the output terminal;

FIG. 21C is a diagram illustrating a voltage waveform at the time of falling of the output terminal;

FIG. 22 is a flowchart illustrating a processing example in which the output circuit controls the numbers of parallel connections of p-channel field effect transistors;

FIG. 23 is a timing chart illustrating a processing example of the output circuit;

FIG. 24 is a flowchart illustrating a processing example in which the output circuit controls the numbers of parallel connections of the n-channel field effect transistors;

FIG. 25 is a timing chart illustrating a processing example of the output circuit; and

FIG. 26 is a diagram illustrating a configuration example of an integrated circuit according to a sixth embodiment.

First Embodiment

FIG. 1 is a circuit diagram illustrating a configuration example of an output circuit according to a first embodiment. The output circuit has a first driver circuit 101 , a second driver circuit 102 and a hysteresis comparison circuit 103 , to which a voltage of an input terminal IN is inputted, and which outputs a voltage to an output OUT. To the input terminal IN, a voltage of binary data is inputted.

The first driver circuit 101 has a p-channel field effect transistor 111 and an n-channel field effect transistor 112 . The p-channel field effect transistor 111 has a source connected to a power supply potential node (first potential node), a gate connected to the input terminal IN, and a drain connected to an output terminal OUT. The n-channel field effect transistor 112 has a source connected to a ground potential node (second potential node), a gate connected to the input terminal IN, and a drain connected to the output terminal OUT. Here, a power supply potential (first potential) is a positive potential when the ground potential (second potential) is 0 V. That is, the power supply potential (first potential) is higher than the ground potential (second potential). The first driver circuit 101 , to which a voltage of the input terminal IN is inputted, outputs a voltage to the output terminal OUT. Specifically, the first driver circuit 101 is an inverter and outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT.

The hysteresis comparison circuit 103 has a comparison circuit 117 and a switch 118 . The switch 118 supplies, when the value of output voltage VA of the comparison circuit 117 is “1” (high level), a first reference voltage V 1 to a positive input node of the comparison circuit 117 and supplies, when the value of the output terminal VA of the comparison circuit 117 is “0” (low level), a second reference voltage V 2 to the positive input node of the comparison circuit 117 . A voltage VB is the voltage of the positive input node of the comparison circuit 117 . As illustrated in FIG. 2B , the first reference voltage V 1 is higher than the second reference voltage V 2 . To a negative input node of the comparison circuit 117 , a voltage of the output terminal OUT is inputted. The comparison circuit 117 outputs a voltage VA with a value “1” when the voltage of the positive input node is higher than the voltage of the negative input node, and outputs a voltage VA with a value “0” when the voltage of the positive input node is lower than the voltage of the negative input node.

The second driver circuit 102 has a first selector 113 , a second selector 114 , a p-channel field effect transistor 115 and an n-channel field effect transistor 116 . The first selector 113 outputs the power supply potential (positive potential) as a voltage S 1 when the voltage VA has a value “0”, and outputs the voltage of the input terminal IN as the voltage S 1 when the voltage VA has a value “1”. The second selector 114 outputs the ground potential as a voltage S 2 when the voltage VA has a value “1”, and outputs the voltage of the input terminal IN as the voltage S 2 when the voltage VA has a value “0”. The p-channel field effect transistor 115 has a source connected to the power supply potential node (positive potential node), a gate connected to a line of the voltage S 1 , and a drain connected to the output terminal OUT. The n-channel field effect transistor 116 has a source connected to the ground potential node, a gate connected to a line of the voltage S 2 , and a drain connected to the output terminal OUT.

FIG. 2A is a diagram illustrating a voltage waveform of the output terminal OUT. A voltage waveform 201 is a voltage waveform of the output terminal OUT when the gates of the p-channel field effect transistor 115 and the n-channel field effect transistor 116 are constantly connected to the input terminal IN. In this case, both the first driver circuit 101 and the second driver circuit 102 operate constantly and hence the driving speed is high, but an overshoot 202 and an undershoot 203 occur. On the other hand, a voltage waveform 204 is a desired voltage waveform of the output terminal OUT for binary data. In this embodiment, the first selector 113 controls the gate voltage of the p-channel field effect transistor 115 and the second selector 114 controls the gate voltage of the n-channel field effect transistor 116 , and thereby the overshoot 202 and the undershoot 203 can be reduced.

FIG. 2B is a voltage waveform for explaining operation of the hysteresis comparison circuit 103 . The first reference voltage V 1 is higher than the second reference voltage V 2 . First, operation at the time of rising of the voltage of the output terminal OUT will be explained. When the voltage of the output terminal OUT is at low level, the voltage of the output terminal OUT is lower than the first reference voltage V 1 and the second reference voltage V 2 , and thus the comparison circuit 117 outputs the voltage VA with a value “1”. In this case, a switch 108 supplies the first reference voltage V 1 to the positive input node of the comparison circuit 117 . The voltage of the output terminal OUT rises from low level to high level. The comparison circuit 117 maintains the value “1” of the voltage VA in a period in which the voltage of the output terminal OUT is lower than the first reference voltage V 1 . When the voltage of the output terminal OUT becomes higher than the first reference voltage V 1 , the comparison circuit 117 outputs the voltage VA with a value “0”. In a period in which the voltage of the output terminal OUT is at high level, the voltage VA becomes a value “0”. When the voltage VA becomes a value “0”, the switch 108 supplies the second reference voltage V 2 to the positive input node of the comparison circuit 117 .

Next, operation at the time of falling of the voltage of the output terminal OUT will be explained. The voltage of the output terminal OUT falls from high level to low level. The comparison circuit 117 maintains the value “0” of the voltage VA in a period in which the voltage of the output terminal OUT is higher than the second reference voltage V 2 . When the voltage of the output terminal OUT becomes lower than the second reference voltage V 2 , the comparison circuit 117 outputs the voltage VA with a value “1”. In a period in which the voltage of the output terminal OUT is at low level, the voltage VA becomes a value “1”. The switch 108 supplies, when the voltage VA becomes a value “1”, the first reference voltage V 1 to the positive input node of the comparison circuit 117 .

FIG. 3A is a circuit diagram illustrating a configuration example of the hysteresis comparison circuit 103 of FIG. 1 . The hysteresis comparison circuit 103 has a comparison circuit 117 , an inverter 301 , n-channel field effect transistors 302 , 304 , and p-channel field effect transistors 303 , 305 . The inverter 301 , the n-channel field effect transistors 302 , 304 and the p-channel field effect transistors 303 , 305 correspond to the switch 118 of FIG. 1 .

When the voltage VA has a value “1”, the n-channel field effect transistor 304 and the p-channel field effect transistor 305 turn on, and the n-channel field effect transistor 302 and the p-channel field effect transistor 303 turn off. Hence, the first reference voltage V 1 is supplied as the voltage VB to the positive input node of the comparison circuit 117 .

When the voltage VA has a value “0”, the n-channel field effect transistor 302 and the p-channel field effect transistor 303 turn on, and the n-channel field effect transistor 304 and the p-channel field effect transistor 305 turn off. Hence, the second reference voltage V 2 is supplied as the voltage VB to the positive input node of the comparison circuit 117 .

FIG. 3B is a circuit diagram illustrating a configuration example of the comparison circuit 117 of FIG. 3A . The comparison circuit 117 has a current supply 311 , p-channel field effect transistors 312 to 314 , n-channel field effect transistors 315 to 319 , a positive input node Vip, a negative input node Vim and an output node Vo. The voltage VB is inputted to the positive input node Vip. The voltage of the output terminal OUT is inputted to the negative input node Vim. The voltage VA is outputted from the output node Vo. When the voltage of the positive input node Vip is higher than voltage of the negative input node Vim, the output node Vo outputs the voltage VA with a value “1”. When the voltage of the positive input node Vip is lower than voltage of the negative input node Vim, the output node Vo outputs the voltage VA with a value “0”.

FIG. 3C is a circuit diagram illustrating a configuration example of the first selector 113 of FIG. 1 . The first selector 113 has an inverter 321 , n-channel field effect transistors 322 , 324 and p-channel field effect transistors 323 , 325 . Note that the second selector 114 has the same configuration as the first selector 113 . Hereinafter, the first selector 113 will be explained as an example.

When the voltage VA has a value “0”, the n-channel field effect transistor 322 and the p-channel field effect transistor 323 turn on, and the n-channel field effect transistor 324 and the p-channel field effect transistor 325 turn off. Hence, the power supply potential of a power supply potential node Vdd is supplied as the voltage S 1 to the gate of the p-channel field effect transistor 115 .

When the voltage VA has a value “1”, the n-channel field effect transistor 324 and the p-channel field effect transistor 325 turn on, and the n-channel field effect transistor 322 and the p-channel field effect transistor 323 turn off. Hence, the voltage of the input terminal IN is supplied as the voltage S 1 to the gate of the p-channel field effect transistor 115 .

FIG. 4 is a timing chart for explaining operation of the output circuit of FIG. 1 . In FIG. 4 , low level of the p-channel field effect transistor 115 represents an operating state, and high level thereof represents a non-operating state (off state). High level of the n-channel field effect transistor 116 represents an operating state, and low level thereof represents a non-operating state (off state). The first driver circuit 101 is an inverter and outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT.

Times t 1 to t 3 are a period in which the voltage of the output terminal OUT rises from low level to high level. At time t 1 , the voltage of the output terminal OUT is at low level. The voltage VA is at high level, and thus the voltage VB of the positive input node of the comparison circuit 117 is the first reference voltage V 1 . The low level voltage of the output terminal OUT is lower than the first reference voltage V 1 , and thus the voltage VA at high level is outputted. In this case, the first selector 113 connects the input terminal IN to the gate of the p-channel field effect transistor 115 . At this time, the voltage of the input terminal IN is at high level, and thus the p-channel field effect transistor 115 is in an off state. The second selector 114 connects the ground potential node to the gate of the n-channel field effect transistor 116 . Hence, the n-channel field effect transistor 116 is in an off state.

Next, at times t 1 to t 2 , the voltage of the output terminal OUT is lower than the first reference voltage V 1 , and thus the voltage VA maintains high level. In this period, the voltage of the input terminal IN becomes lower than high level, and thus the p-channel field effect transistor 115 becomes an operating state. Hence, the output circuit has high driving capability and can drive at high speed at the time of rising.

At time t 2 , the voltage of the output terminal OUT becomes higher than the first reference voltage V 1 , and the voltage VA becomes low level. Hence, the voltage VB of the positive input node of the comparison circuit 117 becomes the second reference voltage V 2 . At times t 2 to t 5 , the voltage of the output terminal OUT is higher than the second reference voltage V 2 , and thus the comparison circuit 117 maintains the voltage VA at low level. Hence, the first selector 113 connects the power supply potential node to the gate of the p-channel field effect transistor 115 , and the p-channel field effect transistor 115 becomes an oft state. Hence, the overshoot 202 of FIG. 2A can be reduced.

Times t 4 to t 6 are a period in which the voltage of the output terminal OUT falls from high level to low level. At times t 4 to t 6 , the voltage of the output terminal OUT is higher than the second reference voltage V 2 , and thus the voltage VA maintains low level. In this period, the voltage of the input terminal IN becomes higher than low level, and thus the n-channel field effect transistor 116 becomes an operating state. Hence, the output circuit has high driving capability and can drive at high speed at the time of falling.

At time t 5 , the voltage of the output terminal OUT becomes lower than the second reference voltage V 2 , and the voltage VA becomes high level. Hence, the voltage VB of the positive input node of the comparison circuit 117 becomes the first reference voltage V 1 . At times t 5 to t 6 , the comparison circuit 117 maintains the voltage VA at high level since the voltage of the output terminal OUT is lower than the second reference voltage V 2 . Hence, the second selector 114 connects the ground potential node to the gate of the n-channel field effect transistor 116 , and the n-channel field effect transistor 116 becomes an off state. Hence, the undershoot 203 of FIG. 2A can be reduced.

As described above, at the time of rising of the voltage of the output terminal OUT, the comparison circuit 117 compares the first reference voltage V 1 with the voltage of the output terminal OUT and, at the time of falling of the voltage of the output terminal OUT, compares the second reference voltage V 2 , which is different from the first reference voltage V 1 , with the voltage of the output terminal OUT. The second driver circuit 102 becomes an off state according to a comparison result of the comparison circuit 117 .

The first selector 113 , to which the output voltage VA of the comparison circuit 117 is inputted, at the time of rising of the voltage of the output terminal OUT connects the gate of the p-channel field effect transistor 115 to the input terminal IN when the voltage of the output terminal OUT is lower than the first reference voltage V 1 , and connects the gate of the p-channel field effect transistor 115 to the power supply potential node when the voltage of the output terminal OUT is higher than the first reference voltage V 1 .

Further, at the time of falling of the voltage of the output terminal OUT, the first selector 113 connects the gate of the p-channel field effect transistor 115 to the power supply potential node when the voltage of the output terminal OUT is higher than the second reference voltage V 2 , and connects the gate of the p-channel field effect transistor 115 to the input terminal IN when the voltage of the output terminal OUT is lower than the second reference voltage V 2 .

The second selector 114 , to which the output voltage VA of the comparison circuit 117 is inputted, at the time of falling of the voltage of the output terminal OUT connects the gate of the n-channel field effect transistor 116 to the input terminal IN when the voltage of the output terminal OUT is higher than the second reference voltage V 2 , and connects the gate of the n-channel field effect transistor 116 to the ground potential node when the voltage of the output terminal OUT is lower than the second reference voltage V 2 .

Further, at the time of rising of the voltage of the output terminal OUT, the second selector 114 connects the gate of the n-channel field effect transistor 116 to the ground potential node when the voltage of the output terminal OUT is lower than the first reference voltage V 1 , and connects the gate of the n-channel field effect transistor 116 to the input terminal IN when the voltage of the output terminal OUT is higher than the first reference voltage V 1 .

By making the first reference voltage V 1 higher than the second reference voltage V 2 , chattering can be prevented. When the second reference voltage V 2 is the same as the first reference voltage V 1 , if vibrations of the overshoot 202 and the undershoot 203 of FIG. 2A occur, the value of the output voltage VA of the comparison circuit 117 changes repeatedly between “1” and “0” at high speed both at the time of rising and at the time of falling, making the operation unstable. By making the first reference voltage V 1 higher than the second reference voltage V 2 , changes at high frequency of the output voltage VA of the comparison circuit 117 can be prevented, to thereby make the operation stable.

Further, by making the first reference voltage V 1 higher than the second reference voltage V 2 , the p-channel field effect transistor 115 can support driving of the first driver circuit 101 in the long rising period of times t 1 to t 2 . Further, by making the second reference voltage V 2 lower than the first reference voltage V 1 , the n-channel field effect transistor 116 can support driving of the first driver circuit 101 in the long falling period of times t 4 to t 5 .

Second Embodiment

FIG. 5 is a circuit diagram illustrating a configuration example of an output circuit according to a second embodiment. The output circuit has a first driver circuit 101 , a second driver circuit 102 a , a third driver circuit 102 b , a fourth driver circuit 102 c and comparison circuits 117 ap , 117 an , 117 bp , 117 bn , 117 cp , 117 cn.

The first driver circuit 101 , to which the voltage of the input terminal IN is inputted, has a p-channel field effect transistor 111 and an n-channel field effect transistor 112 , and outputs a voltage to the output terminal OUT.

The comparison circuit 117 ap compares the first reference voltage V 1 and the voltage of the output terminal OUT and outputs a voltage VAap. The comparison circuit 117 an compares the first reference voltage V 1 with the voltage of the output terminal OUT and outputs a voltage VAan. The voltage VAan is the same as the voltage VAap. The second driver circuit 102 a , to which the voltage of the input terminal IN is inputted, outputs a voltage to the output terminal OUT, and becomes an off state according to comparison results of the comparison circuits 117 ap and 117 an.

The second driver circuit 102 a has a p-channel field effect transistor 115 a , an n-channel field effect transistor 116 a , and selectors 113 a and 114 a . The p-channel field effect transistor 115 a has a source connected to the power supply potential node, and a drain connected to the output terminal OUT. The n-channel field effect transistor 116 a has a source connected to the ground potential node, and a drain connected to the output terminal OUT. The selector 113 a , to which the output voltage VAap of the comparison circuit 117 ap is inputted, connects the gate of the p-channel field effect transistor 115 a to the input terminal IN when the voltage of the output terminal OUT is lower than the first reference voltage V 1 , and connects the gate of the p-channel field effect transistor 115 a to the power supply potential node when the voltage of the output terminal OUT is higher than the first reference voltage V 1 . The selector 114 a , to which the output voltage VAan of the comparison circuit 117 an is inputted, connects the gate of the n-channel field effect transistor 116 a to the input terminal IN when the voltage of the output terminal OUT is higher than the first reference voltage V 1 , and connects the gate of the n-channel field effect transistor 116 a to the ground potential node when the voltage of the output terminal OUT is lower than the first reference voltage V 1 .

The comparison circuit 117 bp compares the second reference voltage V 2 which is different from the first reference voltage V 1 with the voltage of the output terminal OUT, and outputs a voltage VAbp. The comparison circuit 117 bn compares the second reference voltage V 2 with the voltage of the output terminal OUT, and outputs a voltage VAbn. The voltage VAbn is the same as the voltage VAbp. The third driver circuit 102 b , to which the voltage of the input terminal IN is inputted, outputs a voltage to the output terminal OUT, and becomes an off state according to comparison results of the comparison circuits 117 bp and 117 bn.

The third driver circuit 102 b has a p-channel field effect transistor 115 b , an n-channel field effect transistor 116 b , and selectors 113 b and 114 b . The p-channel field effect transistor 115 b has a source connected to the power supply potential node, and a drain connected to the output terminal OUT. The n-channel field effect transistor 116 b has a source connected to the ground potential node, and a drain connected to the output terminal OUT. The selector 113 b , to which the output voltage VAbp of the comparison circuit 117 bp is inputted, connects the gate of the p-channel field effect transistor 115 b to the input terminal IN when the voltage of the output terminal OUT is lower than the second reference voltage V 2 , and connects the gate of the p-channel field effect transistor 115 b to the power supply potential node when the voltage of the output terminal OUT is higher than the second reference voltage V 2 . The selector 114 b , to which the output voltage VAbn of the comparison circuit 117 bn is inputted, connects the gate of the n-channel field effect transistor 116 b to the input terminal IN when the voltage of the output terminal OUT is higher than the second reference voltage V 2 , and connects the gate of the n-channel field effect transistor 116 b to the ground potential node when the voltage of the output terminal OUT is lower than the second reference voltage V 2 .

The comparison circuit 117 cp compares a third reference voltage V 3 which is different from the first reference voltage V 1 and the second reference voltage V 2 with the voltage of the output terminal OUT, and outputs a voltage VAcp. The comparison circuit 117 cn compares the third reference voltage V 3 with the voltage of the output terminal OUT, and outputs a voltage VAcn. The voltage VAcn is the same as the voltage VAcp. The fourth driver circuit 102 c , to which the voltage of the input terminal IN is inputted, outputs a voltage to the output terminal OUT, and becomes an off state according to comparison results of the comparison circuits 117 cp and 117 cn.

The fourth driver circuit 102 c has a p-channel field effect transistor 115 c , an n-channel field effect transistor 116 c , and selectors 113 c and 114 c . The p-channel field effect transistor 115 c has a source connected to the power supply potential node, and a drain connected to the output terminal OUT. The n-channel field effect transistor 116 c has a source connected to the ground potential node, and a drain connected to the output terminal OUT. The selector 113 c , to which the output voltage VAcp of the comparison circuit 117 cp is inputted, connects the gate of the p-channel field effect transistor 115 c to the input terminal IN when the voltage of the output terminal OUT is lower than the third reference voltage V 3 , and connects the gate of the p-channel field effect transistor 115 c to the power supply potential node when the voltage of the output terminal OUT is higher than the third reference voltage V 3 . The selector 114 c , to which the output voltage VAcn of the comparison circuit 117 cn is inputted, connects the gate of the n-channel field effect transistor 116 c to the input terminal IN when the voltage of the output terminal OUT is higher than the third reference voltage V 3 , and connects the gate of the n-channel field effect transistor 116 c to the ground potential node when the voltage of the output terminal OUT is lower than the third reference voltage V 3 .

FIG. 6A is a voltage waveform diagram for explaining operation of the output circuit of FIG. 5 , and FIG. 6B is a voltage waveform diagram at the time of rising of the output terminal OUT after control of driving. The second reference voltage V 2 is higher than the first reference voltage V 1 . The third reference voltage V 3 is higher than the second reference voltage V 2 .

First, a period in which the voltage of the output terminal OUT rises from low level to high level will be explained. In a period Ta in which the voltage of the output terminal OUT is lower than the first reference voltage V 1 , the three p-channel field effect transistors 115 a , 115 b , 115 c become an operating state, driving capability thereof becomes maximum, and driving speed can be made high. Next, in a period Tb in which the voltage of the output terminal OUT is higher than the first reference voltage V 1 and lower than the second reference voltage V 2 , the two p-channel field effect transistors 115 b , 115 c become an operating state, the one p-channel field effect transistor 115 a becomes an off state, and driving capability becomes weaker. Next, in a period Tc in which the voltage of the output terminal OUT is higher than the second reference voltage V 2 and lower than the third reference voltage V 3 , the one p-channel field effect transistor 115 c becomes an operating state, the two p-channel field effect transistors 115 a , 115 b become an off state, and driving capability becomes further weaker. Next, in a period Td in which the voltage of the output terminal OUT is higher than the third reference voltage V 3 , the three p-channel field effect transistors 115 a , 115 b , 115 c become an off state, and driving capability becomes further weaker. At the time of rising, by the above-described control of driving of the p-channel field effect transistors 115 a , 115 b , 115 c , the rising voltage of the output terminal OUT becomes gradually slow in rising speed as illustrated in FIG. 6B , and the overshoot 202 of FIG. 2A can be prevented.

Next, a period in which the voltage of the output terminal OUT falls from high level to low level will be explained. In a period in which the voltage of the output terminal OUT is lower than the third reference voltage V 3 , the three n-channel field effect transistors 116 a , 116 b , 116 c become an operating state, driving capability thereof becomes maximum, and driving speed can be made high. Next, in a period in which the voltage of the output terminal OUT is lower than the third reference voltage V 3 and higher than the second reference voltage V 2 , the two n-channel field effect transistors 116 a , 116 b become an operating state, the one n-channel field effect transistor 116 c becomes an off state, and driving capability becomes weaker. Next, in a period in which the voltage of the output terminal OUT is lower than the second reference voltage V 2 and higher than the first reference voltage V 1 , the one n-channel field effect transistor 116 a becomes an operating state, the two n-channel field effect transistors 116 b , 116 c become an off state, and driving capability becomes further weaker. Next, in a period in which the voltage of the output terminal OUT is lower than the first reference voltage V 1 , the three n-channel field effect transistors 116 a , 116 b , 116 c become an off state, and driving capability becomes further weaker. At the time of falling, by the above-described control of driving of the n-channel field effect transistors 116 a , 116 b , 116 c , the falling voltage of the output terminal OUT becomes gradually slow in falling speed, and the undershoot 203 of FIG. 2A can be prevented.

Third Embodiment

FIG. 7 is a circuit diagram illustrating a configuration example of an output circuit according to a third embodiment. The output circuit of FIG. 7 is obtained by deleting the fourth driver circuit 102 c and the comparison circuits 117 cp , 117 cn from the output circuit of FIG. 5 and adding a control circuit 501 , a measurement circuit 502 and a selector 503 thereto. A comparison circuit 117 a corresponds to the comparison circuits 117 ap and 117 an of FIG. 5 , compares the voltage of the output terminal OUT and the first reference voltage V 1 , and outputs a voltage VAa to the selectors 113 a and 114 a . A comparison circuit 117 b corresponds to the comparison circuits 117 bp and 117 bn of FIG. 5 , compares the voltage of the output terminal OUT and the second reference voltage V 2 , and outputs a voltage VAb to the selectors 113 b and 114 b.

Hereinafter, differences of this embodiment ( FIG. 7 ) from the second embodiment ( FIG. 5 ) will be explained. The second driver circuit 102 a has n n-channel field effect transistors 116 a . The n n-channel field effect transistors 116 a are connected in parallel, have a gate connected to an output node of the selector 114 a , a source connected to the ground potential node, and a drain connected to the output terminal OUT. The control circuit 501 can control the number n of n-channel field effect transistors 116 a connected in parallel between the output terminal OUT and the ground potential node, and can change the size of the n-channel field effect transistors 116 a.

Similarly, the third driver circuit 102 b has m p-channel field effect transistors 115 b . The m p-channel field effect transistors 115 b are connected in parallel, have a gate connected to an output node of the selector 113 b , a source connected to the power supply potential node, and a drain connected to the output terminal OUT. The control circuit 501 can control the number m of p-channel field effect transistors 115 b connected in parallel between the power supply potential node and the output terminal OUT, and can change the size of the p-channel field effect transistors 115 b.

FIG. 8A is a circuit diagram illustrating a configuration example of the selector 503 of FIG. 7 . The control circuit 501 sets “1” to a control signal SA when controlling the number m of parallel connections of the p-channel field effect transistors 115 b , and sets “0” to the control signal SA when controlling the number n of parallel connections of the n-channel field effect transistors 116 a . The selector 503 has inverters 601 , 602 and selectors 603 , 604 . The inverter 601 outputs a logically inverted voltage /VAb of the output voltage VAb of the comparison circuit 117 b . The inverter 602 outputs a logically inverted voltage /VAa of the output voltage VAa of the comparison circuit 117 a . When the control signal SA is “1”, the selector 603 outputs the voltage /VAb as a voltage P, and the selector 604 outputs the voltage /VAa as a voltage Q. When the control signal SA is “0”, the selector 603 outputs the voltage VAa as the voltage P, and the selector 604 outputs the voltage VAb as the voltage Q.

FIGS. 8B and 8C are circuit diagrams illustrating configuration examples of the measurement circuit 502 of FIG. 7 . A buffer 611 , to which the voltage Q is inputted, outputs a voltage F 1 to a capacitor 621 and a buffer 612 . In a flip flop circuit 631 , the voltage P is inputted to a data input terminal, and the voltage F 1 is inputted to a clock input terminal. The buffer 612 , to which the voltage F 1 is inputted, outputs a voltage F 2 to a capacitor 622 and a buffer 613 . In a flip flop circuit 632 , the voltage P is inputted to a data input terminal, and the voltage F 2 is inputted to a clock input terminal. The buffer 613 , to which the voltage F 2 is inputted, outputs a voltage F 3 to a capacitor 623 and a buffer 614 . In a flip flop circuit 633 , the voltage P is inputted to a data input terminal, and the voltage F 3 is inputted to a clock input terminal. The buffer 614 , to which the voltage F 3 is inputted, outputs a voltage F 4 to a capacitor 624 and a buffer 615 . In a flip flop circuit 634 , the voltage P is inputted to a data input terminal, and the voltage F 4 is inputted to a clock input terminal. The buffer 615 , to which the voltage F 4 is inputted, outputs a voltage F 5 to a capacitor 625 . In a flip flop circuit 635 , the voltage P is inputted to a data input terminal, and the voltage F 5 is inputted to a clock input terminal.

When the control signal SA is “1”, as illustrated in FIG. 8B , the voltage /VAa is inputted as the voltage Q to the buffer 611 , and the voltage /VAb is inputted as the voltage P to the data input terminals of the flip flop circuits 631 to 635 .

When the control signal SA is “0”, as illustrated in FIG. 8C , the voltage VAb is inputted as the voltage Q to the buffer 611 , and the voltage VAa is inputted as the voltage P to the data input terminals of the flip flop circuits 631 to 635 .

FIG. 9 is a diagram illustrating a voltage waveform at the time of rising of the output terminal OUT. The second reference voltage V 2 is higher than the first reference voltage V 1 . At time ta, the voltage of the output terminal OUT becomes higher than the first reference voltage V 1 , and the voltage VAa changes from a value “1” to a value “0”. At time tb, the voltage of the output terminal OUT becomes higher than the second reference voltage V 2 , and the voltage VAb changes from a value “1” to a value “0”. The measurement circuit 502 measures rising time Δtp from time ta to time tb. The control circuit 501 controls the number m of parallel connections of the p-channel field effect transistors 115 b so that the rising time Δtp becomes a target time. When the number m of parallel connections is large, the size of the p-channel field effect transistors 115 b is large, and the rising time Δtp becomes short, enabling high-speed driving. On the other hand, when the number m of parallel connections is small, the size of the p-channel field effect transistors 115 b is small, and the rising time Δtp becomes long, enabling prevention of overshoot. By controlling the rising time Δtp to be the target time by the control circuit 501 , both the high speed driving and the overshoot can be achieved together.

FIG. 10 is a flowchart illustrating a processing example in which the output circuit controls the number m of parallel connections of the p-channel field effect transistors 115 b , and FIG. 11 is a timing chart illustrating a processing example of the output circuit.

In step S 801 , the control circuit 501 sets, for example, time Δt 3 as the target time of the rising time Δtp. The time Δt 3 is from rising time t 1 of the voltage /VAa to rising time of the voltage F 3 , as will be described later.

Next, in step S 802 , the control circuit 501 sets “1” to the control signal SA so as to control the number m of parallel connections of the p-channel field effect transistors 115 b . Then, the selector 503 outputs the voltage /VAb as the voltage P, and outputs the voltage /VAa as the voltage Q. Further, the control circuit 501 controls the number m of parallel connections of the p-channel field effect transistors 115 b to be the maximum value.

Next, in step S 803 , a voltage falling from a value “1” to a value “0” is inputted to the input terminal IN. Then, the first driver circuit 101 outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT. The voltage of the output terminal OUT becomes a voltage rising from a value “0” to a value “1”.

Here, a voltage OUT 1 is the voltage of the output terminal OUT at a time of first loop processing of steps S 803 to S 805 . A voltage OUT 2 is the voltage of the output terminal OUT at a time of second loop processing of steps S 803 to S 805 . A voltage OUT 3 is the voltage of the output terminal OUT at a time of third loop processing of steps S 803 to S 805 .

Further, a voltage /VAb 1 is the voltage /VAb at a time of first loop processing of steps S 803 to S 805 . A voltage /VAb 2 is the voltage /VAb at a time of second loop processing of steps S 803 to S 805 . A voltage /VAb 3 is the voltage /VAb at a time of third loop processing of steps S 803 to S 805 .

In the first loop processing, the voltage OUT 1 and the voltage /VAb 1 will be explained. At time t 1 , the voltage OUT 1 becomes higher than the first reference voltage V 1 , and thus the voltage VAa falls from high level to low level, and the voltage /VAa rises from low level to high level. The voltage F 1 is a delayed voltage of the voltage /VAa. The voltage F 2 is a delayed voltage of the voltage F 1 . The voltage F 3 is a delayed voltage of the voltage F 2 . The voltage F 4 is a delayed voltage of the voltage F 3 . The voltage F 5 is a delayed voltage of the voltage F 4 . At time t 2 , the voltage OUT 1 becomes higher than the second reference voltage V 2 , and thus the voltage /VAb 1 rises from low level to high level.

In step S 804 , the control circuit 501 measures the rising time Δtp from time t 1 to time t 2 . The flip flop circuit 631 retains a value “1” of the voltage /VAb 1 at the time of rising of the voltage F 1 . The flip flop circuit 632 retains a value “1” of the voltage /VAb 1 at the time of rising of the voltage F 2 . The flip flop circuit 633 retains a value “1” of the voltage /VAb 1 at the time of rising of the voltage F 3 . The flip flop circuit 634 retains a value “1” of the voltage /VAb 1 at the time of rising of the voltage F 4 . The flip flop circuit 635 retains a value “1” of the voltage /VAb 1 at the time of rising of the voltage F 5 .

In step S 805 , the control circuit 501 judges whether the rising time Δtp from time t 1 to time t 2 matches the target time Δt 3 or not. Specifically, since the values retained in the flip flop circuits 631 to 635 are all “1”, the control circuit 501 judges that the rising time Δtp from time t 1 to time t 2 is shorter than the target time Δt 3 , and proceeds to step S 806 .

In step S 806 , the control circuit 501 controls the number m of parallel connections of the p-channel field effect transistors 115 b to decrease by 1. Thereafter, the control circuit 501 returns to step S 803 , and performs the second loop processing.

In step S 803 , the falling voltage is inputted again to the input terminal IN. In this case, the voltage of the output terminal OUT is the voltage OUT 2 , and the voltage /VAb is the voltage /VAb 2 . At time t 1 , the voltage OUT 2 becomes higher than the first reference voltage V 1 , and thus the voltage VAa falls from high level to low level and the voltage /VAa rises from low level to high level. At time t 3 , the voltage OUT 2 becomes higher than the second reference voltage V 2 , and thus the voltage /VAb 2 rises from low level to high level.

In step S 804 , the control circuit 501 measures the rising time Δtp from time t 1 to time t 3 . The flip flop circuits 631 to 635 each retain the value of the voltage /VAb 2 at the time of rising of the voltages F 1 to F 5 . The flip flop circuit 631 retains a value “0”, and the flip flop circuits 632 to 635 retain a value “1”.

In step S 805 , since the flip flop circuit 631 retains the value “0” and the flip flop circuits 632 to 635 retain the value “1”, the control circuit 501 judges that the rising time Δtp from time t 1 to time t 3 is shorter than the target time Δt 3 , and proceeds to step S 806 .

In step S 806 , the control circuit 501 controls the number m of parallel connections of the p-channel field effect transistors 115 b to further decrease by 1. Thereafter, the control circuit 501 returns to step S 803 , and performs the third loop processing.

In step S 803 , the falling voltage is inputted again to the input terminal IN. In this case, the voltage of the output terminal OUT is the voltage OUT 3 , and the voltage /VAb is the voltage /VAb 3 . At time t 1 , the voltage OUT 3 becomes higher than the first reference voltage V 1 , and thus the voltage VAa falls from high level to low level and the voltage /VAa rises from low level to high level. At time t 4 , the voltage OUT 3 becomes higher than the second reference voltage V 2 , and thus the voltage /VAb 3 rises from low level to high level.

In step S 804 , the control circuit 501 measures the rising time Δtp from time t 1 to time t 4 . The flip flop circuits 631 to 635 each retain the value of the voltage /VAb 3 at the time of rising of the voltages F 1 to F 5 . The flip flop circuits 631 and 632 retain a value “0”, and the flip flop circuits 633 to 635 retain a value “1”.

In step S 805 , since the flip flop circuits 631 and 632 retain the value “0” and the flip flop circuits 633 to 635 retain the value “1”, the control circuit 501 judges that the rising time Δtp from time t 1 to time t 4 substantially matches the target time Δ t 3 , and finishes the processing.

By the above processing, the number m of parallel connections of the p-channel field effect transistors 115 b is controlled so that the rising time Δtp substantially matches the target time Δt 3 , enabling to achieve both high-speed driving and prevention of overshoot. The control circuit 501 changes the size of the p-channel field effect transistors 115 b according to the rising time Δtp from the time when the output voltage VAa of the comparison circuit 117 a is inverted to the time when the output voltage VAb of the comparison circuit 117 b is inverted.

FIG. 12 is a flowchart illustrating a processing example in which the output circuit controls the number n of parallel connections of the n-channel field effect transistors 116 a , and FIG. 13 is a timing chart illustrating a processing example of the output circuit.

In step S 1001 , the control circuit 501 sets, for example, time Δt 3 as the target time of falling time Δtn.

Next, in step S 1002 , the control circuit 501 sets “0” to the control signal SA so as to control the number n of parallel connections of the n-channel field effect transistors 116 a . Then, the selector 503 outputs the voltage VAa as the voltage P, and outputs the voltage VAb as the voltage Q. Further, the control circuit 501 controls the number n of parallel connections of the n-channel field effect transistors 116 a to be the maximum value.

Next, in step S 1003 , a voltage rising from a value “0” to a value “1” is inputted to the input terminal IN. Then, the first driver circuit 101 outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT. The voltage of the output terminal OUT becomes a voltage falling from a value “1” to a value “0”.

In the first loop processing, the voltage of the output terminal OUT is the voltage VOUT 1 , and the voltage VAa is a voltage VAa 1 . At time t 1 , the voltage OUT 1 becomes lower than the second reference voltage V 2 , and thus the voltage VAb rises from low level to high level. The voltage F 1 is a delayed voltage of the voltage VAb. The voltage F 2 is a delayed voltage of the voltage F 1 . The voltage F 3 is a delayed voltage of the voltage F 2 . The voltage F 4 is a delayed voltage of the voltage F 3 . The voltage F 5 is a delayed voltage of the voltage F 4 . At time L 2 , the voltage OUT 1 becomes lower than the first reference voltage V 1 , and thus the voltage VAa 1 rises from low level to high level.

In step S 1004 , the control circuit 501 measures the falling time Δtn from time t 1 to time t 2 . The flip flop circuits 631 to 635 each retain the value of the voltage VAa 1 at the time of rising of the voltages F 1 to F 5 . The flip flop circuits 631 to 635 all retain a value “1”.

In step S 1005 , the control circuit 501 judges whether the falling time Δtn from time t 1 to time t 2 matches the target time Δt 3 or not. Specifically, since the values retained in the flip flop circuits 631 to 635 are all “1”, the control circuit 501 judges that the falling time Δtn from time t 1 to time t 2 is shorter than the target time Δ t 3 , and proceeds to step S 1006 .

In step S 1006 , the control circuit 501 controls the number n of parallel connections of the n-channel field effect transistors 116 a to decrease by 1. Thereafter, the control circuit 501 returns to step S 1003 , and performs the second loop processing.

In step S 1003 , the rising voltage is inputted again to the input terminal IN. In this case, the voltage of the output terminal OUT is the voltage OUT 2 , and the voltage VAa is a voltage VAa 2 . At time t 1 , the voltage OUT 2 becomes lower than the second reference voltage V 2 , and thus the voltage VAb rises from low level to high level. At time t 3 , the voltage OUT 2 becomes lower than the first reference voltage V 1 , and thus the voltage VAa 2 rises from low level to high level.

In step S 1004 , the control circuit 501 measures the falling time Δtn from time t 1 to time t 3 . The flip flop circuits 631 to 635 each retain the value of the voltage VAa 2 at the time of rising of the voltages F 1 to F 5 . The flip flop circuit 631 retains a value “0”, and the flip flop circuits 632 to 635 retain a value “1”.

In step S 1005 , since the flip flop circuit 631 retains the value “0” and the flip flop circuits 632 to 635 retain the value “1”, the control circuit 501 judges that the falling time Δtn from time t 1 to time t 3 is shorter than the target time Δt 3 , and proceeds to step S 1006 .

In step S 1006 , the control circuit 501 controls the number n of parallel connections of the n-channel field effect transistors 116 a to further decrease by 1. Thereafter, the control circuit 501 returns to step S 1003 , and performs the third loop processing.

In step S 1003 , the rising voltage is inputted again to the input terminal IN. In this case, the voltage of the output terminal OUT is the voltage OUT 3 , and the voltage VAa is a voltage VAa 3 . At time t 1 , the voltage OUT 3 becomes lower than the second reference voltage V 2 , and thus the voltage VAb rises from low level to high level. At time t 4 , the voltage OUT 3 becomes lower than the first reference voltage V 1 , and thus the voltage VAa 3 rises from low level to high level.

In step S 1004 , the control circuit 501 measures the falling time Δtn from time t 1 to time t 4 . The flip flop circuits 631 to 635 each retain the value of the voltage VAa 3 at the time of rising of the voltages F 1 to F 5 . The flip flop circuits 631 and 632 retain a value “0”, and the flip flop circuits 633 to 635 retain a value “1”.

In step S 1005 , since the flip flop circuits 631 and 632 retain the value “0” and the flip flop circuits 633 to 635 retain the value “1”, the control circuit 501 judges that the falling time Δtn from time t 1 to time t 4 substantially matches the target time Δt 3 , and finishes the processing.

By the above processing, the number n of parallel connections of the n-channel field effect transistors 116 a is controlled so that the falling time Δtn substantially matches the target time Δt 3 , enabling to achieve both high-speed driving and prevention of undershoot. The control circuit 501 changes the size of the n-channel field effect transistors 116 a according to the falling time Δtn from the time when the output voltage VAb of the comparison circuit 117 b is inverted to the time when the output voltage VAa of the comparison circuit 117 a is inverted.

Fourth Embodiment

FIG. 14 is a circuit diagram illustrating a configuration example of an output circuit according to a fourth embodiment. The output circuit of FIG. 14 is obtained by adding switches 118 ap , 118 an , 118 bp , 118 bn , 118 cp , 118 cn to the output circuit of FIG. 5 . Hereinafter, differences of this embodiment ( FIG. 14 ) from the second embodiment ( FIG. 5 ) will be explained.

The switch 118 ap outputs the first reference voltage V 1 as a voltage VBap to a positive input node of the comparison circuit 117 ap when the voltage VAap has a value “1”, and outputs a reference voltage VL as the voltage VBap to the positive input node of the comparison circuit 117 ap when the voltage VAap has a value “0”.

The switch 118 an outputs the first reference voltage V 1 as a voltage VBan to a positive input node of the comparison circuit 117 an when the voltage VAan has a value “0”, and outputs a reference voltage VH as the voltage VBan to the positive input node of the comparison circuit 117 an when the voltage VAan has a value “1”.

The switch 118 bp outputs the second reference voltage V 2 as a voltage VBbp to a positive input node of the comparison circuit 117 bp when the voltage VAbp has a value “1”, and outputs the reference voltage VL as the voltage VBbp to the positive input node of the comparison circuit 117 bp when the voltage VAbp has a value “0”.

The switch 118 bn outputs the second reference voltage V 2 as a voltage VBbn to a positive input node of the comparison circuit 117 bn when the voltage VAbn has a value “0”, and outputs the reference voltage VH as the voltage VBbn to the positive input node of the comparison circuit 117 bn when the voltage VAbn has a value “1”.

The switch 118 cp outputs the third reference voltage V 3 as a voltage VBcp to a positive input node of the comparison circuit 117 cp when the voltage VAcp has a value “1”, and outputs the reference voltage VL as the voltage VBcp to the positive input node of the comparison circuit 117 cp when the voltage VAcp has a value “0”.

The switch 118 cn outputs the third reference voltage V 3 as a voltage VBcn to a positive input node of the comparison circuit 117 cn when the voltage VAcn has a value “0”, and outputs the reference voltage VH as the voltage VBcn to the positive input node of the comparison circuit 117 cn when the voltage VAcn has a value “1”.

FIG. 15 is a voltage waveform diagram of the output terminal OUT. The first reference voltage V 1 is 0.9 V for example. The second reference voltage V 2 is higher than the first reference voltage V 1 and is 1.65 V for example. The third reference voltage V 3 is higher than the second reference voltage V 2 and is 2.4 V for example. The reference voltage VH is higher than the third reference voltage V 3 and is 3.1 V for example. The reference voltage VL is lower than the first reference voltage V 1 and is 0.2 V for example. The power supply voltage is 3.3 V for example.

FIG. 16 is a timing chart for explaining operation of the p-channel field effect transistors 115 a , 115 b , 115 c . In FIG. 16 , low level of the p-channel field effect transistors 115 a , 115 b , 115 c represents an operating state, and high level thereof represents a non-operating state (off state). The first driver circuit 101 outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT.

Times t 1 to t 5 are a period in which the voltage of the output terminal OUT rises from low level to high level. At time t 1 , the voltage of the output terminal OUT is at low level. The voltages VAap, VAbp, VAcp are at high level, and thus the voltage VBap becomes the first reference voltage V 1 , the voltage VBbp becomes the second reference voltage V 2 , and the voltage VBcp becomes the third reference voltage V 3 . In this case, the selectors 113 a , 113 b , 113 c connect the input terminal IN to the gates of the p-channel field effect transistors 115 a , 115 b , 115 c , respectively. At this time, the voltage of the input terminal IN is at high level, and thus the p-channel field effect transistors 115 a , 115 b , 115 c are in an off state.

Next, at time t 1 to t 2 , the voltage of the output terminal OUT is lower than the first reference voltage V 1 , and thus the voltages VAap, VAbp, VAcp maintain high level. After time t 1 , the voltage of the input terminal IN becomes lower than high level, and thus the p-channel field effect transistors 115 a , 115 b , 115 c becomes an operating state. Hence, the output circuit has high driving capability and can drive at high speed at the time of rising of the output terminal OUT.

At time t 2 , the voltage of the output terminal OUT becomes higher than the first reference voltage V 1 , and the voltage VAap becomes low level. Hence, the voltage VBap of the positive input node of the comparison circuit 117 ap becomes the reference voltage VL. At times t 2 to t 7 , the voltage of the output terminal OUT is higher than the reference voltage VL, and thus the comparison circuit 117 ap maintains the voltage VAap at low level. Hence, the selector 113 a connects the power supply potential node to the gate of the p-channel field effect transistor 115 a , and the p-channel field effect transistor 115 a becomes an off state. Hence, the overshoot 202 of FIG. 2A can be reduced.

At time t 3 , the voltage of the output terminal OUT becomes higher than the second reference voltage V 2 , and the voltage VAbp becomes low level. Hence, the voltage VBbp of the positive input node of the comparison circuit 117 bp becomes the reference voltage VL. At times t 3 to t 7 , the voltage of the output terminal OUT is higher than the reference voltage VL, and thus the comparison circuit 117 bp maintains the voltage VAbp at low level. Hence, the selector 113 b connects the power supply potential node to the gate of the p-channel field effect transistor 115 b , and the p-channel field effect transistor 115 b becomes an off state. Hence, the overshoot 202 of FIG. 2A can be reduced.

At time t 4 , the voltage of the output terminal OUT becomes higher than the third reference voltage V 3 , and the voltage VAcp becomes low level. Hence, the voltage VBcp of the positive input node of the comparison circuit 117 cp becomes the reference voltage VL. At times t 4 to t 7 , the voltage of the output terminal OUT is higher than the reference voltage VL, and thus the comparison circuit 117 cp maintains the voltage VAcp at low level. Hence, the selector 113 c connects the power supply potential node to the gate of the p-channel field effect transistor 115 c , and the p-channel field effect transistor 115 c becomes an off state. Hence, the overshoot 202 of FIG. 2A can be reduced.

As described above, the operating period of the p-channel field effect transistor 115 a is the period from time t 1 to time t 2 . The operating period of the p-channel field effect transistor 115 b is the period from time t 1 to time t 3 . The operating period of the p-channel field effect transistor 115 c is the period from time t 1 to time t 4 .

FIG. 17 is a timing chart for explaining operation of the n-channel field effect transistors 116 a , 116 b , 116 c . In FIG. 17 , high level of the n-channel field effect transistors 116 a , 116 b , 116 c represents an operating state, and low level thereof represents a non-operating state (off state). The first driver circuit 101 outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT.

Times t 1 to t 2 are a period in which the voltage of the output terminal OUT rises from low level to high level. At time t 1 , the voltage of the output terminal OUT is at low level. The voltages VAan, VAbn, VAcn are at high level, and thus the voltages VBan, VBbn, VBcn become the reference voltage VH. In this case, the selectors 114 a , 114 b , 114 c connect the ground potential node to the gates of the n-channel field effect transistors 116 a , 116 b , 116 c , respectively. The n-channel field effect transistors 116 a , 116 b , 116 c are in an off state.

At time t 2 , the voltage of the output terminal OUT becomes higher than the reference voltage VH, and the voltages VAan, VAbn, VAcn becomes low level. Hence, the voltage VBan of the positive input node of the comparison circuit 117 an becomes the first reference voltage V 1 , the voltage VBbn of the positive input node of the comparison circuit 117 bn becomes second reference voltage V 2 , and the voltage VBcn of the positive input node of the comparison circuit 117 cn becomes third reference voltage V 3 . At times t 2 to t 3 , the selectors 114 a , 114 b , 114 c connect the input terminal IN to the gates of the n-channel field effect transistors 116 a , 116 b , 116 c . At this time, the voltage of the input terminal IN is at low level, and thus the n-channel field effect transistors 116 a , 116 b , 116 c are in an off state.

Times t 3 to t 7 are a period in which the voltage of the output terminal OUT falls from high level to low level. After time t 3 , the voltage of the input terminal IN becomes higher than low level, and thus the n-channel field effect transistors 116 a , 116 b , 116 c become an operating state. Hence, the output circuit has high driving capability and can drive at high speed at the time of falling of the output terminal OUT.

At time t 4 , the voltage of the output terminal OUT becomes lower than the third reference voltage V 3 , and the voltage VAcn becomes high level. Hence, the voltage VBcn of the positive input node of the comparison circuit 117 cn becomes the reference voltage VH. At times t 4 to t 9 , the voltage of the output terminal OUT is lower than the reference voltage VH, and thus the comparison circuit 117 cn maintains the voltage VAcn at high level. Hence, the selector 114 c connects the ground potential node to the gate of the n-channel field effect transistor 116 c , and the n-channel field effect transistor 116 c becomes an off state. Hence, the undershoot 203 of FIG. 2A can be reduced.

At time t 5 , the voltage of the output terminal OUT becomes lower than the second reference voltage V 2 , and the voltage VAbn becomes high level. Hence, the voltage VBbn of the positive input node of the comparison circuit 117 bn becomes the reference voltage VH. At times t 5 to t 9 , the voltage of the output terminal OUT is lower than the reference voltage VH, and thus the comparison circuit 117 bn maintains the voltage VAbn at high level. Hence, the selector 114 b connects the ground potential node to the gate of the n-channel field effect transistor 116 b , and the n-channel field effect transistor 116 b becomes an off state. Hence, the undershoot 203 of FIG. 2A can be reduced.

At time t 6 , the voltage of the output terminal OUT becomes lower than the first reference voltage V 1 , and the voltage VAan becomes high level. Hence, the voltage VBan of the positive input node of the comparison circuit 117 an becomes the reference voltage VH. At times t 6 to t 9 , the voltage of the output terminal OUT is lower than the reference voltage VH, and thus the comparison circuit 117 an maintains the voltage VAan at high level. Hence, the selector 114 a connects the ground potential node to the gate of the n-channel field effect transistor 116 a , and the n-channel field effect transistor 116 a becomes an off state. Hence, the undershoot 203 of FIG. 2A can be reduced.

As described above, the operating period of the n-channel field effect transistor 116 a is the period from time t 3 to time t 6 . The operating period of the n-channel field effect transistor 116 b is the period from time t 3 to time t 5 . The operating period of the n-channel field effect transistor 116 c is the period from time t 3 to time t 4 .

As illustrated in FIG. 17 , at the rising time of the voltage of the output terminal OUT, the voltages VBan, VBbn, VBcn are the reference voltage VH, and thus the n-channel field effect transistors 116 a , 116 b , 116 c become an off state. Hence, as illustrated in FIG. 16 , at the rising time of the voltage of the output terminal OUT, the voltage of the output terminal OUT can be made to rise efficiently by operation of the p-channel field effect transistors 115 a , 115 b , 115 c.

Further, as illustrated in FIG. 16 , at the falling time of the voltage of the output terminal OUT, the voltages VBap, VBbp, VBcp are the reference voltage VL, and thus the p-channel field effect transistors 115 a , 115 b , 115 c become an off state. Hence, as illustrated in FIG. 17 , at the falling time of the voltage of the output terminal OUT, the voltage of the output terminal OUT can be made to fall efficiently by operation of the n-channel field effect transistors 116 a , 116 b , 116 c.

As described above, the comparison circuit 117 ap compares the voltage of the output terminal OUT with the first reference voltage V 1 at the time of rising of the voltage of the output terminal OUT, and compares the voltage of the output terminal OUT with the reference voltage VL at the time of falling of the voltage of the output terminal OUT. The comparison circuit 117 an compares the voltage of the output terminal OUT with the first reference voltage V 1 when the voltage of the output terminal OUT falls, and compares the voltage of the output terminal OUT with the reference voltage VH when the voltage of the output terminal OUT rises.

The comparison circuit 117 bp compares the voltage of the output terminal OUT with the second reference voltage V 2 at the time of rising of the voltage of the output terminal OUT, and compares the voltage of the output terminal OUT with the reference voltage VL at the time of falling of the voltage of the output terminal OUT. The comparison circuit 117 bn compares the voltage of the output terminal OUT with the second reference voltage V 2 when the voltage of the output terminal OUT falls, and compares the voltage of the output terminal OUT with the reference voltage VH when the voltage of the output terminal OUT rises.

The comparison circuit 117 cp compares the voltage of the output terminal OUT with the third reference voltage V 3 at the time of rising of the voltage of the output terminal OUT, and compares the voltage of the output terminal OUT with the reference voltage VL at the time of falling of the voltage of the output terminal OUT. The comparison circuit 117 cn compares the voltage of the output terminal OUT with the third reference voltage V 3 when the voltage of the output terminal OUT falls, and compares the voltage of the output terminal OUT with the reference voltage VH when the voltage of the output terminal OUT rises.

The selector 113 a , to which the output voltage VAap of the comparison circuit 117 ap is inputted, at the time of rising of the voltage of the output terminal OUT connects the gate of the p-channel field effect transistor 115 a to the input terminal IN when the voltage of the output terminal OUT is lower than the first reference voltage V 1 , and connects the gate of the p-channel field effect transistor 115 a to the power supply potential node when the voltage of the output terminal OUT is higher than the first reference voltage V 1 .

Further, at the time of falling of the voltage of the output terminal OUT, the selector 113 a connects the gate of the p-channel field effect transistor 115 a to the power supply potential node when the voltage of the output terminal OUT is higher than the reference voltage VL, and connects the gate of the p-channel field effect transistor 115 a to the input terminal IN when the voltage of the output terminal OUT is lower than the reference voltage VL.

The selector 114 a , to which the output voltage VAan of the comparison circuit 117 an is inputted, at the time of falling of the voltage of the output terminal OUT connects the gate of the n-channel field effect transistor 116 a to the input terminal IN when the voltage of the output terminal OUT is higher than the first reference voltage V 1 , and connects the gate of the n-channel field effect transistor 116 a to the ground potential node when the voltage of the output terminal OUT is lower than the first reference voltage V 1 .

Further, at the time of rising of the voltage of the output terminal OUT, the selector 114 a connects the gate of the n-channel field effect transistor 116 a to the ground potential node when the voltage of the output terminal OUT is lower than the reference voltage VH, and connects the gate of the n-channel field effect transistor 116 a to the input terminal IN when the voltage of the output terminal OUT is higher than the reference voltage VH.

The selector 113 b , to which the output voltage VAbp of the comparison circuit 117 bp is inputted, at the time of rising of the voltage of the output terminal OUT connects the gate of the p-channel field effect transistor 115 b to the input terminal IN when the voltage of the output terminal OUT is lower than the second reference voltage V 2 , and connects the gate of the p-channel field effect transistor 115 b to the power supply potential node when the voltage of the output terminal OUT is higher than the second reference voltage V 2 .

Further, at the time of falling of the voltage of the output terminal OUT, the selector 113 b connects the gate of the p-channel field effect transistor 115 b to the power supply potential node when the voltage of the output terminal OUT is higher than the reference voltage VL, and connects the gate of the p-channel field effect transistor 115 b to the input terminal IN when the voltage of the output terminal OUT is lower than the reference voltage VL.

The selector 114 b , to which the output voltage VAbn of the comparison circuit 117 bn is inputted, at the time of falling of the voltage of the output terminal OUT connects the gate of the n-channel field effect transistor 116 b to the input terminal IN when the voltage of the output terminal OUT is higher than the second reference voltage V 2 , and connects the gate of the n-channel field effect transistor 116 b to the ground potential node when the voltage of the output terminal OUT is lower than the second reference voltage V 2 .

Further, at the time of rising of the voltage of the output terminal OUT, the selector 114 b connects the gate of the n-channel field effect transistor 116 b to the ground potential node when the voltage of the output terminal OUT is lower than the reference voltage VH, and connects the gate of the n-channel field effect transistor 116 b to the input terminal IN when the voltage of the output terminal OUT is higher than the reference voltage VH.

The selector 113 c , to which the output voltage VAcp of the comparison circuit 117 cp is inputted, at the time of rising of the voltage of the output terminal OUT connects the gate of the p-channel field effect transistor 115 c to the input terminal TN when the voltage of the output terminal OUT is lower than the third reference voltage V 3 , and connects the gate of the p-channel field effect transistor 115 c to the power supply potential node when the voltage of the output terminal OUT is higher than the third reference voltage V 3 .

Further, at the time of falling of the voltage of the output terminal OUT, the selector 113 c connects the gate of the p-channel field effect transistor 115 c to the power supply potential node when the voltage of the output terminal OUT is higher than the reference voltage VL, and connects the gate of the p-channel field effect transistor 115 c to the input terminal IN when the voltage of the output terminal OUT is lower than the reference voltage VL.

The selector 114 c , to which the output voltage VAcn of the comparison circuit 117 cn is inputted, at the time of falling of the voltage of the output terminal OUT connects the gate of the n-channel field effect transistor 116 c to the input terminal IN when the voltage of the output terminal OUT is higher than the third reference voltage V 3 , and connects the gate of the n-channel field effect transistor 116 c to the ground potential node when the voltage of the output terminal OUT is lower than the third reference voltage V 3 .

Further, at the time of rising of the voltage of the output terminal OUT, the selector 114 c connects the gate of the n-channel field effect transistor 116 c to the ground potential node when the voltage of the output terminal OUT is lower than the reference voltage VH, and connects the gate of the n-channel field effect transistor 116 c to the input terminal IN when the voltage of the output terminal OUT is higher than the reference voltage VH.

Fifth Embodiment

FIG. 18 is a circuit diagram illustrating a configuration example of an output circuit according to a fifth embodiment. The output circuit of FIG. 18 is obtained by adding a control circuit 1801 , a measurement circuit 1802 and a selector 1803 to the output circuit of FIG. 14 . Hereinafter, differences of this embodiment ( FIG. 18 ) from the fourth embodiment ( FIG. 14 ) will be explained.

The second driver circuit 102 a has j n-channel field effect transistors 116 a . The j n-channel field effect transistors 116 a are connected in parallel, have a gate connected to an output node of the selector 114 a , a source connected to the ground potential node, and a drain connected to the output terminal OUT. The control circuit 1801 can control the number j of n-channel field effect transistors 116 a connected in parallel between the output terminal OUT and the ground potential node, and can change the size of the n-channel field effect transistors 116 a.

Similarly, the third driver circuit 102 b has m p-channel field effect transistors 115 b . The m p-channel field effect transistors 115 b are connected in parallel, have a gate connected to an output node of the selector 113 b , a source connected to the power supply potential node, and a drain connected to the output terminal OUT. The control circuit 1801 can control the number m of p-channel field effect transistors 115 b connected in parallel between the power supply potential node and the output terminal OUT, and can change the size of the p-channel field effect transistors 115 b.

Further, the third driver circuit 102 b has n n-channel field effect transistors 116 b . The n n-channel field effect transistors 116 b are connected in parallel, have a gate connected to an output node of the selector 114 b , a source connected to the ground potential node, and a drain connected to the output terminal OUT. The control circuit 1801 can control the number n of n-channel field effect transistors 116 b connected in parallel between the ground potential node and the output terminal OUT, and can change the size of the n-channel field effect transistors 116 b.

Similarly, the fourth driver circuit 102 c has k p-channel field effect transistors 115 c . The k p-channel field effect transistors 115 c are connected in parallel, have a gate connected to an output node of the selector 113 c , a source connected to the power supply potential node, and a drain connected to the output terminal OUT. The control circuit 1801 can control the number k of p-channel field effect transistors 115 c connected in parallel between the power supply potential node and the output terminal OUT, and can change the size of the p-channel field effect transistors 115 c.

FIG. 19A is a circuit diagram illustrating a configuration example of a part of the selector 1803 of FIG. 18 . The control circuit 1801 sets “1” to a control signal Sp when controlling the number m of parallel connections of the p-channel field effect transistors 115 b , and sets “0” to the control signal Sp when controlling the number k of parallel connections of the p-channel field effect transistors 115 c . The selector 1803 has inverters 1901 , 1902 , 1903 and selectors 1904 , 1905 . The inverter 1901 outputs a logically inverted voltage /VAbp of the output voltage VAbp of the comparison circuit 117 bp . The inverter 1902 outputs a logically inverted voltage /VAcp of the output voltage VAcp of the comparison circuit 117 cp . The inverter 1903 outputs a logically inverted voltage /VAap of the output voltage VAap of the comparison circuit 117 ap . When the control signal Sp is “1”, the selector 1904 outputs the voltage /VAbp as a voltage P, and the selector 1905 outputs the voltage /VAap as a voltage Q. When the control signal. Sp is “0”, the selector 1904 outputs the voltage /VAcp as the voltage P, and the selector 1905 outputs the voltage /VAbp as the voltage Q.

FIGS. 19B and 19C are circuit diagrams illustrating configuration examples of the measurement circuit 1802 of FIG. 18 . Similarly to the measurement circuit 502 of FIGS. 8B and 8C , the measurement circuit 1802 has buffers 611 to 615 , capacitors 621 to 625 and flip flop circuits 631 to 635 .

When the control signal Sp is “1”, as Illustrated in FIG. 19B , the voltage /VAap is inputted as the voltage Q to the buffer 611 , and the voltage /VAbp is inputted as the voltage P to the data input terminals of the flip flop circuits 631 to 635 .

When the control signal Sp is “0”, as illustrated in FIG. 19C , the voltage /VAbp is inputted as the voltage Q to the buffer 611 , and the voltage /VAcp is inputted as the voltage P to the data input terminals of the flip flop circuits 631 to 635 .

FIG. 20A is a circuit diagram illustrating a configuration example of another part of the selector 1803 of FIG. 18 . The control circuit 1801 sets “1” to a control signal Sn when controlling the number n of parallel connections of the n-channel field effect transistors 116 b , and sets “0” to the control signal Sn when controlling the number j of parallel connections of the n-channel field effect transistors 116 a . The selector 1803 has selectors 2001 , 2002 . When the control signal Sn is “1”, the selector 2001 outputs the voltage VAbn as the voltage P, and the selector 2002 outputs the voltage VAcn as the voltage Q. When the control signal Sn is “0”, the selector 2001 outputs the voltage VAan as the voltage P, and the selector 2002 outputs the voltage VAbn as the voltage Q.

FIG. 20B is a diagram illustrating the measurement circuit 1802 when the control signal Sn is “1”. The voltage VAcn is inputted as the voltage Q to the buffer 611 , and the voltage VAbn is inputted as the voltage P to the data input terminals of the flip flop circuits 631 to 635 .

FIG. 20C is a diagram illustrating the measurement circuit 1802 when the control signal Sn is “0”. The voltage VAbn is inputted as the voltage Q to the buffer 611 , and the voltage VAan is inputted as the voltage P to the data input terminals of the flip flop circuits 631 to 635 .

FIG. 21A is a voltage waveform diagram of the output terminal OUT. The second reference voltage V 2 is higher than the first reference voltage V 1 . The third reference voltage V 3 is higher than the second reference voltage V 2 . The reference voltage VH is higher than the third reference voltage V 3 . The reference voltage VL is lower than the first reference voltage V 1 .

FIG. 21B is a diagram illustrating a voltage waveform at the time of rising of the output terminal OUT. At time ta, the voltage of the output terminal OUT becomes higher than the first reference voltage V 1 , and the voltage VAap changes from a value “1” to a value “0”. At time tb, the voltage of the output terminal OUT becomes higher than the second reference voltage V 2 , and the voltage VAbp changes from a value “1” to a value “0”. At time tc, the voltage of the output terminal OUT becomes higher than the third reference voltage V 3 , and the voltage VAcp changes from a value “1” to a value “0”. The measurement circuit 1802 measures rising time Δta from time ta to time tb when the control signal Sp is “1”. Further, the measurement circuit 1802 measures rising time Δtb from time tb to time tc when the control signal Sp is “0”.

FIG. 21C is a diagram illustrating a voltage waveform at the time of falling of the output terminal OUT. At time td, the voltage of the output terminal OUT becomes lower than the third reference voltage V 3 , and the voltage VAcn changes from a value “0” to a value “1”. At time te, the voltage of the output terminal OUT becomes lower than the second reference voltage V 2 , and the voltage VAbn changes from a value “0” to a value “1”. At time tf, the voltage of the output terminal OUT becomes lower than the first reference voltage V 1 , and the voltage VAan changes from a value “0” to a value “1”. The measurement circuit 1802 measures falling time Δtc from time td to time te when the control signal Sn is “1”. Further, the measurement circuit 1802 measures falling time Δtd from time te to time tf when the control signal Sn is “0”.

FIG. 22 is a flowchart illustrating a processing example in which the output circuit controls the number m of parallel connections of the p-channel field effect transistors 115 b and the number k of parallel connections of the p-channel field effect transistors 115 c , and FIG. 23 is a timing chart illustrating a processing example of the output circuit.

In step S 2201 , the control circuit 1801 sets target times of rising times Δta and Δtb. For example, it sets the target time of rising time Ata to Δt 3 .

Next, in step S 2202 , the control circuit 1801 sets “1” to the control signal Sp so as to control the number m of parallel connections of p-channel field effect transistors 115 b . Then, the selector 1803 outputs the voltage /VAbp as the voltage P, and outputs the voltage /VAap as the voltage Q. Further, the control circuit 1801 controls the number m of parallel connections of the p-channel field effect transistors 115 b to be the maximum value.

Next, in step S 2203 , a voltage falling from a value “1” to a value “0” is inputted to the input terminal IN. Then, the first driver circuit 101 outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT. The voltage of the output terminal OUT becomes a voltage rising from a value “0” to a value “1”.

Here, a voltage OUT 1 is the voltage of the output terminal OUT at a time of first loop processing of steps S 2203 to S 2205 . A voltage OUT 2 is the voltage of the output terminal OUT at a time of second loop processing of steps S 2203 to S 2205 . A voltage OUT 3 is the voltage of the output terminal OUT at a time of third loop processing of steps S 2203 to S 2205 .

Further, a voltage /VAbp 1 is the voltage /VAbp at a time of first loop processing of steps S 2203 to S 2205 . A voltage /VAbp 2 is the voltage /VAbp at a time of second loop processing of steps S 2203 to S 2205 . A voltage /VAbp 3 is the voltage /VAbp at a time of third loop processing of steps S 2203 to S 2205 .

In the first loop processing, the voltage OUT 1 and the voltage /VAbp 1 will be explained. At time t 1 , the voltage OUT 1 becomes higher than the first reference voltage V 1 , and thus the voltage VAap falls from high level to low level, and the voltage /VAap rises from low level to high level. The voltage F 1 is a delayed voltage of the voltage /VAap. The voltage F 2 is a delayed voltage of the voltage F 1 . The voltage F 3 is a delayed voltage of the voltage F 2 . The voltage F 4 is a delayed voltage of the voltage F 3 . The voltage F 5 is a delayed voltage of the voltage F 4 . At time t 2 , the voltage OUT 1 becomes higher than the second reference voltage V 2 , and thus the voltage /VAbp 1 rises from low level to high level.

In step S 2204 , the control circuit 1801 measures the rising time Δta from time t 1 to time t 2 . The flip flop circuits 631 to 635 each retain a value “1” of the voltage /VAbp 1 at the time of rising of the voltages F 1 to F 5 .

In step S 2205 , the control circuit 1801 judges whether the rising time Δta from time t 1 to time t 2 matches the target time Δt 3 or not. Specifically, since the values retained in the flip flop circuits 631 to 635 are all “1”, the control circuit 1801 judges that the rising time Δta from time t 1 to time t 2 is shorter than the target time Δ t 3 , and proceeds to step S 2206 .

In step S 2206 , the control circuit 1801 controls the number m of parallel connections of the p-channel field effect transistors 115 b to decrease by 1. Thereafter, the control circuit 1801 returns to step S 2203 , and performs the second loop processing.

In step S 2203 , the falling voltage is inputted again to the input terminal IN. In this case, the voltage of the output terminal OUT is the voltage OUT 2 , and the voltage /VAbp is the voltage /VAbp 2 . At time t 1 , the voltage OUT 2 becomes higher than the first reference voltage V 1 , and thus the voltage VAap falls from high level to low level and the voltage /VAap rises from low level to high level. At time t 3 , the voltage OUT 2 becomes higher than the second reference voltage V 2 , and thus the voltage /VAbp 2 rises from low level to high level.

In step S 2204 , the control circuit 1801 measures the rising time Δta from time t 1 to time t 3 . The flip flop circuits 631 to 635 each retain the value of the voltage /VAbp 2 at the time of rising of the voltages F 1 to F 5 . The flip flop circuit 631 retains a value “0”, and the flip flop circuits 632 to 635 retain a value “1”.

In step S 2205 , since the flip flop circuit 631 retains the value “0” and the flip flop circuits 632 to 635 retain the value “1”, the control circuit 1801 judges that the rising time Δta from time t 1 to time t 3 is shorter than the target time Δt 3 , and proceeds to step S 2206 .

In step S 2206 , the control circuit 1801 controls the number m of parallel connections of the p-channel field effect transistors 115 b to further decrease by 1. Thereafter, the control circuit 1801 returns to step S 2203 , and performs the third loop processing.

In step S 2203 , the falling voltage is inputted again to the input terminal IN. In this case, the voltage of the output terminal OUT is the voltage OUT 3 , and the voltage /VAbp is the voltage /VAbp 3 . At time t 1 , the voltage OUT 3 becomes higher than the first reference voltage V 1 , and thus the voltage VAap falls from high level to low level and the voltage /VAap rises from low level to high level. At time t 4 , the voltage OUT 3 becomes higher than the second reference voltage V 2 , and thus the voltage /VAbp 3 rises from low level to high level.

In step S 2204 , the control circuit 1801 measures the rising time Δta from time t 1 to time t 4 . The flip flop circuits 631 to 635 each retain the value of the voltage /VAbp 3 at the time of rising of the voltages F 1 to F 5 . The flip flop circuits 631 and 632 retain a value “0”, and the flip flop circuits 633 to 635 retain a value “1”.

In step S 2205 , since the flip flop circuits 631 and 632 retain the value “0” and the flip flop circuits 633 to 635 retain the value “1”, the control circuit 1801 judges that the rising time Δta from time t 1 to time t 4 substantially matches the target time Δt 3 , and finishes the processing.

By the above processing, the number m of parallel connections of the p-channel field effect transistors 115 b is controlled so that the rising time Δta substantially matches the target time Δt 3 , enabling to achieve both high-speed driving and prevention of overshoot. The control circuit 1801 changes the size of the p-channel field effect transistors 115 b according to the rising time Δta from the time when the output voltage VAap of the comparison circuit 117 ap is inverted to the time when the output voltage VAbp of the comparison circuit 117 bp is inverted.

Next, in step S 2207 , the control circuit 1801 sets “0” to the control signal Sp so as to control the number k of parallel connections of p-channel field effect transistors 115 c . Then, the selector 1803 outputs the voltage /VAcp as the voltage P, and outputs the voltage /VAbp as the voltage Q. Further, the control circuit 1801 controls the number k of parallel connections of the p-channel field effect transistors 115 c to be the maximum value.

Next, in step S 2208 , a voltage falling from a value “1” to a value “0” is inputted to the input terminal IN. Then, the first driver circuit 101 outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT. The voltage of the output terminal OUT becomes a voltage rising from a value “0” to a value “1”.

In step S 2209 , the control circuit 1801 measures the rising time Δtb. The flip flop circuits 631 to 635 each retain a value of the voltage /VAcp at the time of rising of the voltages F 1 to F 5 . The voltages F 1 to F 5 are delayed voltages of the voltage /VAbp.

In step S 2210 , similarly to step S 2205 , the control circuit 1801 judges whether the rising time Δ tb matches the target time or not. When the rising time Δtb is shorter than the target time, the control circuit 1801 proceeds to step S 2211 . In step S 2211 , the control circuit 1801 controls the number k of p-channel field effect transistors 115 c to decrease by 1. Thereafter, the control circuit 1801 returns to step S 2208 .

In step S 2210 , when the rising time Δtb substantially matches the target time, the processing is finished. By the above processing, the number k of parallel connections of the p-channel field effect transistors 115 c is controlled so that the rising time Δtb substantially matches the target time, enabling to achieve both high-speed driving and prevention of overshoot. The control circuit 1801 changes the size of the p-channel field effect transistors 115 c according to the rising time Δtb from the time when the output voltage VAbp of the comparison circuit 117 bp is inverted to the time when the output voltage VAcp of the comparison circuit 117 cp is inverted.

FIG. 24 is a flowchart illustrating a processing example in which the output circuit controls the number j of parallel connections of the n-channel field effect transistors 116 a and the number n of parallel connections of the n-channel field effect transistors 116 b , and FIG. 25 is a timing chart illustrating a processing example of the output circuit.

In step S 2401 , the control circuit 1801 sets target times of falling times Δtc and Δtd. For example, it sets the target time of falling time Δtc to Δt 3 .

Next, in step S 2402 , the control circuit 1801 sets “1” to the control signal Sn so as to control the number n of parallel connections of n-channel field effect transistors 116 b . Then, the selector 1803 outputs the voltage VAbn as the voltage P, and outputs the voltage VAcn as the voltage Q. Further, the control circuit 1801 controls the number n of parallel connections of the n-channel field effect transistors 116 b to be the maximum value.

Next, in step S 2403 , a voltage rising from a value “0” to a value “1” is inputted to the input terminal IN. Then, the first driver circuit 101 outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT. The voltage of the output terminal OUT becomes a voltage falling from a value “1” to a value “0”.

Here, a voltage OUT 1 is the voltage of the output terminal OUT at a time of first loop processing of steps S 2403 to S 2405 . A voltage OUT 2 is the voltage of the output terminal OUT at a time of second loop processing of steps S 2403 to S 2405 . A voltage OUT 3 is the voltage of the output terminal OUT at a time of third loop processing of steps S 2403 to S 2405 .

Further, a voltage VAbn 1 is the voltage VAbn at a time of first loop processing of steps S 2403 to S 2405 . A voltage VAbn 2 is the voltage VAbn at a time of second loop processing of steps S 2403 to S 2405 . A voltage VAbn 3 is the voltage VAbn at a time of third loop processing of steps S 2403 to S 2405 .

In the first loop processing, the voltage OUT 1 and the voltage VAbn 1 will be explained. At time t 1 , the voltage OUT 1 becomes lower than the third reference voltage V 3 , and thus the voltage VAcn rises from low level to high level. The voltage F 1 is a delayed voltage of the voltage VAcn. The voltage F 2 is a delayed voltage of the voltage F 1 . The voltage F 3 is a delayed voltage of the voltage F 2 . The voltage F 4 is a delayed voltage of the voltage F 3 . The voltage F 5 is a delayed voltage of the voltage F 4 . At time t 2 , the voltage OUT 1 becomes lower than the second reference voltage V 2 , and thus the voltage VAbn 1 rises from low level to high level.

In step S 2404 , the control circuit 1801 measures the falling time Δtc from time t 1 to time t 2 . The flip flop circuits 631 to 635 each retain a value “1” of the voltage VAbn 1 at the time of rising of the voltages F 1 to F 5 .

In step S 2405 , the control circuit 1801 judges whether the falling time Δtc from time t 1 to time t 2 matches the target time Δt 3 or not. Specifically, since the values retained in the flip flop circuits 631 to 635 are all “1”, the control circuit 1801 judges that the falling time Δtc from time t 1 to time t 2 is shorter than the target time Δ t 3 , and proceeds to step S 2406 .

In step S 2406 , the control circuit 1801 controls the number n of parallel connections of the n-channel field effect transistors 116 b to decrease by 1. Thereafter, the control circuit 1801 returns to step S 2403 , and performs the second loop processing.

In step S 2403 , the rising voltage is inputted again to the input terminal IN. In this case, the voltage of the output terminal OUT is the voltage OUT 2 , and the voltage VAbn is the voltage VAbn 2 . At time t 1 , the voltage OUT 2 becomes lower than the third reference voltage V 3 , and thus the voltage VAcn rises from low level to high level. At time t 3 , the voltage OUT 2 becomes lower than the second reference voltage V 2 , and thus the voltage VAbn 2 rises from low level to high level.

In step S 2404 , the control circuit 1801 measures the falling time Δtc from time t 1 to time t 3 . The flip flop circuits 631 to 635 each retain the value of the voltage VAbn 2 at the time of rising of the voltages F 1 to F 5 . The flip flop circuit 631 retains a value “0”, and the flip flop circuits 632 to 635 retain a value “1”.

In step S 2405 , since the flip flop circuit 631 retains the value “0” and the flip flop circuits 632 to 635 retain the value “1”, the control circuit 1801 judges that the falling time Δtc from time t 1 to time t 3 is shorter than the target time Δt 3 , and proceeds to step S 2406 .

In step S 2406 , the control circuit 1801 controls the number n of parallel connections of the n-channel field effect transistors 116 b to further decrease by 1. Thereafter, the control circuit 1801 returns to step S 2403 , and performs the third loop processing.

In step S 2403 , the rising voltage is inputted again to the input terminal IN. In this case, the voltage of the output terminal OUT is the voltage OUT 3 , and the voltage VAbn is the voltage VAbn 3 . At time t 1 , the voltage OUT 3 becomes lower than the third reference voltage V 3 , and thus the voltage VAcn rises from low level to high level. At time t 4 , the voltage OUT 3 becomes lower than the second reference voltage V 2 , and thus the voltage VAbn 3 rises from low level to high level.

In step S 2404 , the control circuit 1801 measures the falling time Δtc from time t 1 to time t 4 . The flip flop circuits 631 to 635 each retain the value of the voltage VAbn 3 at the time of rising of the voltages F 1 to F 5 . The flip flop circuits 631 and 632 retain a value “0”, and the flip flop circuits 633 to 635 retain a value “1”.

In step S 2405 , since the flip flop circuits 631 and 632 retain the value “0” and the flip flop circuits 633 to 635 retain the value “1”, the control circuit 1801 judges that the falling time Δtc from time t 1 to time t 4 substantially matches the target time Δt 3 , and finishes the processing.

By the above processing, the number n of parallel connections of the n-channel field effect transistors 116 b is controlled so that the falling time Δtc substantially matches the target time Δt 3 , enabling to achieve both high-speed driving and prevention of undershoot. The control circuit 1801 changes the size of the n-channel field effect transistors 116 b according to the falling time Δtc from the time when the output voltage VAcn of the comparison circuit 117 cn is inverted to the time when the output voltage VAbn of the comparison circuit 117 bn is inverted.

Next, in step S 2407 , the control circuit 1801 sets “0” to the control signal Sn so as to control the number j of parallel connections of n-channel field effect transistors 116 a . Then, the selector 1803 outputs the voltage VAan as the voltage P, and outputs the voltage VAbn as the voltage Q. Further, the control circuit 1801 controls the number j of parallel connections of the n-channel field effect transistors 116 a to be the maximum value.

Next, in step S 2408 , a voltage rising from a value “0” to a value “1” is inputted to the input terminal IN. Then, the first driver circuit 101 outputs a logically inverted voltage of the voltage of the input terminal IN to the output terminal OUT. The voltage of the output terminal OUT becomes a voltage falling from a value “1” to a value “0”.

In step S 2409 , the control circuit 1801 measures the falling time Δtd. The flip flop circuits 631 to 635 each retain a value of the voltage VAan at the time of rising of the voltages F 1 to F 5 . The voltages F 1 to F 5 are delayed voltages of the voltage VAbn.

In step S 2410 , similarly to step S 2405 , the control circuit 1801 judges whether the falling time Δtd matches the target time or not. When the falling time Δtd is shorter than the target time, the control circuit 1801 proceeds to step S 2411 . In step S 2411 , the control circuit 1801 controls the number j of n-channel field effect transistors 116 a to decrease by 1. Thereafter, the control circuit 1801 returns to step S 2408 .

In step S 2410 , when the falling time Δtd substantially matches the target time, the processing is finished. By the above processing, the number j of parallel connections of the n-channel field effect transistors 116 a is controlled so that the falling time Δtd substantially matches the target time, enabling to achieve both high-speed driving and prevention of undershoot. The control circuit 1801 changes the size of the n-channel field effect transistors 116 a according to the falling time Δtd from the time when the output voltage VAbn of the comparison circuit 117 bn is inverted to the time when the output voltage VAan of the comparison circuit 117 an is inverted.

Sixth Embodiment

FIG. 26 is a diagram illustrating a configuration example of an integrated circuit 2600 according to a sixth embodiment. The integrated circuit 2600 has a data generation circuit 2601 , a parallel-serial converter 2602 , a central processing unit (CPU) 2603 , a bus 2604 and a plurality of output circuits 2605 . The plurality of output circuits 2605 correspond to the output circuit of any one of the first to fifth embodiments. The central processing unit 2603 controls the plurality of output circuits 2605 via the bus 2604 . The data generation circuit 2601 generates data. The parallel-serial converter 2602 converts the data generated by the data generation circuit 2601 from a parallel format to a serial format, and outputs a plurality of serial data to each of the plurality of output circuits 2605 . The plurality of output circuits 2605 each adjust a voltage waveform of data inputted from the parallel-serial converter 2602 as in the first to fifth embodiments, and outputs data in which an overshoot and an undershoot are prevented.

It should be noted that the above embodiments merely illustrate specific examples for carrying out the present invention, and the technical scope of the invention should not be construed as limited by these embodiments. That is, the invention may be implemented in various forms without departing from the technical spirit or main features thereof.

By providing the first and second driver circuits, driving speed can be made high, and an overshoot or an undershoot of an output voltage can be prevented with high accuracy.

All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.