Signal analysis circuit and signal analysis method thereof

This application claims priority to China Application Serial Number 201410781165.7, filed Dec. 16, 2014, the entirety of which is herein incorporated by reference.

The disclosure relates to a signal analysis circuit and a signal analysis method thereof.

With the development of the science technology, various signal transmission technologies are widely used in communication devices.

Generally, an electrical transmission line is used to transmit power and signals at the same time to reduce the cost and to save the space occupied by the lines. In the signal transmission technology, the signal analysis circuit analyzes out the signals from the electrical transmission line and provides the signals to a later digital processer. However, the signal analysis circuit is very complex to cause much space occupied to result in a high manufacture cost.

According to a first aspect of the present disclosure. A signal analysis circuit, comprises a peak detector configured to receive a first voltage signal and obtain a peak value of the first voltage signal to generate a second voltage signal; a subtraction amplifying unit configured to generate a compare voltage signal according to the second voltage signal, and amplifying a voltage value difference between the second voltage signal and the compare voltage signal to generate a third voltage signal, wherein a peak-to-peak value of the third voltage signal is larger than a peak-to-peak value of the second voltage signal; and a compare unit electrically connected to the subtraction amplifying unit and configured to compare a voltage value of the third voltage signal and a voltage value of the compare voltage signal to generate an output voltage signal.

Furthermore, according to a second aspect of the present disclosure. The signal analysis method includes following steps: obtaining a peak value of a first voltage signal by a peak detector to generate a second voltage signal; generating a compare voltage signal according to the second voltage signal; amplifying a voltage value difference between the second voltage signal and the compare voltage signal to generate a third voltage signal, wherein a peak-to-peak value of the third voltage signal is larger than a peak-to-peak value of the second voltage signal; and comparing a voltage value of the third voltage signal and a voltage value of the compare voltage signal to generate an output voltage signal.

FIG. 1 is a schematic diagram showing a signal analysis circuit in an embodiment;

FIG. 2 is a schematic diagram showing voltages of a signal analysis circuit in an embodiment;

FIG. 3 is a schematic diagram showing details of a signal analysis circuit in an embodiments, and

FIG. 4 is a flow chart showing a signal analysis method in an embodiment.

Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a schematic diagram showing a signal analysis circuit 100 in an embodiment, and FIG. 2 is a schematic diagram showing voltages of a signal analysis circuit 100 in an embodiment. In the embodiment, the signal analysis circuit 100 includes a rectifying unit 110 , a peak detector 120 , a buffer unit 130 , a subtraction amplifying unit 140 and a compare unit 150 . In the embodiment, the rectifying unit 110 is electrically connected to the peak detector 320 . The buffer unit 130 is electrically connected between the peak detector 120 and the subtraction amplifying unit 140 . The subtraction amplifying unit 140 is electrically connected to the compare unit 150 .

In an embodiment, the rectifying unit 110 receives an input signal VIN, and executes the voltage division and the half wave rectification on the input signal VIN to generate the first voltage signal V 1 . In the embodiment, the input signal VIN is an alternating current (AC) signal with binary signals for a high frequency wave signal with low frequency square wave signals as shown in FIG. 2 ), which is not limited herein. In other embodiments, the input signal VIN is a square wave signal. In an embodiment, the rectifying unit 110 is omitted.

In the embodiment, the peak detector 120 receives the first voltage signal V 1 , detects and obtains a peak value of the first voltage signal V 1 to generate the second voltage signal V 2 .

In the embodiment, the buffer unit 130 isolates the subtraction amplifying unit 140 and the peak detector 120 to avoid a load effect on the peak detector 120 from the subtraction amplifying unit 140 . In an embodiment, the buffer unit 130 is omitted.

In the embodiment, the subtraction amplifying unit 140 receives the second voltage signal V 2 , generates the compare voltage signal VCM according to the second voltage signal V 2 , and amplifies the voltage value difference between the second voltage signal V 2 and the compare voltage signal VCM to generate the third voltage signal V 3 .

In an embodiment, the subtraction amplifying unit 140 executes the low pass filtering to the second voltage signal V 2 to generate the compare voltage signal VCM. The difference between the high voltage level part HV and the low voltage level part LV of the third voltage signal V 3 becomes larger by amplifying the voltage value difference between the second voltage signal V 2 and the compare voltage signal VCM, which benefits the subsequent analysis.

In an embodiment, the peak-to-peak value L 2 of the third voltage signal V 3 is larger than the peak-to-peak value L 1 of the second voltage signal V 2 .

In the embodiment, the compare unit 150 receives the third voltage signal V 3 and the compare voltage signal VCM, and compares the voltage value of the third voltage signal V 3 and that of the compare voltage signal VCM to generate the output voltage signal VOUT. In an embodiment, the output voltage signal VOUT is a square wave signal. When the voltage value of the compare voltage signal VCM is larger than that of the third voltage signal V 3 , the output voltage signal VOUT has a low voltage level, and when the compare voltage signal VCM is smaller than the third voltage signal V 3 , the output voltage signal VOUT has a high voltage level.

As stated above, the input signal VIN is converted to the output voltage signal VOUT in square waveforms, and the subsequent digital processor operates according to the output voltage signal VOUT.

FIG. 3 is a schematic diagram showing details of the signal analysis circuit 100 in an embodiment.

In the embodiment, the rectifying unit 110 includes a diode D 1 and the resistors R 1 and R 2 . The anode of the diode D 1 receives the input signal VIN. The cathode of the diode D 1 is electrically connected to one end of the resistor R 1 . The other end of the resistor R 1 is electrically connected to the node with the first voltage signal V 1 , and connected to the ground via the resistor R 2 .

The rectifying unit 110 rectifies the input signal VIN via the diode D 1 , and the rectifying unit 110 divides the voltage of the input signal VIN via the resistors R 1 and R 2 to generate the first voltage signal V 1 .

In the embodiment, the peak detector 120 includes the operation amplifier OP 1 , the diode D 2 , the resistor R 3 and the capacitor C 1 . The first input end of the operation amplifier OP 1 receives the first voltage signal V 1 , the second input end of the operation amplifier OP 1 is electrically connected to the node with the second voltage signal V 2 . The output end of the operation amplifier OP 1 is electrically connected to the anode of the diode D 2 . The cathode of the diode D 2 is electrically connected to the node with the second voltage signal V 2 . The capacitor C 1 is electrically connected between the node with the second voltage signal V 2 and the ground. The resistor R 3 is electrically connected between the node with the second voltage signal V 2 and the ground, and the resistor R 3 is electrically connected to the capacitor C 1 in parallel. The peak detector 120 obtains the peak value of the first voltage signal V 1 via the capacitor C 1 to generate the second voltage signal V 2 .

In the embodiment, the buffer unit 130 includes the operation amplifiers OP 2 and OP 3 . Both the operation amplifiers OP 2 and OP 3 are follower amplifiers. The operation amplifiers OP 2 and OP 3 are electrically connected between the node with the second voltage signal V 2 and the subtraction amplifying unit 140 to avoid a load effect on the peak detector 120 from the subtraction amplifying unit 140 . In an embodiment, the follower amplifier of the operation amplifier OP 2 is omitted.

In the embodiment, the subtraction amplifying unit 140 includes the subtraction amplifier 142 and the low-pass filter 144 . The first input end of the subtraction amplifier 142 is electrically connected to the output end of the operation amplifier OP 2 to receive the second voltage signal V 2 . The second input end of the subtraction amplifier 142 is electrically connected to the node with the compare voltage signal VCM to receive the compare voltage signal VCM. The output end of the subtraction amplifier 142 is electrically connected to the node with the third voltage signal V 3 . The input end of the low-pass filter 144 receives the second voltage signal V 2 , and the output end of the low-pass filter 144 outputs the compare voltage signal VCM. The low-pass filter 144 executes the low pass filtering on the second voltage signal V 2 to generate the compare voltage signal VCM.

In the embodiment, the low-pass filter 144 includes the resistor R 6 and the capacitor C 2 . The resistor R 6 is electrically connected between the output end of the operation amplifier OP 3 and the node of the compare voltage signal VCM. The capacitor C 2 is electrically connected between the node with the compare voltage signal VCM and the around.

In the embodiment, the subtraction amplifier 142 includes the operation amplifier OP 4 and the resistors R 4 , R 5 , R 7 and R 8 . One end of the resistor R 4 is electrically connected to the output end of the operation amplifier OP 2 , and the other end of the resistor R 4 is connected to the ground via the resistor R 5 and electrically connected to the first input end of the operation amplifier OP 4 . The resistor R 7 is electrically connected between the node with the compare voltage signal VCM and the second input end of the operation amplifier OP 4 . The resistor R 8 is electrically connected between the second input end of the operation amplifier OP 4 and the output end.

The subtraction amplifying unit 140 generates the compare voltage signal VCM via the low-pass filter 144 . Thus, the subtraction amplifying unit 140 amplifies the voltage value difference between the compare voltage signal VCM and the second voltage signal V 2 via the subtraction amplifier 142 to generate the third voltage signal V 3 .

In the embodiment, the compare unit 150 includes the hysteresis comparator 152 and the resistor R 11 . The first input end of the hysteresis comparator 152 receives the third voltage signal V 3 , the second input end of the hysteresis comparator 152 receives the compare voltage signal VCM, and the output end of the hysteresis comparator 152 is electrically connected to the node with the output voltage signal VOUT. The resistor R 11 is electrically connected between a power source with the voltage level VDD and the node with the output voltage signal VOUT.

In detail, the hysteresis comparator 152 includes the comparator CMP and the resistors R 9 and R 10 . The first input end of the comparator CMP receives the third voltage signal V 3 , and the second input end of the comparator CMP is electrically connected to the node with the compare voltage signal VCM via the resistor R 9 , and the second input end of the comparator CMP is electrically connected between the output end of the comparator CMP and the node with the output voltage signal VOUT via the resistor R 10 .

The compare unit 150 compares the voltage value of the third voltage signal V 3 and the voltage value of the compare voltage signal VCM via the hysteresis comparator 152 , and a square wave whose amplitude is the voltage level VDD is generated as the output voltage signal VOUT according to a compare result.

In an embodiment, the resistors R 9 and R 10 are omitted, and the compare unit 150 uses the comparator CMP to compare the voltage values of the third voltage signal V 3 and the compare voltage signal VCM.

In an embodiment, the resistance of the resistor R 1 is 2 kΩ, the resistance of the resistor R 2 is 1 kΩ, the resistance of the resistor R 3 is 150 kΩ, the resistance of the resistor R 4 is 10 kΩ, the resistance of the resistor R 5 is 100 kΩ, the resistance of the resistor R 6 is 1 kΩ, the resistance of the resistor R 7 is 10 kΩ, the resistance of the resistor R 8 is 100 kΩ, the resistance of the resistor R 9 is 100 kΩ, the resistance of the resistor R 10 is 100 kΩ, and the resistance of the resistor R 11 is 10 kΩ. The capacitance of the capacitor C 1 is 47 μF, and the capacitance of the capacitor C 2 is 22 μF. The values are not limited herein.

In an embodiment, the amplifiers OP 1 to OP 4 are integrated to one chip, which is not limited herein.

The signal analysis circuit 100 is achieved via simple components to convert the input signal VIN to the output voltage signal VOUT, and the subsequent digital processor operates according to the output voltage signal VOUT.

FIG. 4 is a flow chart showing, a signal analysis method 200 in an embodiment. The signal analysis method 200 is applied to the signal analysis circuit 100 in FIG. 1 , which is not limited herein. The signal analysis method 200 is illustrated with FIG. 1 in the following. The steps of the signal analysis method 200 do not have a specific sequence unless expressly stated. The steps can be executed at the same time, or the steps have overlaps on the operation time.

In the embodiment, the signal analysis method 200 includes following steps, which is not limited herein.

In the step S 1 , the peak detector 120 obtains the peak value of the first voltage signal V 1 generate the second voltage signal V 2 .

In the step S 2 , the subtraction amplifying unit 140 generates the compare voltage signal VCM according to the second voltage signal V 2 .

In the step S 3 , the subtraction amplifying unit 140 amplifies the voltage value difference between the second voltage signal V 2 and the compare voltage signal VCM to generate the third voltage signal V 3 .

In the step S 4 , the compare unit 150 compares the voltage values of the third voltage signal V 3 and the compare voltage signal VCM to generate the output voltage signal VOUT. In an embodiment, when the voltage value of the third voltage signal V 3 is larger than that of the compare voltage signal VCM, the output voltage signal VOUT has a first level and when the voltage value of the third voltage signal V 3 is smaller than that of the compare voltage signal VCM, the output voltage signal VCM has a second level. The second level is lower than the first level.

The details of the signal analysis method 200 can refer to the previous embodiments, which is omitted herein.

A signal analysis circuit is achieved to convert the first voltage signal to the output voltage signal, and the subsequent digital processor operates according the output voltage signal.