Driver circuit and switch driving method

The present disclosure generally relates to driver circuits. More particularly, the present disclosure relates to gate driver circuits and driving methods for use with switches.

The number of applications that make use of power metal-oxide-semiconductor field effect transistors (MOSFETs) or insulated gated bipolar transistors (IGBTs) has increased in recent years as a result of the technological maturity reached in the manufacture of these devices, but more importantly, as a result of their falling retail prices. For example, discrete silicon carbide power MOSFETs are now affordable, and they can now be used in power supplies of street luminaires, as they provide high voltage switching with negligible dynamic power dissipation due to the low leakage currents afforded by the wide bandgap of silicon carbide

Despite these advantages, several issues remain in integrating power MOSFETs in a wide variety of circuits. For example, in power supply applications, current driver circuits for operating power MOSFETS may output voltage levels that are lower in magnitude than those required to drive SiC power MOSFETs or IGBTs. Furthermore, as a result of threshold voltage drifts encountered in SiC devices, it may be necessary to turn off a SiC power MOSFETs using a negative voltage, a capability that is not currently offered by existing driver circuits.

The embodiments featured herein help solve or mitigate the above-noted issues as well as other issues known in the art. Particularly, in luminaires that make use of light-emitting diodes, LED drivers according to embodiments of the invention can make use of SiC MOSFETs driven with a voltage from 15-20V. Moreover, a negative bias can also be used at around −5V to turn-off the SiC MOSFETs, without running the risk of unwanted turn-ons or weak inversion, as a result of threshold voltage drift. Further, embodiments of the invention provide the same aforementioned capabilities to ballast and driver circuits that make use of IGBTs. In some embodiments, a microcontroller producing a 3.3. V signal, can be level shifted to 5V and used to drive a GaN power, concurrently with negative voltage (−2V) to turn off the GaN MOSFET. Furthermore, while the embodiments are described in the context of IGBTs and SiC MOSFETs for exemplary purposes, they can be used with any power transistor (MOSFET or BJT), such as for example, Gallium Nitride (GaN) MOSFETs. In the latter case, embodiments of the invention are especially useful in allowing operation in either an enhancement or a depletion mode, where providing a negative bias to the power MOSFET control terminal is required. For example, in such embodiments, a microcontroller can produce a 3.3. V signal, which is subsequently level shifted to 5V and used to drive a GaN power MOSFET; a negative voltage (e.g. −2V) can then be used to turn off the GaN power MOSFET.

In one exemplary embodiment, there is provided a driver circuit configured to receive a control signal and operate a power switch. The driver circuit includes a first switch, a second switch, and a capacitor coupled to control terminals of the first and second switches. The driver circuit further includes a first diode coupled to a first bias terminal of the driver circuit and to the capacitor. Furthermore, the driver circuit includes a second diode coupled to a second bias terminal of the driver circuit and to a terminal of the power switch.

In another exemplary embodiment, there is provided a method of operating a power switch. The method includes providing a level-shifted positive bias to a driver circuit of the power switch. Further, the method includes providing a negative bias to the driver circuit of the power switch. Furthermore, the method includes operating the power switch between a first rail substantially equal to the level-shifted positive bias and a second rail substantially equal to the negative bias.

In yet another exemplary embodiment, there is provided a ballast circuit that includes a power switch and a driver circuit configured to operate the power switch. The driver circuit may include a first switch, a second switch, and a capacitor coupled to control terminals of the first and second switches. The driver circuit may further include a first diode coupled to a first bias terminal of the driver circuit and to the capacitor. Furthermore, the driver circuit may include a second diode coupled to a second bias terminal of the driver circuit and to a terminal of the power switch.

Additional features, modes of operations, advantages, and other aspects of various embodiments are described below with reference to the accompanying drawings. It is noted that the present disclosure is not limited to the specific embodiments described herein. These embodiments are presented for illustrative purposes only. Additional embodiments, or modifications of the embodiments disclosed, will be readily apparent to persons skilled in the relevant art(s) based on the teachings provided.

Illustrative embodiments may take form in various components and arrangements of components. Illustrative embodiments are shown in the accompanying drawings, throughout which like reference numerals may indicate corresponding or similar parts in the various drawings. The drawings are only for purposes of illustrating the embodiments and are not to be construed as limiting the disclosure. Given the following enabling description of the drawings, the novel aspects of the present disclosure should become evident to a person of ordinary skill in the relevant art(s).

FIG. 1 is an illustration of a driver circuit, according to an embodiment.

FIG. 2 is an illustration of a driver circuit, according to another embodiment.

FIG. 3 is an illustration of a driver circuit, according to yet another embodiment.

FIG. 4 is an illustration of a method, according to an embodiment.

While the illustrative embodiments are described herein for particular applications, it should be understood that the present disclosure is not limited thereto. Those skilled in the art and with access to the teachings provided herein will recognize additional applications, modifications, and embodiments within the scope thereof and additional fields in which the present disclosure would be of significant utility.

FIG. 1 is an illustration of a driver circuit 100 , according to an embodiment. Driver circuit 100 includes diodes D 1 , D 2 , and D 3 , capacitors C 1 , C 2 , and C 3 , and resistors R 3 and R 4 . Driver circuit 100 further includes switches M 1 and M 2 , which form a complementary pair 101 . M 2 is a p-channel MOSFET whereas M 1 is a n-channel MOSFET. Furthermore, driver circuit 100 includes a low voltage bias input terminal I 1 at which a low voltage bias V 1 can be applied. Furthermore, driver circuit 100 includes a high voltage output terminal O 1 at which a voltage VH is outputted. As explained below, VH is a level-shifted version of V 1 . In some embodiment, VH may be substantially twice the value of V 1 . Driver circuit 100 further includes an input terminal 13 where a logic drive voltage V 2 can be applied from a control circuit (not shown) or supplied through port Y 1 . Logic drive voltage V 2 can be a digital signal that controls complementary pair 101 .

In other embodiments, VH may be a voltage that is “n” times the value of V 1 , where “n” is a positive real number greater than 1. Furthermore, in some embodiments, driver circuit 100 may include a programmable controller that is configured to output a predetermined value of VH based on pre-programmed values of the parameter “n.”

Driver circuit 100 can be interfaced at the output node of complementary pair 101 to a power MOSFET M 3 (as depicted in FIG. 1 ). Without loss of generality, driver circuit 100 can also be interfaced with an IGBT instead of a power MOSFET. During operation, the leakage current of diode D 1 allows capacitor C 2 to charge to a differential voltage equal to the difference between VH and the logic drive voltage V 2 , which controls complementary pair 101 , and consequently, the switching behavior of power MOSFET M 3 .

Diodes D 2 and D 3 and capacitors C 1 and C 3 essentially add to voltage V 1 , thus shifting it to a higher level. In the embodiment shown in FIG. 1 , diodes D 2 and D 3 and capacitors C 1 and C 3 cooperatively function to double voltage V 1 , yielding VH at output terminal O 1 . For example, if V 1 is +12V, VH will be approximately +24V. While driver circuit 100 is implemented using a voltage double network (D 2 , D 3 , C 1 , and C 3 ), any charge pumping architecture or level shifting architecture can be used to obtain a predetermined output voltage VH. For example, additional diodes, or larger capacitances can be used to control voltage VH and obtain a desired multiplied version of low bias voltage V 1 .

The high voltage VH allows the gate of M 3 to be driven with a higher positive voltage (i.e. higher than V 1 ). As such, this is done without the need of a separate auxiliary voltage source. Further, while driver circuit 100 can effectively interface with a power MOSFET requiring only high positive voltages, it must be modified to allow interfacing with SiC power MOSFETs or with IGBTs. Specifically, even though driver 100 circuit provides a high voltage for the ON state of the M 3 , in its OFF-state it still drives the gate of M 3 to zero. As explained above, with any variation in threshold, transistor M 3 may leave the cut-off region and enter weak inversion, thereby causing increased leakage currents and undesired current delivery to a load coupled to M 3 .

As such, a negative voltage source capable of providing a negative turn-off bias to transistor M 3 must be included in driver circuit 100 . This is shown conceptually in FIG. 2 , which depicts a driver circuit 200 that is a partial and modified version of driver circuit 100 .

In driver circuit 200 , VH is generated using a level shifting network like the one described with respect to driver circuit 100 . Logic voltage V 2 drives the complementary pair formed by M 2 and M 1 , and like in driver circuit 100 , the leakage current through diode D 1 charges capacitor C 2 , which effectively sets the drive voltage of the complementary pair as a differential voltage given by the difference of VH and V 2 . Driver circuit 200 , unlike driver circuit 100 , includes an additional voltage source V 3 tied to the source of M 1 . As such, when the complementary pair given by M 1 and M 2 is switching, it does so between VH and V 3 . V 3 can be set below zero to ensure that the gate of power transistor of M 3 is held at a negative potential when in the OFF state.

FIG. 3 is an implementation of a driver circuit 300 , according to an embodiment. Unlike driver circuit 200 , driver circuit 300 accomplishes positive bias level shifting and negative bias generation without increasing the voltage across terminals of the complementary pair formed by M 1 and M 2 beyond a voltage difference equal to VH. In other words, while the embodiment of driver circuit 200 made use of an auxiliary voltage source at the source of M 1 , which sets the voltage across the complementary pair at VH plus the absolute value of V 3 , driver circuit 300 provides the negative bias needed without using an auxiliary voltage source on the source of M 1 . This is done to avoid subjecting M 1 and M 2 to large voltages, as these switches are typically low-voltage rated devices (i.e. CMOS devices). As such, in driver circuit 300 , M 2 and M 1 are switched between VH and ground, while the negative voltage V 3 is provided across a capacitor C 5 and a Zener diode D 4 . Driver circuit 300 interfaces with an IGBT M 5 , whose gate and emitters are tied to the output node of the complementary pair formed by M 2 and M 1 , which forces the gate of M 5 to switch on at VH, and to C 5 , which forces the gate of M 5 to switch off at V 3 , wherein V 3 is a negative voltage.

It is noted that in the case of FIG. 1 , FIG. 2 , and FIG. 3 , each of the driver circuits 100 , 200 , 300 , when taken together with the power transistor they drive, form a ballast circuit, which can be used to drive LED banks in a luminaire. In other applications, the disclosed ballast circuits can also serve as an input stage in a power converter.

Having set forth the structure of the various embodiments, a method consistent with the operation of the embodiments is now provided. FIG. 4 shows a method 400 of operating a power switch. The power switch can be a power transistor such as a SiC MOSFET, a GaN MOSFET, or an IGBT, or any other power transistor or the like. Method 400 can include providing a level-shifted positive bias to a driver circuit of the power switch ( 401 ). Furthermore, method 400 can include providing a negative bias to the driver circuit of the power switch. Method 400 can further include providing a control signal ( 403 ) which governs the operation of the power switch (such as the differential voltage at the input stage of the complementary switch pair formed by switches M 1 and M 2 in FIGS. 1-3 ). Method 400 can further include operating the power switch between a first rail substantially equal to the level-shifted positive bias and a second rail given substantially equal to the negative bias ( 405 ).

As described in references to FIGS. 2-3 , the level-shifted positive bias can be VH and the negative bias V 3 . Method 400 can include doubling a positive bias (such as V 1 in FIG. 1 ) to obtain the level-shifted bias VH. Furthermore, in method 400 , operating the power switch can include setting the voltage at a control terminal of the power switch below zero in its OFF state during a particular switching cycle.

Those skilled in the relevant art(s) will appreciate that various adaptations and modifications of the embodiments described above can be configured without departing from the scope and spirit of the disclosure. Therefore, it is to be understood that, within the scope of the appended claims, the disclosure may be practiced other than as specifically described herein.