Layout modification method and system

With the continual scaling of feature size and the ever-expanding functionalities of chips, the critical pitch of Mid-end-of-line (MEOL) in a semiconductor chip is also reduced. To fabricate such a small critical pitch, a large number of photomasks, or more simply masks, are required during the fabrication. Moreover, when the layout area of a circuit cell in the chip shrinks, electrical characteristics, such as resistance, of elements in the circuit cell are more likely to deviate from the desired characteristics after fabrication. The area shrinkage also causes poor performance of the circuit cell in electromagnetic (EM) immunity.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flow chart of a design flow of an integrated circuit (IC) chip in accordance with some embodiments.

FIG. 2 is a flow diagram illustrating a layout modification method in accordance with some embodiments.

FIG. 3 is a schematic diagram of a circuit cell layout of a circuit cell on a layer of an integrated circuit in accordance with some embodiments.

FIG. 4 is a schematic diagram of a modified circuit cell layout of a circuit cell on a layer of an integrated circuit in accordance with some embodiments.

FIG. 5 is a schematic diagram of a modified circuit cell layout of a circuit cell on a layer of an integrated circuit in accordance with some embodiments.

FIG. 6 is a schematic diagram of a modified circuit cell layout of a vertical circuit cell on a layer of an integrated circuit in accordance with some embodiments.

FIG. 7 is a functional block diagram of a layout modification system in accordance with some embodiments.

FIG. 8 is a block diagram of a hardware system for implementing a layout modification method and a layout modification system in accordance with some embodiments.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, “lower”, “left”, “right” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.

FIG. 1 is a flow chart of a design flow 100 of an integrated circuit (IC) chip in accordance with some embodiments. The design flow 100 utilizes one or more electronic design automation (EDA) tools to carry out one or more operations in the design flow 100 .

At an IC design stage 102 , a high-level design of the IC chip is provided by a circuit designer. In some embodiments, a gate-level netlist is generated through logic synthesis based on the high-level design, and gates in the gate-level netlist are mapped to available cells in a standard cell library. The term “netlist” used herein refers to both a graphical-based representation, such as a schematic, and/or a text-based representation of a circuit.

At a floor planning stage 104 , the gate-level netlist is partitioned into functional blocks and a floorplan for the functional blocks in a design layout of the IC chip is created.

At a power planning stage 106 , power meshes such as a VDD power (e.g. the supply voltage) mesh and a VSS power (e.g. the ground voltage) mesh are routed. The power mesh includes several metal layers. Each metal layer includes power lines or power rails running, for example, horizontally or vertically. The metal layers are stacked such that any adjacent metal layers will have the power lines or power rails running in, for example, orthogonal directions.

At a placement stage 108 , mapped cells of logic gates and registers in the blocks are placed at specific locations in the design layout.

At a parasitic extraction and analysis stage 110 , the design layout, which includes the routing, is analyzed to extract the parasitics in the design layout and accordingly generate a physical netlist.

At a physical verification and signoff stage 112 , a layout-versus-schematic (LVS) is performed on a physical netlist generated from the design layout in order to ensure correspondence of the design layout to the gate-level netlist. Further, a design rule check (DRC) is performed on the design layout in order to ensure the design is cleared of, for example, electrical issues and lithographic issues for manufacturing. Incremental fixing can be performed to achieve a final signoff of the IC chip design before tape-out.

In the process of fabricating an IC, multi-patterning technology may overcome the distortion or deviation on the geometric physical layout when the layout is lithographed by a single mask having a high density of patterns. Generally speaking, the multi-patterning technology includes a process of sequentially using a plurality of different masks, which have different patterns formed thereon, to photolithograph their different features on a layer of the substrate. Therefore, the multi-patterning technology can produce a number of desired features in comparison to the single patterning technology. However, the large amount of mask consumption may directly increase the cost of the IC.

FIG. 2 is a flow diagram illustrating a layout modification method 200 in accordance with some embodiments. The layout modification method 200 may be applied to modifying the design layout of an integrated circuit (IC) so as to reduce the amount of mask consumption during the fabrication of the IC. In particular, the layout modification method 200 is applied to modifying the design layout of a plurality of specific layout segments of a circuit cell in the IC. The specific layout segment may be a via structure (hereinafter referred to as “via”) of the circuit cell. The vias may be the contact-via and/or gate-via of the circuit cell. In some embodiments, the layout modification method 200 may be performed in the floor planning stage 104 , the power planning stage 106 , and/or the placement stage 108 of the design flow 100 described and illustrated in FIG. 1 .

Referring to FIG. 2 , in operation 202 , a design layout of an integrated circuit is received.

In operation 204 , a plurality of layout segments of a circuit cell in the design layout is expanded and/or displayed. The plurality of layout segments comprises a plurality of specific layout segments of the circuit cell. The plurality of specific layout segments may be a plurality of contact-vias, a plurality of gate-vias, a plurality of sources/drains, and/or a plurality of gates. A gate-via may be electrically coupled or directly connected to a gate while a contact-via may be electrically coupled or directly connected to a diffusion region such as a source region or drain region. A gate may be the control terminal of a transistor, while a contact may be the source terminal or drain terminal of a transistor. If a contact-via is electrically coupled to a source terminal, the contact-via is a source-via. If a contact-via is electrically coupled to a drain terminal, the contact-via is a drain-via. In addition, the plurality of contact-vias and the plurality of gate-vias may be in the same layer of the design layout. In particular, the plurality of contact-vias and the plurality of gate-vias are located in the first layer of the design layout. In other words, the plurality of contact-vias and the plurality of gate-vias are the first level vias in the design layout. However, this is not a limitation of the present embodiments.

In operation 206 , allocation of the layout segments in the circuit cell layout is analyzed to, as will be further discussed in operations 2061 to 2064 , determine the positions of gate-vias and source-vias in the circuit cell, determine a line width of the power line in the circuit cell layout, determine if a gate-via and a source-via in the circuit cell layout can be merged, and determine a minimum distance between two vias in the circuit cell layout. In operation 206 , a plurality of gate-vias and source-vias near the cell boundary of the circuit cell are determined.

When the allocation of the layout segments is analyzed, a plurality of gate-vias and source-vias in the first layer of the circuit cell layout are first selected. Then, a cell boundary of the circuit cell layout is determined. In operation 2061 , the gate-vias and source-vias located near the cell boundary are selected, i.e. Criterion 1. Specifically, the layout modification method 200 , based on the distances between the cell boundary and each of the gate-vias and source-vias, determine which via is near the cell boundary. The distance may be measured from an edge of a via to the cell boundary or from the center of a via to the cell boundary. In some embodiments, when the distance between the cell boundary and a via falls within a distance range of about 0˜4 times that of a via width, such as 4 times, the via is regarded as one near the cell boundary. The via width may be the minimum via width in the circuit cell layout. However, this is not a limitation of the present embodiments.

In operation 2062 , the layout modification method 200 identifies the power line in the circuit cell layout, wherein the power line may be electrically coupled to a supply voltage or a ground voltage. Then, the layout modification method 200 measures the line width of the power line to determine if the line width falls within a width range, i.e. Criterion 2. In some embodiments, the width range may be 7.5˜10 times that of a via width, such as 8 times, of a via width or the minimum via width in the circuit cell layout. If the line width falls within the width range, the layout modification method 200 proceeds to operation 2063 . If the line width does not fall within the width range, the layout modification method 200 proceeds to operation 214 .

For some semiconductor manufacturing processes, the gate-via and the source-via of a transistor can be merged into a merged via structure while some semiconductor manufacturing processes do not provide such service. Therefore, in operation 2063 , the layout modification method 200 checks if a gate-via and a source-via in the circuit cell layout can be merged into a merged via structure during a semiconductor manufacturing process, i.e. Criterion 3. If the gate-via and the source-via can be merged, the layout modification method 200 proceeds to operation 2064 . If the gate-via and the source-via cannot be merged, the layout modification method 200 proceeds to operation 214 .

In operation 2064 , the layout modification method 200 checks if a minimum distance between two vias in the circuit cell layout falls within a predetermined distance range, i.e. Criterion 4. In some embodiments, the predetermined distance range may be about a summation of 0.5˜0.75 times that of a gate pitch and 0.85˜1.05 times that of a gate length in the circuit cell layout. The gate pitch may be the minimum gate pitch between two adjacent gate lines in the circuit cell layout. The gate length may be the minimum gate length of a gate line in the circuit cell layout. For example, the predetermined distance range may be a summation of 0.6 that times of the minimum gate pitch and 0.9 times that of the minimum gate length. However, this is not a limitation of the present embodiments. If the minimum distance between two vias falls within the predetermined distance range, the layout modification method 200 proceeds to operation 208 . If the minimum distance between two vias does not fall within the predetermined distance range, the layout modification method 200 proceeds to operation 214 .

In other words, if all Criteria 1-4 checks pass, the layout modification method 200 proceeds to operation 208 . If one of the Criteria 1-4 check fails, the layout modification method 200 proceeds to operation 214 .

In operation 208 , a vertical distance between two vias near the cell boundary is measured to determine if the vertical distance falls within a first distance range, i.e. Rule 1. In some embodiments, the first distance range may be about 4.5˜5.5 times that of a via width in the circuit cell layout. The via width may be the minimum via width in the circuit cell layout. For example, the first distance range may be about 5 times that of the minimum via width. The layout modification method 200 selects via pairs having vertical distances that fall within the first distance range and proceeds to operation 210 . If no vertical distance between two vias falls within the first distance range, the layout modification method 200 proceeds to operation 214 .

In other words, if Rule 1 check passes, the layout modification method 200 proceeds to operation 210 . If Rule 1 check fails, the layout modification method 200 proceeds to operation 214 .

In operation 210 , a horizontal distance between two vias near the cell boundary is measured to determine if the horizontal distance falls within a second distance range, i.e. Rule 2. In some embodiments, the second distance range may be about 6.5˜7.5 times that of a via width in the circuit cell layout. The via width may be the minimum via width in the circuit cell layout. For example, the first distance range may be about 7 times that of the minimum via width. The layout modification method 200 selects all via pairs having the horizontal distances falling within the second distance range and proceeds to operation 212 . If no horizontal distance between two vias falling within the second distance range, the layout modification method 200 proceeds to operation 214 .

In other words, if Rule 2 check passes, the layout modification method 200 proceeds to operation 212 . If Rule 2 check fails, the layout modification method 200 proceeds to operation 214 .

After the operations 208 and 210 , the via pairs, in which each via pair has a vertical distance falling within the first distance range and a horizontal distance falling within the second distance range, are obtained.

In operation 212 , an evaluation is performed upon each via pair obtained in operation 210 in order to determine if the via pair can be merged into a merged via structure. The evaluation includes determining if the via pair is electrically coupled to the same signal level, i.e. Rule A. The minimum distance between two patterns on a mask used for fabricating two vias of the circuit cell layout is also measured in operation 212 in order to determine if the minimum distance falls within a distance range, i.e. Rule B. In some embodiments, the distance range may be about a summation of 1.8˜2 times that of a gate pitch and 0.45˜0.6 times that of a gate length in the circuit cell layout. The gate pitch may be the minimum gate pitch between two adjacent gate lines in the circuit cell layout. The gate length may be the minimum gate length of a gate line in the circuit cell layout. For example, the distance range may be about a summation of 2 times that of the minimum gate pitch and 0.5 times that of the minimum gate length in the circuit cell layout. However, this is not a limitation of the present embodiments. If the via pair is electrically coupled to the same signal level and the minimum distance of the mask falls within the distance range, the layout modification method 200 merges the via pair into a merged via structure. If the via pair are not electrically coupled to the same signal level, the layout modification method 200 does not merge the via pair and keeps the via pair intact. Then, the layout modification method 200 proceeds to operation 208 to continue the checking process.

In other words, the layout modification method 200 checks Rule A and Rule B to selectively merge a via pair. If the via pair passes Rule A and Rule B checks, the layout modification method 200 merges the via pair. If the via pair does not pass Rule A or Rule B check, the layout modification method 200 keeps the via pair intact and checks the next via pair.

Accordingly, the layout modification method 200 iteratively performs the operations 208 - 212 to check and merge the via(s) near the cell boundary of the circuit cell layout until all appropriate vias are merged into a rail. When all vias near the cell boundary are checked and merged according to the rules in operations 206 - 212 , the layout modification method 200 proceeds to operation 214 .

In operation 214 , a modified circuit cell layout of the circuit cell is obtained, in which the vias conforming the rules in operations 206 - 212 are merged into a merged via structure or a rail.

According to the operations 202 - 214 , some of the vias in the circuit cell layout are merged into a merged via structure. The size of the merged via structure is larger than that of the individual via structure not merged. After the fabrication, the merged via structure performs better than the individual via structure yet to be merged. For example, the via resistance or the voltage drop (also known as IR drop) of the merged via structure is smaller than that of the unmerged via structure. Moreover, the process variation of the merged via structure is smaller than that of the unmerged via structure. Furthermore, the merged via structure also has better electromagnetic (EM) immunity.

In some embodiments, when all vias near the cell boundary are checked and merged according to the rules in operations 206 - 212 , the mask consumption during the fabrication of the circuit cell also reduces. FIG. 3 is a schematic diagram of a circuit cell layout 300 of a circuit cell on the first layer of an IC in accordance with some embodiments. For illustrative purpose, the circuit cell layout 300 may be a portion of a layout on the first layer of the IC. The circuit cell layout 300 comprises a plurality of layout segments. In some embodiments, the plurality of layout segments comprises a plurality of contact-vias S 1 -S 12 , a plurality of gate-vias S 13 -S 24 , a plurality of sources/drains S 25 -S 36 , and a plurality of gates S 37 ˜S 44 . The circuit cell comprises a P-type region 302 and an N-type region 304 . A first abutted cell 306 is adjacent to the P-type region 302 . A second abutted cell 308 is adjacent to the N-type region 304 . Accordingly, a first cell boundary 310 may be the boundary between the first abutted cell 306 and the P-type region 302 , and a second cell boundary 312 may be the boundary between the second abutted cell 308 and the N-type region 304 .

When the IC is fabricated under a semiconductor fabrication process, the spatial relationships among the plurality of contact-vias S 1 -S 12 and the plurality of gate-vias S 13 -S 24 should obey the multi-patterning layout rule when the plurality of contact-vias S 1 -S 12 and the plurality of gate-vias S 13 -S 24 are photolithographed by the multi-patterning technology. Basically, the multi-patterning technology is a technology using a plurality of masks to photolithograph the substrate of the wafer in succession for enhancing the feature density on a layer of the integrated circuit.

In some embodiments, for the circuit cell layout 300 prior to performing the layout modification method 200 , the mask count used for fabricating or photolithographing the plurality of contact-vias S 1 -S 12 and the plurality of gate-vias S 13 -S 24 of the circuit cell is eight (8). When the spatial relationships among the plurality of contact-vias S 1 -S 12 and the plurality of gate-vias S 13 -S 24 are analyzed, a plurality of indicating lines are shown on the circuit cell layout 300 . The bold dotted lines connect the plurality of contact-vias S 1 -S 12 , and the fine dotted lines connect the plurality of gate-vias S 13 -S 24 . Specifically, if two contact-vias are connected by a bold dotted line, the two contact-vias should not be photolithographed by the same mask. Further, if two gate-vias are connected by a fine dotted line, the two gate-vias should not be photolithographed by the same mask. Accordingly, to conform to the design rule of the multi-patterning photolithography, the contact-vias S 2 , S 5 , S 8 , and S 11 are photolithographed by a first mask. The contact-vias S 3 and S 9 are photolithographed by a second mask. The contact-vias S 1 , S 6 , S 7 , and S 12 are photolithographed by a third mask. The contact-vias S 4 and S 10 are photolithographed by a fourth mask. The gate-vias S 13 , S 19 , and S 23 are photolithographed by a fifth mask. The gate-vias S 14 , S 15 , 20 , and S 24 are photolithographed by a sixth mask. The gate-vias S 16 and S 21 are photolithographed by a seventh mask. The gate-vias S 17 , S 18 , and S 22 are photolithographed by an eighth mask.

Then, the circuit cell layout 300 can be modified by the layout modification method 200 to reduce the mask count. In operation 2061 , the distance between the cell boundaries 310 , 312 and the distance between each of the gate-vias S 13 -S 24 and contact-vias S 1 -S 12 are calculated to determine if the Criterion 1 is met. For brevity, it is assumed that the contact-vias S 1 -S 12 are source-vias. In some embodiments, the distances between the cell boundary 310 and the vias S 1 -S 4 , S 13 -S 17 fall within a distance range, such as 0˜4 times that of a via width Wvia. The distances between the cell boundary 312 and the vias S 9 -S 12 , S 20 -S 24 fall within the distance range. Therefore, the vias S 1 -S 4 , S 13 -S 17 , S 9 -S 12 , S 20 -S 24 are determined to be ones near the cell boundary of the circuit cell. The via width Wvia is the length of a side, but is not limited to, of the square via as shown in FIG. 3 .

In operation 2062 , a first power line 314 and a second power line 316 are identified. The first power line 314 and the second power line 316 may be disposed substantially above the vias S 1 -S 4 , S 13 -S 17 , S 9 -S 12 , S 20 -S 24 . Moreover, the line widths W 1 , W 2 of the power lines 314 , 316 are checked to determine if the Criterion 2 is met. In some embodiments, the line widths W 1 , W 2 of the power lines 314 , 316 fall within the width range of about 7.5˜10 times that of the via width Wvia.

In some embodiments, it is assumed that the Criterion 3 check passes in operation 2063 . This means the semiconductor manufacturing process used for fabricating the circuit cell layout 300 provides the service to merge a gate-via and a source-via into a merged via structure.

In operation 2064 , the minimum distance Pvia between two vias in the circuit cell layout 300 is measured to determine if the Criterion 4 check passes. The minimum distance Pvia is the center-to-center distance between a via and an adjacent via. However, this is not a limitation of the present embodiments. The minimum distance Pvia may be an edge-to-edge distance between a via and an adjacent via. In some embodiments, the minimum distance Pvia falls within the predetermined distance range of about a summation of 0.5˜0.75 times that of a gate pitch and 0.85˜1.05 times that of the minimum gate length Lg.

Then, in operation 208 , the vertical distances between two vias among the vias S 1 -S 4 , S 13 -S 17 , S 9 -S 12 , S 20 -S 24 are measured to determine if the Rule 1 check passes. For example, the vertical distance between the vias S 1 and S 15 is V 1 . The vertical distance V 1 is measured from an edge of the via S 1 to an edge of the via S 15 . However, this is not a limitation of the present embodiments. The vertical distance V 1 may be measured from the center of the via S 1 to the center of the via S 15 . When all the vertical distances between two vias are obtained, the layout modification method 200 can determine which via pair has a vertical distance that falls within the first distance range of about 4.5˜5.5 times that of the via width Wvia. In some embodiments, the vias S 1 -S 4 , S 13 -S 17 located at the upper side of the circuit cell layout 300 have vertical distances falling within the first distance range. The vias S 9 -S 12 , S 20 -S 24 located at the lower side of the circuit cell layout 300 have vertical distances falling within the first distance range.

Then, in operation 210 , the horizontal distances between two vias among the vias S 1 -S 4 , S 13 -S 17 , S 9 -S 12 , S 20 -S 24 are measured to determine if the Rule 2 check passes. For example, the horizontal distance between the vias S 1 and S 13 is H 1 . The horizontal distance H 1 is measured from an edge of the via S 1 to an edge of the via S 13 . However, this is not a limitation of the present embodiments. The horizontal distance H 1 may be measured from the center of the via S 1 to the center of the via S 13 . When all the horizontal distances between two vias are obtained, the layout modification method 200 can determine which via pair has a horizontal distance that falls within the second distance range of about 6.5˜7.5 times that of the via width Wvia. In some embodiments, for the upper side of the circuit cell layout 300 , the via pairs S 15 and S 1 , S 1 and S 13 , S 13 and S 3 , S 3 and S 16 , S 16 and S 2 , S 2 and S 14 , S 14 and S 4 , S 4 and S 17 have horizontal distances falling within the second distance range. For the lower side of the circuit cell layout 300 , the via pairs S 24 and S 11 , S 11 and S 23 , S 23 and S 9 , S 9 and S 21 , S 21 and S 12 , S 12 and S 24 , S 24 and S 10 , S 10 and S 22 have horizontal distances falling within the second distance range.

After operations 208 and 210 , the via pairs having vertical distances within the first distance range and having horizontal distances within the second distance range are obtained.

In operation 212 , for each via pair having a vertical distance within the first distance range and having a horizontal distance within the second distance range, the layout modification method 200 determines if the via pair is electrically coupled to the same signal level (i.e. Rule A), and determines if the distance between two via patterns on a mask used for fabricating the via pair falls within a distance range of about a summation of 1.8˜2 times that of the gate pitch Pgate and 0.45˜0.6 times that of the gate length Lg (i.e. Rule B). The gate pitch Pgate is measured from the center of a gate to the center of an adjacent gate. However, this is not a limitation of the present embodiments. The gate pitch Pgate may be measured from an edge of a gate to an edge of an adjacent gate. When the via pair passes the Rule A and Rule B checks, the via pair is merged into a merged via structure. In some embodiments, the vias pairs S 1 and S 13 , S 2 and S 14 , S 3 and S 16 , S 4 and S 17 , S 9 and S 21 , S 10 and S 22 , S 11 and S 23 , S 12 and S 24 pass the Rule A and Rule B checks. Therefore, the vias pairs S 1 and S 13 , S 2 and S 14 , S 3 and S 16 , S 4 and S 17 , S 9 and S 21 , S 10 and S 22 , S 11 and S 23 , S 12 and S 24 are merged into the merged via structures Sm 1 -Sm 8 respectively as shown in FIG. 4 .

FIG. 4 is a schematic diagram of a modified circuit cell layout 400 of the circuit cell on the first layer of the IC in accordance with some embodiments. In some embodiments, when the vias pairs S 1 and S 13 , S 2 and S 14 , S 3 and S 16 , S 4 and S 17 , S 9 and S 21 , S 10 and S 22 , S 11 and S 23 , S 12 and S 24 in the circuit cell layout 300 are merged into the merged via structures Sm 1 -Sm 8 respectively, the mask count used for fabricating or photolithographing the vias S 5 -S 8 , S 15 , S 18 -S 20 , and Sm 1 -Sm 8 is reduced to six (6). When the spatial relationships among the vias S 5 -S 8 , S 15 , S 18 -S 20 , and Sm 1 -Sm 8 are analyzed, a plurality of indicating lines are shown on the circuit cell layout 400 . The bold dotted lines connect the plurality of vias S 5 -S 8 , and the fine dotted lines connect the plurality of vias S 15 , S 18 - 20 , Sm 1 -Sm 8 . It is noted that, for brevity, the other similar notations are omitted in FIG. 4 . Specifically, if two vias are connected by a bold dotted line, the two vias should not be photolithographed by the same mask. Moreover, if two vias are connected by a fine dotted line, the two vias should not be photolithographed by the same mask. Accordingly, to conform to the design rule of the multi-patterning photolithography, the vias S 5 and S 8 are photolithographed by a first mask. The vias S 6 and S 7 are photolithographed by a second mask. The vias Sm 1 , S 19 , and Sm 7 are photolithographed by a third mask. The vias Sm 3 and Sm 5 are photolithographed by a fourth mask. The vias Sm 2 and Sm 8 are photolithographed by a fifth mask. The vias S 15 , Sm 4 , S 20 , and Sm 6 are photolithographed by a sixth mask.

It is noted that when a first via and a second via are merged into a merged via structure, the original first and second vias (e.g. S 1 and S 13 ) may be located underneath the merged via structure (e.g. Sm 1 ), and the original first and second vias may not be seen from the top view of the circuit cell layout. Therefore, the vias pairs S 1 and S 13 , S 2 and S 14 , S 3 and S 16 , S 4 and S 17 , S 9 and S 21 , S 10 and S 22 , S 11 and S 23 , S 12 and S 24 are not shown in FIG. 4 . In other words, the merged via structure (e.g. Sm 1 ) may be regarded as a structure configured to electrically couple the first and second vias (e.g. S 1 and S 13 ).

Then, the circuit cell layout 400 can be modified by the operations 208 - 212 of the layout modification method 200 to further reduce the mask count. Similar to the circuit cell layout 300 , in operation 208 , the vertical distances between two vias among the vias S 5 -S 8 , S 15 , S 18 -S 20 , and Sm 1 -Sm 8 are measured.

Then, in operation 210 , the horizontal distances between two vias among the vias S 5 -S 8 , S 15 , S 18 -S 20 , and Sm 1 -Sm 8 are measured.

After operations 208 and 210 , the via pairs having vertical distances within the first distance range and having horizontal distances within the second distance range are obtained.

In operation 212 , for each via pair having a vertical distance within the first distance range and having a horizontal distance within the second distance range, the layout modification method 200 determines if the via pair follows the above mentioned Rule A and Rule B. If the via pair passes Rule A and Rule B checks, the via pair is merged into a merged via structure.

In some embodiments, the layout modification method 200 iteratively performs the operations 208 - 212 to check and merge the via(s) near the cell boundary of the circuit cell layout 400 until all candidate vias are merged into a rail as shown in FIG. 5 . FIG. 5 is a schematic diagram of a circuit cell layout 500 of the circuit cell on the first layer of the IC in accordance with some embodiments. Referring to FIG. 5 , the vias S 5 and Sm 1 -Sm 4 in the circuit cell layout 400 are merged into a first via rail (or simplified as a rail) Sr 1 , and the vias S 20 and Sm 5 -Sm 8 in the circuit cell layout 400 are merged into a second via rail Sr 2 . Accordingly, the mask count used for fabricating or photolithographing the vias S 5 -S 8 , S 18 -S 19 , Sr 1 , and Sr 2 is reduced to five (5). It is noted that, for brevity, other similar notations are omitted in FIG. 5 .

In particular, when the spatial relationships among the vias S 5 -S 8 , S 18 -S 19 , Sr 1 , and Sr 2 are analyzed, a plurality of indicating lines are shown on the circuit cell layout 500 . The bold dotted lines connect the plurality of vias S 5 -S 8 , and the fine dotted lines connect the plurality of vias S 18 -S 19 , Sr 1 , and Sr 2 . Specifically, if two vias are connected by a bold dotted line, the two vias should not be photolithographed by the same mask. Moreover, if two vias are connected by a fine dotted line, the two vias should not be photolithographed by the same mask. Accordingly, to conform to the design rule of the multi-patterning photolithography, the vias Sr 1 and Sr 2 are photolithographed by a first mask. The vias S 5 and S 8 are photolithographed by a second mask. The vias S 6 and S 7 are photolithographed by a third mask. The via S 19 is photolithographed by a fourth mask. The via S 18 is photolithographed by a fifth mask.

As a result, after the circuit cell layout 300 is processed by the layout modification method 200 , the vias S 1 -S 4 and S 13 -S 17 in the upper side of the circuit cell layout 300 are merged into the first via rail Sr 1 , and the vias S 9 -S 12 and S 20 -S 24 in the lower side of the circuit cell layout 300 are merged into the second via rail Sr 2 . Therefore, the layout modification method 200 may simplify the circuit cell layout of a circuit cell and reduce the mask count for fabricating the circuit cell. Moreover, the via rail Sr 1 (or Sr 2 ) has smaller via resistance and smaller process variation. The via rail Sr 1 (or Sr 2 ) also has better electromagnetic (EM) immunity.

It is noted that the above circuit cell layout 300 is the layout of a multi-gate device, but this is not a limitation of the present embodiments. The layout modification method 200 also has similar benefits when the layout modification method 200 is applied to the layout of a vertical device. FIG. 6 is a schematic diagram of a circuit cell layout 600 of a vertical circuit cell on the first layer of an IC in accordance with some embodiments. The circuit cell layout 600 has been modified by the layout modification method 200 . The vertical circuit cell comprises a P-type region 602 and an N-type region 604 . In some embodiments, the vias Sv 1 -Sv 4 located at the upper cell boundary of the circuit cell layout 600 are merged into a first via rail Svr 1 , and the vias Sv 5 -Sv 8 located at the lower cell boundary of the circuit cell layout 600 are merged into a second via rail Svr 2 . Therefore, when the spatial relationships among the first via rail Svr 1 , the second via rail Svr 2 , the plurality of contact-vias Sv 9 -Sv 16 , and the plurality of gate-vias Sv 17 -Sv 18 are analyzed, a plurality of indicating lines are shown on the circuit cell layout 600 . The bold dotted lines connect the plurality of contact-vias Sv 9 -Sv 16 and the plurality of gate-vias Sv 17 -Sv 20 . The fine dotted lines connect the first via rail Svr 1 , the second via rail Svr 2 , and the plurality of gate-vias Sv 17 -Sv 18 . Specifically, if two vias are connected by a bold dotted line, the two vias should not be photolithographed by the same mask. If two vias are connected by a fine dotted line, the two vias should not be photolithographed by the same mask. Accordingly, to conform to the design rule of the multi-patterning photolithography, the first via rail Svr 1 and the second via rail Svr 2 are photolithographed by a first mask. The contact-vias Sv 9 , Sv 11 , Sv 14 , and Sv 16 are photolithographed by a second mask. The contact-vias Sv 10 , Sv 12 , Sv 13 , and Sv 15 are photolithographed by a third mask. The gate-vias Sv 17 and Sv 19 are photolithographed by a fourth mask. The gate-vias Sv 18 and Sv 20 are photolithographed by a fifth mask. The operations to modify the circuit cell layout 600 are similar to the above operations performed upon the circuit cell layout 300 , and thus the detailed description is omitted here for brevity.

FIG. 7 is a functional block diagram of a layout modification system 700 in accordance with some embodiments. In some embodiments, the layout modification system 700 includes an allocation analysis tool 706 and a rule checking tool 708 . The space analysis tool 2406 receives a design layout 702 of an integrated circuit. The display tool 704 is configured to display the plurality of layout segments in the layer of the integrated circuit. The allocation analysis tool 706 is configured to perform the measurements in operations 2061 , 2062 , 2064 , 208 , 210 , and 212 . The allocation analysis tool 706 is configured to perform the measurements in operations 2061 , 2062 , 2064 , 208 , 210 , and 212 . The rule checking tool 708 is configured to perform the checks in operations 2061 , 2062 , 2063 , 2064 , 208 , 210 , and 212 . The display tool 704 is further configured to display the modified circuit cell layout of the integrated circuit.

FIG. 8 is a block diagram of a hardware system 800 for implementing the layout modification method described with reference to FIG. 2 and the layout modification system 700 described with reference to FIG. 7 , in accordance with some embodiments. The system 800 includes at least one processor 802 , a network interface 804 , an input and output (I/O) device 806 , a storage 808 , a memory 812 , and a bus 810 . The bus 810 couples the network interface 804 , the I/O device 806 , the storage 808 and the memory 812 to the processor 802 .

In some embodiments, the memory 812 comprises a random access memory (RAM) and/or other volatile storage device and/or read only memory (ROM) and/or other non-volatile storage device. The memory 812 includes user space 814 and a kernel 816 , configured to store program instructions to be executed by the processor 802 and data accessed by the program instructions.

In some embodiments, the network interface 804 is configured to access program instructions and data accessed by the program instructions stored remotely through a network. The I/O device 806 includes an input device and an output device configured for enabling user interaction with the system 800 . The input device comprises, for example, a keyboard, a mouse, etc. The output device comprises, for example, a display, a printer, etc. The storage device 808 is configured for storing program instructions and data accessed by the program instructions. The storage device 808 comprises, for example, a magnetic disk and an optical disk.

In some embodiments, for executing the program instructions, the processor 802 is configured to perform method embodiments described with reference to FIG. 2 and software system embodiments described with reference to FIG. 7 .

In some embodiments, the program instructions are stored in a non-transitory computer readable recording medium such as one or more optical disks, hard disks and non-volatile memory devices.

In some embodiments, a layout modification method performed by at least one processor is provided. The layout modification method comprises: analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments; determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; and merging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level.

In some embodiments, a circuit cell layout is provided. The circuit cell layout comprises a plurality of specific layout segments and a merged layout segment. The merged layout segment is disposed on a cell boundary of the circuit cell layout for electrically coupling a first specific layout segment and a second specific layout segment in the plurality of specific layout segments. The first specific layout segment and the second specific layout segment are coupled to a same signal level.

In some embodiments, a non-transitory computer-readable storage medium storing program instructions that when executed by a computer cause the computer to perform a layout modification method is provided. The layout modification method comprises: analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments; determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; and merging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.