Semiconductor device

The present invention relates to a semiconductor device for use in high-frequency amplification or the like.

Background Art

Japanese Patent Laid-Open No. H11-103205 discloses an input matching circuit connected to an FET (field-effect transistor). This input matching circuit is provided with a parallel resistor constituting a stabilization circuit.

To reduce unstable operation such as an oscillation, it is preferable to provide a stabilization circuit in a pre-matched circuit. It is preferable to provide a semiconductor device in which unstable operation can be reduced and which is suitable for miniaturization.

The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a semiconductor device in which unstable operation can be reduced and which is suitable for miniaturization.

The features and advantages of the present invention may be summarized as follows.

According to one aspect of the present invention, a semiconductor device includes a package, an input terminal fixed to the package, an input pre-matched substrate provided in the package, a semiconductor element provided in the package and formed on a substrate different from the input pre-matched substrate, a matching circuit including a circuit element formed on the input pre-matched substrate, a first wire for connecting the input terminal and the circuit element, and a second wire for connecting the circuit element and the semiconductor element, a first MIM capacitor formed as part of the circuit element, and a first stabilization circuit formed as part of the circuit element to reduce oscillation. A lower electrode of the first MIM capacitor is connected to the package through a via provided in the input pre-matched substrate.

Other and further objects, features and advantages of the invention will appear more fully from the following description.

FIG. 1 is a general view of a semiconductor device according to first embodiment;

FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1 ;

FIG. 3 is a diagram showing the inside of the package;

FIG. 4 is an equivalent circuit diagram of the semiconductor device according to first embodiment;

FIG. 5 is a plan view of a semiconductor device according to second embodiment;

FIG. 6 is an equivalent circuit diagram of the semiconductor device of FIG. 5 ;

FIG. 7 is a plan view of a semiconductor device according to third embodiment;

FIG. 8 is an equivalent circuit diagram of a semiconductor device of FIG. 7 ;

FIG. 9 is a plan view of a semiconductor device according to fourth embodiment;

FIG. 10 is an equivalent circuit diagram of the semiconductor device of FIG. 9 ;

FIG. 11 is a plan view of a semiconductor device according to fifth embodiment;

FIG. 12 is an equivalent circuit diagram of the semiconductor device of FIG. 11 ;

FIG. 13 is a plan view of a semiconductor device according to sixth embodiment;

FIG. 14 is an equivalent circuit diagram of the semiconductor device of FIG. 13 ;

FIG. 15 is a plan view of a semiconductor device according to seventh embodiment; and

FIG. 16 is an equivalent circuit diagram of the semiconductor device of FIG. 15 .

Semiconductor devices according to embodiments of the present invention will be described with reference to the drawings. The same or corresponding components will be denoted by the same reference signs, and the repetition of explanation thereof may be omitted.

First Embodiment

FIG. 1 is a general view of a semiconductor device according to first embodiment of the present invention. This semiconductor device includes an input terminal 10 , a package 12 , and an output terminal 14 . The input terminal 10 and the output terminal 14 are fixed to the package 12 . The internal configuration of the package 12 cannot be seen from the outside, but is represented by broken lines for convenience of explanation. An input pre-matched substrate P 1 is provided in the package 12 . Moreover, a semiconductor element T 1 formed on a substrate different from the input pre-matched substrate P 1 is provided in the package 12 . The semiconductor element T 1 is a field-effect transistor formed of, for example, GaN or the like.

The input terminal 10 and the input pre-matched substrate P 1 are connected to each other with first wires W 11 , W 12 , W 13 , and W 14 . The input pre-matched substrate P 1 and the semiconductor element T 1 are connected to each other with second wires W 21 , W 22 , W 23 , and W 24 . The semiconductor element T 1 and the output terminal 14 are connected to each other with output wires W 31 , W 32 , W 33 , and W 34 .

FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1 . The package 12 includes a metal base portion 12 a , a side wall portion 12 b , and a lid portion 12 c.

FIG. 3 is a diagram showing the inside of the package 12 . A circuit element 20 is formed on the input pre-matched substrate P 1 . The circuit element 20 , the first wires W 11 , W 12 , W 13 , and W 14 for connecting the input terminal 10 and the circuit element 20 (input pre-matched substrate P 1 ), and the second wires W 21 , W 22 , W 23 , and W 24 for connecting the circuit element 20 and the semiconductor element T 1 constitute a matching circuit.

The circuit element 20 includes a first MIM (Metal Insulator Metal) capacitor C 21 . The first MIM capacitor C 21 includes an upper electrode 30 , a lower electrode 32 , and a dielectric provided therebetween. The upper electrode 30 is connected to a first pad 22 . Portions of the lower electrode 32 which overlap the upper electrode 30 are represented by broken lines. The lower electrode 32 is connected to the package 12 through a via G 1 provided in the input pre-matched substrate P 1 . The via G 1 is formed by, for example, forming a through hole in the input pre-matched substrate P 1 and filling the through hole with a metallic material. Such a via may also be referred to as a via hole. The via G 1 may also be formed by plating. The first MIM capacitor C 21 serves as a shunt capacitor constituting a pre-matched circuit by being connected to the via G 1 .

A second MIM capacitor C 11 is formed on the input pre-matched substrate P 1 . The second MIM capacitor C 11 includes an upper electrode 30 , a lower electrode 34 , and a dielectric provided therebetween. The first MIM capacitor C 21 and the second MIM capacitor C 11 share the common upper electrode 30 . A first resistor R 11 contacts the upper electrode 30 on a left side thereof and contacts the lower electrode 34 on a right side thereof to be connected in parallel to the second MIM capacitor C 11 . The second MIM capacitor C 11 and the first resistor R 11 are collectively referred to as a first stabilization circuit.

The lower electrode 34 is connected to a pad 24 . The second wires W 21 , W 22 , W 23 , and W 24 connect the pad 24 and a gate of the semiconductor element T 1 . The output wires W 31 , W 32 , W 33 , and W 34 connect a drain of the semiconductor element T 1 and the output terminal 14 .

FIG. 4 is an equivalent circuit diagram of the semiconductor device according to first embodiment of the present invention. A capacitance C 21 ′ is a parasitic capacitance between the circuit element 20 and the package 12 .

The first MIM capacitor C 21 according to first embodiment of the present invention is connected to the package 12 (grounded) through the via G 1 . Accordingly, a shunt capacitor (first MIM capacitor C 21 ) can be easily formed on the input pre-matched substrate P 1 .

The second MIM capacitor C 11 and the first resistor R 11 constitute a first stabilization circuit. As the frequency of a signal propagating in the semiconductor device decreases, a signal passing through the second MIM capacitor C 11 decreases, and a signal passing through the first resistor R 11 increases. Accordingly, loss increases. Thus, the entire circuit becomes less likely to oscillate and becomes stable.

Since the first MIM capacitor C 21 and the first stabilization circuit are formed on the same substrate, the size of the semiconductor device can be made smaller than in the case where these are respectively formed on separate substrates. Moreover, forming the first MIM capacitor C 21 and the first stabilization circuit on the same substrate enables the parasitic capacitance C 21 ′ formed by the first MIM capacitor C 21 and the first stabilization circuit to be used as part of the matching circuit. Accordingly, the matching circuit can cover a wider bandwidth and can be made smaller.

Constants of the first stabilization circuit need to be optimized in accordance with a frequency band to be used. In first embodiment of the present invention, the first stabilization circuit is formed on the input pre-matched substrate P 1 , which is separate from the semiconductor element T 1 . Accordingly, a first stabilization circuit suitable for the frequency to be used can be provided without replacing the semiconductor element T 1 every time the frequency to be used is changed. In other words, the same semiconductor element T 1 can be used for semiconductor devices (amplifiers) of different frequency bands.

Since the first MIM capacitor C 21 and the second MIM capacitor C 11 have MIM structures, a desired capacitance value can be easily obtained without changing the structure, e.g., changing the substrate thickness.

The semiconductor device according to first embodiment of the present invention can be variously modified within a range in which features thereof are not lost. The same is true in embodiments below. It should be noted that for semiconductor devices according to the embodiments below, differences from first embodiment will be mainly described.

Second Embodiment

FIG. 5 is a plan view of a semiconductor device according to second embodiment. The first pad 22 is a pad for connecting the first wires W 11 , W 12 , W 13 , and W 14 which is formed on the input pre-matched substrate P 1 . A second resistor R 21 formed on the input pre-matched substrate P 1 is connected to the first pad 22 . An external capacitor C 31 is connected to the second resistor R 21 through a connecting inductor (wire) W 41 .

The external capacitor C 31 is provided in the package 12 . An upper electrode of the external capacitor C 31 is connected to the connecting inductor W 41 , and a lower electrode thereof is connected to the package 12 . The second resistor R 21 , the connecting inductor W 41 , and the external capacitor C 31 constitute a second stabilization circuit. The second stabilization circuit connects the first pad 22 and the package 12 .

FIG. 6 is an equivalent circuit diagram of the semiconductor device of FIG. 5 . In addition to the first stabilization circuit including the second MIM capacitor C 11 and the first resistor R 11 , the second stabilization circuit including the second resistor R 21 , the connecting inductor W 41 , and the external capacitor C 31 is provided.

The semiconductor device according to second embodiment of the present invention includes the first stabilization circuit (C 11 and R 11 ) and the second stabilization circuit (R 21 , W 41 , and C 31 ). Accordingly, a semiconductor device which is stable over a wide bandwidth can be obtained by configuring the semiconductor device such that effective frequencies of the first stabilization circuit and those of the second stabilization circuit are different from each other.

For example, in the circuit formed by the connecting inductor W 41 and the external capacitor C 31 , circuit constants are set so that resonance occurs at a low frequency. Near the frequency of resonance, impedances produced by the external capacitor C 31 and the connecting inductor W 41 are small, and only the second resistor R 21 is effective. Accordingly, the circuit can be stabilized in a low-frequency band.

To make the semiconductor device smaller than in the case of the configuration of FIG. 5 , the external capacitor C 31 can be formed on the input pre-matched substrate P 1 .

Third Embodiment

FIG. 7 is a plan view of a semiconductor device according to third embodiment. This semiconductor device is provided with four first MIM capacitors C 21 , C 22 , C 23 , and C 24 . Each of the first MIM capacitors C 21 , C 22 , C 23 , and C 24 individually has an upper electrode, a dielectric, and a lower electrode.

Each of the four first MIM capacitors C 21 , C 22 , C 23 , and C 24 individually has a first stabilization circuit connected thereto. In other words, there are four first stabilization circuits. Specifically, there are provided a first stabilization circuit including the first resistor R 11 and the second MIM capacitor C 11 , a first stabilization circuit including the first resistor R 12 and the second MIM capacitor C 12 , a first stabilization circuit including the first resistor R 13 and the second MIM capacitor C 13 , and a first stabilization circuit including the first resistor R 14 and the second MIM capacitor C 14 .

Thus, the semiconductor device according to third embodiment is equivalent to a semiconductor device obtained by dividing each of the first MIM capacitor and the first stabilization circuit of second embodiment into four parts. Further, the four first stabilization circuits are connected to each other with third resistors R 31 , R 32 , and R 33 . Specifically, a lower electrode of the second MIM capacitor C 11 and a lower electrode of the second MIM capacitor C 12 are connected to each other with the third resistor R 31 . Further, a lower electrode of the second MIM capacitor C 12 and a lower electrode of the second MIM capacitor C 13 are connected to each other with the third resistor R 32 . Moreover, a lower electrode of the second MIM capacitor C 13 and a lower electrode of the second MIM capacitor C 14 are connected to each other with the third resistor R 33 .

FIG. 8 is an equivalent circuit diagram of a semiconductor device of FIG. 7 . As can be seen in FIGS. 7 and 8 , one first MIM capacitor and one first stabilization circuit are assigned to one cell of the semiconductor element T 1 .

In the semiconductor device according to third embodiment of the present invention, a signal is transmitted through a plurality of first MIM capacitors and a plurality of first stabilization circuits, and the signal is evenly distributed to each cell in the semiconductor element T 1 . Accordingly, the semiconductor element T 1 can evenly operate. Further, since the third resistors R 31 , R 32 , and R 33 are provided between the pre-matched circuits, instability caused by imbalances between the cells can be reduced.

The number of first MIM capacitors may be any number greater than one, and is not limited to four. The number of first stabilization circuits may also be any number greater than one, and is not limited to four. The third resistors R 31 , R 32 , and R 33 may be omitted.

Fourth Embodiment

FIG. 9 is a plan view of a semiconductor device according to fourth embodiment. This semiconductor device have many things in common with the semiconductor device of third embodiment shown in FIG. 7 , and therefore differences from the semiconductor device of third embodiment will be mainly described.

Four first pads 22 are provided. The four first pads 22 are connected to each other with fourth resistors R 41 , R 42 , and R 43 . The four first pads 22 are connected to respective upper electrodes of the four first MIM capacitors C 21 , C 22 , C 23 , and C 24 .

A plurality of first patterns W 51 , W 52 , W 53 , and W 54 are formed on the input pre-matched substrate P 1 . The plurality of first patterns W 51 , W 52 , W 53 , and W 54 connect the first pads 22 and the second resistor R 21 . The lengths of the plurality of first patterns W 51 , W 52 , W 53 , and W 54 are equal. Moreover, the first patterns W 51 , W 52 , W 53 , and W 54 are joined together at one position on the input pre-matched substrate P 1 .

FIG. 10 is an equivalent circuit diagram of the semiconductor device of FIG. 9 . The second stabilization circuit includes the first patterns W 51 , W 52 , W 53 , and W 54 , the second resistor R 21 , the connecting inductor W 41 , and the external capacitor C 31 .

Since the electrical lengths of the first patterns W 51 , W 52 , W 53 , and W 54 are made equal, the impedances looking into the second stabilization circuit from the four pre-matched circuits (first MIM capacitors) are equal. Accordingly, the semiconductor device can be evenly operated. Moreover, since the first patterns W 51 , W 52 , W 53 , and W 54 are joined together on the input pre-matched substrate P 1 , the influence of assembly variation can be made small. Specifically, the length of the connecting inductor W 41 varies in accordance with the assembly variation of the input pre-matched substrate P 1 and the external capacitor C 31 , but such fluctuation does not occur in the first patterns W 51 , W 52 , W 53 , and W 54 .

The wire length of the connecting inductor W 41 can be made short by increasing the lengths of the first patterns W 51 , W 52 , W 53 , and W 54 to a certain extent. Accordingly, the semiconductor device of fourth embodiment is a semiconductor device suitable for miniaturization.

Further, since the fourth resistors R 41 , R 42 , and R 43 are provided, instability caused by imbalances between the cells of the semiconductor element T 1 can be reduced. However, the fourth resistors 41 , R 42 , and R 43 may be omitted if unnecessary.

Fifth Embodiment

FIG. 11 is a plan view of a semiconductor device according to fifth embodiment. This semiconductor device has many things in common with the semiconductor device of fourth embodiment shown in FIG. 9 , and therefore differences from the semiconductor device of fourth embodiment will be mainly described.

External capacitors C 41 , C 42 , C 43 , and C 44 are provided instead of the external capacitor C 31 of fourth embodiment. An upper electrode of the external capacitor C 41 is connected to the first pad 22 , and a lower electrode thereof is connected to the first pattern W 51 . Similarly, upper electrodes of the external capacitors C 42 , C 43 , and C 44 are respectively connected to the first pads 22 , and lower electrodes thereof are respectively connected to the first patterns W 52 , W 53 , and W 54 .

The connecting inductor W 41 is a wiring pattern provided on the input pre-matched substrate P 1 . This connecting inductor W 41 connects the second resistor R 21 and the via G 1 .

The second stabilization circuit includes the external capacitors C 41 , C 42 , C 43 , and C 44 , the first patterns W 51 , W 52 , W 53 , and W 54 , the second resistor R 21 , and the connecting inductor W 41 . This second stabilization circuit is connected to the package 12 through the vias G 1 . It should be noted that FIG. 12 is an equivalent circuit diagram of the semiconductor device of FIG. 11 .

Since the external capacitors C 41 , C 42 , C 43 , and C 44 of the second stabilization circuit are provided on the input pre-matched substrate P 1 , the connecting inductor W 41 does not need to be extended to the outside of the input pre-matched substrate P 1 and connected to a capacitor located outside the input pre-matched substrate P 1 . Accordingly, the number of components can be made smaller than that of the semiconductor device of fourth embodiment. Moreover, characteristic variation caused by assembly variation can be made small.

Sixth Embodiment

FIG. 13 is a plan view of a semiconductor device according to sixth embodiment. This semiconductor device has many things in common with the semiconductor device of third embodiment shown in FIG. 7 , and therefore differences from the semiconductor device of third embodiment will be mainly described.

An output pre-matched substrate P 2 is provided in the package. Second pads 40 are formed on the output pre-matched substrate P 2 . Further, an output-side circuit element is formed on the output pre-matched substrate P 2 . The output-side circuit element includes four structures. One structure includes an interconnection L 11 having one end connected to the second pad 40 , a resistor R 61 disposed at a position in the interconnection L 11 , a capacitor C 51 connected to other end of the interconnection L 11 , and output-side via G 2 connected to the capacitor C 51 . The capacitor C 51 is an MIM capacitor including an upper electrode connected to the interconnection L 11 , a lower electrode (diagonally shaded portion) connected to the output-side via G 2 , and a dielectric provided therebetween. The output-side via G 2 is a portion for electrically connecting the capacitor C 51 and the package.

While one structure of the output-side circuit element has been described, three other structures have structures similar to the above-described one. The three other structures include interconnections L 12 , L 13 , and L 14 , resistors R 62 , R 63 , and R 64 , capacitors C 52 , C 53 , and C 54 , and output-side vias. Thus, the output-side circuit element is connected to the package 12 through the output-side vias G 2 formed in the output pre-matched substrate P 2 .

Outputs (drains) of the semiconductor element T 1 are connected to the second pads 40 with third wires W 61 , W 62 , W 63 , and W 64 . Moreover, the drains of the semiconductor element T 1 are connected to the output terminal 14 with output wires W 31 , W 32 , W 33 , and W 34 . The plurality of second pads 40 are connected to each other with resistors R 51 , R 52 , and R 53 . An equivalent circuit diagram of the semiconductor device of FIG. 13 is shown in FIG. 14 .

Circuit constants of the third wires W 61 , W 62 , W 63 , and W 64 , the interconnections L 11 , L 12 , L 13 , and L 14 , and the capacitors C 51 , C 52 , C 53 , and C 54 are set so that resonance occurs in a range of frequencies lower than a desired frequency band (frequency band to be used). In a low-frequency range, loss is increased by the resistors R 61 , R 62 , R 63 , and R 64 , the semiconductor device becomes stable. Accordingly, instability caused by drain-side factors can be reduced. Moreover, the third wires W 61 , W 62 , W 63 , and W 64 and the aforementioned output-side circuit element act as shunt inductances at frequencies to be used, and therefore act as part of a matching circuit.

Seventh Embodiment

FIG. 15 is a plan view of a semiconductor device according to seventh embodiment. This semiconductor device has many things in common with the semiconductor device of third embodiment shown in FIG. 7 , and therefore differences from the semiconductor device of third embodiment will be mainly described.

Capacitors C 61 , C 62 , C 63 , and C 64 are formed on the input pre-matched substrate P 1 . Upper electrodes of the capacitors C 61 , C 62 , C 63 , and C 64 are connected to pads 42 . The pads 42 and inputs of the semiconductor element are connected to each other with wires W 71 , W 72 , W 73 , and W 74 . Lower electrodes (shaded portions) of the capacitors C 61 , C 62 , C 63 , and C 64 are connected to the vias G 1 .

FIG. 16 is an equivalent circuit diagram of the semiconductor device of FIG. 15 . The capacitors C 61 , C 62 , C 63 , and C 64 and the wires W 71 , W 72 , W 73 , and W 74 constitute harmonic circuits which are matching circuits for harmonics. The harmonic circuits connect the inputs of the semiconductor element T 1 and the vias G 1 , and function as matching circuits for harmonics. As can be seen in FIG. 15 , the harmonic circuit are formed for the cells of the semiconductor element T 1 .

Since the above-described harmonic circuits, the first MIM capacitors C 21 , C 22 , C 23 , and C 24 , and the first and second stabilization circuits are integrally formed on the input pre-matched substrate P 1 , the size of the semiconductor device can be reduced. Moreover, since the matching circuit and the harmonic circuit are integrated, a structure which is relatively immune to assembly variation is obtained.

Arranging the harmonic circuits and the matching circuits (circuit element 20 and the like) in a staggered manner in planar view improves the isolation between transistor cells. Accordingly, stable operation is expected. It should be noted that features of the semiconductor devices of the embodiments described above may be combined as appropriate.

In the present invention, a shunt capacitor connected to a via and a stabilization circuit are formed on an input pre-matched substrate. Accordingly, a semiconductor device in which unstable operation can be reduced and which is suitable for miniaturization can be provided.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.