Multilayer substrate, design method of multilayer substrate, manufacturing method of semiconductor device, and recording medium

This application is based upon and claims the benefit of priority from U.S. Provisional Application No. 62/149,982, filed on Apr. 20, 2015; the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a multilayer substrate, a design method of the multilayer substrate, a manufacturing method of a semiconductor device, and a recording medium.

In multilayer substrates, a signal layer including signal lines may be laid above a ground layer. In this case, it is desired to suppress degradation in electrical characteristics of the signal lines.

FIG. 1 is a plan view showing the configuration of a multilayer substrate according to a first embodiment;

FIG. 2A is an enlarged plan view of part A of FIG. 1 in the first embodiment;

FIG. 2B is a cross-sectional view taken along line B-B of FIG. 2A in the first embodiment;

FIG. 2C is a cross-sectional view taken along line C-C of FIG. 2A in the first embodiment;

FIG. 3 is a diagram showing the paths of a signal current and return currents in the first embodiment;

FIG. 4 is a plan view showing the configuration of a multilayer substrate according to a modified example of the first embodiment;

FIG. 5 is a diagram showing the paths of a signal current and return currents in a modified example of the first embodiment;

FIG. 6 is a plan view showing the configuration of a multilayer substrate according to a second embodiment;

FIG. 7 is a diagram showing the configuration of a computer which can execute a method of designing a multilayer substrate according to a third embodiment;

FIG. 8 is a flow chart showing the method of designing a multilayer substrate according to the third embodiment;

FIG. 9 is a diagram showing layout data of signal lines in the third embodiment;

FIG. 10 is a diagram showing layout data of a mesh ground in the third embodiment;

FIG. 11 is a diagram showing overlap areas between the signal lines and the mesh ground in the third embodiment;

FIG. 12 is a diagram showing overlap areas between the signal lines and the mesh ground after the mesh ground is moved in the third embodiment;

FIG. 13 is a flow chart showing a manufacturing method of a semiconductor device to which the method of designing a multilayer substrate according to the third embodiment is applied;

FIG. 14A is a diagram showing overlap areas between the signal lines and the mesh ground after a shift of the mesh ground (a shift of openings on a per column basis from among the multiple openings) in a modified example of the third embodiment;

FIG. 14B is a diagram showing overlap areas between the signal lines and the mesh ground after a shift of the mesh ground (a shift of openings on a per row basis from among the multiple openings) in a modified example of the third embodiment;

FIG. 15 is a diagram showing overlap areas between the signal lines and the mesh ground after a shift of a signal line in another modified example of the third embodiment; and

FIG. 16 is a flow chart showing a method of designing a multilayer substrate according to a fourth embodiment.

In general, according to one embodiment, there is provided a multilayer substrate including a ground layer and a signal layer. The ground layer includes a mesh ground having multiple openings. The signal layer is laid above the ground layer and including multiple signal lines. The multiple openings include first openings and second openings. The first openings overlap a first signal line from among the multiple signal lines when seen through in a direction perpendicular to a surface of the multilayer substrate. The second openings overlap the first signal line when seen through in the direction perpendicular to the surface of the multilayer substrate. The first openings have a first form, and the second openings have a second form different from the first form.

Exemplary embodiments of a multilayer substrate will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

First Embodiment

A multilayer substrate 1 according to the first embodiment will be described using FIGS. 1 to 2C . FIG. 1 is a plan view showing the configuration of the multilayer substrate 1 and illustrates part of the plan configuration of the multilayer substrate 1 seen from its surface 1 a side. FIG. 2A is an enlarged plan view of part A of FIG. 1 . FIG. 2B is a cross-sectional view taken along line B-B of FIG. 2A . FIG. 2C is a cross-sectional view taken along line C-C of FIG. 2A .

The multilayer substrate 1 has, for example, semiconductor chips (not shown) mounted thereon and can be formed as a semiconductor device (semiconductor package). The multilayer substrate 1 can function as a package substrate.

In the multilayer substrate 1 , as shown in FIGS. 2B, 2C , a signal layer 4 including multiple signal lines 4 a to 4 d may be laid above a ground layer 2 . In the multilayer substrate 1 , for example, an insulating layer 5 , the ground layer 2 , an insulating layer 3 , and the signal layer 4 may be laid one over another in that order. Although the multilayer substrate 1 can have more layers laid one over another, some layers laid one over another in the multilayer substrate 1 are shown in FIGS. 2B, 2C for simplicity of illustration.

A mesh ground 2 a is placed in the ground layer 2 . That is, if moisture stays in the multilayer substrate 1 , then the peeling of the films of the signal lines 4 a to 4 d may occur. Accordingly, moisture in the multilayer substrate 1 needs to be released to the outside, and the mesh ground 2 a having multiple openings 20 is provided to secure release paths. The mesh ground 2 a having rectangular openings 20 regularly arranged is provided in the ground layer 2 . By setting an average one among the respective largest widths of the openings 20 to be greater than or equal to a required size, the long-term reliability of the semiconductor device (semiconductor package) can be improved to be greater than or equal to a required level.

Each of the signal lines 4 a to 4 d is connected on one end side to a signal terminal of a semiconductor chip (not shown) and connected on the other end side to a terminal of a connector (not shown) that can connect to an external controller. That is, because of functioning as a bus line, the signal lines 4 a to 4 d are required to have substantially the same electrical characteristics (e.g., a high frequency characteristic). In this situation, it is desirable to shorten the path of a return current for a signal current flowing through each signal line 4 a to 4 d . Thus, it is desirable to place the signal lines 4 a to 4 d in such a way that the signal lines 4 a to 4 d do not overlap openings 20 of the mesh ground 2 a when seen through in a direction perpendicular to the surface 1 a of the multilayer substrate 1 .

However, as integrated circuits formed in semiconductor chips mounted on the multilayer substrate 1 become finer, the degrees of freedom in placement of the signal lines 4 a to 4 d and the degrees of freedom in placement of the mesh ground 2 a in the multilayer substrate 1 both become more likely to be restricted. Hence, it tends to be difficult to lay them out in such a way that the signal lines 4 a to 4 d do not overlap openings 20 of the mesh ground 2 a when seen through in a direction perpendicular to the surface 1 a of the multilayer substrate 1 .

If the signal lines 4 a to 4 d overlap openings 20 of the mesh ground 2 a when seen through in a direction perpendicular to the surface 1 a of the multilayer substrate 1 , then the path length of a return current flowing through the mesh ground 2 a is likely to be longer as compared with the path length of a signal current flowing through the signal line 4 a to 4 d . If the path length of the return current becomes longer as compared with the path length of the signal current, then the electrical characteristics (e.g., a high frequency characteristic) of the signal current flowing through the signal line 4 a to 4 d is likely to degrade. In this situation, the overlap area between each signal line 4 a to 4 d and openings 20 of the mesh ground 2 a , when seen through in a direction perpendicular to the surface 1 a of the multilayer substrate 1 , is likely to vary, so that the electrical characteristics (e.g., a high frequency characteristic) may vary between the signal lines 4 a to 4 d.

If variation in the electrical characteristics between the signal lines 4 a to 4 d increases, the signal line of the signal lines 4 a to 4 d which has degraded the most in characteristics determines the performance of the multilayer substrate 1 , so that the performance of the multilayer substrate 1 may be considerably restricted.

Accordingly, in the present embodiment, by implementing tactics in the form of openings overlapping signal lines of the signal lines 4 a to 4 d which are likely to degrade from among multiple openings 20 in the mesh ground 2 a , variation in the electrical characteristics between the signal lines 4 a to 4 d can be suppressed.

To be specific, as shown in FIG. 1 , where multiple openings 20 are arranged in a matrix in plan view, let X and Y directions be arrangement directions of the openings 20 and a Z direction be a direction perpendicular to the surface 1 a (see FIG. 2B ) of the multilayer substrate 1 . The X and Y directions are substantially perpendicular to each other in a plane substantially perpendicular to the Z direction. The multiple signal lines 4 a to 4 d are placed substantially parallel to each other in plan view. Suppose that it has been ascertained experimentally beforehand the electrical characteristics of which signal lines of the signal lines 4 a to 4 d are likely to degrade if the forms of the openings 20 are the same.

If the electrical characteristics of the signal lines 4 a , 4 d from among the signal lines 4 a to 4 d are likely to degrade, then the form of second openings 22 a , 22 d from among the multiple openings 20 is made different from the form of first openings 21 a , 21 b , 21 c correspondingly to the layout of the signal lines 4 a , 4 d.

That is, from among the multiple openings 20 , openings overlapping parts 4 a 1 , 4 d 1 of the signal lines 4 a , 4 d extending substantially parallel to either the X direction or the Y direction when seen through in a Z direction are referred to as second openings 22 a , 22 d , and the other openings are referred to as first openings 21 a , 21 b , 21 c.

Of the first openings 21 a , 21 b , 21 c , the first openings 21 a overlap parts 4 a 1 , 4 d 1 of the signal lines 4 a , 4 d extending substantially parallel to the X direction when seen through in a Z direction. The first openings 21 b overlap parts 4 a 2 to 4 d 2 of the signal lines 4 a to 4 d extending across both the X and Y directions when seen through in a Z direction. The first openings 21 c do not overlap the signal lines 4 a to 4 d when seen through in a Z direction.

The form (first form) of the first openings 21 a , 21 b , 21 c includes a substantially rectangular shape of outline, a first orientation with which a diagonal line of the first opening crosses both the X and Y directions, and a first largest width W 1 (see FIG. 2A ).

In contrast, the form (second form) of the second openings 22 a , 22 d includes a substantially rectangular shape of outline, a second orientation with which a diagonal line of the second opening is substantially parallel to either the X direction or the Y direction, and a second largest width W 2 (see FIG. 2A ). The second orientation is an orientation obtained by rotating the first orientation through about 45° around the Z axis. The second largest width W 2 is smaller than the first largest width W 1 so that the placement positions of the second openings 22 a , 22 d are level with the placement positions of the first openings 21 a , 21 b , 21 c . For example, the second largest width W 2 is smaller than the first largest width W 1 so that the X positions of the centers of the second openings 22 a , 22 d are substantially the same as the X positions of the centers of the first openings 21 a , 21 b , 21 c . The center of the first opening 21 a , 21 b , 21 c substantially coincides with the intersection of two diagonal lines of the first opening 21 a , 21 b , 21 c . The center of the second openings 22 a , 22 d substantially coincides with the intersection of two diagonal lines of the second openings 22 a , 22 d . Or, for example, the second largest width W 2 is smaller than the first largest width W 1 so that the width along the X direction of the second openings 22 a , 22 d is substantially the same as the width along the X direction of the first openings 21 a , 21 b , 21 c.

With the second form, the path from a point on the outline on the +X side of the center of the opening along the outline to a point on the outline on the −X side thereof is shorter in length than with the first form. That is, by providing the second openings 22 a , 22 d in the second form, the path lengths of return currents (indicated by broken-line arrows in FIG. 3 ) corresponding to the path lengths of signal currents (indicated by solid arrows in FIG. 3 ) flowing through the parts 4 a 1 , 4 d 1 of the signal lines 4 a , 4 d extending substantially parallel to either the X direction or the Y direction can be shortened as compared with the case of providing the second openings 22 a , 22 d in the first form. FIG. 3 is a diagram showing the paths of a signal current and return currents and is a plan view showing an area including the multiple second openings 22 a in FIG. 2A . Thus, the electrical characteristics of the signal lines 4 a , 4 d , which are likely to degrade in electrical characteristics, from among the multiple signal lines 4 a to 4 d can be selectively improved, so that variation in the electrical characteristics between the signal lines 4 a to 4 d can be suppressed.

It should be noted that the first largest width W 1 and the second largest width W 2 (see FIG. 2A ) are both decided on such that an average one among the largest widths of the openings 20 is greater than or equal to a required size. Therefore, the long-term reliability of the semiconductor device (semiconductor package) can be improved to be greater than or equal to a required level, and variation in the electrical characteristics between the signal lines 4 a to 4 d can be suppressed.

Note that the second form is not limited to the one illustrated in FIG. 1 as long as the path from a point on the outline on the +X side of the center of the opening along the outline to a point on the outline on the −X side thereof is shorter in length than with the first form.

For example, as shown in FIG. 4 , the outline of the opening may be different in shape between the second form and the first form. That is, the form (second form) of the second openings 22 a , 22 d includes a substantially circular shape of outline. A shape of outline in a polygon shape having, e.g., 16 or more corners can be regarded as a substantially circular shape of outline. In contrast, the form (first form) of the first openings 21 a , 21 b , 21 c includes a substantially rectangular shape of outline. In this case, the second largest width (the diameter of the substantially circular shape) included in the second form is smaller than the first largest width (the length of a longer one of two diagonal lines) included in the first form so that the placement positions of the second openings 22 a , 22 d are level with the placement positions of the first openings 21 a , 21 b , 21 c . For example, the second largest width (the diameter of the substantially circular shape) is smaller than the first largest width (the length of a diagonal line) so that the X positions of the centers of the second openings 22 a , 22 d are substantially the same as the X positions of the centers of the first openings 21 a , 21 b , 21 c . The center of the first opening 21 a , 21 b , 21 c substantially coincides with the intersection of two diagonal lines of the first opening 21 a , 21 b , 21 c . The center of the second opening 22 a , 22 d substantially coincides with the center of the substantially circular shape. Or, for example, the second largest width (the diameter of the substantially circular shape) is smaller than the first largest width (the length of a diagonal line) so that the width along the X direction of the second openings 22 a , 22 d are substantially the same as the width along the X direction of the first openings 21 a , 21 b , 21 c.

In this case, with the second form, the path from a point on the outline on the +X side of the center of the opening along the outline to a point on the outline on the −X side thereof is shorter in length than with the first form. FIG. 5 is a diagram showing the paths of a signal current and return currents and is a plan view showing an area including the multiple second openings 22 a in FIG. 4 . By providing the second openings 22 a , 22 d in the second form, the path lengths of return currents (indicated by broken-line arrows in FIG. 5 ) corresponding to the path lengths of signal currents (indicated by solid arrows in FIG. 5 ) flowing through the parts 4 a 1 , 4 d 1 of the signal lines 4 a , 4 d extending substantially parallel to either the X direction or the Y direction can be shortened as compared with the case of providing the second openings 22 a , 22 d in the first form.

Second Embodiment

Next, a multilayer substrate 200 according to the second embodiment will be described. Description will be made below focusing on the differences from the first embodiment.

In the first embodiment, with placement positions in a matrix as the base, by selectively making the form of some of the multiple openings different from that of the other openings, the suppression of variation in electrical characteristics between the multiple signal lines 4 a to 4 d is aimed at.

The second embodiment adopts placement positions in a staggered pattern instead of placement positions in a matrix, and by making the shape of outline of each of multiple openings substantially circular, the suppression of variation in electrical characteristics between the multiple signal lines 4 a to 4 d without selectively making the form of some openings different is aimed at.

Specifically, as shown in FIG. 6 , multiple openings 220 are arranged in a staggered pattern in plan view. FIG. 6 is a plan view showing the configuration of the multilayer substrate 200 and illustrates part of the plan configuration seen from the front side of the multilayer substrate 200 . For example, by displacing placement positions of openings in every other row in the configuration of FIG. 1 by about half of the X-direction placement pitch and changing the shape of outline of each opening to a substantially circular shape with making the largest widths of the openings even, the configuration of FIG. 6 can be obtained. In the configuration shown in FIG. 6 , with placement positions in a staggered pattern as the base, the shape of outline of each of the multiple openings 220 is substantially circular.

With the configuration shown in FIG. 6 , variation between respective overlap areas between the multiple signal lines 4 a to 4 d and conductor parts of a mesh ground 202 a when seen through in a Z direction can be easily suppressed. Thus, variation in electrical characteristics between the multiple signal lines 4 a to 4 d can be suppressed.

In this situation, by setting an average one among the largest widths of the openings 220 to be greater than or equal to a required size, the long-term reliability of the semiconductor device (semiconductor package) can be improved to be greater than or equal to a required level. Thus, while the long-term reliability of the semiconductor device (semiconductor package) can be improved to be greater than or equal to a required level, variation in electrical characteristics between the signal lines 4 a to 4 d can be suppressed.

Third Embodiment

Next, a method of designing a multilayer substrate according to the third embodiment will be described. Description will be made below focusing on the differences from the first embodiment.

In the first embodiment, without changing the relative placement of the signal lines 4 a to 4 d and the mesh ground 2 a in the multilayer substrate 1 , the suppression of variation in electrical characteristics between the multiple signal lines 4 a to 4 d is aimed at.

However, even if the degrees of freedom in placement of the signal lines and the degrees of freedom in placement of the mesh ground in the multilayer substrate 1 are both likely to be restricted, there may be room for a change in the relative placement of the signal lines and the mesh ground.

Accordingly, in the third embodiment, by changing the relative placement of the signal lines and the mesh ground in the multilayer substrate, the suppression of variation in electrical characteristics between the multiple signal lines is aimed at. Such a method of designing a multilayer substrate can be made more efficient by executing by interactive processing and/or batch processing with use of a CAD (Computer Aided Design) tool.

Specifically, the method of designing a multilayer substrate according to the present embodiment is executable on a computer as shown in FIG. 7 . FIG. 7 is a diagram showing the configuration of a computer which can execute the method of designing a multilayer substrate according to the embodiment.

The computer 91 comprises a bus line 99 , a control unit 92 , a display unit 93 , a storage unit 94 , an input unit 96 , and a medium interface 97 .

The control unit 92 , display unit 93 , storage unit 94 , input unit 96 , and medium interface 97 are connected to each other via the bus line 99 . The medium interface 97 is configured such that a recording medium 98 is connectable thereto.

The storage unit 94 stores a layout editor 941 , an analysis tool 944 , signal-layer layout data 942 , and ground-layer layout data 943 .

The layout editor 941 is a CAD tool for performing layout design in the design of a multilayer substrate. The signal-layer layout data 942 is layout data created for a signal layer 304 (see FIG. 14B ). The ground-layer layout data 943 is layout data created for a ground layer 302 (see FIG. 14B ).

The analysis tool 944 is a solver which performs a predetermined calculation to change layout data according to the calculation result in the design of a multilayer substrate. The solver is software which calculates the solution when a mathematical model for optimization is entered in text format or the like. In the present embodiment, layout data is changed to satisfy predetermined restriction conditions using the solver.

The control unit 92 is, for example, a CPU, GPU, DSP, or microcomputer and further includes a cache memory for temporary storage. Further, the control unit 92 includes a layout creating unit 921 and an analysis unit 922 .

The layout creating unit 921 is functionally realized in the control unit 92 by the layout editor 941 being executed. For example, the layout creating unit 921 creates the signal-layer layout data 942 and the ground-layer layout data 943 .

The analysis unit 922 is functionally realized in the control unit 92 by the analysis tool 944 being executed. The control unit 922 receives a physical design standard (design rules), predetermined restriction conditions, the signal-layer layout data 942 , and the ground-layer layout data 943 . The analysis unit 922 determines the layout of openings 320 - 1 to 320 - 12 to satisfy the predetermined restriction conditions within the scope of the design rules being satisfied. The predetermined restriction conditions include the condition that variation between respective overlap areas (coupling areas) between the signal lines 304 a to 304 f and conductor parts of a mesh ground 302 a when seen through in a Z direction (see FIG. 14A ) be within an acceptable range.

The display unit 93 is a display device such as a CRT display, a liquid crystal display, or the like. The storage unit 94 is, for example, a memory, a hard disk, or the like. The input unit 96 is, for example, a key board, a mouse, or the like. The medium interface 97 is, for example, a flexible disk drive, a CD-ROM drive, a USB interface, or the like. The recording medium 98 is a flexible disk, a CD-ROM, a USB memory, or the like. For example, the layout editor 941 and the analysis tool 944 can both be installed into the storage unit 94 from the recording medium 98 via the medium interface 97 .

Next, the method of designing a multilayer substrate will be described using FIGS. 8 to 12 . FIG. 8 is a flow chart showing the method of designing a multilayer substrate. FIG. 9 is a diagram showing layout data of signal lines. FIG. 10 is a diagram showing layout data of a mesh ground. FIG. 11 is a diagram showing overlap areas between the signal lines and the mesh ground. FIG. 12 is a diagram showing overlap areas between the signal lines and the mesh ground after the mesh ground is moved.

The layout creating unit 921 decides on the layout of the multiple signal lines 304 a to 304 f (S 1 ). For example, the layout creating unit 921 places objects of the signal lines 304 a to 304 f on a layout chart as shown in FIG. 9 to create the signal-layer layout data 942 .

The layout creating unit 921 decides on the form of each opening in the mesh ground 302 a (S 2 ). For example, as shown in FIG. 10 , the layout creating unit 921 decides on the longitudinal size 321 and transverse size 322 of a unit region and the longitudinal size 323 and transverse size 324 of the opening according to instructions from a user via the input unit 96 . Or, for example, the layout creating unit 921 decides on the longitudinal size 321 and transverse size 322 of a unit region and the ratio of the area of the opening to the unit region (the opening ratio) according to instructions from a user via the input unit 96 . Or, for example, the layout creating unit 921 decides on the longitudinal size 323 and transverse size 324 of the opening and the distances 325 , 326 between adjacent openings according to instructions from a user via the input unit 96 .

The layout creating unit 921 provisionally decides on the layout of the mesh ground 302 a (the placement positions of the openings) according to the decision at S 2 (S 3 ). For example, as shown in FIG. 10 , the layout creating unit 921 places objects of the openings 320 - 1 to 320 - 12 in a matrix on a layout chart according to the decision at S 2 to create the ground-layer layout data 943 .

The analysis unit 922 receives the signal-layer layout data 942 and the ground-layer layout data 943 from the layout creating unit 921 . The analysis unit 922 places objects of the signal lines 304 a to 304 f and objects of the openings 320 - 1 to 320 - 12 to overlap on a layout chart based on the signal-layer layout data 942 and the ground-layer layout data 943 so as to create intermediate data 945 as shown in FIG. 11 . The analysis unit 922 calculates overlap areas (coupling areas) between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a when seen through in a Z direction (see FIG. 14A ) based on the intermediate data 945 (S 4 ). The analysis unit 922 calculates overlap areas indicated by oblique hatching in FIG. 11 , for example.

The analysis unit 922 determines whether variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a is within an acceptable range. For example, the analysis unit 922 determines whether the difference between the maximum value and minimum value of overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a is less than a specified value (S 5 ).

If the difference between the maximum value and minimum value of the overlap areas exceeds the specified value (No at S 5 ), the analysis unit 922 determines that variation between the overlap areas is not within the acceptable range and moves the placement positions of the openings 320 - 1 to 320 - 12 to change the ground-layer layout data 943 (S 6 ).

The analysis unit 922 moves the placement positions of the openings 320 - 1 to 320 - 12 , for example, from the placement positions shown in FIG. 11 to those shown in FIG. 12 to change the ground-layer layout data 943 . The analysis unit 922 creates intermediate data 945 ′ as shown in FIG. 12 based on the signal-layer layout data 942 and the ground-layer layout data 943 after the change (that is, by laying the signal-layer layout data 942 over the ground-layer layout data 943 after the change). The analysis unit 922 again calculates overlap areas (coupling areas) between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a , when seen through in a Z direction (see FIG. 14A ), based on the intermediate data 945 ′ (S 4 ). The analysis unit 922 calculates overlap areas indicated by oblique hatching in FIG. 12 , for example. FIG. 12 illustrates the case where variation between overlap areas (coupling areas) is improved over the case of FIG. 11 .

If variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a is within the acceptable range (Yes at S 5 ), the analysis unit 922 decides on the layout of the mesh ground 302 a (the placement positions of the openings) (S 7 ). Thus, the ground-layer layout data 943 is decided on.

In the design method shown in FIG. 8 , the process of S 4 to S 7 may be executed by interactive processing instead of batch processing. For example, moving the placement positions of the openings 320 - 1 to 320 - 12 (S 6 ) may be performed using the layout editor 941 . Or in the design method shown in FIG. 8 , the process of S 1 to S 7 may be executed manually without using the CAD tool.

Next, a manufacturing method of a semiconductor device to which the design method of a multilayer substrate according to the present embodiment is applied will be described using FIG. 13 . FIG. 13 is a flow chart showing the manufacturing method of a semiconductor device.

A computer 1 executes the process of S 1 to S 7 shown in FIG. 8 to create design data for a multilayer substrate (S 10 ). The design data for the multilayer substrate includes, for example, the signal-layer layout data 942 and the ground-layer layout data 943 .

A processing apparatus (not shown) processes a base material based on the design data for the multilayer substrate to form the multilayer substrate (S 20 ).

A mounting apparatus (not shown) mounts semiconductor chips (not shown) on the multilayer substrate (S 30 ). Thus, the semiconductor device having semiconductor chips mounted on the multilayer substrate is manufactured.

As described above, in the third embodiment, in the design method of the multilayer substrate, the layout of the multiple openings 320 is decided on such that variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a falls within the acceptable range. Thus, by changing the relative placement of the signal lines 304 a to 304 d and the mesh ground 2 a in the multilayer substrate 1 , variation in electrical characteristics between the multiple signal lines 304 a to 304 d can be suppressed.

Further, in the third embodiment, in the design method of the multilayer substrate, a change in the layout of the multiple openings 320 can be performed by batch processing based on the calculation of overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a . Thus, the work of designing a multilayer substrate can be made more efficient.

It should be noted that, although the third embodiment illustrates the case where, if variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a is not within the acceptable range, the placement positions of the multiple openings 320 are changed overall, the placement positions of some of the multiple openings 320 may be selectively changed.

For example, as shown in FIG. 14A , the placement positions of openings 320 - 1 , 320 - 5 , 320 - 9 of the leftmost column in FIG. 14A from among the multiple openings 320 - 1 to 320 - 12 may be selectively changed by a pitch 331 along a longitudinal direction. For example, for a signal line group having a high proportion of transverse line parts, a longitudinal shift of the mesh ground (a longitudinal shift of some openings 320 on a per column basis) may greatly improve variation between overlap areas (coupling areas). FIG. 14A is a diagram showing overlap areas between the signal lines and the mesh ground after a shift of the mesh ground (a shift of openings on a per column basis from among the multiple openings).

Or, for example, as shown in FIG. 14B , the placement positions of openings 320 - 1 , 320 - 2 , 320 - 3 , 320 - 4 of the topmost row in FIG. 14B from among the multiple openings 320 - 1 to 320 - 12 may be selectively changed by a pitch 332 along a transverse direction. For example, for a signal line group having a high proportion of longitudinal line parts, a transverse shift of the mesh ground (a transverse shift of some openings 320 on a per row basis) may greatly improve variation between overlap areas (coupling areas). FIG. 14B is a diagram showing overlap areas between the signal lines and the mesh ground after a shift of the mesh ground (a shift of openings on a per row basis from among the multiple openings).

Or if variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a is not within the acceptable range, the placement positions of some of the multiple signal lines 304 a to 304 f may be changed in addition to changing the placement positions of the multiple openings 320 .

For example, if the overlap area between the signal line 304 d and conductor parts of the mesh ground 302 a greatly varies from those of the others from among the multiple signal lines 304 a to 304 f , the placement position of the signal line 304 d may be changed from the position indicated by a broken line in FIG. 15 to the position indicated by a solid line within the scope of design rules (minimum line distances) being satisfied. For example, the position of the signal line 304 d may be moved from the position indicated by the broken line by a pitch 341 along a longitudinal direction. FIG. 15 is a diagram showing overlap areas between the signal lines and the mesh ground after a shift of the signal line.

Note that the configuration of the second embodiment may be designed by the design method of the third embodiment. That is, the layout creating unit 921 may determine the shape of outline of each opening in the mesh ground 302 a to be substantially circular (S 2 ) and provisionally determine the placement positions of the openings in the mesh ground 302 a to be placement positions in a staggered pattern (S 3 ).

Fourth Embodiment

Next, a method of designing a multilayer substrate according to the fourth embodiment will be described. Description will be made below focusing on the differences from the third embodiment.

In the third embodiment, by changing the relative placement of the signal lines 304 a to 304 f and the mesh ground 302 a in the multilayer substrate, variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a is made to fall within the acceptable range.

However, even if variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a falls within the acceptable range, there may be room for further improvement in variation in electrical characteristics between the multiple signal lines 304 a to 304 f.

Accordingly, in the fourth embodiment, in the state where variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a is within the acceptable range, by selectively making the form of some of the multiple openings different from that of the other openings as in the first embodiment, the further suppression of variation in electrical characteristics between the multiple signal lines 304 a to 304 f is aimed at.

The layout creating unit 921 decides on the layout of the multiple signal lines 304 a to 304 f (S 1 ) and then provisionally decides on the form of each opening in the mesh ground 302 a (S 11 ).

If variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a is within the acceptable range (Yes at S 5 ), the analysis unit 922 decides on the placement positions of the openings in the mesh ground 302 a (S 12 ).

The analysis unit 922 identifies signal lines likely to degrade in electrical characteristics from among the multiple signal lines 304 a to 304 f and determines the identified signal lines to be signal lines of interest (S 13 ). The analysis unit 922 selects openings to be analyzed from among the multiple openings and determines whether the openings to be analyzed overlap parts extending longitudinally or transversely of the signal lines of interest when seen through in a Z direction (S 14 ).

If the openings to be analyzed overlap parts extending longitudinally or transversely of the signal lines of interest (Yes at S 14 ), then the analysis unit 922 changes the form (at least one of the shape, the orientation, and the largest width) of the openings to a form with which the path length of the return current is shorter (S 15 ).

If the openings to be analyzed do not overlap parts extending longitudinally or transversely of the signal lines of interest (No at S 14 ), then the analysis unit 922 lets the process proceed to S 16 .

The analysis unit 922 determines whether there are not-yet selected openings among the multiple openings (S 16 ). If there are not-yet selected openings (Yes at S 16 ), the analysis unit 922 selects openings to be analyzed from the not-yet selected openings and lets the process return to S 14 .

If there are no not-yet selected openings (No at S 16 ), the analysis unit 922 decides on the layout of the mesh ground 302 a (the form of each opening) (S 17 ). Thus, the ground-layer layout data 943 is decided on.

As described above, in the fourth embodiment, in the design method of the multilayer substrate, in the state where variation between respective overlap areas between the signal lines 304 a to 304 f and conductor parts of the mesh ground 302 a is within the acceptable range, the form of some of the multiple openings are selectively made different from that of the other openings. Thus, the electrical characteristics of signal lines likely to degrade in electrical characteristics from among the multiple signal lines 304 a to 304 f can be selectively improved. As a result, variation in electrical characteristics between the multiple signal lines 304 a to 304 f can be further suppressed.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.