Active load circuit and semiconductor integrated circuit

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-046339, filed on Mar. 9, 2015; the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to an active load circuit and a semiconductor integrated circuit.

In amplifiers, a differential signal received at an input stage is amplified by an active load circuit and outputted as a differential signal. In this case, if a current mirror circuit is used in the active load circuit, parasitic capacitances of transistors are connected to the mirror source and the mirror destination respectively, so that the frequency band of the amplifier is likely to become narrower. Thus, it is desired to make the active load circuit broader in frequency band.

FIG. 1 is a circuit diagram showing the configuration of an active load circuit according to a first embodiment;

FIG. 2 is a circuit diagram showing the configuration of an active load circuit according to a modified example of the first embodiment;

FIG. 3 is a circuit diagram showing the configuration of an active load circuit according to another modified example of the first embodiment;

FIG. 4 is a circuit diagram showing the configuration of a semiconductor integrated circuit according to a second embodiment;

FIGS. 5A and 5B are graphs showing the operation of the semiconductor integrated circuit according to the second embodiment;

FIG. 6 is a circuit diagram showing the configuration of a semiconductor integrated circuit according to a third embodiment;

FIG. 7 is a circuit diagram showing the operation of the semiconductor integrated circuit according to the third embodiment;

FIG. 8 is a circuit diagram showing the operation of the semiconductor integrated circuit according to the third embodiment; and

FIG. 9 is a block diagram showing the configuration of a receiver including a low pass filter to which the semiconductor integrated circuit according to the second and third embodiments is applied.

In general, according to one embodiment, there is provided an active load circuit including a first transistor, a second transistor, a first resistor, a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a line. The first transistor is placed between a first node and a first reference node. The second transistor is placed between a second node and the first reference node. One end of the first resistor is connected to gate of the first transistor and the other end of the first resistor is connected to the first node. One end of the second resistor is connected to gate of the second transistor and the other end of the second resistor is connected to the second node. The third transistor is placed between the first transistor and the first reference node. The fourth transistor is placed between the second transistor and the first reference node. The fifth transistor, together with the second transistor, formes a current mirror circuit and is placed between a third node and the first reference node. The sixth transistor, together with the first transistor, formes a current mirror circuit and is placed between a fourth node and the first reference node. The seventh transistor is placed between the fifth transistor and the first reference node. The eighth transistor is placed between the sixth transistor and the first reference node. a line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.

Exemplary embodiments of an active load circuit will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

(First Embodiment)

An active load circuit 3 according to the first embodiment will be described using FIG. 1 . FIG. 1 is a circuit diagram showing the configuration of the active load circuit 3 .

The active load circuit 3 is included in an amplifier 1 . The amplifier 1 includes an input stage 2 and the active load circuit 3 . In the amplifier 1 , a differential signal (differential voltages Vip, Vin) received by the input stage 2 via a differential input pair (a pair of input terminals Tin 1 , Tin 2 ) is amplified by the active load circuit 3 to output as a differential signal (differential currents Iop, Ion) through a differential output pair (a pair of output terminals Tout 1 , Tout 2 ). The input stage 2 has transistors M 51 , M 52 and a current source CS 1 . The transistors M 51 , M 52 are, for example, NMOS transistors. The gates of the transistors M 51 , M 52 are connected to the differential input pair Tin 1 , Tin 2 . The differential output pair Tout 1 , Tout 2 are connected to nodes N 3 , N 4 in the active load circuit 3 .

For example, in designing the amplifier 1 , current mirror circuits are used in the active load circuit 3 . The active load circuit 3 has transistors M 1 , M 2 , M 5 , and M 6 . The transistors M 1 and M 6 form a current mirror circuit CM 1 . The transistors M 2 and M 5 form a current mirror circuit CM 2 .

The transistor M 1 is placed between a node N 1 and a power supply node (first reference node) Nvdd. The power supply node Nvdd indicates any position on the power supply line and has power supply potential. The transistor M 1 is, for example, a PMOS transistor. The drain and gate of the transistor M 1 are electrically connected to the node N 1 . The node N 1 is connected to the drain of the transistor M 51 . The transistor M 6 is placed between a node N 4 and the power supply node Nvdd. The transistor M 6 is, for example, a PMOS transistor. As to the transistor M 6 , the drain is electrically connected to the node N 4 , and the gate is electrically connected to the node N 1 . Thus, the transistors M 1 and M 6 form the current mirror circuit CM 1 .

The transistor M 2 is placed between a node N 2 and the power supply node Nvdd. The transistor M 2 is, for example, a PMOS transistor. The drain and gate of the transistor M 2 are electrically connected to the node N 2 . The node N 2 is connected to the drain of the transistor M 52 . The transistor M 5 is placed between the node N 3 and the power supply node Nvdd. The transistor M 5 is, for example, a PMOS transistor. As to the transistor M 5 , the drain is electrically connected to the node N 3 , and the gate is electrically connected to the node N 2 . Thus, the transistors M 2 and M 5 form the current mirror circuit CM 2 .

In the current mirror circuit, parasitic capacitances (gate-to-source parasitic capacitances) of transistors are connected to the mirror source and the mirror destination respectively. For example, in the current mirror circuit CM 1 , parasitic capacitances Cgs 1 and Cgs 6 are connected to the transistors M 1 and M 6 respectively. In the current mirror circuit CM 2 , parasitic capacitances Cgs 2 and Cgs 5 are connected to the transistors M 2 and M 5 respectively. If parasitic capacitances of transistors are connected to the mirror source and the mirror destination respectively, then the amount of current to flow needs to be increased in order to speed up, so that the consumption current is likely to increase. Further, in the current mirrors that are an active load, the parasitic capacitances (Cgs 1 , Cgs 2 ) of transistors, the mirror source, and the parasitic capacitances (Cgs 5 , Cgs 6 ) of transistors, the mirror destination, affect the frequency band of the amplifier 1 , so that the band of the amplifier 1 is likely to become narrower.

Accordingly, in the active load circuit 3 , a resistor R 1 is inserted between the gate of the transistor M 1 and the node N 1 , and a resistor R 2 is inserted between the gate of the transistor M 2 and the node N 2 . One end of the resistor R 1 is electrically connected to the gate of the transistor M 1 , and the other end is electrically connected to the node N 1 . One end of the resistor R 2 is electrically connected to the gate of the transistor M 2 , and the other end is electrically connected to the node N 2 . The active load including the resistors R 1 and R 2 can reduce the influence of the parasitic capacitances Cgs 1 , Cgs 2 of the transistors M 1 , M 2 on the band of the amplifier 1 . Thus, it seems possible to broaden the band of (speed up) the amplifier 1 as compared with the case where the resistors R 1 and R 2 do not exist.

However, in the current mirror circuits CM 1 , CM 2 , for example, where the ratio of a dimension (=W/L, W: Gate width, L: Gate length) of the mirror source to the dimension of the mirror destination is at about 1:1, the gain is about 0 dB. In order to raise the gain, the dimension ratio of the mirror destination to the mirror source needs to be increased to 1:2 or so on. If the dimension ratio of the mirror destination to the mirror source is increased, the band of the amplifier 1 is likely to become narrow because the parasitic capacitances of the transistors increase as the dimensions of the transistors increase.

If the dimensions of the transistors are reduced to decrease the parasitic capacitances of the transistors in order to broaden the band of the amplifier 1 , the matching between the mirror source and the mirror destination is likely to degrade. That is, the dimension ratio of the mirror destination to the mirror source is likely to deviate from a target value, so that the mismatching (DC offset) of the common mode output voltages of the amplifier 1 is likely to increase.

Accordingly, in the present embodiment, transistors M 3 , M 4 , M 7 , M 8 that operate as degeneration resistors are added to the active load circuit 3 , and in addition the drains of the transistors M 7 , M 8 are connected by a line CL, thereby achieving both suppression of the DC offset and broadening the band (speeding up) of the amplifier 1 .

Specifically, the active load circuit 3 has the transistors M 3 , M 4 , M 7 , M 8 and the line CL.

The transistor M 3 is placed between the transistor M 1 and the power supply node Nvdd. The transistor M 3 is, for example, a PMOS transistor. As to the transistor M 3 , the source is electrically connected to the power supply node Nvdd, and the drain is electrically connected to the source of the transistor M 1 .

The transistor M 4 is placed between the transistor M 2 and the power supply node Nvdd. The transistor M 4 is, for example, a PMOS transistor. As to the transistor M 4 , the source is electrically connected to the power supply node Nvdd, and the drain is electrically connected to the source of the transistor M 2 .

The transistor M 7 is placed between the transistor M 5 and the power supply node Nvdd. The transistor M 7 is, for example, a PMOS transistor. As to the transistor M 7 , the source is electrically connected to the power supply node Nvdd, and the drain is electrically connected to the source of the transistor M 5 via a node N 5 .

The transistor M 8 is placed between the transistor M 6 and the power supply node Nvdd. The transistor M 8 is, for example, a PMOS transistor. As to the transistor M 8 , the source is electrically connected to the power supply node Nvdd, and the drain is electrically connected to the source of the transistor M 6 via a node N 6 .

The transistors M 3 , M 4 , M 7 , M 8 are configured to operate in a linear region. For example, the transistors M 3 , M 7 can operate as degeneration resistors to decrease the common-mode transconductance gm for the current mirror circuit CM 1 . The transistors M 4 , M 8 can operate as degeneration resistors to decrease the common-mode transconductance gm for the current mirror circuit CM 2 . Thus, the transistors M 3 , M 4 , M 7 , M 8 can improve the matching in common mode between the mirror source and the mirror destination in the current mirror circuits CM 1 , CM 2 . In this case, the dimensions of the transistors M 1 , M 2 , M 5 , M 6 may be even.

The gates of the transistor M 1 , of the transistor M 3 , and of the transistor M 8 are electrically connected to each other and electrically connected to the node N 1 via the resistor R 1 . Thus, a bias voltage to make them operate in the linear region can be supplied to the gates of the transistors M 3 and M 8 .

The gates of the transistor M 2 , of the transistor M 4 , and of the transistor M 7 are electrically connected to each other and electrically connected to the node N 2 via the resistor R 2 . Thus, a bias voltage to make them operate in the linear region can be supplied to the gates of the transistors M 4 and M 7 .

In the active load circuit 3 , the parasitic capacitances Cgs 1 , Cgs 3 , Cgs 8 of the transistors M 1 , M 3 , M 8 are made by the resistor R 1 to be difficult to see from the node N 4 on the output terminal Tout 2 side. The parasitic capacitances Cgs 2 , Cgs 4 , Cgs 7 of the transistors M 2 , M 4 , M 7 are made by the resistor R 2 to be difficult to see from the node N 3 on the output terminal Tout 1 side. Thus, the influence of the parasitic capacitances Cgs 1 , Cgs 2 , Cgs 3 , Cgs 4 , Cgs 7 , Cgs 8 on the band of the amplifier 1 can be reduced.

Further, the nodes N 5 , N 6 are electrically connected by the line CL. The node N 5 is connected to the drain of the transistor M 7 and the source of the transistor M 5 . The node N 6 is connected to the drain of the transistor M 8 and the source of the transistor M 6 . A P-side current Ip flowing through the transistor M 7 and an N-side current In flowing through the transistor M 8 can flow into the line CL to cancel each other out. For example, the P-side current Ip and the N-side current In are substantially equal in the absolute value of the amplitude and opposite in phase. Letting a P-side voltage Vp be the voltage on the node N 5 corresponding to the P-side current Ip and an N-side voltage Vn be the voltage on the node N 6 corresponding to the N-side current In, the P-side voltage Vp and the N-side voltage Vn are substantially equal in the absolute value of the amplitude and opposite in phase. If Vp>0>Vn, the P-side current Ip flows via the node N 5 to the line CL to the node N 6 , and the P-side current Ip and the N-side current In can merge at the node N 6 to cancel each other out. If Vp<0<Vn, the N-side current In flows via the node N 6 to the line CL to the node N 5 , and the P-side current Ip and the N-side current In can merge at the node N 5 to cancel each other out. Thus, the influence of the degeneration resistors (transistors M 7 , M 8 ) on the differential component between the transistors M 5 , M 6 , the mirror destinations, in the current mirror circuits CM 1 , CM 2 can be suppressed substantially. Therefore, the differential transconductance gm for the current mirror circuits CM 1 , CM 2 can be raised by the line CL. That is, when differential operation is considered, the differential transconductance gm is different between the mirror source and the mirror destination in the current mirror circuits CM 1 , CM 2 , and the differential transconductance gm of the mirror destination can be made higher than the differential transconductance gm of the mirror source, so that, e.g., the gain in the low frequency region can be increased.

As described above, in the first embodiment, because the transistors M 3 , M 4 , M 7 , M 8 operate as degeneration resistors in the active load circuit 3 , the common-mode transconductance gm for the current mirror circuits CM, CM 2 can be decreased. Thus, the transistors M 3 , M 4 , M 7 , M 8 can improve the matching in common mode between the mirror source and the mirror destination in the current mirror circuits CM 1 , CM 2 , so that the mismatching (DC offset) of the common mode output voltages can be suppressed. Further, because the drains of the transistors M 7 , M 8 are connected by the line CL, the differential transconductance gm for the current mirror circuits CM 1 , CM 2 can be raised. Therefore, the gain of the amplifier 1 can be increased, and the amplifier 1 can be broadened in band (speeded up). Thus, both suppression of the DC offset and broadening the band (speeding up) of the amplifier 1 can be achieved.

Note that, in the active load circuit 3 shown in FIG. 1 , by changing the power supply node Nvdd to a ground node (first reference node) and replacing the transistors M 1 to M 8 with transistors opposite in conductivity type, an active load circuit having the same function may be configured. The ground node indicates any position on the ground line and has power supply potential and has ground potential.

Alternatively, as shown in FIG. 2 , in an active load circuit 3 i , the transistors M 3 , M 4 , M 7 , M 8 may be configured to operate in the linear region with a bias being supplied from a bias circuit 4 i to their gates. That is, the bias circuit 4 i is electrically connected to the gates of the transistor M 3 , of the transistor M 4 , of the transistor M 7 , and of the transistor M 8 . The bias circuit 4 i has replica transistors M 21 , M 22 and a current source CS 2 . The replica transistor M 21 is formed to have characteristics equivalent to those of the transistor M 1 and, for example, has dimensions equivalent to those of the transistor M 1 . The replica transistor M 22 is formed to have characteristics equivalent to those of the transistor M 3 and, for example, has dimensions equivalent to those of the transistor M 3 . Thus, a replica bias equivalent to the bias supplied to the gates of the transistors M 3 , M 4 , M 7 , M 8 in the configuration shown in FIG. 1 can be supplied to the gates of the transistors M 3 , M 4 , M 7 , M 8 , so that the transistors M 3 , M 4 , M 7 , M 8 can be made to operate in the linear region.

Alternatively, as shown in FIG. 3 , an active load circuit 3 j may be configured such that the common mode voltage of the transistors M 3 , M 4 is extracted and applied to the gates of the transistors M 7 , M 8 . That is, the active load circuit 3 j further has resistors R 3 , R 4 . One end of the resistor R 3 is electrically connected to the gate of the transistor M 3 , and the other end is electrically connected to an intermediate node N 11 . One end of the resistor R 4 is electrically connected to the gate of the transistor M 4 , and the other end is electrically connected to the intermediate node N 11 . The intermediate node N 11 is electrically connected to the gates of the transistors M 7 and M 8 via a node N 12 .

In this configuration, the transistor M 3 is connected at the gate to the gate of the transistor M 1 and can operate in the linear region as in the configuration of FIG. 1 . The transistor M 4 is connected at the gate to the gate of the transistor M 2 and can operate in the linear region as in the configuration of FIG. 1 . By making the resistance of the resistor R 3 and the resistance of the resistor R 4 even, the common mode voltage of the transistors M 3 , M 4 can be extracted to be a voltage on the intermediate node N 11 , and the common mode voltage extracted can be transmitted from the intermediate node N 11 to the node N 12 to the gates of the transistors M 7 , M 8 . Thus, the transistors M 7 , M 8 can be made to operate in the linear region. Further, because accuracy in having the P-side current Ip of the transistor M 7 and the N-side current In of the transistor M 8 cancel out by the line CL can be improved, the differential transconductance gm for the current mirror circuits CM 1 , CM 2 can be further raised.

(Second Embodiment)

Next, a semiconductor integrated circuit 200 according to the second embodiment will be described using FIG. 4 . FIG. 4 is a circuit diagram showing the configuration of the semiconductor integrated circuit 200 .

The semiconductor integrated circuit 200 includes the same amplifier 1 as in the first embodiment as a one-stage amplifier and further includes a two-stage amplifier 4 and a common-mode feedback (CMFB) circuit 8 .

The one-stage amplifier 1 and the two-stage amplifier 4 are electrically connected in parallel between a differential input pair Tin 1 , Tin 2 and a differential output pair Tout 1 , Tout 2 . The one-stage amplifier 1 is formed of an input stage 2 and one stage of the active load circuit 3 (see FIG. 1 ) as a gain stage. Hereinafter, the active load circuit 3 as a gain stage is simply referred to as a gain stage 3 . The two-stage amplifier 4 is formed of an input stage 5 and two stages of gain stages 6 , 7 .

The differential input pair Tin 1 , Tin 2 are electrically connected to the input stage 5 . The input stage 5 has transistors M 31 , M 32 and a current source CS 3 . The transistors M 31 , M 32 are, for example, PMOS transistors. The transistors M 31 , M 32 have their gates electrically connected to the differential input pair Tin 1 , Tin 2 , their sources connected to the current source CS 3 , and their drains connected to nodes N 7 , N 8 .

The gain stage 6 is electrically connected between the input stage 5 and the gain stage 7 . The gain stage 6 , together with the input stage 5 , forms a differential amplifying circuit. The gain stage 6 can be called a differential stage. The gain stage 6 has transistors M 41 , M 42 and resistors R 5 , R 6 . The transistor M 41 is placed between the node N 7 and a ground node Ngnd. The ground node Ngnd has reference potential (e.g., ground potential). The transistor M 41 is, for example, an NMOS transistor. The transistor M 41 has its gate electrically connected to one end of the resistor R 5 , to one end of the resistor R 6 , and to the gate of the transistor M 42 , its drain connected to the node N 7 , and its source connected to the ground node Ngnd.

The transistor M 42 is placed between the node N 8 and the ground node Ngnd. The transistor M 42 is, for example, an NMOS transistor. The transistor M 42 has its gate electrically connected to one end of the resistor R 5 , to one end of the resistor R 6 , and to the gate of the transistor M 41 , its drain connected to the node N 8 , and its source connected to the ground node Ngnd.

The resistor R 5 has its one end connected to one end of the resistor R 6 , to the gate of the transistor M 41 , and to the gate of the transistor M 42 , and the other end connected to the node N 7 .

The resistor R 6 has its one end connected to one end of the resistor R 5 , to the gate of the transistor M 41 , and to the gate of the transistor M 42 , and the other end connected to the node N 8 .

The gain stage 7 is electrically connected between the gain stage 6 and the differential output pair Tout 1 , Tout 2 . The gain stage 7 has transistors M 9 , M 10 . The transistor M 9 is placed between the node N 9 and the ground node Ngnd. The node N 9 is electrically connected to the output terminal Tout 1 . The transistor M 9 is, for example, an NMOS transistor. The transistor M 9 has its gate electrically connected to the node N 8 , its drain connected to the node N 9 , and its source connected to the ground node Ngnd.

The transistor M 10 is placed between the node N 10 and the ground node Ngnd. The node N 10 is electrically connected to the output terminal Tout 2 . The transistor M 10 is, for example, an NMOS transistor. The transistor M 10 has its gate electrically connected to the node N 7 , its drain connected to the node N 10 , and its source connected to the ground node Ngnd.

The CMFB circuit 8 is connected between the intermediate node N 11 and the differential output pair Tout 1 , Tout 2 . The intermediate node N 11 is an intermediate node of the differential output pair Tout 1 , Tout 2 . The intermediate node N 11 is connected to the output terminal Tout 1 via a resistor R 7 and connected to the output terminal Tout 2 via a resistor R 8 , and it is configured such that a common mode voltage is extracted via the resistors R 7 and R 8 .

The CMFB circuit 8 has a differential amplifier 9 and transistors M 13 , M 14 . The differential amplifier 9 has its inputs connected respectively to the intermediate node N 11 and a reference voltage Vref and its output connected to the gates of the transistors M 13 , M 14 . The transistor M 13 is, for example, an NMOS transistor. The transistor M 13 has its source connected to the ground node Ngnd and its drain connected to the node N 9 . The transistor M 14 is, for example, an NMOS transistor. The transistor M 14 has its source connected to the ground node Ngnd and its drain connected to the node N 10 .

When the one-stage amplifier 1 and the two-stage amplifier 4 in the semiconductor integrated circuit 200 are compared, the two-stage amplifier 4 is higher in gain because the load resistance is higher as indicated by a broken line in FIG. 5A . The one-stage amplifier 1 can operate faster (over a broader band) because the load resistance is lower as indicated by a dot-dashed line in FIG. 5A . FIGS. 5A and 5B are graphs showing the operation of the semiconductor integrated circuit 200 . In the gain characteristic of the two-stage amplifier 4 indicated by the broken line in FIG. 5A , two poles P 1 , P 2 exist, and in the band around the pole P 1 , the phase of the output is likely to be delayed changing from 0° to −90°, and in the band around the pole P 2 , the phase of the output is likely to be delayed changing from −90° to −180°. In view of the usage of the semiconductor integrated circuit 200 configured to use negative feedback, the phase becoming −180° needs to be avoided because it may cause the circuit to oscillate.

Accordingly, in the semiconductor integrated circuit 200 , the one-stage amplifier 1 and the two-stage amplifier 4 are connected in parallel, so that the two-stage amplifier 4 higher in gain is made to operate dominantly in the lower band, whereas the one-stage amplifier 1 broader in band is made to operate dominantly in the higher band, thus performing phase compensation as shown in FIG. 5B . In the gain characteristic of the semiconductor integrated circuit 200 shown in FIG. 5B , in the band around the pole P 2 , the phase of the output starts to be delayed changing from −90° to −180°, but in the band around the zero Z 2 , the operation of the one-stage amplifier 1 becomes dominant, so that the phase of the output advances toward −90°. Thus, the phase of the output becoming −180° can be avoided, and two-pole one-zero phase compensation that can compensate the phase while broadening the band of the amplifier in the semiconductor integrated circuit 200 can be achieved.

In this case, for example, if three blocks, i.e., the input stage and output stage of the two-stage amplifier and the one-stage amplifier are individually formed, then current is consumed in each block, so that the consumption current of the semiconductor integrated circuit 200 is likely to increase.

In contrast, in the second embodiment, transistors M 9 , M 10 of the output stage (gain stage 7 ) of the two-stage amplifier 4 and transistors M 5 , M 6 , folded-back output destinations, of the current mirrors of the one-stage amplifier 1 are constituted by transistors of opposite conductivity types and connected in inverters. For example, the transistors M 9 , M 10 are constituted by NMOS transistors, and the transistors M 5 , M 6 are constituted by PMOS transistors, and those transistors are connected in inverters. That is, the drains of the transistors M 9 , M 10 are respectively connected to the drains of the transistors M 5 , M 6 . Thus, current can be common to the transistor M 5 , M 6 and the transistor M 9 , M 10 . That is, current can be common to the output stage of the two-stage amplifier 4 and the one-stage amplifier 1 , so that the consumption current of the semiconductor integrated circuit 200 can be reduced.

Note that, in order to achieve the two-pole one-zero phase compensation, a multi-stage, three or more stage, amplifier may be connected in parallel with the one-stage amplifier 1 . In this case, by configuring the output stage of the multi-stage amplifier and the folded-back output destinations of the current mirrors of the one-stage amplifier 1 in the same way as in FIG. 4 , current may be made common to them.

(Third Embodiment)

Next, a semiconductor integrated circuit 300 according to the third embodiment will be described. Description will be made below focusing on the differences from the second embodiment.

Although in the second embodiment the phase compensation method is fixed at the two-pole one-zero phase compensation, the third embodiment enables switching the phase compensation method according to the required band.

Specifically, the semiconductor integrated circuit 300 has a two-stage amplifier 4 a and a CMFB circuit 8 a instead of the two-stage amplifier 4 and the CMFB circuit 8 (see FIG. 4 ).

The two-stage amplifier 4 a has a gain stage 7 a instead of the gain stage 7 (see FIG. 4 ). The gain stage 7 a further has capacitance elements C 1 , C 2 and switches SW 1 , SW 2 . One end of the capacitance element C 1 is electrically connected to the output terminal Tout 1 via the node N 9 , and the other end is electrically connected to one end of the switch SW 1 . One end of the switch SW 1 is electrically connected to the other end of the capacitance element C 1 , and the other end is electrically connected to the node N 8 in the gain stage 6 . The switch SW 1 is turned on to activate a region RG 3 and turned off to deactivate the region RG 3 . When the region RG 3 is activated, the capacitance element C 1 functions as mirror capacitance so as to perform mirror compensation.

One end of the capacitance element C 2 is electrically connected to the output terminal Tout 2 via the node N 10 , and the other end is electrically connected to one end of the switch SW 2 . One end of the switch SW 2 is electrically connected to the other end of the capacitance element C 2 , and the other end is electrically connected to the node N 7 in the gain stage 6 . The switch SW 2 is turned on to activate a region RG 4 and turned off to deactivate the region RG 4 . When the region RG 4 is activated, the capacitance element C 2 functions as mirror capacitance so as to perform mirror compensation.

The CMFB circuit 8 a further has transistors M 11 , M 12 and switches SW 3 , SW 4 , SW 5 , SW 6 . The differential amplifier 9 has its output side connected to the gates of the transistors M 11 , M 12 and to the gates of the transistors M 13 , M 14 . The transistor M 11 is, for example, a PMOS transistor. As to the transistor M 11 , the source is connected to the power supply node Nvdd, and the drain is connected to one end of the switch SW 3 . The transistor M 12 is, for example, a PMOS transistor. As to the transistor M 12 , the source is connected to the power supply node Nvdd, and the drain is connected to one end of the switch SW 4 .

One end of the switch SW 3 is connected to the drain of the transistor M 11 , and the other end is connected to the output terminal Tout 1 via the node N 3 . One end of the switch SW 4 is connected to the drain of the transistor M 12 , and the other end is connected to the output terminal Tout 2 via the node N 4 . The switches SW 3 , SW 4 are turned on to activate a region RG 2 and turned off to deactivate the region RG 2 . When the region RG 2 is activated, mirror compensation is performed.

One end of the switch SW 5 is connected to the drain of the transistor M 13 , and the other end is connected to the output terminal Tout 1 via the node N 9 . One end of the switch SW 6 is connected to the drain of the transistor M 14 , and the other end is connected to the output terminal Tout 2 via the node N 10 . The switches SW 5 , SW 6 are turned on to activate a region RG 1 and turned off to deactivate the region RG 1 . When the region RG 1 is activated, the two-pole one-zero phase compensation is performed.

The semiconductor integrated circuit 300 is configured to be able to switch the phase compensation method (phase compensation operation) between the two-pole one-zero phase compensation (first phase compensation operation) and the mirror compensation (second phase compensation operation) according to the required band. The two-pole one-zero phase compensation is a phase compensation method which covers a broader band but requires current through the one-stage amplifier 1 . The mirror compensation is a phase compensation method which covers a narrower band but can reduce current through the one-stage amplifier 1 .

For example, where the required band is broad in the use of the semiconductor integrated circuit 300 , the semiconductor integrated circuit 300 is controlled to be in a two-pole one-zero phase compensation mode by an external control unit (control circuit) 120 (see FIG. 9 ) as shown in FIG. 7 . The control unit 120 continuously supplies an ON signal to the control terminals of the switches SW 5 , SW 6 and an OFF signal to the control terminals of the switches SW 1 to SW 4 . Thus, the switches SW 5 , SW 6 are kept in an ON state, and the switches SW 1 to SW 4 are kept in an OFF state. The region RG 1 is kept in an activated state, and the regions RG 2 to RG 4 are kept in a deactivated state. At this time, the two-stage amplifier 4 a has no mirror compensation, and the one-stage amplifier 1 is in an active state. As a result, the semiconductor integrated circuit has a parallel configuration of the two-stage amplifier 4 a and the one-stage amplifier 1 as in the second embodiment, thus achieving the two-pole one-zero phase compensation suitable for a broad band.

For example, where the required band is narrow in the use of the semiconductor integrated circuit 300 , the semiconductor integrated circuit 300 is controlled to be in a mirror compensation mode by an external control unit (control circuit) 120 (see FIG. 9 ) as shown in FIG. 8 . The control unit 120 continuously supplies an OFF signal to the control terminals of the switches SW 5 , SW 6 and an ON signal to the control terminals of the switches SW 1 to SW 4 . Thus, the switches SW 5 , SW 6 are kept in the OFF state, and the switches SW 1 to SW 4 are kept in the ON state. The region RG 1 is kept in the deactivated state, and the regions RG 2 to RG 4 are kept in the activated state. At this time, in the two-stage amplifier 4 a , the mirror compensation is being performed, and the one-stage amplifier 1 is cut off. Because of becoming the two-stage amplifier 4 a using the mirror compensation in configuration, the semiconductor integrated circuit 300 is thought to become narrower in band than in the two-pole one-zero phase compensation mode. However, the consumption current can be reduced by the amount of current consumed by the differential pair of the one-stage amplifier 1 .

As described above, in the third embodiment, the semiconductor integrated circuit 300 performs the two-pole one-zero phase compensation suitable for a broad band if the required band is broad and performs the mirror compensation with the one-stage amplifier 1 being cut off if the required band is narrow. Thus, if the required band is broad, the one-stage amplifier 1 can be made to operate so as to achieve broadening the band, and if the required band is narrow, the one-stage amplifier 1 can be cut off so as to achieve lower power consumption.

Next, a receiver 100 including a low pass filter 106 to which the semiconductor integrated circuit according to the second and third embodiments is applied will be described using FIG. 9 . FIG. 9 is a block diagram showing the configuration of the receiver 100 .

The receiver 100 shown in FIG. 8 receives radio waves (radio frequency signals). Specifically, the receiver 100 comprises a receiving antenna 101 , a band pass filter 102 , a low noise amplifier (LNA) 103 , a buffer 104 , a mixer 105 , the low pass filter 106 , a variable gain amplifier 107 , an AD converter (ADC) 108 , an OFDM (Orthogonal Frequency-Division Multiplexing) demodulator 109 , and the control unit (control circuit) 120 .

The receiving antenna 101 receives radio waves (a radio frequency signal) propagating through the space. The receiving antenna 101 supplies the received radio frequency signal to the band pass filter 102 .

The band pass filter 102 selectively extracts a desired frequency component from the radio frequency signal received by the receiving antenna 101 . The band pass filter 102 supplies the extracted radio frequency signal to the low noise amplifier 103 .

The low noise amplifier 103 amplifies the radio frequency signal extracted by the band pass filter 102 . The low noise amplifier 103 supplies the amplified radio frequency signal to the buffer 104 .

The buffer 104 supplies the radio frequency signal supplied from the low noise amplifier 103 to the mixer 105 .

The mixer 105 receives the radio frequency signal amplified by the low noise amplifier 103 via the buffer 104 and converts that radio frequency signal into a base band signal or an intermediate frequency signal according to local oscillator signals LI, LQ. The mixer 105 supplies the converted signal to the low pass filter 106 .

The low pass filter 106 removes unnecessary high-band components from the signal supplied from the mixer 105 . The low pass filter 106 supplies the high-band component removed signal to the variable gain amplifier 107 .

The variable gain amplifier 107 amplifies the signal having passed through the low pass filter 106 . At this time, the variable gain amplifier 107 may amplify the signal with, e.g., a gain controlled by the control unit 120 . The variable gain amplifier 107 supplies the amplified signal to the AD converter 108 .

The AD converter 108 A/D converts the signal supplied from the variable gain amplifier 107 to produce digital values. The AD converter 108 supplies the produced digital values to the OFDM demodulator 109 .

The OFDM demodulator 109 performs OFDM demodulation processing on the supplied digital values. For example, the OFDM demodulator 109 reconstructs the original data from multiplexed digital values. The OFDM demodulator 109 supplies the reconstructed data to a predetermined circuit and the control unit 120 .

Note that a differential signal can be used as the signal transmitted from the band pass filter 102 to the AD converter 108 . Further, where the semiconductor integrated circuit 300 according to the third embodiment is applied to the low pass filter 106 , the ON signal and OFF signal for the switches SW 1 to SW 6 may be supplied from the control unit 120 to the semiconductor integrated circuit 300 in the low pass filter 106 .

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.