Data compensator and display device including the same

Korean Patent Applications No. 10-2015-0014079, filed on Jan. 29, 2015, and entitled, “Data Compensator and Display Device Including the Same,” is incorporated by reference herein in its entirety.

1. Field

One or more embodiments described herein relate to a data compensator and a display device including a data compensator.

2. Description of the Related Art

An organic light emitting display generates images using organic light emitting diodes. Because these diodes are self-emissive, a backlight unit is not used as is typically found in a liquid crystal display. An organic light emitting display offers many advantages over other types of flat panel displays. For example, organic light emitting displays are relatively thin and light and have low power consumption, improved luminance, and improved response speed compared to liquid crystal displays. As a result, organic light emitting displays are often used in portable electronic devices.

Some television channels broadcast information that is to be continuously displayed on a screen. Examples include network or channel logos (e.g. NBC, CBS). These logos are displayed with the same pattern, with high luminance, and at a same location on a screen. Consequently, the mobility of the driving transistors of pixels that display the logo may degrade over time. Once a pixel circuit degrades, image sticking may occur, e.g., the logo may be displayed on the screen for images which are not supposed to have the logo. As a result, display quality is degraded.

In accordance with one or more embodiments, a data compensator includes a block compensation coefficient generator to calculate block compensation coefficients corresponding to blocks in a first frame based on first pixel data of the first frame; a gamma applier to generate first gamma applied pixel data by applying a first gamma curve corresponding to a first frame compensation margin to the first pixel data of the first frame, the gamma applier to generate second gamma applied pixel data by applying a second gamma curve corresponding to a second frame compensation margin to a second pixel data of a second frame, which is a next frame of the first frame; a compensation margin generator to generate the second frame compensation margin based on the block compensation coefficients and the first gamma applied pixel data; a block compensation coefficient storage to store the block compensation coefficients, to select some block compensation coefficients among the block compensation coefficients based on a pixel coordinate, to output the selected block compensation coefficients; a pixel compensation coefficient generator to generate a pixel compensation coefficient corresponding to the second pixel data by interpolating the selected block compensation coefficients based on the pixel coordinate; and a first multiplier to generate output pixel data by multiplying the second gamma applied pixel data and the pixel compensation coefficient.

The compensation margin generator may include a gamma applied block data generator to generate gamma applied block data corresponding to the blocks in the first frame based on the first gamma applied pixel data; a second multiplier to generate compensated gamma applied block data by multiplying the block compensation coefficients and the gamma applied block data, respectively; a maximum compensated gamma applied block data generator configured to output a largest value among the compensated gamma applied block data as a maximum compensated gamma applied block data; and a compensation margin calculator to calculate the second frame compensation margin based on the maximum compensated gamma applied block data. The compensation margin calculator may determine the second frame compensation margin based on a ratio of the maximum compensated gamma applied block data to a limit value of the gamma applied block data.

A first axis of the first gamma curve may correspond to each of the first pixel data and a second axis of the first gamma curve may correspond to each of the first gamma applied pixel data, and the first gamma curve may be generated by scaling a base gamma curve along the second axis based on the first frame compensation margin.

A first axis of the second gamma curve may corresponds to the second pixel data and a second axis of the second gamma curve may correspond to the second gamma applied pixel data, and the second gamma curve may be generated by scaling a base gamma curve along the second axis based on the second frame compensation margin.

The block compensation coefficient storage may output a first block compensation coefficient of a first block, a second block compensation coefficient of a second block, a third block compensation coefficient of a third block, and a fourth block compensation coefficient of a fourth block as the selected block compensation coefficients, the second block may be adjacent to the first block at a right side of the first block, the third block may be adjacent to the first block at a lower side of the first block, the fourth block may be adjacent to the second block at a lower side of the second block, and the fourth block is adjacent to the third block at a right side of the third block.

The pixel coordinate may correspond to the second pixel data. The block compensation coefficients may be inversely proportional to driving currents of the blocks, respectively. The driving current of a first block may be based on an average of driving currents of pixels in the first block. The block compensation coefficients may be inversely proportional to driving voltages of the blocks, respectively. The driving voltage of a first block may be based on an average of driving voltages of pixels in the first block. The block compensation coefficients may be proportional to degradation of pixels in the blocks. At least one of the block compensation coefficient generator, gamma applier, compensation margin generator, pixel compensation coefficient generator, and first multiplier may be implemented by instructions to be performed by a processor.

In accordance with one or more other embodiments, a display device includes a data compensator to generate an output pixel data; a timing controller to generate a data driver control signal and a scan driver control signal based on the output pixel data; a display panel including a plurality of pixels; a data driver to generate a plurality of data signals based the data driver control signal, the data driver to provide the data signals to the pixels through a plurality of data signal lines; and a scan driver to generate a plurality of scan signals based on the scan driver control signal, the scan driver to provide the scan signals to the pixels through a plurality of scan signal lines.

The data compensator includes a block compensation coefficient generator to calculate block compensation coefficients corresponding to blocks in a first frame based on first pixel data of the first frame; a gamma applier to generate first gamma applied pixel data by applying a first gamma curve corresponding to a first frame compensation margin to the first pixel data of the first frame, the gamma applier to generate second gamma applied pixel data by applying a second gamma curve corresponding to a second frame compensation margin to a second pixel data of a second frame, which is a next frame of the first frame; a compensation margin generator to generate the second frame compensation margin based on the block compensation coefficients and the first gamma applied pixel data; a block compensation coefficient storage to store the block compensation coefficients, to select some of the block compensation coefficients based on a pixel coordinate, to output the selected block compensation coefficients; a pixel compensation coefficient generator to generate a pixel compensation coefficient corresponding to the second pixel data by interpolating the selected block compensation coefficients based on the pixel coordinate; and a first multiplier to generate the output pixel data by multiplying the second gamma applied pixel data and the pixel compensation coefficient.

The compensation margin generator may include a gamma applied block data generator to generate gamma applied block data corresponding to the blocks in the first frame based on the first gamma applied pixel data; a second multiplier to generate compensated gamma applied block data by multiplying the block compensation coefficients and the gamma applied block data, respectively; a maximum compensated gamma applied block data generator to output the biggest value among the compensated gamma applied block data as a maximum compensated gamma applied block data; and a compensation margin calculator to calculate the second frame compensation margin based on the maximum compensated gamma applied block data. The compensation margin calculator may determine the second frame compensation margin based on a ratio of the maximum compensated gamma applied block data to a limit value of the gamma applied block data.

In accordance with one or more other embodiments, a compensator includes first logic to calculate block compensation coefficients for blocks in a first frame based on first pixel data of the first frame; second logic to generate first gamma applied pixel data based on the first pixel data of the first frame and to generate second gamma applied pixel data based on the first gamma applied pixel data and second pixel data of a second frame adjacent the first frame; third logic to select a number of the block compensation coefficients based on a pixel coordinate; fourth logic to generate a pixel compensation coefficient corresponding to the second pixel data by interpolating the selected block compensation coefficients based on the pixel coordinate; and fifth logic to generate output pixel data based on the second gamma applied pixel data and the pixel compensation coefficient.

The second logic may generate the first gamma applied pixel data by applying a first gamma curve corresponding to a first frame compensation margin to the first pixel data of the first frame, and generate the second gamma applied pixel data by applying a second gamma curve corresponding to a second frame compensation margin to the second pixel data of the second frame. The compensator may include sixth logic to generate the second frame compensation margin based on the block compensation coefficients and the first gamma applied pixel data. At least one of the first through fifth logic may be implemented by instructions for controlling a computer.

Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:

FIG. 1 illustrates an embodiment of a data compensator;

FIG. 2 illustrates an embodiment of a compensation margin generator;

FIG. 3 illustrates an example of a first frame including a plurality of blocks;

FIG. 4 illustrates an example of compensation coefficients for the blocks;

FIG. 5 illustrates an embodiment of a pixel compensation coefficient generator;

FIG. 6 illustrates an example of the location of degraded pixels;

FIG. 7 illustrates an example of pixel compensation coefficients of a first pixel row;

FIG. 8 illustrates another example of compensation coefficients for the blocks;

FIG. 9 illustrates a comparative example of a compensation margin calculation;

FIGS. 10 and 11 illustrate examples of gamma applied block data;

FIGS. 12 and 13 illustrate examples of compensated gamma applied block data;

FIG. 14 illustrates an embodiment of a compensation margin calculation;

FIG. 15 illustrates an embodiment of a display device;

FIG. 16 illustrates an embodiment of an electronic device.

Example embodiments are described hereinafter with reference to the drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. The embodiments may be combined to form additional embodiments. Like reference numerals refer to like elements throughout.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

FIG. 1 illustrates an embodiment of a data compensator 100 which includes a block compensation coefficient generator BSFG 110 , a gamma applier GA 150 , a compensation margin generator CMG 130 , a block compensation coefficient storage BSFS 120 , a pixel compensation coefficient generator PSFG 140 , and a first multiplier 160 . The block compensation coefficient generator 110 calculates block compensation coefficients BSF corresponding to blocks in a first frame based on first pixel data RGB 1 of the first frame.

The gamma applier 150 generates first gamma applied pixel data GRGB 1 , by applying a first gamma curve corresponding to a first frame compensation margin CM 1 to the first pixel data RGB 1 of the first frame. The compensation margin generator 130 generates the second frame compensation margin CM 2 based on the block compensation coefficients BSF and the first gamma applied pixel data GRGB 1 .

The gamma applier 150 generates second gamma applied pixel data GRGB 2 by applying a second gamma curve corresponding to the second frame compensation margin CM 2 to a second pixel data RGB 2 of a second frame, which is next frame of the first frame.

The block compensation coefficient storage 120 stores the block compensation coefficients BSF, selects some block compensation coefficients SBSF among the block compensation coefficients BSF based on a pixel coordinate COOR, and outputs the selected some block compensation coefficients SBSF. The pixel compensation coefficient generator 140 generate a pixel compensation coefficient PSF corresponding to the second pixel data RGB 2 by interpolating the selected some block compensation coefficients SBSF based on the pixel coordinate COOR. The first multiplier 160 generates an output pixel data OUTPUT_RGB by multiplying the second gamma applied pixel data GRGB 2 and the pixel compensation coefficient PSF. The pixel coordinate COOR may be a coordinate of a pixel corresponding to the second pixel data RGB 2 .

FIG. 2 illustrates an embodiment of a compensation margin generator, which, for example, may be included in the data compensator 100 of FIG. 1 . Referring to FIG. 2 , the compensation margin generator 130 includes a gamma applied block data generator GBDG 134 , a second multiplier 131 , a maximum compensated gamma applied data generator MDG 132 , and a compensation margin calculator CMC 133 .

The gamma applied block data generator 134 generates gamma applied block data GBD corresponding to the blocks in the first frame based on the first gamma applied pixel data GRGB 1 . In an example embodiment, the gamma applied block data generator 134 may generate an average value of the first gamma applied pixel data GRGB 1 corresponding to pixels in each of the blocks as the gamma applied block data GBD. In another example embodiment, the gamma applied block data generator 134 may generate a median value of the first gamma applied pixel data GRGB 1 corresponding to pixels in each of the blocks as the gamma applied block data GBD.

The second multiplier 131 generates compensated gamma applied block data GSFD by multiplying the block compensation coefficients BSF and the gamma applied block data GBD. The maximum compensated gamma applied block data generator 132 may output the largest value among the compensated gamma applied block data GSFD as a maximum compensated gamma applied block data MD. The compensation margin calculator 133 may calculate the second frame compensation margin CM 2 based on the maximum compensated gamma applied block data MD.

The compensation margin calculator 133 determines the second frame compensation margin CM 2 based on a ratio of the maximum compensated gamma applied block data MD to a limit value of the gamma applied block data GBD. In an example embodiment, the second frame compensation margin CM 2 may have a value of (the maximum compensated gamma applied block data (MD)/the limit value of the gamma applied block data (GBD))−1.

FIG. 3 illustrates an example of a first frame 200 including a plurality of blocks. Referring to FIG. 3 , the first frame 200 includes 9 blocks B 1 through B 9 . In another embodiment, the first frame 200 may include a different number of blocks. FIG. 3 illustrates that some pixel in the third block B 3 are used to form a logo image (e.g. “SBS”), and thus are degraded.

FIG. 4 illustrating an example of block compensation coefficients corresponding to blocks in the first frame of FIG. 3 . Referring to FIG. 4 , the block compensation coefficient generator 110 outputs 0.8 as the first block compensation coefficient BSF 1 corresponding to the first block B 1 in the first frame 200 . The block compensation coefficient generator 110 outputs 0.8 as the second block compensation coefficient BSF 2 corresponding to the second block B 2 in the first frame 200 . The block compensation coefficient generator 110 outputs 1.4 as the third block compensation coefficient BSF 3 corresponding to the third block B 3 in the first frame 200 . The block compensation coefficient generator 110 outputs 0.8 as the fourth block compensation coefficient BSF 4 corresponding to the fourth block B 4 in the first frame 200 . The block compensation coefficient generator 110 outputs 0.8 as the fifth block compensation coefficient BSF 5 corresponding to the fifth block B 5 in the first frame 200 . The block compensation coefficient generator 110 outputs 0.8 as the sixth block compensation coefficient BSF 6 corresponding to the sixth block B 6 in the first frame 200 . The block compensation coefficient generator 110 outputs 0.8 as the seventh block compensation coefficient BSF 7 corresponding to the seventh block B 7 in the first frame 200 . The block compensation coefficient generator 110 outputs 0.8 as the eighth block compensation coefficient BSF 8 corresponding to the eighth block B 8 in the first frame 200 . The block compensation coefficient generator 110 outputs 0.8 as the ninth block compensation coefficient BSF 9 corresponding to the ninth block B 9 in the first frame 200 .

In an example embodiment, the block compensation coefficients BSF 1 through BSF 9 may be inversely proportional to driving currents of the blocks B 1 through B 9 , respectively. Driving current of a first block B 1 may be an average of driving currents of pixels in the first block B 1 . Driving current of a second block B 2 may be an average of driving currents of pixels in the second block B 2 . Driving current of a third block B 3 may be an average of driving currents of pixels in the third block B 3 . The driving current of the remaining blocks B 4 through B 9 may be similarly determined.

FIG. 4 may be understood as a case where the third block compensation coefficient BSF 3 is larger than other block compensation coefficients BSF 1 , BSF 2 , BSF 4 through BSF 9 because the driving current of the third block B 3 is lower than the driving currents of other blocks B 1 , B 2 , B 4 through B 9 .

In another example embodiment, the block compensation coefficients BSF 1 through BSF 9 may be inversely proportional to driving voltages of the blocks B 1 through B 9 , respectively. Driving voltage of a first block B 1 may be an average of driving voltages of pixels in the first block B 1 . Driving voltage of a second block B 2 may be an average of driving voltages of pixels in the second block B 2 . Driving voltage of a third block B 3 may be an average of driving voltages of pixels in the third block B 3 . The driving voltages of the remaining blocks B 4 through B 9 may be determined in a similar manner.

FIG. 4 may be understood as a case where the third block compensation coefficient BSF 3 is larger than other block compensation coefficients BSF 1 , BSF 2 , BSF 4 through BSF 9 because the driving voltage of the third block B 3 is lower than the driving voltages of other blocks B 1 , B 2 , B 4 through B 9 .

In another example embodiment, the block compensation coefficients BSF 1 through BSF 9 may be proportional to degradation of pixels in the blocks B 1 through B 9 . FIG. 4 may be understood as a case that the third block compensation coefficient BSF 3 is larger than other block compensation coefficients BSF 1 , BSF 2 , BSF 4 through BSF 9 because the third block B 3 is more degraded than other blocks B 1 , B 2 , B 4 through B 9 .

FIG. 5 illustrates an example of an operation of the pixel compensation coefficient generator 140 in the data compensator of FIG. 1 . Referring to FIG. 5 , the pixel compensation coefficient generator 140 generates the pixel compensation coefficient PSF corresponding to the second pixel data RGB 2 when the second pixel data RGB 2 corresponds to a pixel P which have X-axis coordinate 320 and Y-axis coordinate 200 included in the second block B 2 .

The block compensation coefficient storage 120 may output a second block compensation coefficient BSF 2 of the second block B 2 including the pixel P, a third block compensation coefficient BSF 3 of a third block B 3 , a fifth block compensation coefficient BSF 5 of the fifth block B 5 , and a sixth block compensation coefficient BSF 6 of the sixth block B 6 as the selected some block compensation coefficients SBSF. The third block B 3 may neighbor to the second block B 2 through a right side of the second block B 2 . The fifth block B 5 may neighbor to the second block B 2 through a lower side of the second block B 2 . The sixth block B 6 may neighbor to the third block B 3 through a lower side of the third block B 3 , and the sixth block B 6 may neighbor to the fifth block B 5 through a right side of the fifth block B 5 .

The pixel compensation coefficient generator 140 may receive the second, third, fifth, and sixth block compensation coefficients BSF 2 , BSF 3 , BSF 5 , and BSF 6 as the selected come block compensation coefficients SBSF.

FIG. 5 shows a case that the pixel compensation coefficient generator 140 generates the pixel compensation coefficient PSF by X-axis interpolation after Y-axis interpolation. The pixel compensation coefficient generator 140 may generate the pixel compensation coefficient PSF by Y-axis interpolation after X-axis interpolation.

The pixel compensation coefficient generator 140 may calculate 0.8 (=0.8*30/150+0.8*120/150) as the first interpolated compensation coefficient ISF 1 by interlotting the second block compensation coefficient BSF 2 and the fifth block compensation coefficient BSF 5 . The pixel compensation coefficient generator 140 may calculate 0.92 (=1.4*30/150+0.8*120/150) as the second interpolated compensation coefficient ISF 2 by interlotting the third block compensation coefficient BSF 3 and the sixth block compensation coefficient BSF 6 . The pixel compensation coefficient generator 140 may calculate 0.872 (=0.8*80/200+0.92*120/200) as the pixel compensation coefficient PSF by interlotting the first interpolated compensation coefficient ISF 1 and the second interpolated compensation coefficient ISF 2 .

FIG. 6 illustrates an example of a location of degraded pixels among the first row pixels in the first frame. Referring to FIG. 6 , the case is discussed were the first frame 300 includes 600 pixels in X-axis and the first frame 300 includes 450 pixels in Y-axis. The first row pixels 310 , which is a set of pixels having 80 as Y-axis value, includes a first degraded pixel, second degraded pixels, and a third degraded pixel. The first degraded pixel is located on a point of (450, 80). The second degraded pixels are located between a point of (480, 80) and a point of (500, 80). The third degraded pixel is located on a point of (550, 80).

FIG. 7 illustrates an example of pixel compensation coefficients of the first row pixels of FIG. 6 . Referring to FIG. 7 , pixel compensation coefficient (PSF(450, 80) of the first degraded pixel, pixel compensation coefficients (PSF(480, 80)˜PSF(500, 80)) of the second degraded pixels, and pixel compensation coefficient (PSF(550, 80)) have 1.6 which is relatively greater than 0.8 which is the pixel compensation coefficient of the other pixel.

FIG. 8 illustrates an example of block compensation coefficients of blocks in the first frame of FIG. 6 . Referring to FIG. 8 , the third block compensation coefficient BSF 3 of the third block B 3 has 1.4 because of the existence of the first degraded pixel, the second degraded pixels, and the third degraded pixel. Remaining block compensation coefficients BSF 1 , BSF 2 , BSF 4 through BSF 9 , other than the third block compensation coefficient BSF 3 , have 0.8 because the remaining blocks B 1 , B 2 , B 4 through B 9 other than the third block B 3 are not degraded.

FIG. 9 illustrates an example of a compensation margin calculation according to a comparative example. Referring to FIG. 9 , in the comparative example, the second frame compensation margin CM 2 is calculated as 0.200 (=1.2/1−1) by only using the third block compensation coefficient BSF 3 , which has the maximum value among the block compensation coefficients BSF 1 through BSF 9 .

The gamma applier 150 generates the second gamma applied pixel data GRGB 2 by applying a compensation margin applied gamma curve GC_CMA to the second pixel data RGB 2 . The compensation margin applied gamma curve GC_CMA is generated by scaling the base gamma curve GC_ORIG along the Y-axis based on 0.2, the second frame compensation margin CM 2 . In this case, the first undisplayable gradation area AREA_ND 1 exists from 204 to 255 of the second gamma applied pixel data GRGB 2 . In the comparative example, the first undisplayable gradation area AREA_ND 1 is relatively huge.

FIGS. 10 and 11 illustrate an example of gamma applied block data of the compensation margin generator of FIG. 2 . Referring to FIGS. 10 and 11 , the case is illustrated where the gamma applied block data generator 134 generates 200 as the first gamma applied block data GBD 1 through the ninth gamma applied block data GBD 9 when all pixel data in the first frame 200 is the same each other.

FIGS. 12 and 13 illustrating examples of compensated gamma applied block data of the compensation margin generator of FIG. 2 . Referring to FIGS. 12 and 13 , the second multiplier 131 generates the first through ninth compensated gamma applied block data GSFD 1 through GSFD 9 by multiplying the first through ninth block compensation coefficients BSF 1 through BSF 9 of FIG. 4 and the first through ninth gamma applied block data GBD 1 through GBD 9 of FIG. 10 , respectively. The third compensated gamma applied block data GSFD 3 has 280, and remaining compensated gamma applied block data GSFD 1 , GSFD 2 , GSFD 4 through GSFD 9 have 160. Because the third block B 3 is degraded, the third compensated gamma applied block data GSFD 3 corresponding to the third block B 3 is greater than other compensated gamma applied block data GSFD 1 , GSFD 2 , GSFD 4 through GSFD 9 .

FIG. 14 illustrates an embodiment of a compensation margin calculation. Referring to FIG. 14 , the maximum compensated gamma applied block data generator 132 may output 280 , which is the third compensated gamma applied block data GSFD 3 , as the maximum compensated gamma applied block data MD. If the limit value of the first through ninth gamma applied block data GBD 1 through GBD 9 is 255, the compensation margin calculator 133 may calculate 0.098 (=(280/255)−1) as the second frame compensation margin CM 2

The gamma applier 150 generates the second gamma applied pixel data GRGB 2 by applying a compensation margin applied gamma curve GC_CMA to the second pixel data RGB 2 . The compensation margin applied gamma curve GC_CMA is generated by scaling the base gamma curve GC_ORIG along the Y-axis based on 0.098, the second frame compensation margin CM 2 . In this case, the second undisplayable gradation area AREA_ND 2 exists from 230 to 255 of the second gamma applied pixel data GRGB 2 . The second undisplayable gradation area AREA_ND 2 is relatively smaller than the first undisplayable gradation area AREA_ND 1 of FIG. 9 according to the comparative example.

FIG. 15 illustrates an embodiment of a display device 400 including a data compensator according to any of the aforementioned embodiments. Referring to FIG. 15 , a display device 400 includes a data compensator COMP 450 , a timing controller TIMING CNTRL 440 , a display panel DISPLAY PANEL 420 , a data driver DATA DRIVER 410 , and a scan driver SCAN DRIVER 430 .

The data compensator 450 includes a block compensation coefficient generator, a gamma applier, a compensation margin generator, a block compensation coefficient storage, a pixel compensation coefficient generator, and a first multiplier. The block compensation coefficient generator calculates block compensation coefficients corresponding to blocks in a first frame based on first pixel data RGB 1 of the first frame. The gamma applier generates first gamma applied pixel data by applying a first gamma curve corresponding to a first frame compensation margin to the first pixel data RGB 1 of the first frame. The gamma applier generates second gamma applied pixel data by applying a second gamma curve corresponding to a second frame compensation margin to a second pixel data RGB 2 of a second frame, which is next frame of the first frame.

The compensation margin generator generates the second frame compensation margin based on the block compensation coefficients and the first gamma applied pixel data. The block compensation coefficient storage stores the block compensation coefficients, selects some block compensation coefficients among the block compensation coefficients based on a pixel coordinate, and outputs the selected some block compensation coefficients. The pixel compensation coefficient generator generates a pixel compensation coefficient corresponding to the second pixel data by interpolating the selected some block compensation coefficients based on the pixel coordinate. The first multiplier generates the output pixel data RGBC by multiplying the second gamma applied pixel data and the pixel compensation coefficient.

The data compensator 450 may have the same or similar structure with the data compensator 100 of FIG. 1 . The data compensator 450 may be understood based on the references to FIGS. 1 through 14 .

The timing controller 440 generates a data driver control signal DCS and a scan driver control signal SCS based on the output pixel data RGBC. The display panel 420 includes a plurality of pixels 421 . The data driver 410 generates a plurality of data signals based the data driver control signal DCS and provides the data signals to the pixels 421 through a plurality of data signal lines D 1 , D 2 through DN. The scan driver 430 generates a plurality of scan signals based on the scan driver control signal SCS. The scan driver 430 provides the scan signals to the pixels 421 through a plurality of scan signal lines S 1 , S 2 through SM.

FIG. 16 illustrates an embodiment of an electronic device 500 which includes a display device according to any of the aforementioned embodiments. Referring to FIG. 16 , the electronic device 500 includes a processor 510 , a memory device 520 , a storage device 530 , an input/output (I/O) device 540 , a power supply 550 , and a display device 560 . The electronic device 500 may further include a plurality of ports for communicating a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. Although the electronic device 500 is implemented as a smart-phone, a kind of the electronic device 500 is not limited thereto.

The processor 510 may perform various computing functions. The processor 510 may be a micro processor, a central processing unit (CPU), etc. The processor 510 may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, the processor 510 may be coupled to an extended bus such as a peripheral component interconnection (PCI) bus.

The memory device 520 may store data for operations of the electronic device 500 . For example, the memory device 520 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc, and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.

The storage device 530 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I/O device 540 may be an input device such as a keyboard, a keypad, a touchpad, a touch-screen, a mouse, etc, and an output device such as a printer, a speaker, etc. The power supply 550 may provide a power for operations of the electronic device 500 . The display device 560 may communicate with other components via the buses or other communication links.

The display device 560 may be the display device 400 of FIG. 15 . The display device 560 may be understood based on the references to FIGS. 1 through 15 .

The example embodiments may be applied to any electronic system 500 having the display device 560 . For example, the present embodiments may be applied to the electronic system 500 , such as a digital or 3D television, a computer monitor, a home appliance, a laptop, a digital camera, a cellular phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a MP3 player, a portable game console, a navigation system, a video phone, etc.

The present invention may be applied to an OLED display device and an electronic device including the same. For example, the invention may be applied to a monitor, a television, a computer, a laptop computer, a digital camera, a mobile phone, a smartphone, a smart pad, a PDA, a PMP, a MP3 player, a navigation system, and camcorder.

The compensation coefficient generators, gamma appliers, compensation margin generators, pixel compensation coefficient generator, multipliers, and/or other generators or processing features of the embodiments disclosed herein may be implemented in logic which, for example, may include hardware, software, or both. When implemented at least partially in hardware, the compensation coefficient generators, gamma appliers, compensation margin generators, pixel compensation coefficient generator, multipliers, and/or other generators or processing features may be, for example, any one of a variety of integrated circuits including but not limited to an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-chip, a microprocessor, or another type of processing or control circuit.

When implemented in at least partially in software, the compensation coefficient generators, gamma appliers, compensation margin generators, pixel compensation coefficient generator, multipliers, and/or other generators or processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.

The methods, processes, and/or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the following claims.