Power converter with pseudo-constant-on-time control and the control circuit and method thereof

This application claims the benefit of CN application No. 201410300831.0, filed on Jun. 26, 2014, and incorporated herein by reference.

The present invention relates generally to electronic circuits, and more particularly but not exclusively to power converters and control circuits and methods thereof.

The switching frequency varies with an output voltage V OUT in a typical power converter with COT (constant-on-time) control. To keep the switching frequency constant regardless of variation of the output voltage V OUT , PCOT (pseudo-constant-on-time) control is often applied in the power converters.

FIG. 1 illustrates a prior art PCOT power converter 100 . The PCOT power converter 100 as illustrated comprises an on-time generating circuit 101 , a comparison circuit 102 , a logic circuit 103 , a switching circuit 104 , a ramp compensation circuit 105 and a feedback circuit 106 .

In the illustrated PCOT power converter 100 of FIG. 1 , the on time T ON of a main switch M 1 of the switching circuit 104 is determined by the on-time generating circuit 101 as:

The amplitude V SLOPE(PP) of a ramp compensation signal V SLOPE generated by the ramp compensation circuit 105 is:

By substituting equation (1) into equation (2), there is:

As can be observed from equation (3), in the PCOT power converter 100 of FIG. 1 , the amplitude V SLOPE(PP) of the ramp compensation signal V SLOPE is partly determined by the duty cycle D of the PCOT power converter 100 . In more detail, the larger the duty cycle D is, the smaller the amplitude V SLOPE(PP) is. Such small amplitude of the ramp compensation signal may easily result in an unstable system.

Embodiments of the present invention are directed to a control circuit for a power converter. The power converter converts an input voltage into an output voltage. The power converter has a switching circuit. The switching circuit has a main switch, a freewheeling element and an inductor having a first terminal and a second terminal. The control circuit has an on-time generating circuit, a ramp compensation circuit, a ramp regulating circuit, a comparison circuit and a logic circuit. The on-time generating circuit generates an on-time control signal. The ramp compensation circuit generates a ramp compensation signal. The amplitude of the ramp compensation signal is proportional to 1−D with a scaling factor. D represents the duty cycle of the main switch. The ramp regulating circuit generates a ramp regulating signal. The amplitude of the ramp regulating signal is proportional to D with the scaling factor. The comparison circuit is electrically coupled to the ramp compensation circuit and the ramp regulating circuit. The comparison circuit is configured to generate a comparison signal based on a feedback signal representative of the output voltage, a reference signal and the sum of the ramp compensation signal and the ramp regulating signal. The logic circuit generates a control signal based on the on-time control signal and the comparison signal to control the main switch and the freewheeling element.

Embodiments of the present invention are also directed to a power converter for converting an input voltage into an output voltage. The power converter has a switching circuit and a control circuit. The switching circuit has a main switch, a freewheeling element and an inductor having a first terminal and a second terminal. The control circuit has an on-time generating circuit, a ramp compensation circuit, a ramp regulating circuit, a comparison circuit and a logic circuit. The on-time generating circuit generates an on-time control signal. The ramp compensation circuit generates a ramp compensation signal. The amplitude of the ramp compensation signal is proportional to 1−D with a scaling factor. D represents the duty cycle of the main switch. The ramp regulating circuit generates a ramp regulating signal. The amplitude of the ramp regulating signal is proportional to D with the scaling factor. The comparison circuit is electrically coupled to the ramp compensation circuit and the ramp regulating circuit. The comparison circuit is configured to generate a comparison signal based on a feedback signal representative of the output voltage, a reference signal and the sum of the ramp compensation signal and the ramp regulating signal. The logic circuit generates a control signal based on the on-time control signal and the comparison signal to control the main switch and the freewheeling element.

Embodiments of the present invention are further directed to a control method for a power converter. The power converter has a switching circuit. The switching circuit has a main switch and a freewheeling element. And the switching circuit is configured to provide an output voltage. The control method has the following steps: generating an on-time control signal; generating a ramp compensation signal, wherein the amplitude of the ramp compensation signal is proportional to 1−D with a scaling factor, and wherein D represents the duty cycle of the main switch; generating a ramp regulating signal, wherein the amplitude of the ramp regulating signal is proportional to D with the scaling factor; generating a comparison signal based on a feedback signal representative of the output voltage, a reference signal and the sum of the ramp compensation signal and the ramp regulating signal; and controlling the main switch and the freewheeling element on and off according to the on-time control signal and the comparison signal.

The present invention can be further understood with reference to the following detailed description and the appended drawings, wherein like elements are provided with like reference numerals.

FIG. 1 illustrates a prior art PCOT power converter 100 ;

FIG. 2 illustrates a power converter 200 in accordance with an embodiment of the present invention;

FIG. 3A ˜ FIG. 3C illustrate an optional current circuit 30 A for implementation of the current circuit of FIG. 2 in accordance with an embodiment of the present invention;

FIG. 4 illustrates a power converter 400 in accordance with an embodiment of the present invention;

FIG. 5 illustrates a ramp compensation method 500 for a power converter in accordance with an embodiment of the present invention.

The present invention is now described. While it is disclosed in its preferred form, the specific embodiments of the invention as disclosed herein and illustrated in the drawings are not to be considered in a limiting sense. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Indeed, it should be readily apparent in view of the present description that the invention may be modified in numerous ways. Among other things, the present invention may be embodied as devices, methods, software, and so on. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. The following detailed description is, therefore, not to be taken in a limiting sense.

Throughout the specification, the meaning of “a,” “an,” and “the” may also include plural references.

FIG. 2 illustrates a power converter 200 in accordance with an embodiment of the present invention. The power converter 200 comprises a switching circuit 204 , a feedback circuit 207 and a control circuit which comprises an on-time generating circuit 201 , a comparison circuit 202 , a logic circuit 203 , a ramp compensation circuit 205 and a ramp regulating circuit 206 .

The on-time generating circuit 201 is configured to generate an on-time control signal COT to control the on time of the switch/switches of the switching circuit 204 . The on-time generating circuit 201 comprises a resistor R FREQ , a capacitor C TON , a switch S TON and a comparator CMP 1 . The resistor R FREQ has a first terminal and a second terminal, wherein the first terminal is configured to receive an input voltage V IN . The capacitor C TON has a first terminal and a second terminal, wherein the first terminal is electrically coupled to the second terminal of the resistor R FREQ , and the second terminal is electrically coupled to a reference ground. The switch S TON has a first terminal, a second terminal and a control terminal, wherein the first terminal is electrically coupled to the second terminal of the resistor R FREQ , and the second terminal is electrically coupled to the reference ground. The comparator CMP 1 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is electrically coupled to the first terminal of the capacitor C TON to receive the voltage thereacross, and the second terminal is configured to receive a reference signal V REF1 . The comparator CMP 1 compares the voltage across the capacitor C TON with the reference signal V REF1 and generates the on-time control signal COT at the output terminal. It should be noted that the on-time generating circuit 201 of FIG. 2 is for illustrative purpose and should not be construed as limiting the scope of the present invention in any manner, of course, other embodiments are contemplated where the on-time generating circuit may take any other appropriate configuration.

As an option, the switching circuit 204 is implemented with a synchronous buck topology in FIG. 2 , as illustrated. The switching circuit 204 comprises a main switch M 1 , a freewheeling switch M 2 , an inductor L and a capacitor C OUT . The switching circuit 204 is configured to convert the input voltage V IN into an output voltage V OUT by controlling the switching actions of the main switch M 1 and the freewheeling switch M 2 . One terminal of the main switch M 1 is configured to receive the input voltage V IN and the other terminal is electrically coupled to one terminal of the freewheeling switch M 2 . The other terminal of the freewheeling switch M 2 is electrically coupled to the reference ground. The inductor L has a first terminal and a second terminal, wherein the first terminal is electrically coupled to the common node of the main switch M 1 and the freewheeling switch M 2 . The capacitor C OUT is electrically coupled between the second terminal of the inductor L and the reference ground. The voltage across the capacitor C OUT serves as the output voltage V OUT .

In one embodiment, the main switch M 1 and/or the freewheeling switch M 2 may be accomplished with any controllable semiconductor switching device, such as a Metal-Oxide-Semiconductor filed effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT) etc. In another embodiment, the freewheeling switch M 2 may be alternatively replaced by any other type of freewheeling device, like a diode. In further another embodiment, the switching circuit 204 may be implemented with any appropriate converting topologies, such as a buck-boost converter.

The ramp compensation circuit 205 comprises a compensation resistor R C and a compensation capacitor C C . In particular, the compensation resistor R C has a first terminal and a second terminal, wherein the first terminal is electrically coupled to the first terminal of the inductor L. The compensation capacitor C C has a first terminal and a second terminal, wherein the first terminal is electrically coupled to the second terminal of the compensation resistor R C , and the second terminal is electrically coupled to the second terminal of the inductor L. The common node of the compensation resistor R C and the compensation capacitor C C serves as an output terminal of the ramp compensation circuit 205 to provide a ramp compensation signal V SLOPE having an amplitude V SLOPE(PP) which can be calculated by equation (3).

Persons of ordinary skill in the art will recognize that, the ramp compensation circuit 205 of FIG. 2 is for illustrative purpose and should not be construed as limiting the scope of the present invention in any manner, in another embodiment, the ramp compensation circuit may take any other appropriate configuration, just by way of example, a ramp compensation circuit accomplished with digital circuits, or a ramp compensation circuit capable of emulating the current flowing through the inductor L with a configuration of current sources and/or current sinks.

The ramp regulating circuit 206 comprises a current circuit and the compensation capacitor C C of the ramp compensation circuit 205 . The current circuit is electrically coupled to the first terminal of the compensation capacitor C C to charge or discharge the compensation capacitor C C , which in turn provides a ramp regulating signal V ADJ at the first terminal of the compensation capacitor C C . When the main switch M 1 is turned on, the current circuit delivers a current with an absolute value

to the compensation capacitor C C . While when the freewheeling switch M 2 is turned on, the current circuit absorbs a current with an absolute value

V OUT R C × D 1 - D

from the compensation capacitor C C . More specifically, as illustrated in FIG. 2 , the current circuit comprises a current source CS 1 , a current sink CS 2 and a switch S 1 . The current source CS 1 is electrically coupled to the first terminal of the compensation capacitor C C to deliver a current I 1 with an absolute value

to the compensation capacitor C C . The current sink CS 2 is serially coupled to the switch S 1 and the first terminal of the compensation capacitor C C and absorbs a current I 2 with an absolute value

V OUT R C × D 1 - D

from the compensation capacitor C C , wherein the switch S 1 and the freewheeling switch M 2 are turned on and off synchronously.

Thus, the amplitude V ADJ(PP) of the ramp regulating signal V ADJ can be expressed as:

Applying equations (3) and (4), the amplitude V SLOPE1(PP) of the sum V SLOPE1 of the ramp compensation signal and the ramp regulating signal can be expressed as:

As can be observed from equation (5), with a given capacitor C TON and resistors R FREQ and R C , and also a given reference signal V REF1 , the amplitude V SLOPE1(PP) of the sum signal V SLOPE1 is a constant value and does not vary with the duty cycle D of the power converter 200 , thus resulting in a more stable system.

The feedback circuit 207 comprises a voltage divider consisting of serially-connected resistors R 1 and R 2 . The feedback circuit 207 is electrically coupled between the output terminal of the switching circuit 204 and the reference ground and is configured to provide a feedback signal V FB at the common node of the resistors R 1 and R 2 based on the output voltage V OUT .

The comparison circuit 202 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is electrically coupled to the output terminals of the feedback circuit 207 , the ramp compensation circuit 205 and the ramp regulating circuit 206 to receive the sum V SLOPE1 of the feedback signal V FB , the ramp compensation signal V SLOPE and the ramp regulating signal V ADJ , and the second input terminal is configured to receive a reference signal V REF2 . The comparison circuit 202 compares the sum V SLOPE1 with the reference signal V REF2 and thereby generates a comparison signal SET at the output terminal.

The logic circuit 203 has a first input terminal and a second input terminal, wherein the first input terminal is electrically coupled to the on-time generating circuit 201 to receive the on-time control signal COT, and the second input terminal is electrically coupled to the comparison circuit 202 to receive the comparison signal SET. The logic circuit 203 is configured to generate controls signals Q and Q′ based on the on-time control signal COT and the comparison signal SET so as to control the switching actions of the main switch M 1 and the freewheeling switch M 2 of the switching circuit 204 as well as the switch actions of the switch S TON of the on-time generating circuit 201 .

The power converter 200 illustrated in FIG. 2 is so configured to operate in a Continuous-Conduction-Mode (CCM). In another embodiment where the power converter 200 operates in a Discontinuous-Conduction-Mode (DCM), the current source CS 1 may be coupled to the first terminal of the compensation capacitor C C through an additional switch, wherein the additional switch is turned off when both the main switch M 1 and the freewheeling switch M 2 are in an off state and remains on in the left time of a switching cycle.

FIG. 3A illustrates an optional current circuit 30 A for implementation of the current circuit of FIG. 2 in accordance with an embodiment of the present invention. As illustrated in FIG. 3A , the current circuit 30 A comprises current mirrors 301 , 302 and 303 , wherein each pair of matched transistors of the current mirrors 301 , 302 and 303 have substantially identical parameters. The current mirror 301 is configured to receive the output voltage V OUT and to further provide a reference current

at an input terminal. Thus, the currents I MP1 and I MP2 respectively provided by transistors MP 1 and MP 2 at two output terminals of the current mirror 301 have the same value of

V OUT R C ,

in accordance with the well known operating principle of current mirrors. In current mirror 302 , a switch S 1 is serially coupled with a transistor MN 1 and is controlled by the control signal Q′, thus making the on time of the switch S 1 equal to (1−D)×T and the off time thereof equal to D×T. Thus, there is (1−D)×I MN2 =(1−D)×I MN3 =I MP1 . As a result, the currents I MN2 and I MN3 respectively provided by the transistors MN 2 and MN 3 at two output terminals of the current mirror 302 have the same value of

V OUT R C × 1 1 - D .

In current mirror 303 , a switch S 2 is serially coupled with a transistor MP 3 and is controlled by the control signal Q. The current mirror 303 is configured to receive the current I MN3 , thus, the current provided by the transistor MP 3 is

FIG. 3B illustrates an equivalent circuit 30 B of the current circuit 30 A of FIG. 3A . As the switch S 2 is controlled by the control signal Q while the switch S 1 is controlled by the complementary signal Q′ of the control signal Q, the equivalent circuit 30 B may be further equivalent to the circuit 30 C as illustrated in FIG. 3C . As shown by the equivalent circuit 30 C, the current circuit 30 A of FIG. 3A is an exemplary circuit to implement the current circuit of FIG. 2 .

FIG. 4 illustrates a power converter 400 in accordance with an embodiment of the present invention. The power converter 400 comprises a switching circuit 404 , a feedback circuit 407 and a control circuit which comprises an on-time generating circuit 401 , a comparison circuit 402 , a logic circuit 403 , a ramp compensation circuit 405 and a ramp regulating circuit 406 .

The on-time generating circuit 401 is configured to generate an on-time control signal COT to control the on time of the switch/switches of the switching circuit 404 . The feedback circuit 407 is configured to receive an output voltage V OUT provided by the switching circuit 404 and to generate a feedback voltage V FB based on the output voltage V OUT .

The ramp compensation circuit 405 is configured to generate a ramp compensation signal V SLOPE having an amplitude V SLOPE(PP) . The amplitude V SLOPE(PP) of the ramp compensation signal V SLOPE is proportional to 1−D with a scaling factor K, that is:

V SLOPE(PP) =K ×(1− D )   (6)

wherein D represents the duty cycle of the main switch of the switching circuit 404 .

The ramp regulating circuit 406 is configured to generate a ramp regulating signal V ADJ having an amplitude V ADJ(PP) . The amplitude V ADJ(PP) of the ramp regulating signal V ADJ is proportional to the duty cycle D with the same scaling factor K, that is:

V ADJ(PP) =K×D   (7)

V SLOPE1 represents the sum of the ramp compensation signal V SLOPE and the ramp regulating signal V ADJ , wherein the amplitude V SLOPE1(PP) of the sum signal V SLOPE1 may be expressed as:

V SLOPE1(PP) =K ×(1 −D )+ K×D=K   (8)

As can be observed from equation (8), the amplitude V SLOPE1(PP) of the sum signal V SLOPE1 is irrelevant to the duty cycle D as the scaling factor K is constant, thus making a more stable system.

The comparison circuit 402 is configured to compare the sum of the feedback signal V FB and the sum signal V SLOPE1 with a reference signal V REF2 to generate a comparison signal SET.

The logic circuit 403 is configured to receive the on-time control signal COT and the comparison signal SET and to generate a control signal CTRL based on the on-time control signal COT and the comparison signal SET. The switching circuit 404 is configured to receive an input voltage V IN and to convert the input voltage V IN into the output voltage V OUT based on the control signal CTRL.

FIG. 5 illustrates a ramp compensation method 500 for a power converter in accordance with an embodiment of the present invention. The power converter comprises a switching circuit which comprises an inductor, a main switch M 1 and a freewheeling element M 2 . The switching circuit is configured to generate an output voltage V OUT . As shown in FIG. 5 , the ramp compensation method 500 comprises steps 501 - 505 . When the compensation method 500 gets started, step 501 is performed to generate an on-time control signal. A ramp compensation signal is provided in step 502 , wherein the amplitude of the ramp compensation signal is directly proportional to 1−D, and wherein D represents the duty cycle of the main switch Ml. And a ramp regulating signal is provided in step 503 , wherein the amplitude of the ramp regulating signal is directly proportional to the duty cycle D. In the following step 504 , it is performed to compare a reference signal with the sum of the ramp compensation signal, the ramp regulating signal and a feedback signal representative of the output voltage V OUT and to thereby generate a comparison result. Then in the next step 505 , the main switch M 1 and the freewheeling element M 2 are turned on and off according to the on-time control signal and the comparison result.

In one embodiment, the ramp compensation signal is provided by a ramp compensation circuit comprising a compensation resistor R C electrically coupled to the inductor and a compensation capacitor C C . In another embodiment, the step 503 of providing the ramp regulating signal comprises: delivering a current with an amplitude of

to the compensation capacitor C C when the main switch M 1 is turned on; absorbing a current with an amplitude of

V OUT R C × D 1 - D

from the compensation capacitor C C when the freewheeling element M 2 is turned on; providing the voltage across the compensation capacitor C C as the ramp compensation signal.

It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described herein above. Rather the scope of the present invention is defined by the appended claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not in the prior art.