Organic light-emitting display apparatus

Korean Patent Application No. 10-2015-0010026, filed on Jan. 21, 2015, and entitled, “Organic Light-Emitting Display Apparatus,” is incorporated by reference herein in its entirety.

1. Field

One or more embodiments herein relate to organic light-emitting display apparatus.

2. Description of the Related Art

A variety of flat panel displays have been developed. Examples include liquid crystal displays, field emission displays, plasma display panels, and organic light-emitting displays. These displays are lighter and larger than cathode ray tube displays.

In an organic light-emitting display, pixels emit light when electrons and holes combine in an emission layer that includes organic compounds. This type of display has fast response time, low power consumption, and excellent brightness, color purity, and driving voltage characteristics.

In operation, light is emitted from color pixels to form an image. Each pixel emits light with a brightness that is based on a data voltage received by a pixel circuit. The pixel circuit includes a plurality of transistors and one or more storage capacitors for controlling driving current supplied to an organic light emitting diode (OLED) of the pixel.

In accordance with one or more embodiments, an organic light-emitting display apparatus includes a plurality of pixel circuits, each of the pixel circuits to receive a data signal and to output a driving current to an output node based on the data signal, the pixel circuits to sequentially operate in an anode initialization period, a threshold voltage compensation period, a data write period, and an emission period; and a plurality of organic light-emitting diodes to emit light based on the driving currents transferred through the output nodes of respective ones of the pixel circuits, wherein: the pixel circuits are in multiple rows and multiple columns, each of the pixel circuits includes an anode initialization transistor to output an initialization voltage to the output node based on a first control signal received through a first control line, and the first control line connected to the anode initialization transistor of a pixel circuit in an odd row is different from the first control line connected to the anode initialization transistor of a pixel circuit in an even row.

Each of the pixel circuits may include a capacitor, a driving transistor, a switching transistor, and an emission control transistor, the capacitor has a first electrode connected to a first node and a second electrode connected to the output node, the driving transistor has a gate electrode connected to the first node, a first electrode connected to a second electrode of the emission control transistor, and a second electrode connected to the output node, the switching transistor has a gate electrode connected to a scan line, a first electrode connected to a data line, and a second electrode connected to the first node, and the emission control transistor has a gate electrode connected to a second control line and a first electrode connected to a first power supply.

A second control line connected to an emission control transistor of the pixel circuit in the odd row may be different from a second control line connected to an emission control transistor of the pixel circuit in the even row. The anode initialization transistor may have a first electrode connected to the data line and a second electrode connected to the output node, and the anode initialization transistor may output a voltage from the data line to the output node based on the first control signal.

The data write period of the pixel circuit in the odd row may overlap the emission period of the pixel circuit in the even row. The data write period of the pixel circuit in the even row may overlap the emission period of the pixel circuit in the odd row. The anode initialization transistor may output the initialization voltage to the output node during the anode initialization period based on the first control signal.

During the threshold voltage compensation period, the emission control transistor may be turned on based on a second control signal received through the second control line and may output a first voltage received through the first power supply to the first electrode of the driving transistor, and the switching transistor may output a reference voltage to the first node based on a scan signal received through the scan line.

The reference voltage may be set such that a level of a voltage applied to the output node is lower than a level of a turn-on voltage of the organic light-emitting diode. A level of the initialization voltage may be lower than a level of a turn-on voltage of the organic light-emitting diode.

In accordance with one or more other embodiments, an organic light-emitting display apparatus includes a plurality of pixel circuits, each of the pixel circuits to receive a data signal and to output a driving current to an output node based on the data signal, the pixel circuits to sequentially operate in an anode initialization period, a threshold voltage compensation period, a data write period, and an emission period; and a plurality of organic light-emitting diodes to emit light based on the driving currents transferred through the output nodes of respective ones of the pixel circuits, wherein: the pixel circuits are in multiple rows and multiple columns, each of the pixel circuits includes an anode initialization transistor having a first electrode connected to an initialization voltage line, a second electrode connected to the output node, and a gate electrode connected to a first control line, the anode initialization transistor to output an initialization voltage from the initialization voltage line to the output node based on a first control signal received through the first control line, and a first control line connected to an anode initialization transistor of a pixel circuit in an odd row is different from a first control line connected to an anode initialization transistor of a pixel circuit in an even row.

The data write period of the pixel circuit in the odd row may overlap the emission period of the pixel circuit in the even row, and the data write period of the pixel circuit in the even row may overlap the emission period of the pixel circuit in the odd row. An initialization voltage may be applied to the initialization voltage line during the anode initialization period, and a level of the data signal may be substantially equal to a level of a reference voltage during the threshold voltage compensation period. The reference voltage may be set such that a level of a voltage applied to the output node is lower than a level of a turn-on voltage of the organic light-emitting diode. A level of the initialization voltage may be lower than a level of a turn-on voltage of the organic light-emitting diode.

In accordance with one or more other embodiments, a display includes a first pixel circuit to output a driving current to a first light emitter; and a second pixel circuit to output a driving current to a second light emitter; wherein the first pixel circuit is in an odd row and the second pixel circuit is in an even row, each of the first and second pixel circuits including an anode initialization transistor to output an initialization voltage to an output node based on a first control signal from a first control line, the first control line connected to the first pixel circuit different from the first control line connected to the second pixel circuit.

Each of the first and second pixel circuits may operate in an anode initialization period, a threshold voltage compensation period, a data write period, and an emission period. The anode initialization transistor of each of the first and second pixel circuits may output the initialization voltage during the anode initialization period. A level of the initialization voltage may be lower than a level of a turn-on voltage of the light emitter in each of the first and second pixel circuits. A data write period of one of the first or second pixel circuits may overlap an emission period of the other of the first or second pixel circuits.

Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:

FIG. 1 illustrates an embodiment of an organic light-emitting display apparatus;

FIG. 2 illustrates an embodiment of a display panel;

FIG. 3 illustrates an embodiment of a pixel circuit;

FIG. 4 illustrates an example of control signals for the pixel circuit;

FIG. 5 illustrates an embodiment of pixel circuits;

FIG. 6 illustrates an example of control signals for the pixel circuits;

FIG. 7 illustrates another embodiment of pixel circuits; and

FIG. 8 illustrates an example of control signals for the pixel circuits in FIG. 7 .

Example embodiments are described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. The embodiments may be combined to form additional embodiments. Like reference numerals refer to like elements throughout.

FIG. 1 illustrates an embodiment of an organic light-emitting display apparatus 100 which includes a timing control unit 110 , a data driving unit 120 , a scan driving unit 130 , a control driving unit 140 , and a display panel 150 . The organic light-emitting display apparatus 100 includes a first power supply ELVDD and a second power supply ELVSS.

The timing control unit 110 controls the data driving unit 120 , the scan driving unit 130 , and the control driving unit 140 based on control (e.g., synchronization) signals. The timing control unit 110 generates new data by changing bits of externally applied pixel data. The new data may compensate for mobility and a threshold voltage of a driving transistor in each of the pixels.

The data driving unit 120 generates data signals corresponding to data from the timing control unit 110 . The data driving unit 120 supplies data signals to data lines in synchronization with scan signals from the scan driving unit 130 through scan lines during one frame time of a data write period. In addition, the data driving unit 120 supplies an initialization voltage and/or a reference voltage to the data lines. The reference voltage is used for initializing the gate electrode of the driving transistor and is set to a predetermined voltage. The initialization voltage is used for initializing anode electrodes of the OLEDs in the pixels and is set to a voltage at which the OLEDs do not emit light.

The scan driving unit 130 supplies scan signals to the scan lines. For example, as illustrated in FIG. 4 , the scan driving unit 130 may supply the scan signals to the scan lines during one frame time of an anode initialization period and a threshold voltage (V th ) compensation period. The scan driving unit 130 may sequentially supply the scan signals to the scan lines during a data write period. The scan signal is set to a voltage sufficient to turn on the transistors in the pixels. For example, when PMOS transistors are in the pixels, the scan signal is set to a low voltage. When NMOS transistors are in the pixels, the scan signal is set to a high voltage.

The control driving unit 140 supplies control signals to one or more control lines, which, for example, may be commonly connected to the pixels. The control driving unit 140 may supply an emission control signal to turn on emission control transistors in the pixels during the emission period.

The display panel 150 includes the pixels in regions partitioned by the scan lines and the data lines. The pixels charge data signals during the data write period and emit light based on the charged data signals during the emission period. The pixels control an amount of current flowing from the first power supply ELVDD through the OLED to the second power supply ELVSS based on the data signal.

In FIG. 1 , the control lines receive the control signals from the control driving unit 140 . In another embodiment, the control lines may receive the control signals from the scan driving unit 130 .

FIG. 2 illustrates an arrangement of the pixels in the display panel 150 .

Referring to FIG. 2 , the display panel 150 includes the pixels in regions partitioned by the scan lines and the data lines. The pixels are arranged in multiple rows and multiple columns. Pixels PX 1 to PX 2n in the left first row will be described in greater detail below.

The pixels include pixels in odd rows and pixels in even rows. The scan lines may be between pixels in a first direction, and the data lines may be between pixels in a second direction. The first direction may be a horizontal direction and the second direction may be a vertical direction, or vice versa.

When apparatus 100 is a simultaneous emission type organic light-emitting display apparatus, a scan operation may be sequentially performed on the scan lines in the first direction. In the scan operation, data signals of an image frame are sequentially written to first pixels connected to the scan lines. The first pixels may be in the first row, e.g., pixel PX 1 and subsequent pixels in the horizontal direction from the pixel PX 1 .

When writing of data to the first pixels has been completed, data is written to second pixels. The second pixels may be pixels in the second row, e.g., pixel PX 2 and subsequent pixels in the horizontal direction from the pixel PX 2 .

The scan line connected to the first pixels may be different from the scan line connected to the second pixels. For example, the scan lines may include scan lines from the first scan line connected to the pixels in the first row (pixel PX 1 and subsequent pixels in the horizontal direction from the pixel PX 1 ) to the 2n th scan line connected to the pixels in the last row (pixel PX 2n and subsequent pixels in the horizontal direction from the pixel PX 2n ).

FIG. 3 illustrate an embodiment of a pixel circuit of the organic light-emitting display apparatus 100 . Referring to FIG. 3 , the pixel circuit included a driving transistor TR d , an emission control transistor TR ge , a switching transistor TR s , capacitor Cst, and an OLED. The pixel circuit may be used, for example, in a simultaneous emission type organic light-emitting display apparatus. The pixel circuit may be representative of the pixels circuits in the other pixels.

In the pixel circuit, the driving transistor TR d has a gate electrode connected to a second electrode of the switching transistor TR s and a first electrode of the capacitor C st . A first electrode of the driving transistor TR d is connected to a second electrode of the emission control transistor TR ge , and a second electrode of the driving transistor TR d is connected to an anode electrode of the OLED.

The switching transistor TR s has a first electrode is connected to a data line DL, and a gate electrode of the switching transistor TR s is connected to a scan line SL.

The emission control transistor TR ge has a first electrode connected to the first power supply ELVDD and a gate electrode connected to an emission control line and receives an emission control signal EC.

A second electrode of the capacitor C st is connected to the anode electrode of the OLED and the second electrode of the driving transistor TR d through an output node. A cathode electrode of the OLED is connected to the second power supply ELVSS.

A voltage V G of the gate node corresponds to a voltage supplied from the data line DL through the switching transistor TR s . The switching transistor TR s is turned on based on the scan signal supplied from the scan line SL and outputs a voltage supplied from the data line DL to the gate node.

The capacitor C st is charged with a voltage applied to the gate node. The voltage charged in the capacitor C st corresponds to an anode voltage V A of the OLED.

The emission control transistor TR ge is turned on based on the emission control signal EC from the emission control line and outputs a voltage of the first power supply ELVDD to the driving transistor TR d .

A current corresponding to the voltage of the first power supply ELVDD, a threshold voltage of the driving transistor TR d , and a data voltage supplied from the data line DL flows through the OLED, and the OLED emits light corresponding to the current.

FIG. 4 illustrates an example of control signals for the pixel circuit of FIG. 3 . The control signals include signals and voltages applied to the pixel circuit of FIG. 3 during one frame time. In FIG. 4 , the vertical axis represents the first scan line SL[ 1 ] connected to the pixels in the first row from above, the n th scan line SL[n] connected to the pixels in the last row, the emission control signal EC, the voltage of the second power supply ELVSS, the voltage of the first power supply ELVDD, and the data signal DATA.

The frame time may be divided into an anode initialization period, a threshold voltage (V th ) compensation period, a data write period, and an emission period. In the anode initialization period, the voltage of the first power supply ELVDD is reduced to a low voltage to initialize the anode voltage V A to a low voltage. At this time, the emission control signal EC is maintained at a high level so that the emission control transistor TR ge maintains a turned-on state. The data signal has a level of a reference voltage V ref .

In the threshold voltage (V th ) compensation period, the data signal is set to a level of the reference voltage V ref so that a level of a gate node voltage V G becomes equal to the level of the reference voltage V ref . The anode voltage V A may therefore have a level of V ref −V th , and thus the threshold voltage of the driving transistor TR d is compensated.

In the data write period, data voltages are sequentially written to the gate nodes of the pixels. At this time, data voltages are sequentially written to pixels respectively connected to the first to nth scan lines SL[ 1 ] to SL[n].

In the emission period, since the emission control signal EC has a high voltage, a high voltage of the first power supply ELVDD is supplied to the pixel circuit by the emission control transistor TR ge , a current corresponding to the data voltage written to each pixel is supplied to the OLED through the driving transistor TR d , and the OLED emits light based on the magnitude of the current supplied through the driving transistor TR d .

Since such a simultaneous emission type pixel circuit has a sufficient threshold voltage compensation time, the threshold voltage compensation is facilitated and IR-drop compensation is achieved.

However, in the simultaneous emission type pixel circuit as illustrated in FIG. 3 , as the resolution of the display panel 150 and the size of the display panel 150 increase, the number of pixels in the horizontal direction increases and the load of the scan lines and the data lines increases, thereby causing an increase in RC delay. Consequently, the data write time increases and the emission time decreases. Due to this decrease in emission time, light with higher brightness may be emitted during the emission period. However, this results in an increase in emission current.

When the emission current increases, IR-drop between ELVDD and ELVSS increases. Thus, the power supply voltage may be increased, thereby resulting in an increase in power consumption.

FIG. 5 illustrates an embodiment of pixel circuits PC_ODD and PC_EVEN respectively disposed in an odd row and an even row. The two pixel circuits PC_ODD and PC_EVEN are in the same column, share one data line DL, and have the same structure.

The pixel circuit PC_ODD in the odd row receives a data signal and outputs a driving current corresponding to the data signal to an output node V OUT _ ODD . As described above with reference to FIGS. 1 and 2 , the display panel 150 includes a plurality of pixel circuits PC_ODD in rows and columns. In addition, the pixel circuit PC_ODD is included in the organic light-emitting display apparatus together with a plurality of OLEDs that emit light according to the driving current transferred through the output node V OUT _ ODD .

The pixel circuit PC_ODD further includes an anode initialization transistor TR IO in addition to the pixel circuit of FIG. 3 . The anode initialization transistor TR IO is connected to the output node V OUT _ ODD and outputs an initialization voltage to the output node V OUT _ ODD based on a first control signal received through a first control line CL 1 _ODD. The anode initialization transistor TR IO has a first electrode connected to the data line DL and a second electrode connected to the output node V OUT _ ODD . The anode initialization transistor TR IO outputs a voltage applied from the data line DL to the output node V OUT _ ODD based on the first control signal.

As in the pixel circuit of FIG. 3 , the pixel circuit PC_ODD includes a capacitor C STO , a driving transistor TR DO , a switching transistor TR SO , and an emission control transistor TR EMO . A first electrode of the capacitor C STO is connected to a first node V 1 _ ODD and a second electrode of the capacitor C STO is connected to the output node V OUT _ ODD . A gate electrode of the driving transistor TR DO is connected to the first node V 1 _ ODD and a second electrode of the driving transistor TR DO is connected to the output node V OUT _ ODD .

The switching transistor TR SO has a gate electrode connected to a scan line SL[ 2 n −1], a first electrode of the switching transistor TR SO is connected to the data line DL, and a second electrode of the switching transistor TR SO is connected to the first node V 1 _ ODD . The emission control transistor TR EMO has a gate electrode connected to a second control line CL 2 _ODD and a first electrode connected to the first power supply ELVDD. The gate electrode of the emission control transistor TR EMO is connected to the second control line CL 2 _ODD and receives a second control signal.

The pixel circuit PC_EVEN in the even row receives a data signal and outputs a driving current corresponding to the data signal to an output node V OUT _ EVEN . As described above with reference to FIGS. 1 and 2 , the display panel 150 includes a plurality of pixel circuits PC_EVEN in rows and columns. In addition, the pixel circuit PC_EVEN is included in the organic light-emitting display apparatus together with a plurality of OLEDs that emit light according to the driving current transferred through the output node V OUT _ EVEN .

The pixel circuit PC_EVEN further includes an anode initialization transistor TR IE in addition to the pixel circuit of FIG. 3 . The anode initialization transistor TR IE is connected to the output node V OUT _ EVEN and outputs an initialization voltage to the output node V OUT _ EVEN based on a first control signal received through a first control line CL 1 _EVEN. The anode initialization transistor TR IE has a first electrode connected to the data line DL and a second electrode connected to the output node V OUT _ EVEN . The anode initialization transistor TR IE outputs a voltage applied from the data line DL to the output node V OUT _ EVEN based on the first control signal.

As in the pixel circuit of FIG. 3 , the pixel circuit PC_EVEN includes a capacitor C STE , a driving transistor TR DE , a switching transistor TR SE , and an emission control transistor TR EME . The capacitor C STE has a first electrode connected to a first node V 1 _ EVEN and a second electrode connected to the output node V OUT _ EVEN .

The driving transistor TR DE has a gate electrode connected to the first node V 1 _ EVEN and a second electrode connected to the output node V OUT _ EVEN .

The switching transistor TR SE has a gate electrode connected to a scan line SL[ 2 n ], a first electrode connected to the data line DL, and a second electrode connected to the first node V 1 _ EVEN . A gate electrode of the emission control transistor TR EME is connected to a second control signal CL 2 _EVEN and a first electrode of the emission control transistor TR EME is connected to the first power supply ELVDD. The gate electrode of the emission control transistor TR EME is connected to the second control line CL 2 _EVEN and receives a second control signal.

FIG. 6 illustrates an example of control signals for the pixel circuits PC_ODD and PC_EVEN in FIG. 5 . In FIG. 6 , the driving waveform of the pixel circuit PC_ODD in the odd row is illustrated in the upper side and the driving waveform of the pixel circuit PC_EVEN in the even row is illustrated in the lower side.

Referring to FIG. 6 , the pixel circuits PC_ODD and PC_EVEN sequentially have an anode initialization period, a threshold voltage (V th ) compensation period, a data (odd data/even data) write period, and an emission (odd emission/even emission) period.

The emission period of the pixel circuit PC_ODD in the odd row may not overlap the emission period of the pixel circuit PC_EVEN in the even row. For example, operation during one frame time is performed in the order of the odd anode initialization, an odd threshold voltage (V th ) compensation, an odd data writing, an odd emission, an even anode initialization, an even threshold voltage (V th ) compensation, an even data writing, and an even emission. However, the emission period of the pixel circuit PC_ODD in the odd row may overlap the emission period of the pixel circuit PC_EVEN in the even row.

Operation of the pixel circuit PC_ODD in the odd row will now be described.

During the anode initialization period, a voltage of a high level is applied to all the scan lines SL[ 1 ], SL[ 3 ], . . . , SL[ 2 n −1] and all the switching transistors TR SO are turned on. At this time, the second control signal of a low level is applied through the second control line CL 2 _ODD and all the emission control transistors TR EMO are turned off. The first control signal of a high level is applied through the first control line CL 1 _ODD and the anode initialization transistor TR IO is turned on. Since a low initialization voltage V int is applied to the data line DL, the output node V OUT _ ODD is initialized to the initialization voltage V int . The initialization voltage V int is set to a voltage lower than a turn-on voltage of the OLED so that the OLED does not emit light.

In the threshold voltage (V th ) compensation period, since the first control signal of the low level is applied through the first control line CL 1 _ODD, the anode initialization transistor TR IO is turned off. Since the second control signal of the high level is applied through the second control line CL 2 _ODD, the emission control transistor TR EMO is turned off. Since the reference voltage V ref is applied to the data line DL, the voltage of the first node V 1 _ ODD becomes the reference voltage V ref .

At this time, a voltage of V ref −V th is applied to the output node V OUT _ ODD by source follow. The voltage of V ref −V th applied to the output node V OUT _ ODD is set to a voltage lower than a turn-on voltage of the OLED so that the OLED does not emit light.

During the data write period, the control signal of the low level is applied to both the first control line CL 1 _ODD and the second control line CL 2 _ODD. Thus, both the anode initialization transistor TR IO and the emission control transistor TR EMO are turned off.

The voltage of the high voltage is sequentially applied to the scan lines SL[ 1 ], SL[ 3 ], . . . , SL[ 2 n −1], and data voltages Vdata are sequentially applied to the first node V 1 _ODD. At this time, due to a coupling between the capacitor C STO and the capacitor C OLEDO of the OLED, the voltage of the output node V OUT _ ODD may be determined based on Equation (1).

During the emission period, the voltages of the low level are applied to all the scan lines SL[ 1 ], SL[ 3 ], . . . , SL[ 2 n −1] and the first control line CL 1 _ODD, so that the switching transistor TR SO and the anode initialization transistor TR IO are turned off. The voltage of the high voltage are applied to the second control line CL 2 _ODD, so that the emission control transistor TR EMO is turned on.

The current generated in the driving transistor TR DO is output to the OLEDs through the output node V OUT _ ODD , so that the OLEDs in the odd row emit light.

The magnitude of current flowing through the OLED is proportional to (V data −V OUT _ ODD −V th ) 2 . Therefore, the emission current, which compensates for the threshold voltage of the driving transistor TR DO , flows through the OLED, thereby exhibiting uniform brightness.

Operation of the pixel circuit PC_EVEN in the even row is substantially the same as the operation of the pixel circuit PC_ODD in the odd row. However, light is emitted in a current frame by data written in a previous frame operation.

In the simultaneous emission type pixel circuit in FIGS. 3 and 4 , as the resolution of the display panel 150 and the size of the display panel 150 increase, the number of pixels in the horizontal direction increases and the load of the scan lines and the data lines increases, thereby causing an increase in RC delay. Consequently, the data write time increases and the emission time decreases. Due to the decrease in emission time light may be emitted with higher brightness during the emission period, which may result in an increase in emission current. Therefore, IR-drop between the ELVDD and the ELVSS increases and thus the power supply voltage may be increased, which results in an increase in power consumption.

In the organic light-emitting display apparatus according to the exemplary embodiment, both the pixel circuit PC_ODD in the odd row and the pixel circuit PC_EVEN in the even row perform light emission within one frame time as described above with reference to FIGS. 5 and 6 . Therefore, the reduction in the data write time does not occur and the emission time is secured accordingly. In addition, since a frame frequency does not decrease, a flicker problem may not occur. Since all pixels within one frame perform light emission, the organic light-emitting display apparatus is robust against the reduction in resolution or interlaced crosstalk.

FIG. 7 illustrates another embodiment of pixel circuits PC_ODD and PC_EVEN. In FIG. 7 , the pixel circuit PC_ODD is in an odd row and the pixel circuit PC_EVEN is in an even row.

Referring to FIG. 7 , an anode initialization transistor TR IO has a first electrode connected to an initialization voltage line VL, a second electrode connected to an output node V OUT _ ODD , and a gate electrode connected to a first control line CL 1 _ODD. The anode initialization transistor TR IO outputs an initialization voltage from the initialization voltage line VL to the output node V OUT _ ODD based on a first control signal received through the first control line CL 1 _ODD.

An anode initialization transistor TR IE has a first electrode connected to the initialization voltage line VL, a second electrode connected to an output node V OUT _ EVEN , and a gate electrode connected to a second control line CL 1 _EVEN. The anode initialization transistor TR IE outputs an initialization voltage received from the initialization voltage line VL to the output node V OUT _ EVEN based on a second control signal received through the second control line CL 1 _EVEN.

Thus, the anode initialization transistors TR IO and TR IE in the pixel circuits PC_ODD and PC_EVEN are connected to the initialization voltage line VL, instead of data line DL, and receive the initialization voltage from initialization voltage line VL.

FIG. 8 illustrates an example of control signals for the pixel circuits PC_ODD and PC_EVEN of FIG. 7 . The driving waveform of FIG. 8 is substantially similar to the driving waveform of FIG. 6 , but the reference voltage V ref instead of the initialization voltage V int is applied to the data line during the anode initialization period.

Since the anode initialization transistors TR IO and TR IE of the pixel circuits PC_ODD and PC_EVEN of FIG. 5 are connected to the data line DL and receive the initialization voltage, the initialization voltage V int is applied to the data line DL during the initialization period.

However, since the anode initialization transistors TR IO and TR IE of the pixel circuits PC_ODD and PC_EVEN of FIG. 7 are connected to the initialization voltage line VL, instead of the data line DL, and receive the initialization voltage from the initialization voltage line VL, the initialization voltage V int may not be applied to the data line DL. Therefore, the reference voltage V ref is continuously applied to the data line DL during the anode initialization period and the threshold voltage (V th ) compensation period.

In accordance with one or more of the aforementioned embodiments, it is an organic light-emitting display apparatus increases emission time by decreasing a data write time.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the following claims.