Memory device and programming method thereof

1. Field of the Invention

The invention relates to a device and an operating method thereof, and more particularly, to a memory device and a programming method thereof.

2. Description of Related Art

A flash memory generally adopts the memory array of a NAND or a NOR architecture, wherein the NAND memory array is popular due to the suitability thereof in the application of high-density data storage. In general, a NAND memory array includes a plurality of memory cell strings, and each of the memory cell strings is electrically connected between a corresponding bit line and common source line. Moreover, the programming method of the NAND memory array usually includes programming a plurality of memory cells in a memory cell string from one side of the NAND memory array adjacent to a common source line along the direction toward a bit line one by one. Moreover, when the programmed memory cells are read, offset often occurs to the threshold voltage of the memory cells due to a back pattern effect. Therefore, current programming methods prevent an offset of the threshold voltage caused by the back pattern effect by changing the programming order of the memory cells. However, as the programming order of the memory cells is changed, the channel voltage of the memory cell string that does not need to be programmed may be blocked by memory cells having high threshold voltage and cannot be properly increased, thus causing program disturbance.

The invention provides a memory device and a programming method thereof capable of preventing influence from a back pattern effect, and can reduce program disturbance through the pre-increase of the channel voltage of the memory cells.

A programming method for a memory device of the invention includes the following steps, wherein the memory array in the memory device includes a first memory cell string and a second memory cell string. During a first period, a first voltage from a common source line is transmitted to first ends of the first memory cell string and the second memory cell string, and second ends of the first memory cell string and the second memory cell string are floated. The common source line is located at the first side of the memory array. Moreover, during a second period, the first ends of the first memory cell string and the second memory cell string are floated, a second voltage and a third voltage are respectively transmitted to the second ends of the first memory cell string and the second memory cell string, and a programming voltage and a plurality of passing voltages are applied, so as to inhibit programming of the first memory cell string and sequentially program a plurality of memory cells in the second memory cell string from the second side of a memory array.

A memory device of the invention includes a memory array and a memory controller. The memory array includes a first memory cell string and a second memory cell string. During a first period, the memory controller transmits a first voltage from a common source line to first ends of the first memory cell string and the second memory cell string, and floats second ends of the first memory cell string and the second memory cell string. The common source line is located at the first side of the memory array. During a second period, the memory controller floats the first ends of the first memory cell string and the second memory cell string, and respectively transmits a second voltage and a third voltage to the second ends of the first memory cell string and the second memory cell strings, and applies a programming voltage and a plurality of passing voltages, so as to inhibit programming of the first memory cell string and sequentially program a plurality of memory cells in the second memory cell string from the second side of the memory array.

Based on the above, in the invention, the first voltage from the common source line is transmitted to the first end of the memory cell strings during the first period, and memory cells are sequentially programmed from the second side of the memory array during the second period. Accordingly, influence from a back pattern effect can be prevented, and program disturbance can be reduced through the pre-increase of the channel voltage of the memory cells.

In order to make the aforementioned features and advantages of the disclosure more comprehensible, embodiments accompanied with figures are described in detail below.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic of a memory device according to an embodiment of the invention.

FIG. 2 is a flow chart of a programming method of a memory device according to an embodiment of the invention.

FIG. 3 is a detailed flow chart describing each step of FIG. 2 .

FIG. 4 is a timing diagram for describing a programming method of a memory device according to an embodiment of the invention.

FIG. 5 is a schematic describing a channel voltage of a memory cell string according to an embodiment of the invention.

FIG. 1 is a schematic of a memory device according to an embodiment of the invention. As shown in FIG. 1 , a memory device 100 includes a memory array 110 and a memory controller 120 . The memory array 110 can be, for instance, a NAND memory array, and the memory array 110 includes a plurality of select transistors 131 and 132 , a plurality of ground transistors 141 and 142 , and a plurality of memory cells 151 to 154 and 161 to 164 . The select transistors 131 and 132 are electrically connected to a string select line SSL 1 , the ground transistors 141 and 142 are electrically connected to a ground select line GSL 1 , and the memory cells 151 to 154 and 161 to 164 are electrically connected to word lines WL 1 to WL 4 .

The memory cells 151 to 154 are electrically connected in series to form a memory cell string 111 . Moreover, the first end of the memory cell string 111 is electrically connected to a common source line CSL 1 through the ground transistor 141 , and the second end of the memory cell string 111 is electrically connected to a bit line BL 1 through the select transistor 131 . Similarly, the first end of the memory cell string 112 formed by the memory cells 161 to 164 is electrically connected to the common source line CSL 1 through the ground transistor 142 , and the second end of the memory cell string 112 is electrically connected to a bit line BL 2 through the select transistor 132 . In particular, the common source line CSL 1 is located at the first side of the memory array 110 , and the bit lines BL 1 and BL 2 are located at the second side of the memory array 110 .

The memory controller 120 includes a first decoder 121 and a second decoder 122 . The first decoder 121 and the second decoder 122 can select memory cells in the memory array 110 according to an address to perform a programming procedure, a reading procedure, or an erase procedure on the selected memory cells. Moreover, in an embodiment, the memory array 110 can be, for instance, a 2 D array structure, and the first decoder 121 and the second decoder 122 can be, for instance, a row decoder and a column decoder. In another embodiment, the memory array 110 can be, for instance, a 3 D array structure, the first decoder 121 includes a row decoder and a plane decoder, and the second decoder 122 can be, for instance, a column decoder.

It should be mentioned that, the programming procedure of the memory array 110 includes a precharge operation and a programming operation. A memory cell string (such as the memory cell string 112 ) in the memory array 110 to be programmed can be regarded as a selected memory cell string, and the remaining memory cell strings (such as the memory cell string 111 ) can be regarded as non-selected memory cell strings. During a programming operation, the memory controller 120 can program memory cells in the selected memory cell string from a side of the memory array 110 adjacent to a bit line along the direction toward the common source line CSL 1 one by one. Moreover, before a programming operation is performed on the selected memory cell string, the memory controller 120 can increase the channel voltage of each of the memory cell strings through the precharge operation. Accordingly, the precharge operation can pre-increase the channel voltage of the non-selected memory cell strings, thus reducing program disturbance of the memory cells.

To allow those having ordinary skill in the art to better understand the invention, FIG. 2 is a flow chart of a programming method of a memory device according to an embodiment of the invention. As shown in step S 210 , during a first period, the memory controller 120 can transmit a first voltage from the common source line CSL 1 to the first end of the memory cell string 111 (that is, the first memory cell string), and transmit the first voltage to the first end of the memory string 112 (that is, the second memory cell string). Moreover, the memory controller 120 can float the second ends of the memory cell strings 111 and 112 . Accordingly, the memory controller 120 can perform a precharge operation on the memory array 110 , so as to increase the channel voltages of the memory cell strings 111 and 112 through the first voltage.

For instance, FIG. 3 is a detailed flow chart for describing each step of FIG. 2 , and FIG. 4 is a timing diagram for describing a programming method of a memory device according to an embodiment of the invention. In particular, the labels VBL 1 , VBL 2 , VCSL 1 , VSSL 1 , and VGSL 1 in FIG. 4 are respectively used to represent voltages applied to the bit line BL 1 , the bit line BL 2 , the common source line CSL 1 , the string select line SSL 1 , and the ground select line GSL 1 .

In terms of the detailed steps of step S 210 , as shown in step S 310 , during a first period T 41 , the memory controller 120 can apply a first voltage V 41 to the common source line CSL 1 . Moreover, as shown in step S 320 , the memory controller 120 can apply a high voltage VH 4 to the ground select line GSL 1 so as to turn on the ground transistors 141 and 142 through the high voltage VH 4 . Accordingly, the first voltage V 41 can be transmitted to the first ends of the memory cell strings 111 and 112 through the ground transistors 141 and 142 . Moreover, as shown in step S 330 , the memory controller 120 can apply a low voltage VL 4 to the string select line SSL 1 , so as to turn off the select transistors 131 and 132 , and make the second ends of the memory cell strings 111 and 112 remain in a floating state. In this way, during the first period T 41 , the memory controller 120 can pre-increase the channel voltages of the memory cell strings 111 and 112 through the first voltage V 41 .

Referring further to FIG. 1 and FIG. 2 , as shown in step S 220 , during the second period, the memory controller 120 can float the first ends of the memory cell strings 111 and 112 , and respectively transmit the second voltage and the third voltage to the second ends of the memory cell strings 111 and 112 . Accordingly, the memory cell string 111 can be regarded as a non-selected memory cell string, and the memory cell string 112 can be regarded as a selected memory cell string to be programmed. Moreover, the memory controller 120 can apply a programming voltage and a plurality of passing voltages to inhibit the programming of the memory cell string 111 , and sequentially program the memory cells 161 to 164 in the memory cell string 112 from the second side of the memory array 110 .

For instance, referring to FIG. 1 , FIG. 3 , and FIG. 4 at the same time, during the second period T 42 , as shown in step S 340 , the memory controller 120 can transmit a second voltage V 42 to the bit line BL 1 , and transmit a third voltage V 43 to the bit line BL 2 . The second voltage V 42 can be, for instance, the high voltage VH 4 (such as 3.3 volts), and the third voltage V 43 can be, for instance, a low voltage (such as 0 volts). Moreover, the first voltage V 41 can be, for instance, 2 volts. That is, the first voltage V 41 is less than the second voltage V 42 , and the first voltage V 41 is greater than the third voltage V 43 . Moreover, as shown in step S 350 , the memory controller 120 can turn off the ground transistors 141 and 142 through the low voltage VL 4 transmitted by the ground select line GSL 1 , and can turn on the select transistors 131 and 132 through the high voltage VH 4 transmitted by the string select line SSL 1 . Accordingly, the first end of the memory cell string 111 is floated, and the second end of the memory cell string 111 can receive the second voltage V 42 . Similarly, the first end of the memory cell string 112 is floated, and the second end of the memory cell string 112 can receive the third voltage V 43 .

As shown in step S 360 , the memory controller 120 can select each of the memory cells in the memory cell string 112 from the second side of the memory array 110 one by one, so as to set each of the memory cells in the memory cell string 112 as a selected memory cell one by one. Moreover, as shown in step S 370 , the memory array 110 can apply a programming voltage V 44 to a word line electrically connected to the selected memory cell, and apply a passing voltage V 45 to the remaining word lines. For instance, the memory cell 164 is first selected as a selected memory cell. At this point, the memory controller 120 applies the programming voltage V 44 to the word line WL 4 , and applies the passing voltage V 45 to the word lines WL 1 to WL 3 , so as to program the memory cell 164 .

In other words, the memory controller 120 applies the programming voltage V 44 to the word lines WL 1 to WL 4 from the second side of the memory array 110 one by one, so as to program the memory cells 161 to 164 one by one. That is, the memory controller 120 programs the memory cells 161 to 164 in the memory cell string 112 from the top down one by one. Therefore, even in the case that the programmed memory cell 161 has a high threshold voltage, influence to the threshold voltage of the memory cell 161 from a back pattern effect can still be prevented.

Moreover, during the programming of the memory cell string 112 (that is, the selected memory cell string), the channel voltage of the memory cell string 111 (that is, the non-selected memory cell string) is increased in response to the passing voltage. It should be mentioned that, when the memory cell 154 in the memory cell string 111 adjacent to the second side of the memory array 110 has a high threshold voltage, the memory cell 154 blocks an increase in the channel voltage of the memory cell string 111 . Moreover, when the channel voltage of the memory cell string 111 is too low, the threshold voltage of the memory cells in the memory cell string 111 is changed due to the influence from the programming of the memory cell string 112 , thus causing program disturbance. Therefore, to prevent the above program disturbance, before the programming of the memory cell string 112 is performed, the memory controller 120 can first increase the channel voltage of the memory cell string 111 through a precharge operation. In this way, during the programming process of the memory cell string 112 , the memory cell string 111 has a sufficiently high channel voltage to prevent a change to the threshold voltage of the memory cells 151 to 154 , thus reducing program disturbance.

For instance, FIG. 5 is a schematic describing a channel voltage of a memory cell string according to an embodiment of the invention. In the embodiment of FIG. 5 , the memory cell string 111 (that is, the non-selected memory cell string) includes a plurality of memory cells connected to the word lines WL 1 to WL 15 . Moreover, FIG. 5 illustrates the channel voltages of the select transistor 131 , the plurality of memory cells, and the ground transistor 141 , and the corresponding string select line SSL 1 , word lines WL 1 to WL 15 , and ground select line GSL 1 are labeled along the horizontal axis.

As shown in a curve 510 , when the memory controller 120 does not pre-increase the channel voltage of the memory cell string 111 , and the memory cell 154 does not have a high threshold voltage, the channel voltage of the memory cell string 111 is increased to about 8.5 volts in response to the passing voltage. Moreover, as shown in a curve 520 , when the memory cell 154 has a high threshold voltage, and the memory controller 120 does not pre-increase the channel voltage of the memory cell string 111 , the channel voltage of the memory cell string 111 is increased to about 6.7 volts in response to the passing voltage.

Moreover, as shown in a curve 530 , when the memory cell 154 has a high threshold voltage, and the memory controller 120 first increases the channel voltage of the memory cell string 111 through a precharge operation, the channel voltage of the memory cell string 111 can be increased to about 8.5 volts in response to the passing voltage. In other words, since the memory controller 120 can first increase the channel voltage of the memory cell string 111 through a precharge operation, during the programming process of the memory cell string 112 , the memory cell string 111 has a sufficiently high channel voltage to prevent a change to the threshold voltage of the memory cells 151 to 154 , thus reducing program disturbance.

Based on the above, in the invention, the first voltage from the common source line is transmitted to the first ends of the memory cell strings during the first period, so as to pre-increase the channel voltage of the memory cells. In particular, the common source line is located at the first side of the memory array. Moreover, in the invention, memory cells are sequentially programmed from the second side of the memory array during the second period. Accordingly, influence from a back pattern effect can be prevented, and program disturbance can be reduced through the pre-increase of the channel voltage of the memory cells.

Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.