Semiconductor device having a transistor and first and second embedded layers

The disclosure of Japanese Patent Application No. 2014-107950 filed on May 26, 2014 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

The present invention relates to a semiconductor device and is, for example, a technology applicable to a semiconductor device having a diffusion layer embedded into a substrate.

In a semiconductor device, it sometimes happens that a diffusion layer is embedded into a substrate and a transistor is formed over the diffusion layer. In the transistor, a substance formed by epitaxially growing a semiconductor layer over a semiconductor substrate acting as a base is used as the substrate for example. Then the diffusion layer is: formed by an ion implantation method after the semiconductor layer is formed in some cases; or formed when the semiconductor layer is epitaxially grown in other cases.

Meanwhile, Japanese Unexamined Patent Application Publication No. Sho 62 (1987)-40719 describes that p-type impurities are diffused over the surface of a p-type substrate acting as a base by a thermal diffusion method and successively an epitaxial layer is grown over the substrate.

Further, Japanese Unexamined Patent Application Publication No. 2002-176177 describes that a semiconductor substrate is formed by forming an n-type epitaxial layer over the surface of a p-type substrate acting as a base and a trench gate type IGBT is formed by using the semiconductor substrate. In Japanese Unexamined Patent Application Publication No. 2002-176177, the epitaxial layer has a configuration formed by stacking a low-concentration n-type layer over a high-concentration n-type layer.

When a semiconductor layer is formed over a substrate acting as a base, a diffusion layer is embedded into the semiconductor layer, and a transistor is formed over the diffusion layer, the withstand voltage of the transistor is dominated by the distance between the substrate acting as the base and the diffusion layer in some cases. Since impurities are also introduced into the substrate however, there has been the possibility that the impurities diffuse from the substrate to the semiconductor layer in the manufacturing process of a semiconductor device and the withstand voltage of the transistor deteriorates. Other problems and novel features will be obvious from the descriptions and attached drawings in the present specification.

According to an embodiment, a first electrically conductive type semiconductor layer is formed over a first electrically conductive type base substrate. The impurity concentration of the semiconductor layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the semiconductor layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the semiconductor layer.

According to the embodiment, it is possible to inhibit: impurities from diffusing from the substrate to the semiconductor layer; and the withstand voltage of the transistor from deteriorating.

FIG. 1 is a sectional view showing the configuration of a semiconductor device according to First Embodiment.

FIG. 2 is a plan view of a transistor.

FIG. 3 is a sectional view showing a manufacturing method of a semiconductor device.

FIG. 4 is a sectional view showing the manufacturing method of the semiconductor device.

FIG. 5 is a sectional view showing the manufacturing method of the semiconductor device.

FIGS. 6A and 6B are views for explaining the distribution of impurities in the depth direction of a substrate.

FIGS. 7A and 7B are sectional views showing a manufacturing method of a semiconductor device according to Second Embodiment.

FIGS. 8A and 8B are views for explaining the distribution of impurities in the depth direction of a substrate.

FIG. 9 is a sectional view showing the configuration of a semiconductor device according to Third Embodiment.

FIGS. 10A and 10B are views for explaining the distribution of impurities in the depth direction of a substrate.

FIG. 11 is a sectional view showing the configuration of a semiconductor device according to Fourth Embodiment.

Embodiments are explained in reference to the drawings hereunder. In all the drawings, similar constituent components are represented by similar reference numerals and explanations are omitted appropriately.

First Embodiment

FIG. 1 is a sectional view showing the configuration of a semiconductor device SD according to First Embodiment. The semiconductor device SD according to the present embodiment is formed by using a substrate SUB. The substrate SUB is formed by growing an epitaxial layer EPI (semiconductor layer) comprising a semiconductor (for example silicon) over a base substrate BSUB comprising a bulk semiconductor (for example monocrystal silicon). Both the base substrate BSUB and the epitaxial layer EPI are an identical electrically conductive type (first electrically conductive type: for example P-type). The impurity concentration of the base substrate BSUB is higher than that of the epitaxial layer EPI.

A first embedded layer BINPL 1 that is an electrically conductive type (second electrically conductive type: for example n-type) different from the epitaxial layer EPI is formed in the epitaxial layer EPI. The first embedded layer BINPL 1 is kept away from the base substrate BSUB. The first embedded layer BINPL 1 : either may be formed when the epitaxial layer EPI is grown epitaxially; or may be formed by an ion implantation method after the epitaxial layer EPI is formed. In the former case, the first embedded layer BINPL 1 is formed over the whole surface of the substrate SUB.

Further, a second embedded layer BINPL 2 is formed in the epitaxial layer EPI. The second embedded layer BINPL 2 is a second electrically conductive type impurity layer, is deeper than the first embedded layer BINPL 1 , and is kept away from the first embedded layer BINPL 1 . The impurity concentration of the second embedded layer BINPL 2 is lower than that of the first embedded layer BINPL 1 . The second embedded layer BINPL 2 is formed in order to inhibit: the impurities of the base substrate BSUB from diffusing in the epitaxial layer EPI; and the first electrically conductive type impurity concentration in the lower layer of the epitaxial layer EPI from increasing.

Then transistors TR 2 and TR 3 constituting a logic circuit and a transistor TR 1 for electric power control are formed in the epitaxial layer EPI. At least the transistor TR 1 overlaps with the first embedded layer BINPL 1 in a planar view.

The following explanations are based on the case where the first electrically conductive type is a p-type and the second electrically conductive type is an n-type. It is also possible however that the first electrically conductive type is an n-type and the second electrically conductive type is a p-type.

The transistor TR 2 is an n-type low withstand voltage transistor and has a gate electrode GE 2 , a source SOU 2 , and a drain DRN 2 . The transistor TR 3 is a p-type low withstand voltage transistor and has a gate electrode GE 3 , a source SOU 3 , and a drain DRN 3 . The transistors TR 2 and TR 3 include a CMOS transistor. Meanwhile, a gate insulating film (not shown in the figure) is formed under the gate electrodes GE 2 and GE 3 .

The transistor TR 1 is a horizontal transistor for electric power control and has a withstand voltage higher than the transistors TR 2 and TR 3 . The transistor TR 1 has a gate electrode GE 1 , a source SOU 1 , and a drain DRN 1 . The distance between the drain DRN 1 and the gate electrode GE 1 is larger than the distance between the source SOU 1 and the gate electrode GE 1 . As a result, the withstand voltage between the drain DRN 1 and the gate electrode GE 1 is higher. A gate insulating film (not shown in the figure) is formed under the gate electrode GE 1 . The gate insulating film is thicker than the gate insulating film of the transistors TR 2 and TR 3 . Here, an element isolation insulating film formed by an STI method or a LOCOS method is formed between the drain DRN 1 and the gate electrode GE 1 .

The drain DRN 1 has an n-type well WL 12 and an n-type high concentration region HINPL 13 formed over the surface layer of the n-type well WL 12 . The high concentration region HINPL 13 is coupled to a contact CON 3 . Further, an n − -type offset region NOF 11 is formed around the n-type well WL 12 . In other words, the n-type well WL 12 is formed in the surface layer of the offset region NOF 11 .

Meanwhile, the source SOU 1 has an n-type high concentration region HINPL 12 . The high concentration region HINPL 12 is formed in the surface layer of a p-type well WL 21 . Although it is not shown in the figure, a p-type high concentration region is formed at a part of the p-type well WL 21 located adjacent to the high concentration region HINPL 12 . Then a contact CON 2 is coupled to the p-type high concentration region and the high concentration region HINPL 12 .

Then an insulating film HMSK 1 and an interlayer insulating film INSL 1 are formed over the substrate SUB. The insulating film HMSK 1 is a silicon nitride film for example and the interlayer insulating film INSL 1 is a silicon oxide film for example. Contacts CON 2 , CON 3 , CON 4 , CON 5 , CONE, and CON 7 are embedded into the insulating film HMSK 1 and the interlayer insulating film INSL 1 . The contact CON 2 is coupled to the source SOU 1 of the transistor TR 1 and the contact CON 3 is coupled to the drain DRN 1 of the transistor TR 1 . The contact CON 4 is coupled to the source SOU 2 of the transistor TR 2 and the contact CON 5 is coupled to the drain DRN 2 of the transistor TR 2 . The contact CON 6 is coupled to the source SOU 3 of the transistor TR 3 and the contact CON 7 is coupled to the drain DRN 3 of the transistor TR 3 . Meanwhile, although they are not shown in the figure, a contact coupled to the gate electrode GE 1 , a contact coupled to the gate electrode GE 2 , a contact coupled to the gate electrode GE 3 , and a contact coupled to a deep well DWL (described later) are also embedded into the insulating film HMSK 1 and the interlayer insulating film INSL 1 .

Wires INC 2 , INC 3 , INC 4 , INC 5 , INC 6 , and INC 7 are formed over the interlayer insulating film INSL 1 . The wires INC 2 , INC 3 , INC 4 , INC 5 , INC 6 , and INC 7 comprise a metal such as aluminum for example and are coupled to the contacts CON 2 , CON 3 , CON 4 , CON 5 , CON 6 , and CON 7 respectively. Meanwhile, wires (not shown in the figure) coupled to the respective gate electrodes and a wire (not shown in the figure) coupled to the deep well DWL are also formed over the interlayer insulating film INSL 1 .

The transistor TR 1 is formed in a first element region EL 1 and the transistors TR 2 and TR 3 are formed in a second element region EL 2 . More specifically, the single transistor TR 1 is formed in the first element region EL 1 . In contrast, the plural transistors TR 2 and TR 3 are formed in the second element region EL 2 . Meanwhile, in FIG. 1 , only a pair of the transistors TR 2 and TR 3 are shown in the second element region EL 2 for the simplification of the figure. Then the first element region EL 1 and the second element region EL 2 are surrounded by element isolation trenches SDTR respectively. The element isolation trenches SDTR pass through the first embedded layer BINPL 1 but do not reach the base substrate BSUB. Further in the example shown in the figure, the bottom parts of the element isolation trenches SDTR do not reach even the second embedded layer BINPL 2 . In other words, the element isolation trenches SDTR are formed so as to be shallower than the second embedded layer BINPL 2 .

Then an embedded insulating film BINSL is embedded into the element isolation trenches SDTR. In the example shown in the figure, the embedded insulating film BINSL is a part of the interlayer insulating film INSL 1 over the substrate SUB.

Meanwhile, the n-type deep well DWL and an embedded contact BCON are further formed in the substrate SUB. The bottom face of the deep well DWL reaches the first embedded layer BINPL 1 and the deep well DWL gives a fixed potential to the first embedded layer BINPL 1 . The embedded contact BCON is a contact embedded into the substrate SUB and passes through the first embedded layer BINPL 1 and the second embedded layer BINPL 2 . As a result, a fixed potential is given by the embedded contact BCON to the epitaxial layer EPI and the base substrate BSUB under the second embedded layer BINPL 2 .

In the example shown in the figure, a p-type impurity region INPL 1 is formed in the region of the epitaxial layer EP 1 touching the bottom face of the embedded contact BCON. The impurity concentration of the impurity region INPL 1 is higher than that of the epitaxial layer EP 1 . The contact resistance between the embedded contact BCON and the epitaxial layer EP 1 decreases by forming the impurity region INPL 1 .

A groove (or hole) into which the embedded contact BCON is embedded is formed through the same process as a contact hole into which the contact CON 2 is embedded for example. The groove (or hole) may otherwise be formed through an independent process. An insulating film (thermally-oxidized film for example) INSL 2 is formed over the inner face of the groove. As a result, the embedded contact BCON is insulated from the first embedded layer BINPL 1 and the part of the epitaxial layer EPI located above the first embedded layer BINPL 1 . Further, the embedded contact BCON is formed through the same process as the contact CON 2 and other contacts. As a result, the embedded contact BCON passes through the interlayer insulating film INSL 1 and the insulating film HMSK 1 and the top end is coupled to a wire INC 8 over the interlayer insulating film INSL 1 .

Meanwhile, the potential of the first embedded layer BINPL 1 may be either a floating potential or a fixed potential. In the latter case, an impurity region for raising the first embedded layer BINPL 1 electrically to the surface layer of the epitaxial layer EPI is formed in the epitaxial layer EPI. The lower part of the impurity region is coupled to the first embedded layer BINPL 1 and a contact is coupled to the upper part of the impurity region.

FIG. 2 is a plan view of a transistor TR 1 . A gate electrode GE 1 surrounds an n-type well WL 12 of a drain DRN 1 and a p-type well WL 21 surrounds the gate electrode GE 1 . Then an element isolation trench SDTR is formed along the sides of a polygon (rectangle in the example shown in the figure) and surrounds the p-type well WL 21 . In other words, the transistor TR 1 is located inside the element isolation trench SDTR.

FIGS. 3 to 5 are sectional views showing a manufacturing method of a semiconductor device SD. The figures correspond to FIG. 1 .

Firstly, as shown in FIG. 3 , a base substrate BSUB is prepared. Successively, an epitaxial layer EPI is formed over the base substrate BSUB. On this occasion, a second embedded layer BINPL 2 and a first embedded layer BINPL 1 are formed by switching gases for introducing impurities in midstream. At the step, the second embedded layer BINPL 2 is located immediately over the base substrate BSUB (in other words, at the lowermost layer of the epitaxial layer EPI) for example.

Successively, as shown in FIG. 4 , various kinds of wells (including a deep well DWL) and an offset region NOF 11 are formed in the epitaxial layer EPI by an ion implantation method for example. Successively, a groove is formed in the epitaxial layer EPI and an insulating film, a silicon oxide film for example, is embedded into the groove. As a result, an element isolation insulating film (not shown in the figure) is formed. Meanwhile, the various wells and the offset region NOF 11 may otherwise be formed after the element isolation insulating film is formed.

Successively, a gate insulating film for transistors TR 1 , TR 2 , and TR 3 is formed. Successively, a film (polysilicon film for example) as a material for gate electrodes is formed and the film is selectively removed. As a result, gate electrodes GE 1 , GE 2 , and GE 3 are formed. Successively, high concentration regions (HINPL 12 and HINPL 13 for example) are formed in the epitaxial layer EPI by an ion implantation method for example.

Meanwhile, sidewalls may be formed over the side faces of the gate electrodes GE 1 , GE 2 , and GE 3 in some cases. In such a case, the high concentration regions are formed after the sidewalls are formed.

Further, heat treatment is applied after the high concentration regions are formed in the epitaxial layer EPI. Impurities diffuse by the heat treatment and as a result the second embedded layer BINPL 2 gets away from the base substrate BSUB.

Successively, as shown in FIG. 5 , an insulating film HMSK 1 is formed over the epitaxial layer EPI. Successively, a resist pattern (not shown in the figure) is formed over the insulating film HMSK 1 . The resist pattern has openings in the region where element isolation trenches SDTR are to be formed. Successively, the insulating film HMSK 1 is etched with the resist pattern used as a mask. As a result, the openings are formed in the region of the insulating film HMSK 1 where the element isolation trenches SDTR are to be formed.

Successively, the epitaxial layer EPI (also the element isolation insulating film in some locations) is etched with the insulating film HMSK 1 used as a mask. As a result, the element isolation trenches SDTR are formed. When the resist pattern remains thereafter, the resist pattern is removed.

Successively, an interlayer insulating film INSL 1 is formed. On this occasion, parts of the interlayer insulating film INSL 1 are embedded into the element isolation trenches SDTR and come to be an embedded insulating film BINSL. On this occasion, voids may be formed in the element isolation trenches SDTR in some cases. Since the voids are occluded with the interlayer insulating film INSL 1 (embedded insulating film BINSL) and are not exposed even at the succeeding processes however, the voids do not influence the quality of the semiconductor device SD.

Successively, a resist pattern (not shown in the figure) is formed over the interlayer insulating film INSL 1 and the interlayer insulating film INSL 1 is etched with the resist pattern used as a mask. As a result, contact holes for forming contacts are formed. In the process, a contact hole is also formed in the region of the interlayer insulating film INSL 1 where an embedded contact BCON is to be formed. The contact hole reaches down to the bottom of a groove formed in the epitaxial layer EPI. Impurities are injected into the contact hole. As a result, an impurity region INPL 1 is formed. Then a metal such as W is embedded into the contact holes. As a result, the contacts and the embedded contact BCON are formed.

Successively, a metal film (Al for example) is formed over the interlayer insulating film INSL 1 . Successively, the metal film is selectively removed. As a result, wires are formed.

FIGS. 6A and 6B are views for explaining the distribution of impurities in the depth direction of a substrate SUB. FIG. 6A shows the distribution of impurities in a substrate SUB before the substrate SUB is subjected to heat treatment and FIG. 6B shows the result of simulating the distribution of the impurities in the substrate SUB after the substrate SUB is subjected to heat treatment.

As shown in FIG. 6A , a base substrate BSUB contains p-type impurities of a high concentration and an epitaxial layer EPI contains p-type impurities of a concentration lower than that of the base substrate BSUB. Then an n-type second embedded layer BINPL 2 is formed in the region of the epitaxial layer EPI touching the base substrate BSUB. Here, the p-type impurities contained in the base substrate BSUB comprise B for example and the n-type impurities contained in the second embedded layer BINPL 2 comprise P for example.

When the substrate SUB shown in FIG. 6A is subjected to heat treatment, the impurities contained in the respective layers diffuse thermally. In the state after heat treatment, the second embedded layer BINPL 2 is defined as the region where an n-type impurity concentration is higher than a p-type impurity concentration. The second embedded layer BINPL 2 according to the definition is located on the side closer to the surface of the epitaxial layer EPI than the second embedded layer BINPL 2 in the state of FIG. 6A .

Meanwhile, when the second embedded layer BINPL 2 is not formed in the state of FIG. 6A , the p-type impurities in the base substrate BSUB diffuse into the epitaxial layer EPI and hence the withstand voltage between the base substrate BSUB and a first embedded layer BINPL 1 deteriorates.

In the present embodiment in contrast, since the second embedded layer BINPL 2 is formed, the p-type impurities diffusing from the base substrate BSUB to the epitaxial layer EPI are offset by the n-type impurities contained in the second embedded layer BINPL 2 . As a result, the withstand voltage between the base substrate BSUB and a first embedded layer BINPL 1 is inhibited from deteriorating. Here, when the epitaxial layer EPI is a silicon layer for example, the thermal diffusion rate of P is nearly identical to the thermal diffusion rate of B at about 1,000° C. Consequently, the offset effect is particularly large when B is elected as the p-type impurities contained in the base substrate BSUB and P is selected as the n-type impurities contained in the second embedded layer BINPL 2 .

Further, the second embedded layer BINPL 2 is formed so as to be deeper than the element isolation trenches SDTR. As a result, it is possible to bring the second embedded layer BINPL 2 closer to the base substrate BSUB. As a result, it is possible to effectively offset the impurities diffusing from the base substrate BSUB to the epitaxial layer EPI.

Second Embodiment

FIGS. 7A and 7B are sectional views showing a manufacturing method of a semiconductor device SD according to Second Embodiment. Firstly, as shown in FIG. 7A , a base substrate BSUB is prepared. Successively, n-type impurities are injected into the base substrate BSUB by thermal diffusion or ion implantation. As a result, a second embedded layer BINPL 2 is formed in the surface layer of the base substrate BSUB.

Successively, an epitaxial layer EPI is formed over the base substrate BSUB. The method for forming the epitaxial layer EPI is the same as the method for forming an epitaxial layer EPI in First Embodiment except that the second embedded layer BINPL 2 is not formed.

The succeeding processes are the same as First Embodiment.

FIGS. 8A and 8B are views for explaining the distribution of impurities in the depth direction of a substrate SUB according to the present embodiment and correspond to FIGS. 6A and 6B in First Embodiment. FIG. 8A shows the distribution of impurities in a substrate SUB before the substrate SUB is subjected to heat treatment and FIG. 8B shows the result of simulating the distribution of the impurities in the substrate SUB after the substrate SUB is subjected to heat treatment.

As shown in FIG. 8A , in the state before heat treatment, a second embedded layer BINPL 2 is formed in the surface layer of a base substrate BSUB. As shown in FIG. 8B in contrast, when a substrate SUB is subjected to heat treatment, the second embedded layer BINPL 2 is defined as the region where the concentration of n-type impurities is higher than the concentration of p-type impurities in the same manner as First Embodiment. The second embedded layer BINPL 2 according to the definition is located inside an epitaxial layer EPI in the example shown in the figure.

In the present embodiment too, the second embedded layer BINPL 2 is formed in the substrate SUB and hence it is possible to inhibit the withstand voltage between the base substrate BSUB and a first embedded layer BINPL 1 from deteriorating.

Third Embodiment

FIG. 9 is a sectional view showing the configuration of a semiconductor device SD according to Third Embodiment. The semiconductor device SD according to the present embodiment has a configuration similar to the semiconductor device SD according to Second Embodiment except that the semiconductor device SD according to the present embodiment has a third embedded layer BINPL 3 instead of a second embedded layer BINPL 2 .

The third embedded layer BINPL 3 is a layer into which an element (hereunder described as a diffusion inhibiting element) to inhibit impurities in a base substrate BSUB from thermally diffusing is introduced. The third embedded layer BINPL 3 is formed by introducing a diffusion inhibiting element into the surface layer of the base substrate BSUB instead of n-type impurities in FIG. 7A of Second Embodiment. The diffusion inhibiting element is at least one of N, C, and O for example. The concentration of the diffusion inhibiting element in the third embedded layer BINPL 3 is identical to or lower than the concentration of the p-type impurities in the base substrate BSUB and higher than the concentration of the p-type impurities in an epitaxial layer EPI, for example.

FIGS. 10A and 10B are views for explaining the distribution of impurities in the depth direction of a substrate SUB according to the present embodiment and correspond to FIGS. 8A and 8B in Second Embodiment. FIG. 10A shows the distribution of impurities in a substrate SUB before the substrate SUB is subjected to heat treatment and FIG. 10B shows the distribution of the impurities in the substrate SUB after the substrate SUB is subjected to heat treatment.

As shown in FIG. 10A , in the state before heat treatment, a third embedded layer BINPL 3 is formed in the surface layer of a base substrate BSUB. As shown in FIG. 10B in contrast, when the substrate SUB is subjected to heat treatment, impurities in the base substrate BSUB diffuse toward an epitaxial layer EPI but the quantity of the diffusion is small because the third embedded layer BINPL 3 is formed. Here, a diffusion inhibiting element in the third embedded layer BINPL 3 also diffuses in the substrate SUB. As a result, the width of the third embedded layer BINPL 3 increases.

In the present embodiment, the third embedded layer BINPL 3 is formed in the substrate SUB and hence the impurities in the base substrate BSUB hardly diffuse toward the epitaxial layer EPI. As a result, it is possible to inhibit the withstand voltage between the base substrate BSUB and a first embedded layer BINPL 1 from deteriorating.

Fourth Embodiment

FIG. 11 is a sectional view showing the configuration of a semiconductor device SD according to Fourth Embodiment. The semiconductor device SD according to the present embodiment has a configuration similar to any one of First to Third Embodiments except that the semiconductor device SD according to the present embodiment has a backside electrode EL instead of an embedded contact BCON. The figure shows the case of a configuration similar to First Embodiment.

The backside electrode EL is formed over the surface of a base substrate BSUB where an epitaxial layer EPI is not formed and gives a fixed potential to the base substrate BSUB. The backside electrode EL comprises a metal such as Al for example. The backside electrode EL is formed by a sputtering method for example.

In the present embodiment too, it is possible to inhibit the withstand voltage between the base substrate BSUB and a first embedded layer BINPL 1 from deteriorating.

Although the invention established by the present inventors has heretofore been explained concretely on the basis of the embodiments, it goes without saying that the present invention is not limited to the embodiments and can be modified variously within the scope not departing from the tenor of the invention.