Short-circuit detection device and method used in inverter circuit

This application claims priority to Chinese Application Serial Number 201410241037.3, filed May 30, 2014, which is herein incorporated by reference.

The present disclosure relates to an inverter technology. More particularly, the present disclosure relates to a short-circuit detection device and method used in an inverter circuit.

Inverters are commonly utilized in power systems and users have higher and higher expectations to the maintainability. Taking a multi-level inverter as an example, the multi-level inverter is especially useful in applications requiring high voltage and high power. However, the structure and the control mechanism of the circuit become more complicated as the level of the inverter circuit increases result in a higher probability of the failure of the power device. The system reliability is significantly decreased.

Common conditions that cause failures, such as the existence of an open-circuited switch, a short-circuited switch, an incorrect wiring connection, a wiring disconnection or a unsuccessful driving condition, will damage the components or the system. If there is no efficient way to determine that whether there is a short-circuited condition in the inverter circuit, the inverter circuit is very likely to be damaged during its operation and may do harm to, for instance, production delays or serious and catastrophic incidents.

Therefore, an appropriate solution of a short-circuit detection device and method used in an inverter circuit has yet been developed, in order to address the above problems.

The present disclosure provides a method for detecting a short circuit fault in a multi-level inverter circuit. The inverter circuit includes a plurality of single phase branches, each of which includes a plurality of switches. The short-circuit detection method includes transmitting at least a detection pulse sequence to the plurality of switches of the single phase branch; determining whether a conducting loop is formed in the single phase branch according to the detection pulse sequence; and determining a position of a malfunctioned switch of the single phase branch according to a path of the conducting loop when the conducting loop exists.

An aspect of the present disclosure provides a short-circuit detection device for a multi-level inverter circuit. The inverter circuit includes a plurality of single phase branches, wherein each of the plurality of single phase branches includes a plurality of switches. The short-circuit detection device includes a pulse transmitting module, a loop determining module and a fault detection module. The pulse transmitting module transmits at least one detection pulse sequence to the plurality of switches of the single phase branch. The loop determining module determines that whether a conducting loop is formed in the single phase branch according to the detection pulse sequence. The fault detection module determines a position of a malfunctioned switch of the single phase branch according to a path of the conducting loop when the conducting loop exists.

An aspect of the present disclosure provides a three-phase three-level inverter circuit. The three-phase three-level inverter circuit includes a capacitor module, three single phase branches and a fault detection module. The capacitor module includes a first capacitor and a second capacitor, which are electrically coupled in series via a first node. Each single phase branch is coupled to the capacitor module in parallel. Each single phase branch includes a first diode, a second diode, a first switch, a second switch, a third switch and a fourth switch. The first diode and the second diode are electrically coupled in series between a third node and a fourth node via a second node, wherein the second node is electrically coupled to the first node. The first switch and the second switch are electrically coupled via the third node. The third switch and the fourth switch are electrically coupled via the fourth node, wherein the second switch and the third switch are electrically coupled via a fifth node. The fault detection module transmits a detection pulse sequence comprising numbers of “0” and “1” to the first switch, the second switch, the third switch and the fourth switch in the single phase branch. The fault detection module determines whether a conducting loop is formed in the single phase branch according to the detection pulse sequence, and determines a position of at least one malfunctioned switch in the single phase branches according to a path of the conducting loop when the conducting loop exists in the single phase branch.

It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings,

FIG. 1 is a circuit diagram illustrating an inverter circuit according to an embodiment of the present disclosure.

FIG. 2A to FIG. 2C are circuit diagrams illustrating a capacitor module and a single phase branch according to an embodiment of the present disclosure.

FIG. 3A to FIG. 3C are circuit diagrams illustrating a capacitor module and a single phase branch according to another embodiment of the present disclosure.

FIG. 4A and FIG. 4B are circuit diagrams illustrating a capacitor module and a single phase branch according to yet another embodiment of the present disclosure.

FIG. 5A and FIG. 5B are circuit diagrams illustrating a capacitor module and a single phase branch according to yet another embodiment of the present disclosure.

FIG. 6 is a flowchart illustrating a method for detecting a short circuit fault in a multi-level inverter circuit according to an embodiment of the present disclosure.

FIG. 7 is a circuit diagram illustrating an inverter circuit according to an embodiment of the present disclosure.

Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

Reference is now made to FIG. 1 . FIG. 1 is a circuit diagram illustrating an inverter circuit 1 according to an embodiment of the present disclosure. The inverter circuit 1 includes a capacitor module 10 , single phase branches 12 , 14 and 16 , and a fault detection module 18 .

The capacitor module 10 includes a first capacitor C 1 and a second capacitor C 2 electrically coupled in series via a first node P 1 . In an embodiment, the capacitor module 10 is coupled to other external circuits via a bus (not illustrated). The external circuit can be, for instance, a rectifier circuit (not illustrated), but is not limited thereto.

Each of the single phase branches 12 , 14 and 16 is coupled to the capacitor module 10 in parallel. In an embodiment, the single phase branches 12 , 14 and 16 have the same structure. The single phase branch 12 is utilized as an example for the descriptions below. The single phase branch 12 can be a two-level converter, a three-level converter or a five-level converter in different embodiments. The single phase branch 12 shown in FIG. 1 is realized with a three-level converter as an example, and the single phase branch 12 includes a first diode D 1 , a second diode D 2 , a first switch 120 , a second switch 122 , a third switch 124 and a fourth switch 126 .

The first diode D 1 and the second diode D 2 are electrically coupled in series between a third node P 3 and a fourth node P 4 via a second node P 2 . The second node P 2 is electrically coupled to the first node P 1 .

The first switch 120 and the second switch 122 are electrically coupled in series via the third node P 3 . The third switch 124 and the fourth switch 126 are electrically coupled in series via the fourth node P 4 . The second switch 122 and the third switch 124 are electrically coupled in series via a fifth node P 5 .

In an embodiment, the first switch 120 , the second switch 122 , the third switch 124 and the fourth switch 126 have the same structure. Taking the first switch 120 as an example, the first switch 120 includes an IGBT (Insulated Gate Bipolar Switch) 121 A and a diode 121 B, electrically coupled in parallel. The IGBT 121 A can be turned on or off according to a voltage signal applied to a gate terminal of the IGBT 121 A. The first, second, third and fourth switches 120 , 122 , 124 and 126 can be implemented by other structures in other embodiments, and are not limited to the present embodiment.

The fault detection module 18 can transmit detection pulse sequences to the first, second, third and fourth switches 120 , 122 , 124 and 126 in each of the single phase branches 12 , 14 , 16 respectively. The detection pulse sequence comprises a number of low level signals of “0” and high level signals of “1”. In an embodiment shown in FIG. 1 , an exemplary detection pulse sequence S 1 -S 4 is transmitted to the single phase branch 12 from the fault detection module 18 . The pulses S 1 , S 2 , S 3 and S 4 of the detection pulse sequence S 1 -S 4 correspond to the first, second, third and fourth switches 120 , 122 , 124 and 126 respectively.

Taking the pulse S 1 in the detection pulse sequence S 1 -S 4 as an example, when the pulse S 1 is “0” the corresponding first switch 120 is turned off, and when the pulse S 1 is “1”, the corresponding first switch 120 is turned on. When the switches of the single phase branch 12 function normally, the detection pulse sequence S 1 -S 4 does not cause any conducting loops to form in the single phase branch 12 .

Therefore, the fault detection module 18 determines whether there is a conducting loop formed in the single phase branch 12 according to the detection pulse sequence S 1 -S 4 being transmitted. When a conducting loop exists in the single phase branch 12 , the fault detection module 18 determines a position of a malfunctioned switch in the single phase branch 12 according to a path of the conducting loop.

Reference is now made to FIG. 2A to FIG. 2C . FIG. 2A to FIG. 2C are circuit diagrams illustrating the capacitor module 10 and the single phase branch 12 according to an embodiment of the present disclosure.

In FIG. 2A to FIG. 2C , the purpose of the detection pulse sequence transmitted by the fault detection module 18 is to turn on one of the first switch 120 , the second switch 122 , the third switch 124 and the fourth switch 126 , while keeping the other three being turned off.

For instance, in FIG. 2A , the transmitted detection pulse sequence S 1 -S 4 is “1000”. The first switch 120 receiving a high level (i.e. “1”) pulse is illustrated by solid lines, while the second switch 122 , the third switch 124 and the fourth switch 126 that receives a low level (i.e. “0”) pulse respectively, are illustrated by dotted lines.

When the second switch 122 and the third switch 124 function normally, the second switch 122 and the third switch 124 are turned off according to the detection pulse sequence S 2 , S 3 , and regardless of whether the fourth switch 126 functions normally or not, no conducting loop is formed between the single phase branch 12 and the capacitor module 10 . However, when a conducting loop is formed between the single phase branch 12 and the capacitor module 10 , it means the second switch 122 and the third switch 124 are defectively short-circuited.

As shown in FIG. 2A , the conducting loop LOOP 1 includes the first switch 120 , the second switch 122 , the third switch 124 , the capacitor C 1 and the second diode D 2 . If the conducting loop LOOP 1 is formed between the single phase branch 12 and the capacitor module 10 , the second switch 122 and third switch 124 of the conducting loop LOOP 1 are determined to be short-circuited, since the detection sequence is supposed to make the loop open-circuited. Hence whether the second switch 122 and the third switch 124 are short-circuited can be determined according to the detection pulse sequence S 1 -S 4 of “1000”.

In FIG. 2B , the transmitted detection pulse sequence S 1 -S 4 is “0100”. The second switch 122 that receives the high level (i.e. “1”) pulse is illustrated by solid lines, while the first switch 120 , the third switch 124 and the fourth switch 126 that receive a low level (i.e. “0”) pulse respectively, are illustrated by dotted lines.

When the first switch 120 and the third switch 124 function normally, the first switch 120 and the third switch 124 are turned off according to the pulses S 1 , S 3 . However, when a conducting loop LOOP 2 is formed between the single phase branch 12 and the capacitor module 10 , it means that the first switch 120 and the third switch 124 are defectively short-circuited.

In an embodiment, the fault detection module 18 determines that whether a conducting loop is formed in the single phase branch 12 according to the above detection pulse sequence and a hardware short-circuit protection mechanism.

As shown in FIG. 2B , the conducting loop LOOP 2 includes a first switch 120 , a second switch 122 , a third switch 124 , the capacitor C 1 and the second diode D 2 . If the conducting loop LOOP 2 is formed between the single phase branch 12 and the capacitor module 10 , the first switch 120 and the third switch 124 of the conducting loop LOOP 2 are determined to be short-circuited, since the detection sequence is supposed to make the loop open-circuited. Hence, whether the first switch 120 and the third switch 124 are short-circuited can be determined according to the detection pulse sequence S 1 -S 4 of “0100”.

However, it is noted that when the detection pulse sequence S 1 -S 4 is transmitted such that a conduction loop including the second switch 122 , the third switch 124 and the fourth switch 126 is formed via the capacitor C 2 and the first diode D 1 , it means that both the third switch 124 and the fourth switch 126 are defectively short-circuited.

On the other hand, when the detection pulse sequence S 1 -S 4 is transmitted such that a conduction loop including the first switch 120 , the second switch 122 , the third switch 124 and the fourth switch 126 is formed, it means that the first switch 120 , the third switch 124 and the fourth switch 126 are all defectively short-circuited.

In FIG. 2C , the transmitted detection pulse sequence S 1 -S 4 is “0010”. The third switch 124 that receives a high level (i.e. “1”) pulse is illustrated by solid lines, while the first switch 120 , the second switch 122 and the fourth switch 126 that receive a low level (i.e. “0”) pulse respectively, are illustrated by dotted lines.

When the second switch 122 and the fourth switch 126 function normally, the second switch 122 and the fourth switch 126 are turned off according to the pulses S 2 , S 4 , so there are no conducting loops formed between the single phase branch 12 and the capacitor module 10 . However, when a conducting loop LOOP 3 is formed between the single phase branch 12 and the capacitor module 10 , it means that the second switch 122 and the fourth switch 126 are defectively short-circuited.

As shown in FIG. 2C , the conducting loop LOOP 3 includes a second switch 122 , a third switch 124 , a fourth switch 126 , the capacitor C 2 and the first diode D 1 . If the conducting loop LOOP 3 is formed between the single phase branch 12 and the capacitor module 10 , the second switch 122 and the fourth switch 126 of the conducting loop LOOP 3 are determined to be short-circuited, since the detection sequence is supposed to make the loop open-circuited. Hence whether the second switch 122 and the fourth switch 126 are short-circuited can be determined according to the detection pulse sequence S 1 -S 4 of “0010”.

When the detection pulse sequence S 1 -S 4 is transmitted such that a conduction loop including the first switch 120 , the second switch 122 and the third switch 124 , the capacitor C 1 and the second diode D 2 is formed, both the first switch 120 and the second switch 122 are determined to be defectively short-circuited.

On the other hand, when the detection pulse sequence S 1 -S 4 is transmitted such that a conduction loop including the first switch 120 , the second switch 122 , the third switch 124 and the fourth switch 126 is formed, the first switch 120 , the second switch 122 and the fourth switch 126 are all determined to be defectively short-circuited.

A detection pulse sequence S 1 -S 4 of “0001” has the same effect as “1000” so in an embodiment, there is no need to transmit the detection pulse sequence S 1 -S 4 of “0001”.

Reference is now made to FIG. 3A to FIG. 3C . FIG. 3A to FIG. 3C are circuit diagrams illustrating the capacitor module 10 and the single phase branch 12 according to an embodiment of the present disclosure.

In FIG. 3A to FIG. 3C , the purpose of the detection pulse sequence transmitted by the fault detection module 18 is to turn on two of the first switch 120 , the second switch 122 , the third switch 124 and the fourth switch 126 , while keeping the other two being turned off.

For instance, in FIG. 3A , the transmitted detection pulse sequence S 1 -S 4 is “1100”. Each of the first switch 120 and the second switch 122 that receives a high level (i.e. “1”) pulse is illustrated by solid lines, while the third switch 124 and the fourth switch 126 that receive a low level (i.e. “0”) pulse respectively, are illustrated by dotted lines.

When the third switch 124 , which is next to the first switch 120 and the second switch 122 , functions normally, the third switch 124 is turned off according to the pulse S 3 . No conducting loop is formed between the single phase branch 12 and the capacitor module 10 , regardless of whether the fourth switch 126 functions normally. However, when a conducting loop LOOP 4 is formed between the single phase branch 12 and the capacitor module 10 , it means that the third switch 124 is defectively short-circuited.

As shown in FIG. 3A , the conducting loop LOOP 4 is formed via the first switch 120 , the second switch 122 , the third switch 124 , the capacitor C 1 and the second diode D 2 . If the conducting loop LOOP 4 is formed between the single phase branch 12 and the capacitor module 10 , the third switch 124 of the conducting loop LOOP 4 is determined to be short-circuited, since the detection sequence is supposed to make the loop open-circuited. Hence, whether the third switch 124 is short-circuited can be determined according to the detection pulse sequence S 1 -S 4 of “1100”.

In FIG. 3B , the transmitted detection pulse sequence S 1 -S 4 is “0011”. Each of the third switch 124 and the fourth switch 126 that receives a high level (i.e. “1”) pulse is illustrated by solid lines, while the first switch 120 and the second switch 122 , that receive a low level (i.e. “0”) pulse respectively, are illustrated by dotted lines.

When the second switch 122 next to the third switch 124 and the fourth switch 126 functions normally, the second switch 122 is turned off according to the pulse S 2 . No conducting loops are formed between the single phase branch 12 and the capacitor module 10 , regardless of whether the first switch 120 functions normally or not. However, when a conducting loop LOOP 5 is formed between the single phase branch 12 and the capacitor module 10 , it means that the second switch 122 is defectively short-circuited.

As shown in FIG. 3B , the conducting loop LOOP 5 is formed via the second switch 122 , the third switch 124 , the fourth switch 126 , the capacitor C 2 and the first diode D 1 . If the conducting loop LOOP 5 is formed between the single phase branch 12 and the capacitor module 10 , the second switch 122 of the conducting loop LOOP 5 is determined to be short-circuited, since the detection sequence is supposed to make the loop open-circuited. Hence whether the second switch 122 is short-circuited can be determined according to the detection pulse sequence S 1 -S 4 of “0011”.

In FIG. 3C , the transmitted detection pulse sequence S 1 -S 4 is “0110”. Each of the second switch 122 and the third switch 124 that receives a high level (i.e. “1”) pulse is illustrated by solid lines, while the first switch 120 and the fourth switch 126 that receive a low level (i.e. “0”) pulse respectively, are illustrated by dotted lines.

When the first switch 120 and the fourth switch 126 next to the second switch 122 and the third switch 124 respectively function normally, the first switch 120 and the fourth switch 126 are turned off according to the pulses S 1 and S 4 , and no conducting loop is formed. However, when a conducting loop LOOP 6 is formed between the single phase branch 12 and the capacitor module 10 , it means that the first switch 120 is defectively short-circuited.

As shown in FIG. 3C , the conducting loop LOOP 6 is formed via the first switch 120 , the second switch 122 , the third switch 124 , the capacitor C 1 and the second diode D 2 . If the conducting loop LOOP 6 is formed between the single phase branch 12 and the capacitor module 10 , the first switch 120 of the conducting loop LOOP 6 is determined to be short-circuited, since the detection sequence is supposed to make the loop open-circuited. Hence, whether the first switch 120 is short-circuited can be determined according to the detection pulse sequence S 1 -S 4 of “0110”.

In the present embodiment, when the detection pulse sequence S 1 -S 4 is transmitted such that a conduction loop including the capacitor C 2 , the first diode D 1 , the second switch 122 , the third switch 124 and the fourth switch 126 is formed, the fourth switch 126 is determined to be defectively short-circuited.

On the other hand, when the detection pulse sequence S 1 -S 4 is transmitted such that a conduction loop including the first switch 120 , the second switch 122 , the third switch 124 and the fourth switch 126 is formed, the first switch 120 and the fourth switch 126 are both determined to be defectively short-circuited.

Reference is now made to FIG. 4A and FIG. 4B . FIG. 4A and FIG. 4B are circuit diagrams illustrating the capacitor module 10 and the single phase branch 12 according to another embodiment of the present disclosure.

In FIG. 4A and FIG. 4B , the purpose of the detection pulse sequence transmitted by the fault detection module 18 is to turn on three of the first switch 120 , the second switch 122 , the third switch 124 and the fourth switch 126 , while keeping the rest one being turned off.

The fault detection module 18 can transmit the detection pulse sequence S 1 -S 4 to the respective first to fourth switches 120 - 126 via respective control signal lines (not illustrated). If the control signal lines corresponding to the respective first switch 120 and second switch 122 neighboring to each other are reversely coupled to the second switch 122 and first switch 120 respectively, unintended short-circuit may occur.

For instance, in FIG. 4A , the transmitted detection pulse sequence S 1 -S 4 is “1011”. Each of the first switch 120 , the third switch 124 and the fourth switch 126 that receives a high level (i.e. “1”) pulse is illustrated by solid lines, while the second switch 122 that receives a low level (i.e. “0”) pulse is illustrated by dotted lines.

When the control signal lines corresponding to the first switch 120 and the second switch 122 are not coupled reversely, there is no conducting loop being formed between the single phase branch 12 and the capacitor module 10 . However, when a conducting loop LOOP 7 is formed between the single phase branch 12 and the capacitor module 10 , it means that the control signal lines corresponding to the respective first switch 120 and the second switch 122 are reversely coupled as shown in FIG. 4A , and the second switch 122 is short-circuited.

As shown in FIG. 4A , the conducting loop LOOP 7 is formed via the capacitor C 2 , the first diode D 1 , the second switch 122 , the third switch 124 and the fourth switch 126 . If the conducting loop LOOP 7 is formed between the single phase branch 12 and the capacitor module 10 , the control signal lines corresponding to the respective first switch 120 and the second switch 122 can be determined to be reversely coupled. The conducting loop LOOP 7 is formed due to the second switch 122 being turned on as the control signal line corresponding to the first switch 120 is reversely coupled to the second switch 122 . Hence, whether the first switch 120 and the second switch 122 are short-circuited due to the corresponding control signal lines being reversely coupled can be determined according to the detection pulse sequence S 1 -S 4 of “1011”.

On the other hand, if the control signal lines corresponding to the third switch 124 and the fourth switch 126 are reversely coupled, unintended short-circuit can also occur.

For instance, in FIG. 4B , the transmitted detection pulse sequence S 1 -S 4 is “1101”. Each of the first switch 120 , the second switch 122 and the fourth switch 126 that receives a high level (i.e. “1”) pulse is illustrated by solid lines, while the third switch 124 that receives a low level (i.e. “0”) pulse is illustrated by dotted lines.

When the control signal lines corresponding to the third switch 124 and the fourth switch 126 are not reversely coupled, there is no conducting loop being formed between the single phase branch 12 and the capacitor module 10 . However, when the control signal lines corresponding to the respective third switch 124 and fourth switch 126 are reversely coupled as shown in FIG. 4B , the third switch 124 is short-circuited such that a conducting loop LOOP 8 is formed between the single phase branch 12 and the capacitor module 10 .

As shown in FIG. 4B , the conducting loop LOOP 8 is formed via the capacitor C 1 , the first switch 120 , the second switch 122 , the third switch 124 and the second diode D 2 . If the conducting loop LOOP 8 is formed between the single phase branch 12 and the capacitor module 10 , the control signal lines corresponding to the respective third switch 124 and fourth switch 126 can be determined to be reversely coupled, so the conducting loop LOOP 8 is formed due to the third switch 124 being turned on as the control signal line corresponding to the fourth switch 126 is reversely coupled to the third switch 124 . Hence, whether the third switch 124 and the fourth switch 126 are short-circuited due to the corresponding signal lines being reversely coupled can be determined according to the detection pulse sequence S 1 -S 4 of “1101”.

Reference is now made to FIG. 5A and FIG. 5B . FIG. 5A and FIG. 5B are circuit diagrams illustrating the capacitor module 10 and the single phase branch 12 according to another embodiment of the present disclosure.

The above detection pulse sequence can also be utilized to determine whether a physically reverse coupling condition of the first switch 120 and the second switch 122 , or of the third switch 124 and the fourth switch 126 occurs.

For instance, in FIG. 5A , the transmitted detection pulse sequence S 1 -S 4 is “1011”. Each of the first switch 120 , the third switch 124 and the fourth switch 126 that receives a high level (i.e. “1”) pulse is illustrated by solid lines, while the second switch 122 that receives a low level (i.e. “0”) pulse is illustrated by dotted lines.

When the first switch 120 and the second switch 122 are not reversely coupled, there is no conducting loop formed between the single phase branch 12 and the capacitor module 10 . However, when a conducting loop LOOP 9 is formed between the single phase branch 12 and the capacitor module 10 , it means that the first switch 120 and the second switch 122 are reversely coupled as shown in FIG. 5A .

As shown in FIG. 5A , the conducting loop LOOP 9 includes the second switch 122 , the third switch 124 , the fourth switch 126 , the capacitor C 2 and the first diode D 1 . If the conducting loop LOOP 9 is formed between the single phase branch 12 and the capacitor module 10 , the first switch 120 and the second switch 122 of the conducting loop LOOP 9 can be determined to be physically and reversely coupled. The conducting loop LOOP 9 is formed due to the second switch 122 being turned on as the control signal line corresponding to the first switch 120 is reversely coupled to the second switch 122 . Hence, whether the first switch 120 and the second switch 122 are short-circuited due to being physically and reversely coupled can be determined according to the detection pulse sequence S 1 -S 4 of “1011”.

On the other hand, if the control signal lines corresponding to the third switch 124 and the fourth switch 126 neighboring to each other are coupled reversely, unintended short-circuit can also occur.

For instance, in FIG. 5B , the transmitted detection pulse sequence S 1 -S 4 is “1101”. Each of the first switch 120 , the second switch 122 and the fourth switch 126 that receives a high level (i.e. “1”) pulse is illustrated by solid lines, while the third switch 124 that receives a low level (i.e. “0”) pulse is illustrated by dotted lines.

When the third switch 124 and the fourth switch 126 are not reversely coupled, there is no conducting loop formed between the single phase branch 12 and the capacitor module 10 . However, when a conducting loop LOOP 10 is formed between the single phase branch 12 and the capacitor module 10 , it means that the third switch 124 and the fourth switch 126 are reversely coupled as shown in FIG. 5B .

As shown in FIG. 5B , the conducting loop LOOP 10 is formed via the first switch 120 , the second switch 122 , the third switch 124 , the capacitor C 1 and the second diode D 2 . If the conducting loop LOOP 10 is formed between the single phase branch 12 and the capacitor module 10 , the third switch 124 and the fourth switch 126 of the conducting loop LOOP 10 can be determined to be physically and reversely coupled. The conducting loop LOOP 10 is formed due to the fourth switch 126 being turned on as the control signal line corresponding to the third switch 124 is reversely coupled to the fourth switch 126 . Hence, whether the third switch 124 and the fourth switch 126 are short-circuited due to being physically and reversely coupled can be determined according to the detection pulse sequence S 1 -S 4 of “1101”.

In an embodiment, the fault detection module 18 sequentially transmits a multiple of detection pulse sequences to each of the single phase branches 12 , 14 and 16 , so as to determine whether the switches are defectively short-circuited. Further, in an embodiment, an order of the detection pulse sequences being transmitted is determined based on the number of switches intended to be turned on in a single phase branch, in which the detection pulse sequences corresponding to less number of switches intended to be turned on are transmitted first. For instance, the fault detection module 18 can determine short-circuits by sequentially transmitting 6 detection pulse sequences S 1 -S 4 (“1000”, “0100”, “0010”, “1100”, “0011”, “0110”, “1011” and “1101”) to the first to the fourth switches 120 - 126 .

In an embodiment, the inverter circuit 1 which corresponds to three-phase AC (alternating current) power, includes three single phase branches, such as the single phase branches 12 , 14 and 16 as shown in FIG. 1 . The fault detection module 18 can sequentially transmit the detection pulse sequence S 1 -S 4 mentioned above to each of the single phase branches 12 , 14 and 16 .

In an embodiment, the above-mentioned short-circuit detections can be initiated once a voltage of the bus that the capacitor module 10 is coupled to is charged to a predetermined value. In different embodiments, the short-circuit detections can be initiated when the inverter circuit 1 starts to operate, or during the operation of the inverter circuit 1 . When at least one of the first to the fourth switches 120 - 126 is short-circuited or reversely coupled, the fault detection module 18 can perform a short-circuit protection process such as, but not limited to stop transmitting pulse signals that control the operation of the first to the fourth switches 120 - 126 to shut down the inverter circuit 1 . In addition, the fault detection module 18 can generate a fault detection result analysis according to a result of the short-circuit detection.

Reference is now made to FIG. 6 . FIG. 6 is a flowchart illustrating a short-circuit detection method 600 for detecting a short circuit fault in the multi-level inverter circuit, such as the multi-level inverter circuit 1 illustrated in FIG. 1 , according to an embodiment of the present disclosure. The method 600 includes the following steps (Unless specified otherwise, steps in the present embodiment can be performed in different orders according to practical needs. All steps, or a set of steps can even be performed at the same time, according to practical needs.)

In step 601 , the short-circuit detection process starts.

In step 602 , the bus is charged to a predetermined voltage.

In step 603 , at least one detection pulse sequence is transmitted to switches of each of the single phase branches 12 , 14 and 16 .

In step 604 , whether a conducting loop is formed in each of the single phase branches 12 , 14 and 16 is determined.

When a conducting loop is formed, the fault detection module 18 performs short-circuit protection in step 605 and locates a position of a malfunctioned switch in each of the single phase branches 12 , 14 and 16 according to a path of the conducting loop.

When there is no defective short-circuit, the detection pulse sequences are transmitted in the step 606 to determine whether the reverse coupling condition exists in between the first and the second switches 120 , 122 , or in between the third and the fourth switches 124 , 126 .

In step 607 , whether any conducting loops is formed in each of the single phase branches 12 , 14 and 16 can be determined according to the detection pulse sequences.

When a conducting loop is formed, the fault detection module 18 performs a short-circuit protection process in step 605 and determines a position of a malfunctioned switch in each of the single phase branches 12 , 14 and 16 according to a path of the conducting loop.

When there are no defective short-circuits, or the fault detection module 18 has completed the short-circuit protection and has confirmed the position of the malfunctioning switch, the fault detection module 18 performs a fault detection result analysis in step 608 and the short-circuit detection process is finished in step 609 .

Reference is now made to FIG. 7 . FIG. 7 is a circuit diagram illustrating an inverter circuit 7 according to an embodiment of the present disclosure. The inverter circuit 7 includes a capacitor module 70 , single phase branches 72 , 74 and 76 , and a fault detection module 78 .

The inverter circuit 7 can be a three-phase inverter circuit similar to the inverter circuit 1 as shown in FIG. 1 . The inverter circuit 7 includes 3 single phase branches 72 , 74 and 76 which are coupled to the capacitor module 70 in parallel. The inverter circuit 7 is different from the inverter circuit 1 in FIG. 1 in that the single phase branches 72 , 74 and 76 of the inverter circuit 7 can be two-level inverters. In an embodiment, the single phase branches 72 , 74 and 76 have the same structure and the detail structure of each of the single phase branch is described by using the single phase branch 72 as an example. The single phase branch 72 includes a first switch 720 and a second switch 722 coupled in series.

Similar to the inverter circuit 1 , the inverter circuit 7 can transmit a detection pulse sequence S 1 -S 2 to the first switch 720 and the second switch 722 of the single phase branch 72 via the fault detection module 78 . For instance, the fault detection module 78 can transmit a detection pulse sequence S 1 -S 2 of “01” and determine whether a conducting loop is formed in the single phase branch 72 . When a conducting loop exists, the fault detection module 78 can determine a position of the defective short-circuit according to a switch corresponding to the “0” of the “01” of the detection pulse sequence S 1 -S 2 .

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.