Differential reference signal distribution method and system

The present application claims the benefit of U.S. Provisional Application 61/990,107 filed May 8, 2014, which is incorporated herein by reference.

Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

Reference signals are mostly required in integrated circuit (IC) subsystems, either for the purpose of analog signal processing computations (e.g., A/D conversion, thresholding, offset shifting, measurement reference, etc.), or to determine the bias level of analog circuits.

Accurate distribution of reference signals to multiple subsystems on a large or complex integrated circuit is a frequent challenge to designers, especially in the modern “system on a chip” approach. Due to the inaccuracy of the absolute values of IC component parameters (e.g., capacitance, resistance, transistor threshold and gain), it is difficult to generate precision reference voltages or currents on integrated circuits. Circuit designs, that are commonly used to generate precision reference currents or voltages, often occupy large space, consume much power, have special start-up requirements and may require active trimming during IC production. For these reasons, when precision referencing is needed in any IC system, it is usually preferable to generate only one such reference signal centrally, either on the chip, or by an external component. “Copies” of this reference signal are then distributed to the subsystems where it is needed.

Conventional approaches of distributing either reference voltage or reference current to various subsystems in a large integrated circuit are inadequate. For example, distribution of multiple copies of a current signal can lead to unwanted circuit complexity (the signal distribution to each destination requires an individual signal wire) and power consumption (due to centrally generating multiple copies of a current signal at a subsystem).

The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. These drawings depict only several embodiments in accordance with the disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings.

FIG. 1 is a functional schematic of one example reference signal distribution system;

FIG. 2 is a functional schematic of another example reference signal distribution system;

FIG. 3 is a functional schematic of another example reference signal distribution system;

FIG. 4 is a functional schematic of another example reference signal distribution system; and

FIG. 5 is a flowchart of an illustrative embodiment of a method for operating the reference signal distribution reference signal distribution system, all arranged in accordance with at least some embodiments of the present disclosure.

The technical details set forth in the following description enable a person skilled in the art to implement one or more embodiments of the present disclosure.

FIG. 1 is a functional schematic of one example reference signal distribution system 100 in accordance with at least some embodiments of the present disclosure. FIG. 2 is a functional schematic of another example reference signal distribution system 200 in accordance with at least some embodiments of the present disclosure. FIG. 3 is a functional schematic of another example reference signal distribution system 300 in accordance with at least some embodiments of the present disclosure. FIG. 4 is a functional schematic of another example reference signal distribution system 400 in accordance with at least some embodiments of the present disclosure. Each of the reference signal distribution systems 100 , 200 , 300 and 400 includes a plurality of subsystems SUB 1 -SUBm (m is a positive integer larger than 1) which may be electrically connected to each other via two signals wires W 1 and W 2 . One of the subsystems SUB 1 -SUBm (hereafter as “reference subsystem”) may be biased by a controllable reference current, either centrally generated or externally supplied, in order to establish a differential voltage between a first terminal (designated by a node N 1 ) and a second terminal (designated by a node N 2 ) of the reference subsystem. The differential voltage may then be distributed as a reference signal to another one or multiple subsystems (hereafter as “destination subsystem”) when needed. Based on the distributed reference signal, copy of the reference current may be reproduced on one or multiple destination subsystems.

In the reference signal distribution system 100 illustrated in FIG. 1 and the reference signal distribution system 200 illustrated in FIG. 2 , each of the subsystems SUB 1 -SUBm may include a first-type transistor, a second-type transistor, a power supply and a power offset. QN 1 -QNm represent the first-type transistors of the subsystems SUB 1 -SUBm, respectively. QP 1 -QPm represent the second-type transistors of the subsystems SUB 1 -SUBm, respectively. QN 1 and QP 1 may also be referred to as diode-connected devices, because their gates are coupled to their drains. V SUPPLY1 -V SUPPLYm represent the power supplies of the subsystems SUB 1 -SUBm, respectively. V OFFSET1 -V OFFSETm represent the power offsets of the subsystems SUB 1 -SUBm, respectively. The transistors QN 1 -QNm and QP 1 -QPm may be, but not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), or another type of transistors having similar function. For illustrative purposes, each of the transistors QN 1 -QNm is depicted as a MOSFET having a first end (drain) and a control end (gate) connected together at the node N 1 , and each of the transistors QP 1 -QPm is depicted as a MOSFET having a first end (drain) and a control end (gate) connected together at the node N 2 in FIGS. 1-4 .

In an embodiment according to the present disclosure, the first-type transistors QN 1 -QNm and the second-type transistors QP 1 -QPm are doped with different types of carriers. For illustrative purposes, each of the first-type transistors QN 1 -QNm is depicted as a N type metal-oxide-semiconductor field-effect transistor (N-MOSFET), and each of the second-type transistors QP 1 -QPm is depicted as a P type metal-oxide-semiconductor field-effect transistor (P-MOSFET) in FIGS. 1-4 .

For illustrative purposes, it is assumed that reference signals are provided in the reference subsystem SUB 1 and then distributed to one or multiple destination subsystems SUB 2 -SUBm in order to generate copies of the reference signals. In an embodiment according to the present disclosure, a reference current I REF may be supplied into the drain of the first-type transistor QN 1 by a reference current source IS in the reference subsystem SUB 1 , as depicted by the reference signal distribution system 100 illustrated in FIG. 1 and the reference signal distribution system 300 illustrated in FIG. 3 . In another embodiment according to the present disclosure, a reference current I REF may be drawn from the drain of the second-type transistor QP 1 by the reference current source IS in the reference subsystem SUB 1 , as depicted by the reference signal distribution system 200 illustrated in FIG. 2 and the reference signal distribution system 400 illustrated in FIG. 4 .

In each subsystem of the reference signal distribution systems 100 , 200 , 300 and 400 , the second ends (sources) of the first-type and second type transistors are connected together to create a floating complimentary metal-oxide-semiconductor (CMOS) series transistor pair. If the reference current I REF is supplied into the drain of the transistor QN 1 or drawn from the drain of the transistor QP 1 , the floating CMOS series transistor pair formed by QN 1 and QP 1 may be biased to create a voltage difference between the two nodes N 1 and N 2 . This differential voltage V DIFF established between the nodes N 1 and N 2 may be distributed to one or multiple subsystems SUB 2 -SUBm using two signal wires W 1 and W 2 .

When the reference subsystem SUB 1 is connected to the destination subsystem SUB 2 via the two signal wires W 1 and W 2 , the floating CMOS series transistor pair formed by QN 2 and QP 2 may be biased by the differential voltage V DIFF . Consequently, a copy current I COPY2 associated with the reference current I REF may flow through the load resistance of the destination subsystem SUB 2 . The value of the copy current I COPY2 is determined by the ratio between the sizes of the transistors QN 2 and QN 1 and by the ratio between the sizes of the transistors QP 2 and QP 1 .

In an embodiment when the transistors QN 1 , QP 1 , QN 2 and QP 2 have the same size in width, the copy current I COPY2 flowing through the destination subsystem SUB 2 may be (approximately) the same as the reference current I REF flowing through the reference subsystem SUB 1 , regardless of any differences (within certain limits) between the power supply V SUPPLY1 of the reference subsystem SUB 1 and the power supply V SUPPLY2 of the destination subsystem SUB 2 and regardless of any differences (within certain limits) between the power offset V OFFSET1 of the reference subsystem SUB 1 and the power offset V OFFSET2 of the destination subsystem SUB 2 .

In another embodiment, the copy current I COPY2 flowing through the destination subsystem SUB 2 may be a scaled replica of the reference current I REF flowing through the reference subsystem SUB 1 . This can be achieved by scaling the width of the first-type transistor QN 2 by the required scaling factor relative to the width of the first-type transistor QN 1 , and by scaling the width of the second-type transistor QP 2 by the required scaling factor relative to the width of the second-type transistor QP 1 .

At least one benefit of the above described approach is that the reference current I REF can be reproduced anywhere in the reference signal distribution system 100 , without the need to access or reference to the exact supply voltages used at the reference subsystem (V SUPPLY1 and V OFFSET1 of the reference subsystem SUB 1 ).

Yet another benefit with the above described approach is that the reference current I REF can be reproduced multiple times without compromising the differential voltage between the signal lines W 1 and W 2 . The reason is that the gates of all diode-connected devices in the destination subsystems draw no current from the nodes N 1 and N 2 . Since the copy current I COPY2 flowing through the destination subsystem SUB 2 is solely dependent on the voltage difference between the nodes N 1 and N 2 , the magnitude of the reproduced copy current I COPY2 will be independent of local variations in supply voltages (V SUPPLY2 and V OFFSET2 of the destination subsystem SUB 2 ).

Yet another benefit with the above described approach is the ability to reproduce any number or magnitude of copies of the original reference current without causing extra power dissipation. The reason is that distribution of a reference signal as a differential voltage using two signal wire consumes much less power than the prior art method of distributing all required copies of the reference current which are generated at the reference subsystem.

Yet another benefit with the above described approach is the ability to reproduce any number or magnitude of copies of the original reference current without causing circuit complexity. The reason is that distribution of a reference signal as a differential voltage according to the present disclosure only requires two signal wires, instead of using individual wires to distribute all required copies of the reference current to each destination in the prior art.

If higher precision in the reproduction of the reference currents, or greater independence from local supply variations, is required, a cascoded approach, as shown in FIG. 3 and FIG. 4 , may be implemented. In the reference signal distribution system 300 illustrated in FIG. 3 and the reference signal distribution system 400 illustrated in FIG. 4 , the reference subsystem SUB 1 further includes two cascode bias V 1 and V 2 , and each of the destination subsystem SUB 2 -SUBm further includes an additional first-type transistor and an additional second-type transistor coupled in series to the local CMOS series transistor pair. QN 2 ′-QNm′ represent the additional first-type transistors of the subsystems SUB 2 -SUBm, respectively. QP 2 ′-QPm′ represent the additional second-type transistors of the subsystems SUB 2 -SUBm, respectively. The transistors QN 2 ′-QNm′ and QP 2 ′-QPm′ may be, but not limited to, MOSFETs, BJTs, or another type of transistors having similar function. In FIG. 3 and FIG. 4 for illustrative purposes, the additional first-type transistors QN 1 ′-QNm′ of the subsystems SUB 1 -SUBm are depicted as NMOSFETS each having a first end (drain) and a control end (gate) connected together at a node N 3 , and the additional second-type transistors QP 1 ′-QPm′ of the subsystems SUB 1 -SUBm are depicted as PMOSFETS each having a first end (drain) and a control end (gate) connected together at a node N 4 .

In the destination subsystem SUB 2 of the reference signal distribution system 200 illustrated in FIG. 3 and FIG. 4 , the first-type transistor QN 2 and the second-type transistor QP 2 form a transconductance amplifier, and the additional first-type transistor QN 2 ′ and the additional second-type transistor QP 2 ′ forms a current buffer. The purpose of QN 2 ′ and QP 2 ′ is to ensure that QN 2 and QP 2 respectively, may each see a constant drain-to-source voltage and thus generate currents that are now independent of local supplies (within limits) or load resistance (within limits). Four signal wires W 1 -W 4 are now required to transmit the reference signal from a reference subsystem to one or multiple destination subsystems in the reference signal distribution systems 300 and 400 . The generated copies may still be dependent only on the differential voltage V DIFF between the nodes N 1 and N 2 and unaffected by the local variations in supply voltage or load resistance.

FIG. 5 is a flowchart of an illustrative embodiment of a method to distribute reference signals in accordance with at least some embodiments of the present disclosure. Method 500 may include one or more operations, functions or actions as illustrated by one or more of blocks 502 , 504 , 506 , and/or 508 . The various blocks may be combined into fewer blocks, divided into additional blocks, and/or eliminated based upon the desired implementation. Method 500 may also be performed by a reference signal distribution system, such as the ones described in conjunction with FIGS. 1, 2, 3 , and 4 .

Processing for method 500 may begin at block 502 , “provide a reference current”. Block 502 may be followed by block 504 , “bias a first floating CMOS series transistor pair by the reference current to establish a differential voltage between a first node and a second node.” Block 504 may be followed by block 506 , “couple a second floating CMOS series transistor pair to the first node and the second node to receive the differential voltage.” Block 506 may be followed by block 508 , “generate a copy current associated with the reference current using the second floating CMOS series transistor pair driven by the differential voltage.”

Although the approach discussed above in conjunction with FIG. 1 to FIG. 5 principally refers to a reference current distribution system, it should be apparent to those skilled in the art to use such a reference signal distribution system to distribute reference voltages. More specifically, the current source IS in the reference signal distribution systems 100 and 200 may be replaced by a reference voltage source V REF in series with a resistor for providing the reference current I REF . Copies of the reference current I REF may be reproduced at each destination subsystem and then converted back to copy voltages through a matched resistor at each destination subsystem. The reference current V REF can be reproduced anywhere and many times in the reference signal distribution systems 100 and 200 without the need to access or reference to the exact supply voltages used at the reference subsystem, without compromising the differential voltage between the signal lines W 1 and W 2 , and without causing extra power dissipation or circuit complexity.

Although the present disclosure has been described with reference to specific exemplary embodiments, it will be recognized that the disclosure is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense.