Semiconductor structure

This application claims the benefit of People's Republic of China application Serial No. 201510150356.8, filed Apr. 1, 2015, the subject matter of which is incorporated herein by reference.

The disclosure relates in general to a semiconductor structure, and more particularly to a semiconductor structure comprising an electrostatic discharge (ESD) protection device.

Electrostatic discharge (ESD) may cause damage to sensitive electronic devices. As such, ESD protection devices are typically provided in semiconductor structures. There are several requirements for an ESD protection device to be achieved, such as human body model (HBM) standard and machine model (MM) standard. In the HBM standard, a 2 kV level is required. In the MM standard, a 200 V level is required.

A middle-voltage NMOS structure may be applied in an ESD protection device. However, a p-type ESD (hereinafter PESD) mask is needed to achieve the HBM and MM requirements. An ESD protection device saving the PESD mask may be beneficial for manufacturing cost, etc.

The disclosure is directed to a semiconductor structure, which comprises an ESD protection device saving the PESD mask.

According to some embodiment, the semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The well has a first doping type. The first lightly doped region is disposed in the well. The first lightly doped region has a second doping type. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The second lightly doped region has the second doping type. The first heavily doped region is disposed in the first lightly doped region. The first heavily doped region has the second doping type. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has the second doping type. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region.

FIGS. 1A-1B show a semiconductor structure according to one embodiment.

FIGS. 2-3 show features of examples/an example according to one embodiment.

FIG. 4 shows a circuit in which a semiconductor structure according to one embodiment may be applied.

FIGS. 5A-5B show a semiconductor structure according to one embodiment.

FIG. 6 shows a circuit in which a semiconductor structure according to one embodiment may be applied.

FIG. 7 shows a semiconductor structure according to one embodiment.

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

Referring to FIGS. 1A-1B , a semiconductor structure 100 according to one embodiment is shown. FIG. 1A shows a top view of the semiconductor structure 100 . FIG. 1B shows a cross-sectional view of the semiconductor structure 100 roughly reflecting the cross section along 1 - 1 ′ line in FIG. 1A .

The semiconductor structure 100 comprises a well 102 , a first lightly doped region 104 , a second lightly doped region 106 , a first heavily doped region 108 , a second heavily doped region 110 and a gate 114 . The well 102 has a first doping type. The first lightly doped region 104 is disposed in the well 102 . The first lightly doped region 104 has a second doping type. The second lightly doped region 106 is disposed in the well 102 and separated from the first lightly doped region 104 . The second lightly doped region 106 has the second doping type. The first heavily doped region 108 is disposed in the first lightly doped region 104 . The first heavily doped region 108 has the second doping type. The second heavily doped region 110 is partially disposed in the second lightly doped region 106 . The second heavily doped region 110 has the second doping type. The second heavily doped region 110 has a surface 112 contacting the well 102 . The gate 114 is disposed on the well 102 between the first heavily doped region 108 and the second heavily doped region 110 .

In this embodiment, the surface 112 contacting the well 102 is located near the gate 114 . According to one embodiment, the surface 112 contacting the well 102 preferably has a width D equal to or higher than 0.5 μm, such as equal to or higher than 0.75 μm, or equal to or higher than 1 μm. The upper limit of the width D is restricted by the rule of the second heavily doped region 110 , such as 2.5 μm. Due to the surface 112 contacting the well 102 , an additional PESD mask is unneeded.

In one embodiment, the first doping type is p-type, and the second doping type is n-type. In one embodiment, the first heavily doped region 108 and the second heavily doped region 110 comprise dopants of different concentrations implanted into different depths. For example, the first heavily doped region 108 and the second heavily doped region 110 may comprise phosphorus (P) of 3×10 13 cm −3 with a depth of 4000 nm and arsenic (As) of 6×10 15 cm −3 with a depth of 6000 nm. Further, the first lightly doped region 104 and the second lightly doped region 106 may comprise phosphorus of 2.9×10 13 cm −3 with a depth of 9000 nm.

The semiconductor structure 100 may further comprise a deep well 116 . The deep well 116 has the second doping type. The well 102 is disposed in the deep well 116 . The semiconductor structure 100 may further comprise a third heavily doped region 118 disposed in the well 102 . The third heavily doped region 118 has the first doping type. For example, the third heavily doped region 118 may comprise boron (B) of 3.15×10 15 cm −3 with a depth of 800 nm and boron of 7×10 13 cm −3 with a depth of 2000 nm. The semiconductor structure 100 may further comprise contacts 120 , 122 and 124 connecting to the first heavily doped region 108 , the second heavily doped region 110 and the third heavily doped region 118 , respectively.

The semiconductor structure 100 may comprise a plurality of ESD protection devices 105 - 1 to 105 - 4 . Each of them comprises the well 102 , the first lightly doped region 104 , the second lightly doped region 106 , the first heavily doped region 108 , the second heavily doped region 110 and the gate 114 . In one embodiment, two adjacent ESD protection devices may share the second lightly doped region 106 and the second heavily doped region 110 , such as the ESD protection devices 105 - 1 and 105 - 2 . In another embodiment, two adjacent ESD protection devices may share the first lightly doped region 104 and the first heavily doped region 108 , such as the ESD protection devices 105 - 2 and 105 - 3 . The ESD protection devices 105 - 1 to 105 - 4 may achieve the HBM and MM requirements. In other words, the HBM test result of the ESD protection device 105 - 1 / 105 - 2 / 105 - 3 / 105 - 4 is equal to or higher than 2 kV, and the MM test result of the ESD protection device 105 - 1 / 105 - 2 / 105 - 3 / 105 - 4 is equal to or higher than 200 V.

Referring to FIG. 2 , test results of examples according to this embodiment and comparative examples are shown. A typical middle-voltage NMOS without a PESD mask is used in comparative example 1. A middle-voltage NMOS with a PESD mask is used in comparative example 2. ESD protection devices according to the embodiment in which D=0.5 μm, D=0.75 μm and D=1 μm are used in examples 1, 2 and 3, respectively. Breakdown voltages (BV), Vt 1 s, It 2 s, HBM test results and MM test results are listed in Table 1. The Vt 1 values of the examples according to the embodiment, 12.5 V, are lower than the junction breakdown voltage, which typically is about 15 V, and thereby high turn-on speed can be achieved. Besides, the holding voltages of the examples according to the embodiment are higher than circuit operation voltage. As such, the examples according to the embodiment can be used as ESD protection devices. Further, it is notes that, even the PESD mask is not used, the examples according to the embodiment have good ESD protection performance (HBM test result≧2 kV, MM test result≧200 V).

Referring to FIG. 3 , simulation results of lattice temperatures of an example according to the embodiment and a comparative example are shown. It is noted that, under the same drain current, the lattice temperature of the example according to the embodiment is lower. As such, hot spot shrinks, or even disappears completely. FIG. 4 shows a circuit in which the semiconductor structure 100 may be applied.

Now referring to FIGS. 5A-5B , a semiconductor structure 200 according to one embodiment is shown. FIG. 5A shows a top view of the semiconductor structure 200 . FIG. 5B shows a cross-sectional view of the semiconductor structure 200 roughly reflecting the cross section along 2 - 2 ′ line in FIG. 5A .

In this embodiment, the second lightly doped region 206 is configured such that the surface 212 contacting the well 102 is located in a middle area of the second heavily doped region 110 . Other features of the semiconductor structure 200 are the same as the features of the semiconductor structure 100 . According to one embodiment, the surface 212 contacting the well 102 preferably has a width D equal to or higher than 1 μm.

While not shown in the figures are listed here, the ESD protection devices 205 - 1 to 205 - 4 according to this embodiment can achieve the HBM and MM requirements. Further, hot spot shrinks in the example according to this embodiment. FIG. 6 shows a circuit in which the semiconductor structure 200 may be applied.

Referring to FIG. 7 , a semiconductor structure 300 according to one embodiment is shown. More specifically, FIG. 7 shows a cross-sectional view of the semiconductor structure 300 . In this embodiment, the second lightly doped region 306 and the second heavily doped region 310 are configured such that the second heavily doped region 310 has a depth d 1 equal to or deeper than a depth d 2 of the second lightly doped region 306 , and thereby a surface 312 of the second lightly doped region 306 directly contacts the well 102 . Other features of the semiconductor structure 300 are the same as the features of the semiconductor structure 100 .

The semiconductor structure according to the embodiments can be easily fabricated by a typical MOS manufacturing process without an additional PESD mask. As such, the ESD protection function can be achieved by a lower cost.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.