Reception unit and receiving method

The present disclosure relates to a reception unit that receives a data signal, and to a receiving method used in such a reception unit.

In many communication systems, a transmission unit transmits a data signal, and a clock and data recovery (CDR) circuit in a reception unit reproduces a clock signal and the data signal from the received data signal. More specifically, the CDR circuit reproduces the clock signal from the received data signal, and performs retiming on the received data signal with use of the reproduced clock signal to reproduce the data signal. Japanese Unexamined Patent Application Publication Nos. H8-213979, 2007-181000, and 2009-239510 disclose a CDR circuit using a so-called gated voltage controlled oscillator (VCO) that reproduces a clock signal and a data signal based on a burst signal.

In general, for a communication system, high communication quality is desired, and further improvement of the communication quality is expected.

It is desirable to provide a reception unit and a receiving method that are capable of improving the communication quality.

According to an embodiment of the present disclosure, there is provided a reception unit including a transition detection section, an oscillation section, a first sampling section, and a control section. The transition detection section is configured to detect a transition of an input data signal. The oscillation section is configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section. The clock signal has a frequency in accordance with a first control signal. The first sampling section is configured to sample the input data signal based on the clock signal and thereby generate an output data signal. The control section is configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.

According to an embodiment of the present disclosure, there is provided a receiving method including: detecting a transition of an input data signal; generating a clock signal and varying a phase of the clock signal based on the transition of the input data signal, the clock signal having a frequency in accordance with a first control signal; sampling the input data signal based on the clock signal, and thereby generating an output data signal; and generating the first control signal based on the input data signal, the output data signal, and the clock signal.

In the reception unit and the receiving method of the embodiments of the present disclosure, the phase of the clock signal is varied based on the transition of the input data signal, the input data signal is sampled based on the clock signal, and the output data signal is thereby generated. The frequency of the clock signal is controlled, with use of the first control signal, based on the input data signal, the output data signal, and the clock signal.

According to the reception unit and the receiving method of the embodiments of the present disclosure, the first control signal is generated based on the input data signal, the output data signal, and the clock signal. As a result, it is possible to improve the communication quality. It is to be noted that effects of the present disclosure are not necessarily limited to the effects described above, and may include any of effects described herein.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the specification, serve to explain the principles of the technology.

FIG. 1 is a block diagram illustrating a configuration example of a reception unit according to an embodiment of the present disclosure.

FIG. 2 is a circuit diagram illustrating a configuration example of a variable delay circuit illustrated in FIG. 1 .

FIG. 3 is a timing waveform chart illustrating an operation example of the variable delay circuit illustrated in FIG. 1 .

FIG. 4 is a circuit diagram illustrating a configuration example of an oscillator circuit illustrated in FIG. 1 .

FIG. 5 is a timing waveform chart illustrating an operation example of a variable delay circuit and an oscillator circuit according to a first embodiment.

FIG. 6 is a timing waveform chart illustrating an operation example of flip-flop circuits illustrated in FIG. 1 .

FIG. 7 is a timing waveform chart illustrating another operation example of the flip-flop circuits illustrated in FIG. 1 .

FIG. 8 is a block diagram illustrating a configuration example of a control circuit according to the first embodiment.

FIG. 9 is a timing waveform chart illustrating an operation example of a reception unit according to the first embodiment.

FIG. 10 is a timing waveform chart illustrating an operation example of a reception unit according to a modification of the first embodiment.

FIG. 11 is a timing waveform chart illustrating an operation example of a reception unit according to another modification of the first embodiment.

FIG. 12 is a timing waveform chart illustrating an operation example of a reception unit according to another modification of the first embodiment.

FIG. 13A is a block diagram illustrating a configuration example of an oscillator circuit according to another modification of the first embodiment.

FIG. 13B is a block diagram illustrating a configuration example of an oscillator circuit according to another modification of the first embodiment.

FIG. 13C is a block diagram illustrating a configuration example of an oscillator circuit according to another modification of the first embodiment.

FIG. 14A is a block diagram illustrating a configuration example of a reception unit according to another modification of the first embodiment.

FIG. 14B is a block diagram illustrating a configuration example of a reception unit according to another modification of the first embodiment.

FIG. 15A is a block diagram illustrating a configuration example of a reception unit according to another modification of the first embodiment.

FIG. 15B is a block diagram illustrating a configuration example of a reception unit according to another modification of the first embodiment.

FIG. 15C is a block diagram illustrating a configuration example of a reception unit according to another modification of the first embodiment.

FIG. 16 is a block diagram illustrating a configuration example of a reception unit according to another modification of the first embodiment.

FIG. 17 is a timing waveform chart illustrating an operation example of flip-flop circuits illustrated in FIG. 16 .

FIG. 18 is a timing waveform chart illustrating another operation example of the flip-flop circuits illustrated in FIG. 16 .

FIG. 19 is a block diagram illustrating a configuration example of a reception unit according to another modification of the first embodiment.

FIG. 20 is a block diagram illustrating a configuration example of a control circuit illustrated in FIG. 19 .

FIG. 21 is a block diagram illustrating a configuration example of a reception unit according to another modification of the first embodiment.

FIG. 22 is a block diagram illustrating a configuration example of a control circuit illustrated in FIG. 21 .

FIG. 23 is a timing waveform chart illustrating an operation example of a variable delay circuit and an oscillator circuit according to a second embodiment.

FIG. 24 is a block diagram illustrating a configuration example of a control circuit according to the second embodiment.

FIG. 25 is a timing waveform chart illustrating an operation example of a reception unit according to the second embodiment.

FIG. 26 is a block diagram illustrating a configuration example of a reception unit according to another modification of the second embodiment.

FIG. 27 is a block diagram illustrating a configuration example of a variable delay circuit according to another modification.

FIG. 28 is a block diagram illustrating a configuration example of a reception unit according to another modification.

FIG. 29 is a block diagram illustrating a configuration example of a variable delay circuit illustrated in FIG. 28 .

FIG. 30 is a block diagram illustrating a configuration example of a reception unit according to another modification.

Some embodiments of the present disclosure are described below in detail with reference to the drawings. The description is provided in the following order.

1. First Embodiment

2. Second Embodiment

1. First Embodiment

Configuration Example

FIG. 1 illustrates a configuration example of a reception unit (a reception unit 1 ) according to a first embodiment of the present disclosure. It is to be noted that a receiving method according to an embodiment of the present disclosure is embodied by the present embodiment, and is therefore described together.

The reception unit 1 may be a CDR circuit that reproduces a clock signal CK and a data signal DT 2 from a received data signal DT. For example, the data signal DT may be scrambled, and may include a signal portion that toggles consecutively as “1010”. The reception unit 1 may include a variable delay circuit 20 , an oscillator circuit 30 , flip-flop circuits 11 and 12 , and a control circuit 40 .

The variable delay circuit 20 delays the data signal DT by a delay amount in accordance with a control signal CTLP, and outputs the delayed signal as a data signal DT 1 .

FIG. 2 illustrates a configuration example of the variable delay circuit 20 . The variable delay circuit 20 includes a delay circuit 21 and an inverter 22 . It is to be noted that, although one delay circuit 21 is used to configure the variable delay circuit 20 in this example, the number of the delay circuit 21 is not limited to one, and a plurality of delay circuits 21 that are connected in series to one another may be used to configure the variable delay circuit 20 .

The delay circuit 21 delays the data signal DT by a delay amount in accordance with the control signal CTLP and inverts the data signal, as well as outputs the delayed and inverted signal. The delay circuit 21 includes current sources 26 and 29 and transistors 27 and 28 . Each of the current sources 26 and 29 is a so-called variable current source that generates a current, having a current value in accordance with the control signal CTLP, from a first terminal thereof to a second terminal thereof. The first terminal of the current source 26 is supplied with a power voltage VDD, and the second terminal thereof is connected to a source of the transistor 27 . The first terminal of the current source 29 is connected to a source of the transistor 28 , and the second terminal thereof is grounded. The transistor 27 is a P-channel metal oxide semiconductor (MOS) transistor. A gate of the transistor 27 is supplied with the data signal DT, the source thereof is connected to the second terminal of the current source 26 , and a drain thereof is connected to a drain of the transistor 28 and is connected to an input terminal of the inverter 22 . The transistor 28 is an N-channel MOS transistor. A gate of the transistor 28 is supplied with the data signal DT, the drain thereof is connected to the drain of the transistor 27 and is connected to the input terminal of the inverter 22 , and the source thereof is connected to the first terminal of the current source 29 .

In the delay circuit 21 , this configuration allows the transistors 27 and 28 to function as inverters to invert the data signal DT and output the inverted signal. At that time, the current sources 26 and 29 each generate the current having the current value in accordance with the control signal CTLP. Accordingly, in the delay circuit 21 , when the current value is large, an output voltage makes a transition in a short time, which results in a small delay amount, and when the current value is small, the output voltage makes a transition slowly, which results in a large delay amount. The delay circuit 21 thus functions as a current-control-type delay circuit. It is to be noted that, although the delay amount is controlled based on the current value in this example, the configuration to be employed is not limited thereto. Alternatively, various configurations that are capable of adjusting the delay amount may be employed. For example, a method of controlling the delay amount based on a load capacitance value may be employed.

The inverter 22 inverts a signal supplied from the delay circuit 21 , and outputs the inverted signal as the data signal DT 1 .

FIG. 3 illustrates an operation example of the variable delay circuit 20 , in which (A) illustrates a waveform of the data signal DT, and (B) illustrates a waveform of the data signal DT 1 . (B) of FIG. 3 illustrates the data signals DT 1 in three cases C 1 to C 3 . The case C 1 is a case where a delay amount “d” is small, the case C 2 is a case where the delay amount “d” is medium, and the case C 3 is a case where the delay amount “d” is large. In the variable delay circuit 20 , both of the delay circuit 21 and the inverter 22 invert the signals inputted thereto and output the inverted signals. Accordingly, a polarity of the signal (the data signal DT) inputted to the variable delay circuit 20 is the same as a polarity of a signal (the data signal DT 1 ) outputted from the variable delay circuit 20 . The delay amount “d” of the variable delay circuit 20 corresponds to sum of the delay amount of the delay circuit 21 and the delay amount of the inverter 22 . The delay amount “d” is so controlled by the control circuit 40 with use of the control signal CTLP that a falling timing of the clock signal CK (described later) coincides with a transition timing of the data signal DT 1 , which is described later.

The oscillator circuit 30 generates the clock signal CK that has a frequency in accordance with the control signal CTLF. The oscillator circuit 30 also has a function of varying a phase of the clock signal CK based on the data signal DT.

FIG. 4 illustrates a configuration example of the oscillator circuit 30 . The oscillator circuit 30 includes an edge detection circuit 37 , delay circuits 31 to 35 , and an AND circuit 36 . It is to be noted that, although five delay circuits 31 to 35 are used in this example, the number of the delay circuits is not limited to five. Alternatively, four-or-less delay circuits may be used, or six or more delay circuits may be used.

The edge detection circuit 37 detects a rising edge and a falling edge of the data signal DT, and thereby generates a signal E 1 . More specifically, the edge detection circuit 37 sets the signal E 1 to a high level when the data signal DT makes no transition, and sets the signal E 1 to a low level in a period PG when the data signal DT makes a transition. The period PG is a period having a length that is about half of a bit length (a unit interval UI) of the data signal DT.

Each of the delay circuits 31 to 35 delays a signal inputted thereto by a delay amount in accordance with the control signal CTLF and inverts the signal, as well as outputs the delayed and inverted signal. Each of the delay circuits 31 to 35 may have a configuration similar to the configuration of the delay circuit 21 illustrated in FIG. 2 , for example. The delay circuits 31 to 35 are connected in series to one another in this order. An input terminal of the most-upstream delay circuit 31 is connected to an output terminal of the AND circuit 36 , and an output terminal of the most-downstream delay circuit 35 is connected to a first input terminal of the AND circuit 36 .

The AND circuit 36 calculates a logical product (AND) of a signal supplied to the first input terminal thereof and a signal supplied to the second input terminal thereof, and outputs a result of the calculation as the clock signal CK. The first input terminal of the AND circuit 36 is connected to the output terminal of the delay circuit 35 , the second input terminal thereof is connected to an output terminal of the edge detection circuit 37 and is supplied with the signal E 1 , and the output terminal thereof is connected to the input terminal of the delay circuit 31 . It is to be noted that, in addition to the function of calculating AND, the AND circuit 36 may further have a function of setting a delay amount in accordance with the control signal CTLF as with the delay circuits 31 to 35 .

Due to this configuration, in the oscillator circuit 30 , when the data signal DT makes no transition, the signal E 1 is kept at the high level. Accordingly, a loop including the delay circuits 31 to 35 and the AND circuit 36 configures a so-called ring oscillator, and generates the clock signal CK having the frequency in accordance with the control signal CTLF. More specifically, for example, when the respective delay amounts of the delay circuits 31 to 35 are large, a delay amount of the loop is made large, which causes the frequency of the clock signal CK to be low. For example, when the respective delay amounts of the delay circuits 31 to 35 are small, the delay amount of the loop is made small, which causes the frequency of the clock signal CK to be high. As will be described later, the frequency of the clock signal CK is so controlled by the control circuit 40 with use of the control signal CTLF that a value of a bit rate of the data signal DT become the same as a value of the frequency of the clock signal CK.

In the oscillator circuit 30 , when the data signal DT makes a transition, the phase of the clock signal CK is varied in response to the transition of the data signal DT. Specifically, when the data signal DT makes a transition, the signal E 1 is set to the low level for a predetermined period in response to the transition of the data signal DT. The AND circuit 36 therefore sets the output signal (the clock signal CK) to the low level. In other words, the oscillator circuit 30 corrects the phase of the clock signal CK in response to the transition of the data signal DT. After this transition, the loop in the oscillator circuit 30 functions as the ring oscillator. In such a manner, the oscillator circuit 30 varies the phase of the clock signal CK based on the data signal DT.

FIG. 5 illustrates an operation example of the variable delay circuit 20 and the oscillator circuit 30 , in which (A) illustrates the waveform of the data signal DT, (B) illustrates a waveform of the signal E 1 , (C) illustrates the waveform of the data signal DT 1 , and (D) illustrates a waveform of the clock signal CK.

In this example, first, the edge detection circuit 37 in the oscillator circuit 30 detects a rising edge of the data signal DT at a timing t 11 , and sets the signal E 1 to the low level in a period PG that starts from a timing t 12 ((B) of FIG. 5 ). The timing t 12 is a timing that is later than the timing t 11 by a circuit delay. In response to varying of the signal E 1 to the low level at the timing t 12 , the AND circuit 36 sets the clock signal CK to the low level in a predetermined period that starts from a timing t 13 . The timing t 13 is a timing that is later than the timing t 12 by a circuit delay. In a similar manner, for example, the edge detection circuit 37 detects a falling edge of the data signal DT at a timing t 14 , and sets the signal E 1 to the low level in a period PG starting from a timing t 15 that is a timing that is later than the timing t 14 by a circuit delay. In response to varying of the signal E 1 to the low level at the timing t 15 , the AND circuit 36 sets the clock signal CK to the low level in a predetermined period starting from a timing t 16 that is a timing that is later than the timing t 15 by a circuit delay.

The variable delay circuit 20 delays the data signal DT that rises at the timing t 11 and falls at the timing t 14 to generate the data signal DT 1 that rises at the timing t 13 and falls at the timing t 16 . As a result, a timing at which the clock signal CK falls almost coincides with a timing at which the data signal DT 1 makes a transition in the reception unit 1 , as illustrated in FIG. 5 . In such a manner, the delay amount of the variable delay circuit 20 is so controlled that the falling timing of the clock signal CK coincides with the transition timing of the data signal DT 1 in the reception unit 1 .

In this example, the flip-flop circuit (F/F) 11 samples the data signal DT 1 at the rising timing of the clock signal CK, and thereby generates the data signal DT 2 . As illustrated in (C) and (D) of FIG. 5 , the rising timing of the clock signal CK is near the middle of the unit interval UI of the data signal DT 1 . In other words, the flip-flop circuit 11 functions as a so-called decision circuit. Further, the flip-flop circuit 11 supplies the generated data signal DT 2 to the control circuit 40 , and supplies the generated data signal DT 2 to a circuit downstream of the reception unit 1 via the output terminal of the flip-flop circuit 11 .

In this example, the flip-flop circuit (F/F) 12 samples the data signal DT 1 at the falling timing of the clock signal CK, and thereby generates the signal D 1 . Further, the flip-flop circuit 12 supplies the generated signal D 1 to the control circuit 40 .

It is to be noted that, although the flip-flop circuit 11 samples the data signal DT 1 at the rising timing of the clock signal CK and the flip-flop circuit 12 samples the data signal DT 1 at the falling timing of the clock signal CK in this example, the configuration to be employed is not limited thereto. Alternatively, the flip-flop circuit 11 may sample the data signal DT 1 at the falling timing of the clock signal CK and the flip-flop circuit 12 may sample the data signal DT 1 at the rising timing of the clock signal CK.

FIGS. 6 and 7 each illustrate operations of the flip-flop circuits 11 and 12 . FIG. 6 illustrates a case where the phase of the clock signal CK is advanced, and FIG. 7 illustrates a case where the phase of the clock signal CK is delayed. In each of FIGS. 6 and 7 , (A) illustrates the waveform of the data signal DT 1 , (B) illustrates the waveform of the clock signal CK, (C) illustrates a waveform of the data signal DT 2 , and (D) illustrates a waveform of the signal D 1 .

In this example, the reception unit 1 is supplied with the data signal DT 1 that includes data Q n and data Q n+1 . The flip-flop circuit 11 samples the data signal DT 1 at a timing when the clock signal CK rises, and thereby generates the data signal DT 2 . As a result, the data Q n and the data Q n+1 appear in the data signal DT 2 as illustrated in FIGS. 6 and 7 . The flip-flop circuit 12 samples the data signal DT 1 at a timing when the clock signal CK falls, and thereby generates the signal D 1 .

In the case where the phase of the clock signal CK is advanced ( FIG. 6 ), the falling timing of the clock signal CK (for example, a timing t 22 ) is earlier than the transition timing of the data signal DT 1 (for example, a timing t 23 ). Accordingly, the data signal DT 1 (in this example, the data Q n ) at a timing earlier than this transition timing of the data signal DT 1 appears in the signal D 1 . The signal D 1 (the data Q n ) in a period from the timing t 22 to a timing t 25 is the same as the data signal DT 2 (the data Q n ) in a period from the timing t 21 to a timing t 24 .

On the other hand, in the case where the phase of the clock signal CK is delayed ( FIG. 7 ), the falling timing of the clock signal CK (for example, a timing t 33 ) is later than the transition timing of the data signal DT 1 (for example, a timing t 32 ). Accordingly, the data signal DT 1 (in this example, the data Q n+1 ) at a timing later than this transition timing of the data signal DT 1 appears in the signal D 1 . The signal D 1 (the data Q n+1 ) in a period from the timing t 33 to a timing t 35 is the same as the data signal DT 2 (the data Q n+1 ) in a period from a timing t 34 to a timing t 36 .

In such a manner, the flip-flop circuits 11 and 12 sample the data signal DT 1 and thereby generate the data signal DT 2 and the signal D 1 , respectively. Further, the control circuit 40 described next makes a comparison between the data signal DT 1 and the signal D 1 , and thereby generates the control signals CTLP and CTLF.

The control circuit 40 generates the control signals CTLP and CTLF based on the data signal DT 2 , the signal D 1 , and the clock signal CK.

FIG. 8 illustrates a configuration example of the control circuit 40 . The control circuit 40 may include an edge detection circuit 41 , a phase comparison circuit 42 , a phase determination circuit 43 , a frequency determination circuit 44 , and integration circuits 45 and 46 .

The edge detection circuit 41 detects a rising edge and a falling edge of the data signal DT 2 based on the data signal DT 2 and the clock signal CK. Further, the edge detection circuit 41 generates an edge detection signal SE that becomes enable when the edge detection circuit 41 detects an edge.

The phase comparison circuit 42 determines whether the phase of the clock signal CK is advanced or delayed based on the data signal DT 2 , the signal D 1 , and the clock signal CK, and generates a phase comparison signal SP based on a result of the determination. More specifically, as illustrated in FIGS. 6 and 7 , the phase comparison circuit 42 makes a comparison between data of the data signal DT 2 and data of the signal D 1 , and thereby determines whether the phase of the clock signal CK is advanced or delayed. When the phase comparison circuit 42 determines that the phase of the clock signal CK is advanced as illustrated in FIG. 6 , the phase comparison circuit 42 sets the phase comparison signal SP to “1”. When the phase comparison circuit 42 determines that the phase of the clock signal CK is delayed as illustrated in FIG. 7 , the phase comparison circuit 42 sets the phase comparison signal SP to “0”.

The phase determination circuit 43 generates a signal SIGP based on the edge detection signal SE, the phase comparison signal SP, and the clock signal CK. More specifically, the phase determination circuit 43 sets the signal SIGP to “+1” when the phase determination circuit 43 determines that the phase of the clock signal CK is supposed to be delayed because the phase of the clock signal CK is advanced. The phase determination circuit 43 sets the signal SIGP to “−1” when the phase determination circuit 43 determines that the phase of the clock signal CK is supposed to be advanced because the phase of the clock signal CK is delayed. The phase determination circuit 43 sets the signal SIGP to “0” when the phase determination circuit 43 determines that the phase of the clock signal CK is supposed to be kept as it is.

The integration circuit 45 functions as a so-called loop filter, and integrates values of the signal SIGP. Further, the integration circuit 45 generates the control signal CTLP based on the integrated value, and supplies the control signal CTLP to the variable delay circuit 20 .

The frequency determination circuit 44 generates a signal SIGF based on the edge detection signal SE, the phase comparison signal SP, and the clock signal CK. More specifically, the frequency determination circuit 44 sets the signal SIGF to “+1” when the frequency determination circuit 44 determines that the frequency of the clock signal CK is supposed to be lower because the frequency of the clock signal CK is high. The frequency determination circuit 44 sets the signal SIGF to “−1” when the frequency determination circuit 44 determines that the frequency of the clock signal CK is supposed to be higher because the frequency of the clock signal CK is low. The frequency determination circuit 44 sets the signal SIGF to “0” when the frequency determination circuit 44 determines that the frequency of the clock signal CK is supposed to be kept as it is.

The integration circuit 46 functions as a so-called loop filter, and integrates values of the signal SIGF. Further, the integration circuit 46 generates the control signal CTLF based on the integrated value, and supplies the control signal CTLF to the oscillator circuit 30 .

In this embodiment, the edge detection circuit 37 corresponds to a specific but non-limiting example of “transition detection section” in the present disclosure. The delay circuits 31 to 35 and the AND circuit 36 correspond to specific but non-limiting examples of “oscillation section” in the present disclosure. The variable delay circuit 20 corresponds to a specific but non-limiting example of “delay section” in the present disclosure. The flip-flop circuit 11 corresponds to a specific but non-limiting example of “first sampling section” in the present disclosure. The flip-flop circuit 12 and the control circuit 40 correspond to specific but non-limiting examples of “control section” in the present disclosure. The flip-flop circuit 12 corresponds to a specific but non-limiting example of “second sampling section” in the present disclosure. The control circuit 40 corresponds to a specific but non-limiting example of “signal generation section” in the present disclosure. The data signal DT corresponds to a specific but non-limiting example of “input data signal” in the present disclosure. The data signal DT 2 corresponds to a specific but non-limiting example of “output data signal” in the present disclosure. The control signal CTLF corresponds to a specific but non-limiting example of “first control signal” in the present disclosure. The control signal CTLP corresponds to a specific but non-limiting example of “second control signal” in the present disclosure.

[Operation and Function]

Next, an operation and a function of the reception unit 1 of the first embodiment are described.

[Outline of General Operation]

First, referring to FIG. 1 , etc., an outline of a general operation of the reception unit 1 is described. The variable delay circuit 20 delays the data signal DT by the delay amount in accordance with the control signal CTLP, and outputs the delayed signal as the data signal DT 1 . The oscillator circuit 30 generates the clock signal CK having the frequency in accordance with the control signal CTLF, and varies the phase of the generated clock signal CK based on the data signal DT. The flip-flop circuit 11 samples the data signal DT 1 at the rising timing of the clock signal CK, and thereby generates the data signal DT 2 . The flip-flop circuit 12 samples the data signal DT 1 at the falling timing of the clock signal CK, and thereby generates the signal D 1 . The control circuit 40 generates the control signals CTLP and CTLF based on the data signal DT 2 , the signal D 1 , and the clock signal CK.

[Detailed Operation]

FIG. 9 illustrates an operation example of the reception unit 1 , in which (A) illustrates the waveform of the data signal DT 1 , (B) illustrates the waveform of the clock signal CK, (C) illustrates the waveform of the data signal DT 2 , (D) illustrates the waveform of the signal D 1 , (E) illustrates a waveform of the edge detection signal SE, (F) illustrates a waveform of the phase comparison signal SP, (G) illustrates the signal SIGP, and (H) illustrates the signal SIGF. In (C) to (F) of FIG. 9 , “1” and “0” are denoted in addition to the waveforms for the sake of convenience in description. “1” indicates that a signal attached with “1” is at a high level, and “0” indicates that a signal attached with “0” is at a low level. Also, the number of toggles NT (described later) is also denoted in (E) of FIG. 9 .

The flip-flop circuit 11 samples the data signal DT 1 at the rising timing of the clock signal CK, and thereby generates the data signal DT 2 ((C) of FIG. 9 ). The flip-flop circuit 12 samples the data signal DT 1 at the falling timing of the clock signal CK, and thereby generates the signal D 1 ((D) of FIG. 9 ).

The edge detection circuit 41 in the control circuit 40 detects the rising edge and the falling edge of the data signal DT 2 , and thereby generates the edge detection signal SE ((E) of FIG. 9 ). More specifically, for example, because the data signal DT 2 makes a transition at a timing t 42 , the edge detection circuit 41 sets the edge detection signal SE to a high level (to be enable) in a period from the timing t 42 to a timing t 43 . The same applies to a period from the timing t 43 to a timing t 47 . Also, for example, because the data signal DT 2 makes no transition before or after the timing t 47 , the edge detection circuit 41 sets the edge detection signal SE to a low level in a period from the timing t 47 to a timing t 48 . Also, for example, because the data signal DT 2 makes a transition at the timing t 48 , the edge detection circuit 41 sets the edge detection signal SE to the high level (to be enable) in a period from the timing t 48 to a timing t 49 . The same applies to a period from the timing t 49 to a timing t 51 .

The phase comparison circuit 42 makes a comparison between the data signal DT 2 and the signal D 1 , and thereby generates the phase comparison signal SP ((F) of FIG. 9 ). More specifically, because the signal D 1 (“0”) at the timing t 42 is the same as the data signal DT 2 (“0”) in the period from the timing t 42 to the timing t 43 , the phase comparison circuit 42 determines that the phase of the clock signal CK is delayed as in the case illustrated in FIG. 7 , and sets the phase comparison signal SP in the period from the timing t 42 to the timing t 43 to “0”. Also, for example, because the signal D 1 (“0”) at the timing t 43 is the same as the data signal DT 2 (“0”) in the period from the timing t 42 to the timing t 43 , the phase comparison circuit 42 determines that the phase of the clock signal CK is advanced as in the case illustrated in FIG. 6 , and sets the phase comparison signal SP in a period from the timing t 43 to the timing t 44 to “1”. The same applies to a period from the timing t 44 to the timing t 47 . Also, for example, because the signal D 1 (“1”) at the timing t 48 is the same as the data signal DT 2 (“1”) in the period from the timing t 48 to the timing t 49 , the phase comparison circuit 42 determines that the phase of the clock signal CK is delayed as in the case illustrated in FIG. 7 , and sets the phase comparison signal SP in the period from the timing t 48 to the timing t 49 to “0”. The same applies to the period from the timing t 49 to the timing t 51 .

It is to be noted that, because the signal D 1 (“0”) at the timing t 47 is the same as both of the data signal DT 2 (“0”) in the period from the timing t 46 to the timing t 47 and the data signal DT 2 (“0”) in the period from the timing t 47 to the timing t 48 , the phase comparison circuit 42 sets the phase comparison signal SP in the period from the timing t 47 to the timing t 48 to “0” in this example.

The phase determination circuit 43 generates the signal SIGP based on the edge detection signal SE and the phase comparison signal SP ((G) of FIG. 9 ). More specifically, the phase determination circuit 43 first counts the number of unit intervals UI in which the edge detection signal SE is continuously enable, and thereby acquires the number of toggles NT in a case where the data signal DT 2 toggles alternately on a unit-interval UI unit basis ((E) of FIG. 9 ). The phase determination circuit 43 sets the signal SIGP to “0” when the number of toggles NT is less than predetermined number (in this example, 4). Also, the phase determination circuit 43 generates the signal SIGP based on the phase comparison signal SP when the number of toggles NT is equal to or greater than the predetermined number (in this example, 4). At this time, the phase determination circuit 43 sets the signal SIGP to “+1” when the phase comparison signal SP is “1”, and sets the signal SIGP to “−1” when the phase comparison signal SP is “0”. Also, the phase determination circuit 43 sets the signal SIGP to “0” when the edge detection signal SE is “0”. In other words, the phase determination circuit 43 sets the signal SIGP to “0” when the data signal DT 2 makes no transition.

In this example, the number of toggles NT is equal to or greater than “4” in a period from the timing t 45 to the timing t 47 . Accordingly, the phase determination circuit 43 sets the signal SIGP to “+1” based on the phase comparison signal SP (“1”) in this period from the timing t 45 to the timing t 47 . Also, the phase determination circuit 43 sets the signal SIGP to “0” in other periods.

The integration circuit 45 integrates the signal SIGP, and thereby generates the control signal CTLP. Further, the variable delay circuit 20 varies the delay amount based on the generated control signal CTLP. In such a manner, negative feedback control is so performed on the delay amount of the variable delay circuit 20 that the falling timing of the clock signal CK coincides with the transition timing of the data signal DT 1 in the reception unit 1 .

The frequency determination circuit 44 generates the signal SIGF based on the edge detection signal SE and the phase comparison signal SP ((H) of FIG. 9 ). More specifically, the frequency determination circuit 44 first acquires the number of toggles NT in a manner similar to that in the phase determination circuit 43 . Further, the frequency determination circuit 44 sets the signal SIGF to “0” when the number of toggles NT is equal to or greater than the predetermined number (in this example, 4). The frequency determination circuit 44 generates the signal SIGF based on the edge detection signal SE and the phase comparison signal SP when the number of toggles NT is less than the predetermined number. At this time, the frequency determination circuit 44 sets the signal SIGF to “0” when the edge detection signal SE is “0”. In other words, the frequency determination circuit 44 sets the signal SIGF to “0” when the data signal DT 2 makes no transition. In the case where the edge detection signal SE is “1”, the frequency determination circuit 44 sets the signal SIGF to “+1” when the phase comparison signal SP is “1”, and sets the signal SIGF to “−1” when the phase comparison signal SP is “0”.

In this example, the number of toggles NT is less than “4” in a period from the timing t 41 to the timing t 45 . In this period, in the period from the timing t 41 to the timing t 42 , the frequency determination circuit 44 sets the signal SIGF to “0”, because the edge detection signal SE is “0”. In the period from the timing t 42 to the timing t 43 , the frequency determination circuit 44 sets the signal SIGF to “−1”, because the edge detection signal SE is “1” and the phase comparison signal SP is “0”. In the period from the timing t 43 to the timing t 45 , the frequency determination circuit 44 sets the signal SIGF to “+1”, because the edge detection signal SE is “1” and the phase comparison signal SP is “1”.

In the period from the timing t 45 to the timing t 47 , because the number of toggles NT is equal to or greater than “4”, the frequency determination circuit 44 sets the signal SIGF to “0”.

In a period from the timing t 47 to the timing t 51 , the number of toggles NT is less than “4”. In this period, in the period from the timing t 47 to the timing t 48 , the frequency determination circuit 44 sets the signal SIGF to “0”, because the edge detection signal SE is “0”. In the period from the timing t 48 to the timing t 50 , the frequency determination circuit 44 sets the signal SIGF to “−1”, because the edge detection signal SE is “1” and the phase comparison signal SP is “0”.

The integration circuit 46 integrates the signal SIGF, and thereby generates the control signal CTLF. Further, the oscillator circuit 30 varies the frequency of the clock signal CK based on the generated control signal CTLF. In such a manner, negative feedback control is so performed on the frequency of the clock signal CK that the value of the frequency of the clock signal CK becomes the same as the value of the bit rate of the data signal DT.

In such a manner, in the reception unit 1 , the frequency of the clock signal CK is controlled based on the data signal DT 2 and the signal D 1 . As a result, for example, unlike the circuit disclosed in Japanese Unexamined Patent Application Publication No. H8-213979, it is possible to control the frequency of the clock signal without using a reference clock signal. Accordingly, it is possible to make the configuration of the entire system including the reception unit 1 simple. To give an example, a configuration without a circuit that generates the reference clock signal may be employed.

Moreover, in the reception unit 1 , the variable delay circuit 20 is provided, and the control circuit 40 controls the delay amount of the variable delay circuit 20 . As a result, the transition timing of the data signal DT 1 inputted to the flip-flop circuit 11 is allowed to coincide with the falling timing of the clock signal CK inputted to the flip-flop circuit 11 . In other words, if the variable delay circuit 20 is not provided, the transition timing of the data signal DT 1 may not coincide with the falling timing of the clock signal CK. Further, for example, as in the circuit disclosed in Japanese Unexamined Patent Application Publication No. 2009-239510, these timings may not coincide with each other even when a replica circuit is inserted to adjust the timings. In such a case, even when the value of the frequency of the clock signal CK is almost the same as the value of the bit rate of the data signal DT, the control circuit 40 determines that the value of the frequency of the clock signal CK is different from the value of the bit rate of the data signal DT, and therefore controls the frequency of the clock signal CK. This causes a malfunction. On the other hand, in the reception unit 1 , the variable delay circuit 20 is provided, and the control circuit 40 controls the delay amount of the variable delay circuit 20 based on the data signal DT 2 and the signal D 1 . Accordingly, it is possible to adjust the delay amount to be a desired amount based on the result of the phase comparison performed by the phase comparison circuit 42 , which reduces possibility that such a malfunction is caused. As a result, it is possible to decrease an error rate of the received data, and to therefore improve the communication quality.

Moreover, in the reception unit 1 , the phase determination circuit 43 generates the signal SIGP based on the phase comparison signal SP when the number of toggles NT is equal to or greater than the predetermined number. Accordingly, it is possible to effectively control the delay amount of the variable delay circuit 20 . Specifically, first, when the number of toggles NT is equal to or greater than the predetermined number, the data signal DT toggles alternately on the unit-interval UI unit basis in a period corresponding to the predetermined number. In such a case, the oscillator circuit 30 corrects the phase of the clock signal CK based on the data signal DT in each of the unit intervals UI. In other words, the phase of the clock signal CK is corrected sufficiently with use of the data signal DT. In such a case, the frequency of the clock signal CK less influences the phase comparison signal SP accordingly, and a difference between the delay amount of the variable delay circuit 20 and a desired delay amount thereof is reflected to the phase comparison signal SP as a result. More specifically, for example, when the delay amount of the variable delay circuit 20 is smaller than the desired delay amount, the phase of the data signal DT 1 is advanced, and the phase of the clock signal CK is therefore delayed relatively, which causes the phase comparison signal SP to be “0”. For example, when the delay amount of the variable delay circuit 20 is larger than the desired delay amount, the phase of the data signal DT 1 is delayed, and the phase of the clock signal CK is therefore advanced relatively, which causes the phase comparison signal SP to be “1”. In the reception unit 1 , the phase determination circuit 43 generates the signal SIGP based on the phase comparison signal SP when the number of toggles NT is equal to or greater than the predetermined number. As a result, it is possible to effectively control the delay amount of the variable delay circuit 20 in the reception unit 1 .

Moreover, in the reception unit 1 , the frequency determination circuit 44 generates the signal SIGF based on the phase comparison signal SP when the number of toggles NT is less than the predetermined number. As a result, it is possible to effectively control the frequency of the clock signal CK. Specifically, in the reception unit 1 , in the case where the data signal DT toggles alternately on the unit-interval UI unit basis, the oscillator circuit 30 corrects the phase of the clock signal CK based on the data signal DT in each of the unit intervals UI, as described above. In other words, the clock signal CK toggles in response to the transition of the data signal DT irrespective of the setting of the frequency set with use of the control signal CTLF. Accordingly, if the frequency determination circuit 44 operates based on such a clock signal CK, the frequency determination circuit 44 may determine that the value of the frequency of the clock signal CK is the same as the value of the bit rate of the data signal DT even when these values are different from each other, for example. For this reason, the frequency of the clock signal CK may not be controlled effectively. On the other hand, in the reception unit 1 , the frequency determination circuit 44 generates the signal SIGF based on the phase comparison signal SP when the number of toggles NT is less than the predetermined number, and such an error in determination is not caused accordingly. As a result, it is possible to effectively control the frequency of the clock signal CK.

[Effects]

As described above, in the first embodiment, the variable delay circuit is provided, and the control circuit controls the delay amount of the variable delay circuit. This allows the transition timing of the data signal inputted to the flip-flop circuit to coincide with the falling timing of the clock signal inputted to the flip-flop circuit. As a result, it is possible to reduce the possibility of causing a malfunction, and to therefore reduce the error rate of the received data. As a result, it is possible to improve the communication quality.

Moreover, in the first embodiment, the phase determination circuit generates the signal SIGP based on the phase comparison signal when the number of toggles is equal to or greater than the predetermined number. Accordingly, it is possible to effectively control the delay amount of the variable delay circuit. As a result, it is possible to improve the communication quality.

Moreover, in the first embodiment, the frequency determination circuit generates the signal SIGF based on the phase comparison signal when the number of toggles is less than the predetermined number. Accordingly, it is possible to effectively control the frequency of the clock signal CK. As a result, it is possible to improve the communication quality.

[Modification 1-1]

In the first embodiment described above, the frequency determination circuit 44 generates the signal SIGF based on the number of toggles NT; however, the method of generating the signal SIGF is not limited thereto. Alternatively, for example, as in a reception unit 1 A illustrated in FIG. 10 , the signal SIGF may be generated without using the number of toggles NT. A frequency determination circuit 44 A in the reception unit 1 A generates the signal SIGF based on the edge detection signal SE and the phase comparison signal SP ((H) of FIG. 10 ). More specifically, in a case where the edge detection signal SE is “0”, the frequency determination circuit 44 A sets the signal SIGF to “0”. In a case where the edge detection signal SE is “1”, the frequency determination circuit 44 A sets the signal SIGF to “+1” when the phase comparison signal SP is “1”, and sets the signal SIGF to “−1” when the phase comparison signal SP is “0”. Also when such a configuration is employed, it is possible to improve the communication quality in the reception unit 1 A.

[Modification 1-2]

In the first embodiment described above, the phase determination circuit 43 and the frequency determination circuit 44 generate the signals SIGP and SIGF, respectively, based on the number of toggles NT; however, the method of generating the signals SIGP and SIFG is not limited thereto. Alternatively, for example, the signals SIGP and SIGF may be generated based on the number of digits NC in a case where an identical digit consecutively appears in the data signal DT 2 . The present modification is described below in detail.

FIG. 11 illustrates an operation example of a reception unit 1 B according to the present modification, in which (A) illustrates the waveform of the data signal DT 1 , (B) illustrates the waveform of the clock signal CK, (C) illustrates the waveform of the data signal DT 2 , (D) illustrates the waveform of the signal D 1 , (E) illustrates the waveform of the edge detection signal SE, (F) illustrates the waveform of the phase comparison signal SP, (G) illustrates the signal SIGP, and (H) illustrates the signal SIGF. The number of digits NC is also denoted in (E) of FIG. 11 .

A frequency determination circuit 44 B in the reception unit 1 B generates the signal SIGF based on the edge detection signal SE and the phase comparison signal SP ((H) of FIG. 11 ). More specifically, the frequency determination circuit 44 B first counts the number of unit intervals UI in which the edge detection signal SE are continuously set to “0”, and thereby acquires the number of digits NC in the case where the identical digit consecutively appears in the data signal DT 2 ((E) of FIG. 11 ). Further, in a case where the number of digits NC is equal to or greater than predetermined number (in this example, 4), the frequency determination circuit 44 B generates the signal SIGF at a time when the edge detection signal SE first becomes “1” after the number of digits NC has become equal to or greater than the predetermined number, based on the phase comparison signal SP. In this case, the frequency determination circuit 44 B sets the signal SIGF to “+1” when the phase comparison signal SP is “1”, and sets the signal SIGF to “−1” when the phase comparison signal SP is “0”. In other cases, the frequency determination circuit 44 B sets the signal SIGF to “0”.

In this example, in a period from a timing t 58 to a timing t 59 , the frequency determination circuit 44 B sets the signal SIGF to “−1”, because the edge detection signal SE is “1”, the number of digits NC in a period immediately before the period from the timing t 58 to the timing t 59 is equal to or greater than “4”, and the phase comparison signal SP is “0”. In other periods, the frequency determination circuit 44 B sets the signal SIGF to “0”.

The phase determination circuit 43 B in the reception unit 1 B generates the signal SIGP based on the edge detection signal SE and the phase comparison signal SP ((G) of FIG. 11 ). More specifically, the phase determination circuit 43 B first acquires the number of digits NC in a manner similar to that in the frequency determination circuit 44 B ((E) of FIG. 11 ). In a case where the acquired number of digits NC is equal to or greater than the predetermined number (in this example, 4), the phase determination circuit 43 B sets the signal SIGP, at a time when the edge detection signal SE first becomes “1” after the number of digits NC has become equal to or greater than the predetermined number, to “0”. In other cases, in a case where the edge detection signal SE is “1”, the phase determination circuit 43 B sets the signal SIGF to “+1” when the phase comparison signal SP is “1”, and sets the signal SIGF to “−1” when the phase comparison signal SP is “0”. In the case where the edge detection signal SE is “0”, the phase determination circuit 43 B sets the signal SIGP to “0”.

In this example, in a period from a timing t 51 to a timing t 52 , the phase determination circuit 43 B sets the signal SIGP to “0”, because the edge detection signal SE is “0”. In a period from a timing t 52 to a timing t 53 , the phase determination circuit 43 B sets the signal SIGP to “−1”, because the edge detection signal SE is “1”, the number of digits NC in a period immediately before is less than “4”, and the phase comparison signal SP is “0”. In a period from the timing t 53 to a timing t 55 , the phase determination circuit 43 B sets the signal SIGP to “+1”, because the edge detection signal SE is “1”, and the phase comparison signal SP is “1”. In a period from the timing t 55 to the timing t 58 , the phase determination circuit 43 B sets the signal SIGP to “0”, because the edge detection signal SE is “0”. In the period from the timing t 58 to the timing t 59 , the phase determination circuit 43 B sets the signal SIGP to “0”, because the edge detection signal SE is “1”, and the number of digits NC in a period immediately before is equal to or greater than “4”. In a period from the timing t 59 to a timing t 61 , the phase determination circuit 43 B sets the signal SIGP to “−1”, because the edge detection signal SE is “1”, and the phase comparison signal SP is “0”.

In such a manner, in the reception unit 1 B, in the case where the number of digits NC is equal to or greater than the predetermined number, the frequency determination circuit 44 B generates the signal SIGF, at the time when the edge detection signal SE first becomes “1” after the number of digits NC has become equal to or greater than the predetermined number, based on the phase comparison signal SP. As a result, it is possible to effectively control the frequency of the clock signal CK. In other words, in the case where the number of digits NC is equal to or greater than the predetermined number, the oscillator circuit 30 does not correct the phase of the clock signal CK during a period corresponding to that number of digits NC. Accordingly, when the data signal DT 2 first makes a transition after the period corresponding to the number of digits NC, an influence of a difference between the frequency of the clock signal CK and the bit rate of the data signal DT on the phase comparison signal SP is made larger, whereas, an influence of a difference between the delay amount of the variable delay circuit 20 and the desired delay amount thereof on the phase comparison signal SP is made smaller. More specifically, for example, in a case where the frequency of the clock signal CK is higher than the bit rate of the data signal DT, the phase of the clock signal CK is advanced, and the phase comparison signal SP therefore becomes “1”. For example, in a case where the frequency of the clock signal CK is lower than the bit rate of the data signal DT, the phase of the clock signal CK is delayed, and the phase comparison signal SP therefore becomes “0”. In the reception unit 1 B, the frequency determination circuit 44 B generates the signal SIGF based on the phase comparison signal SP in the case where the number of digits NC is equal to or greater than the predetermined number. As a result, it is possible to effectively control the frequency of the clock signal CK.

In the example described above, the phase determination circuit 43 B generates the signal SIGP based on the number of digits NC; however, the method of generating the signal SIGP is not limited thereto. Alternatively, for example, as a reception unit 1 C illustrated in FIG. 12 , the signal SIGP may be generated without using the number of digits NC. A phase determination circuit 44 C in the reception unit 1 C generates the signal SIGP based on the edge detection signal SE and the phase comparison signal SP ((G) of FIG. 12 ). More specifically, in a case where the edge detection signal SE is “0”, a phase determination circuit 43 C sets the signal SIGP to “0”. In a case where the edge detection signal SE is “1”, the phase determination circuit 44 C sets the signal SIGP to “+1” when the phase comparison signal SP is “1”, and sets the signal SIGP to “−1” when the phase comparison signal SP is “0”. Also when such a configuration is employed, it is possible to improve the communication quality in the reception unit 1 C.

[Modification 1-3]

In the first embodiment described above, the oscillator circuit 30 is configured using the AND circuit 36 ; however, the configuration of the oscillator circuit 30 is not limited thereto. The present modification is described below referring to some examples.

FIG. 13A illustrates a configuration example of an oscillator circuit 30 D 1 according to the present modification. The oscillator circuit 30 D 1 includes four delay circuits 31 to 34 and a NAND circuit 36 D. The NAND circuit 36 D calculates an inverted logical product (NAND) of a signal supplied to a first input terminal thereof and a signal supplied to a second input terminal thereof, and outputs a result of the calculation as the clock signal CK. The first input terminal of the NAND circuit 36 D is connected to an output terminal of the delay circuit 34 , the second input terminal thereof is connected to the output terminal of the edge detection circuit 37 and is supplied with the signal E 1 , and an output terminal thereof is connected to the input terminal of the delay circuit 31 . In the oscillator circuit 30 D 1 , when the data signal DT makes a transition, the signal E 1 is set to the low level for a predetermined period in response to the transition of the data signal DT, which causes the NAND circuit 36 D to set the output signal (the clock signal CK) to the high level. In such a manner, the oscillator circuit 30 D 1 varies the phase of the clock signal CK based on the data signal DT.

FIG. 13B illustrates a configuration example of another oscillator circuit 30 D 2 according to the present modification. The oscillator circuit 30 D 2 includes an edge detection circuit 37 D, five delay circuits 31 to 35 , and an OR circuit 38 . In a case where the data signal DT makes no transition, the edge detection circuit 37 D sets the signal E 1 to the low level. In a case where the data signal DT makes a transition, the edge detection circuit 37 D sets the signal E 1 to the high level in the period PG having a length that is about half of the bit length (the unit interval UI) of the data signal DT. The OR circuit 38 calculates a logical sum (OR) of a signal supplied to a first input terminal thereof and a signal supplied to a second input terminal thereof, and outputs a result of the calculation as the clock signal CK. The first input terminal of the OR circuit 38 is connected to the output terminal of the delay circuit 35 , the second input terminal thereof is connected to an output terminal of the edge detection circuit 37 D and is supplied with the signal E 1 , and an output terminal thereof is connected to the input terminal of the delay circuit 31 . In the oscillator circuit 30 D 2 , when the data signal DT makes a transition, the signal E 1 is set to the high level for a predetermined period in response to the transition of the data signal DT, which causes the OR circuit 38 to set the output signal (the clock signal CK) to the high level. In such a manner, the oscillator circuit 30 D 2 varies the phase of the clock signal CK based on the data signal DT.

FIG. 13C illustrates a configuration example of another oscillator circuit 30 D 3 according to the present modification. The oscillator circuit 30 D 3 includes the edge detection circuit 37 D, the four delay circuits 31 to 34 , and a NOR circuit 38 D. The NOR circuit 38 D calculates an inverted logical sum (NOR) of a signal supplied to a first input terminal thereof and a signal supplied to a second input terminal thereof, and outputs a result of the calculation as the clock signal CK. The first input terminal of the NOR circuit 38 D is connected to the output terminal of the delay circuit 34 , the second input terminal thereof is connected to the output terminal of the edge detection circuit 37 D and is supplied with the signal E 1 , and an output terminal thereof is connected to the input terminal of the delay circuit 31 . In the oscillator circuit 30 D 3 , when the data signal DT makes a transition, the signal E 1 is set to the high level for a predetermined period in response to the transition of the data signal DT, which causes the NOR circuit 38 D to set the output signal (the clock signal CK) to the low level. In such a manner, the oscillator circuit 30 D 3 varies the phase of the clock signal CK based on the data signal DT.

[Modification 1-4]

In the first embodiment described above, the variable delay circuit 20 is arranged upstream of the flip-flop circuits 11 and 12 ; however, the arrangement of the variable delay circuit 20 is not limited thereto. Alternatively, for example, as in a reception unit 1 E 1 illustrated in FIG. 14A , the variable delay circuit 20 may be arranged upstream of the oscillator circuit 30 . Alternatively, for example, as in a reception unit 1 E 2 illustrated in FIG. 14B , the variable delay circuit 20 may be arranged downstream of the oscillator circuit 30 . The output signal (the clock signal CK) of the variable delay circuit 20 may be thereby supplied to the flip-flop circuits 11 and 12 and the control circuit 40 , and may be thereby supplied to a circuit downstream of the reception unit 1 E 2 via the output terminal of the variable delay circuit 20 .

In the first embodiment described above, one variable delay circuit 20 is provided; however, the number of variable delay circuits is not limited thereto. Alternatively, for example, as in a reception unit 1 F 1 illustrated in FIG. 15A , a reception unit 1 F 2 illustrated in FIG. 15B , and a reception unit 1 F 3 illustrated in FIG. 15C , a plurality of variable delay circuits may be provided.

As illustrated in FIG. 15A , the reception unit 1 F 1 includes variable delay circuits 20 A and 20 B, and a control circuit 40 F 1 . The variable delay circuit 20 A delays the data signal DT by a delay amount in accordance with a control signal CTLPA, and supplies the delayed data signal to the flip-flop circuits 11 and 12 . The variable delay circuit 20 B delays the data signal DT by a delay amount in accordance with a control signal CTLPB, and supplies the delayed data signal to the oscillator circuit 30 . The control circuit 40 F 1 generates the control signals CTLPA, CTLPB, and CTLF, based on the data signal DT 2 , the signal D 1 , and the clock signal CK.

As illustrated in FIG. 15B , the reception unit 1 F 2 includes variable delay circuits 20 A and 20 C, and a control circuit 40 F 2 . The variable delay circuit 20 C delays the output signal of the oscillator circuit 30 by a delay amount in accordance with a control signal CTLPC, and outputs the delayed signal as the clock signal CK. The control circuit 40 F 2 generates the control signals CTLPA, CTLPC, and CTLF, based on the data signal DT 2 , the signal D 1 , and the clock signal CK.

As illustrated in FIG. 15C , the reception unit 1 F 3 includes variable delay circuits 20 A 1 , 20 A 2 , and 20 B, and a control circuit 40 F 3 . The variable delay circuit 20 A 1 delays the data signal DT by a delay amount in accordance with a control signal CTLPA 1 , and supplies the delayed data signal to the flip-flop circuit 11 . The variable delay circuit 20 A 2 delays the data signal DT by a delay amount in accordance with a control signal CTLPA 2 , and supplies the delayed data signal to the flip-flop circuit 12 . The control circuit 40 F 3 generates the control signals CTLPA 1 , CTLPA 2 , CTLPB, and CTLF, based on the data signal DT 2 , the signal D 1 , and the clock signal CK.

[Modification 1-5]

In the first embodiment described above, the reception unit 1 has a configuration of a so-called full-rate architecture in which the value of the frequency of the clock signal CK is almost the same as the value of the bit rate of the data signal DT; however, the configuration of the reception unit is not limited thereto. Alternatively, for example, the reception unit may have a configuration of a so-called half-rate architecture in which the value of the frequency of the clock signal is almost the same as half of the value of the bit rate of the data signal DT, or may have a configuration of a so-called quarter-rate architecture in which the value of the frequency of the clock signal is almost the same as ¼ of the value of the bit rate of the data signal DT. The present modification is described below referring to a reception unit 1 G having the half-rate architecture configuration, as an example.

FIG. 16 illustrates a configuration example of the reception unit 1 G. The reception unit 1 G includes an oscillator circuit 30 G, flip-flop circuits 51 to 54 , and a control circuit 40 G.

The oscillator circuit 30 G generates two clock signals CKI and CKQ that have frequencies in accordance with the control signal CTLF. The clock signals CKI and CKQ are signals that have phases shifted by about 90 degrees from each other. Values of the frequencies of the clock signals CKI and CKQ are almost the same as half of the value of the bit rate of the data signal DT.

The flip-flop circuit 51 samples the data signal DT 1 at a rising timing of the clock signal CKI, and thereby generates a data signal DT 21 . The flip-flop circuit 52 samples the data signal DT 1 at a falling timing of the clock signal CKI, and thereby generates a data signal DT 22 . The flip-flop circuit 53 samples the data signal DT 1 at a rising timing of the clock signal CKQ, and thereby generates a signal D 11 . The flip-flop circuit 54 samples the data signal DT 1 at a falling timing of the clock signal CKQ, and thereby generates a signal D 12 .

FIGS. 17 and 18 each illustrate operations of the flip-flop circuits 51 to 54 . FIG. 17 illustrates a case where the phases of the clock signals CKI and CKQ are advanced, and FIG. 18 illustrates a case where the phases of the clock signals CKI and CKQ are delayed. In other words, FIG. 17 corresponds to FIG. 6 in the case of the first embodiment described above, and FIG. 18 corresponds to FIG. 7 in the case of the first embodiment described above. In FIGS. 17 and 18 , (A) illustrates the waveform of the data signal DT 1 , (B) illustrates a waveform of the clock signal CKI, (C) illustrates a waveform of the clock signal CKQ, (D) illustrates a waveform of the data signal DT 21 , (E) illustrates a waveform of the data signal DT 22 , (F) illustrates a waveform of the signal D 11 , and (G) illustrates a waveform of the signal D 12 . The flip-flop circuit 51 samples the data signal DT 1 at the rising timing of the clock signal CKI, and thereby generates the data signal DT 21 . The flip-flop circuit 52 samples the data signal DT 1 at the falling timing of the clock signal CKI, and thereby generates the data signal DT 22 . Accordingly, as illustrated in FIGS. 17 and 18 , the data Q n appears in the data signal DT 21 , and the data Q n+1 appears in the data signal DT 22 . The flip-flop circuit 53 samples the data signal DT 1 at the rising timing of the clock signal CKQ, and thereby generates the signal D 11 . The flip-flop circuit 54 samples the data signal DT 1 at the falling timing of the clock signal CKQ, and thereby generates the signal D 12 . Accordingly, as illustrated in FIGS. 17 and 18 , the data Q n and the data Q n+1 appear in the signals D 11 and D 12 in accordance with the advance or delay of the phases of the clock signals CKI and CKQ.

The control circuit 40 G generates the control signals CTLP and CTLF based on the data signals DT 21 and DT 22 , the signals D 11 and D 12 , and the clock signal CKI. More specifically, the control circuit 40 G makes a comparison between the data signals DT 21 and DT 22 and the signals D 11 and D 12 , and thereby generates the control signals CTLP and CTLF, as with the control circuit 40 in the first embodiment described above.

[Modification 1-6]

In the first embodiment described above, the frequency of the clock signal CK is controlled based on the data signal DT. However, for example, the frequency of the clock signal CK may be controlled also based on a reference clock signal REFCK at a time of activating a power supply, or the like. A reception unit 1 H according to the present modification is described below in detail.

FIG. 19 illustrates a configuration example of the reception unit 1 H according to the present modification. The reception unit 1 H includes a control circuit 40 H. The control circuit 40 H generates the control signals CTLP and CTLF based on the data signal DT 2 , the signal D 1 , and the clock signal CK, as with the control circuit 40 according to the first embodiment described above. The control circuit 40 H also has a function of generating the control signal CTLF based on the reference clock signal REFCK, for example, at the time of activating the power supply of the reception unit 1 H, or the like. In this example, a value of the frequency of the reference clock signal REFCK is “1/N” of the value of the bit rate of the data signal DT.

FIG. 20 illustrates a configuration example of the control circuit 40 H. The control circuit 40 H includes a frequency divider circuit 47 H, a frequency comparison circuit 48 H, and an integration circuit 46 H. The frequency divider circuit 47 H divides the frequency of the clock signal CK by N, and outputs a signal having the divided frequency. The frequency comparison circuit 48 H makes a comparison between the frequency of the output signal of the frequency divider circuit 47 H and the frequency of the reference clock signal REFCK, for example, at the time of activating the power supply, or the like, and supplies a result of the comparison to the integration circuit 46 H. In other words, the frequency divider circuit 47 H is so inserted as to cause the frequencies of the two signals inputted to the frequency comparison circuit 48 H to be about the same. The integration circuit 46 H integrates the values of the signal SIGF, and generates the control signal CTLF based on the integrated value, as with the integration circuit 46 in the first embodiment described above. The integration circuit 46 H also integrates the comparison results supplied from the frequency comparison circuit 48 H, and generates the control signal CTLF based on the integrated value, for example, at the time of activating the power supply.

In the reception unit 1 H, this configuration allows a negative feedback operation to be so performed that the value of the frequency of the clock signal CK becomes closer to the value of the bit rate of the data signal DT, for example, at the time of activating the power supply. Accordingly, it is possible to allow the value of the frequency of the clock signal CK to be closer to the value of the bit rate of the data signal DT before the data signal DT is supplied to the reception unit 1 H, for example, at the time of activating the power supply, or the like. As a result, the reception unit 1 H is allowed to start generating the desired data signal DT 2 and the desired clock signal CK immediately after the data signal DT is supplied thereto.

In this example, the reference clock signal REFCK is used; however, the signal to be used is not limited thereto. Alternatively, for example, at the time of activating the power supply, or the like, the transmission unit may transmit the data signal DT having an alternating pattern, and the reception unit may control the frequency of the clock signal CK based on the transmitted data signal DT. A reception unit 1 J according to the present modification is described below in detail.

FIG. 21 illustrates a configuration example of the reception unit 1 J according to the present modification. The reception unit 1 J includes a control circuit 40 J. The control circuit 40 J also has a function of generating the control signal CTLF based on the data signal DT having an alternating pattern, for example, at the time of activating the power supply, or the like. In this example, the alternating pattern of the data signal DT toggles alternately on the unit-interval UI unit basis. In this case, the value of the frequency of this signal is ½ of the value of the bit rate of the supposed data signal DT. It is to be noted that the alternating pattern of the data signal DT is not limited thereto, and may toggle alternately on two-unit-interval UI unit basis, for example. In this case, the value of the frequency of the signal is ¼ of the value of the bit rate of the supposed data signal DT.

FIG. 22 illustrates a configuration example of the control circuit 40 J. The control circuit 40 J includes a frequency divider circuit 47 J and a frequency comparison circuit 49 J. The frequency divider circuit 47 J performs frequency division on the clock signal CK, and outputs a signal having the divided frequency. The frequency comparison circuit 49 J makes a comparison between the frequency of the output signal of the frequency divider circuit 47 J and the frequency of the data signal DT, and supplies a result of the comparison to the integration circuit 46 H. In other words, the frequency divider circuit 47 J is so inserted as to cause the frequencies of the two signals inputted to the frequency comparison circuit 49 J to be about the same.

Also when such a configuration is employed, the value of the frequency of the clock signal CK is allowed to be closer to the value of the bit rate of the data signal DT, for example, at the time of activating the power supply.

[Other Modifications]

Moreover, two or more of the above-described modifications may be employed in combination.

2. Second Embodiment

Next, a reception unit 2 according to a second embodiment is described. The second embodiment is different from the first embodiment described above in the method of controlling the delay amount of the variable delay circuit 20 and the frequency of the clock signal CK. It is to be noted that components substantially the same as those in the reception unit 1 according to the first embodiment described above are designated with the same numerals, and description thereof is omitted where appropriate.

As illustrated in FIG. 1 , the reception unit 2 reproduces the clock signal CK and the data signal DT 2 from the received data signal DT, as with the reception unit 1 . In this example, the data signal DT may include a signal portion that toggles consecutively, for example, as “1010”, or may include almost no such signal portion. The reception unit 2 includes an oscillator circuit 60 and a control circuit 70 .

As illustrated in FIG. 4 , the oscillator circuit 60 includes an edge detection circuit 67 . The edge detection circuit 67 detects a falling edge of the data signal DT, and thereby generates the signal E 1 . More specifically, the edge detection circuit 67 sets the signal E 1 to the high level when the data signal DT makes no transition, and sets the signal E 1 to the low level in the period PG when the data signal DT makes a transition from the high level to the low level. The period PG is a period having a length that is about half of the bit length (the unit interval UI) of the data signal DT. Due to this configuration, in the oscillator circuit 60 , when the data signal DT makes a transition from the high level to the low level, the phase of the clock signal CK is varied in response to the transition of the data signal DT. In other words, unlike the oscillator circuit 30 according to the first embodiment, the oscillator circuit 60 corrects the phase of the clock signal CK only with use of the falling transition of the data signal DT.

FIG. 23 illustrates an operation example of the variable delay circuit 20 and the oscillator circuit 60 . In this example, first, the edge detection circuit 67 in the oscillator circuit 60 detects a falling edge of the data signal DT at a timing t 81 , and sets the signal E 1 to the low level in a period PG starting from a timing t 82 that is a timing that is later than the timing t 81 by a circuit delay ((B) of FIG. 23 ). In response to varying of the signal E 1 to the low level at the timing t 82 , the oscillator circuit 60 sets the clock signal CK to the low level in a predetermined period starting from a timing t 83 that is a timing that is later than the timing t 82 by a circuit delay. Also, the variable delay circuit 20 delays the data signal DT that falls at the timing t 81 and rises at the timing t 84 , and thereby generates the data signal DT 1 that falls at the timing t 83 and rises at a timing t 85 . In the reception unit 2 , the delay amount of the variable delay circuit 20 is so controlled that the falling timing of the clock signal CK coincides with the transition timing of the data signal DT 1 , as in the reception unit 1 according to the first embodiment.

FIG. 24 illustrates a configuration example of the control circuit 70 . The control circuit 70 includes an edge detection circuit 71 , a phase determination circuit 73 , and a frequency determination circuit 74 .

The edge detection circuit 71 generates, based on the data signal DT 2 and the clock signal CK, a rising edge detection signal SE 1 that becomes enable when the rising edge of the data signal DT 2 is detected. The edge detection circuit 71 also generates, based on the data signal DT 2 and the clock signal CK, a falling edge detection signal SE 2 that becomes enable when the falling edge of the data signal DT 2 is detected.

The phase determination circuit 73 generates the signal SIGP based on the rising edge detection signal SE 1 , the falling edge detection signal SE 2 , the phase comparison signal SP, and the clock signal CK. The frequency determination circuit 74 generates the signal SIGF based on the rising edge detection signal SE 1 , the falling edge detection signal SE 2 , the phase comparison signal SP, and the clock signal CK.

FIG. 25 illustrates an operation example of the reception unit 2 , in which (A) illustrates the waveform of the data signal DT 1 , (B) illustrates the waveform of the clock signal CK, (C) illustrates the waveform of the data signal DT 2 , (D) illustrates the waveform of the signal D 1 , (E) illustrates a waveform of the rising edge detection signal SE 1 , (F) illustrates a waveform of the falling edge detection signal SE 2 , (G) illustrates the waveform of the phase comparison signal SP, (H) illustrates the signal SIGP, and (I) illustrates the signal SIGF. It is to be noted that the waveforms illustrated in (A) to (D) of FIG. 25 are the same as the waveforms illustrated in (A) to (D) in FIG. 9 according to the first embodiment.

The edge detection circuit 71 in the control circuit 70 detects the rising edge of the data signal DT 2 , and thereby generates the rising edge detection signal SE 1 ((E) of FIG. 25 ), as well as detects the falling edge of the data signal DT 2 , and thereby generates the falling edge detection signal SE 2 . More specifically, for example, because the data signal DT 2 makes a transition from the high level to the low level at a timing t 92 , the edge detection circuit 71 sets the falling edge detection signal SE 2 to the high level (to be enable) in a period from the timing t 92 to a timing t 93 . Also, for example, because the data signal DT 2 makes a transition from the low level to the high level at the timing t 93 , the edge detection circuit 71 sets the rising edge detection signal SE 1 to the high level (to be enable) in a period from the timing t 93 to a timing t 94 . The same applies to the subsequent periods.

The phase determination circuit 73 generates the signal SIGP based on the rising edge detection signal SE 1 , the falling edge detection signal SE 2 , and the phase comparison signal SP ((H) of FIG. 25 ). More specifically, the phase determination circuit 73 first detects a pair PE including a falling edge of the data signal DT 2 and a rising edge of the data signal DT 2 immediately after that falling edge, based on the rising edge detection signal SE 1 and the falling edge detection signal SE 2 ((E) and (F) of FIG. 25 ). Further, in a case where the phase comparison signal SP at the time when the falling detection signal SE 2 is “1” is the same as the phase comparison signal SP at the time when the rising detection signal SE 1 is “1” in the detected pair PE, the phase determination circuit 73 generates the signal SIGP at a time when the rising detection signal SE 1 is “1”, based on the phase comparison signal SP. In other words, the phase determination circuit 73 sets the signal SIGP to “+1” when the phase comparison signal SP is “1”, and sets the signal SIGP to “−1” when the phase comparison signal SP is “0”. In other cases, the phase determination circuit 73 sets the signal SIGP to “0”.

In this example, the falling edge detection signal SE 2 is “1” in a period from the timing t 92 to the timing t 93 , and the rising edge detection signal SE 1 is “1” in the subsequent period from the timing t 93 to the timing t 94 . Accordingly, the phase determination circuit 73 detects the pair PE in a period from the timing t 92 to the timing t 94 . In the detected pair PE, because the phase comparison signal SP in the period from the timing t 92 to the timing t 93 is “0”, and the phase comparison signal SP in the period from the timing t 93 to the timing t 94 is “1”, these phase comparison signals SP in the respective periods are different from each other. Accordingly, the phase determination circuit 73 sets the signal SIGP in the period from the timing t 93 to the timing t 94 to “0”.

The falling edge detection signal SE 2 in a period from the timing t 94 to a timing t 95 is “1”, and the rising edge detection signal SE 1 in a subsequent period from the timing t 95 to a timing t 96 is “1”. Accordingly, the phase determination circuit 73 detects the pair PE in a period from the timing t 94 to the timing t 96 . In the detected pair PE, both of the phase comparison signals SP in the period from the timing t 94 to the timing t 95 and in the period from the timing t 95 to the timing t 96 are “1”. Accordingly, the phase determination circuit 73 sets the signal SIGP in the period from the timing t 95 to the timing t 96 to “+1”.

The falling edge detection signal SE 2 in a period from the timing t 96 to a timing t 97 is “1”, and the rising edge detection signal SE 1 in a period from a timing t 98 to a timing t 99 is “1”. Accordingly, the phase determination circuit 73 detects the pair PE in a period from the timing t 96 to the timing t 99 . In the detected pair PE, because the phase comparison signal SP in the period from the timing t 96 to the timing t 97 is “1” and the phase comparison signal SP in the period from the timing t 98 to the timing t 99 is “0”, these phase comparison signals SP in the respective periods are different from each other. Accordingly, the phase determination circuit 73 sets the signal SIGP in the period from the timing t 98 to the timing t 99 to “0”.

The falling edge detection signal SE 2 in a period from the timing t 99 to a timing t 100 is “1”, and the rising edge detection signal SE 1 in a subsequent period from the timing t 100 to a timing t 101 is “1”. Accordingly, the phase determination circuit 73 detects the pair PE in a period from the timing t 99 to the timing t 101 . In the detected pair PE, both of the phase comparison signals SP in the period from the timing t 99 to the timing t 100 and in the period from the timing t 100 to the timing t 101 are “0”. Accordingly, the phase determination circuit 73 sets the signal SIGP in the period from the timing t 100 to the timing t 101 to “−1”.

The integration circuit 45 integrates the signal SIGP, and thereby generates the control signal CTLP. Further, the variable delay circuit 20 varies the delay amount based on the generated control signal CTLP.

The frequency determination circuit 74 generates the signal SIGF based on the rising edge detection signal SE 1 , the falling edge detection signal SE 2 , and the phase comparison signal SP ((I) of FIG. 25 ). More specifically, the frequency determination circuit 74 first detects the pair PE, as with the phase determination circuit 73 ((E) and (F) of FIG. 25 ). Further, in a case where the phase comparison signal SP at the time when the falling detection signal SE 2 is “1” is different from the phase comparison signal SP at the time when the rising detection signal SE 1 is “1” in the detected pair PE, the frequency determination circuit 74 generates the signal SIGP, based on the phase comparison signal SP at the time when the rising detection signal SE 1 is “1”. In other words, the frequency determination circuit 74 sets the signal SIGF to “+1” when the phase comparison signal SP is “1”, and sets the signal SIGF to “−1” when the phase comparison signal SP is “0”. In other cases, the frequency determination circuit 74 sets the signal SIGF to “0”.

For example, because the phase comparison signal SP (“0”) in the period from the timing t 92 to the timing t 93 is different from the phase comparison signal SP (“1”) in the period from the timing t 93 to the timing t 94 in the pair PE in the period from the timing t 92 to the timing t 94 , the frequency determination circuit 74 sets the signal SIGF in the period from the timing t 93 to the timing t 94 to “+1” based on the phase comparison signal SP (“1”) in the period from the timing t 93 to the timing t 94 .

Because both of the phase comparison signals SP in the period from the timing t 94 to the timing t 95 and in the period from the timing t 95 to the timing t 96 are “1” in the pair PE in the period from the timing t 94 to the timing t 96 , the frequency determination circuit 74 sets the signal SIGF in the period from the timing t 95 to the timing t 96 to “0”.

Because the phase comparison signal SP (“1”) in the period from the timing t 96 to the timing t 97 is different from the phase comparison signal SP (“0”) in the period from the timing t 98 to the timing t 99 in the pair PE in the period from the timing t 96 to the timing t 99 , the frequency determination circuit 74 sets the signal SIGF in the period from the timing t 98 to the timing t 99 to “−1” based on the phase comparison signal SP (“0”) in the period from the timing t 98 to the timing t 99 .

Because both of the phase comparison signals SP in the period from the timing t 99 to the timing t 100 and in the period from the timing t 100 to the timing t 101 are “0” in the pair PE in a period from the timing t 99 to the timing t 101 , the frequency determination circuit 74 sets the signal SIGF in the period from the timing t 100 to the timing t 101 to “0”.

The integration circuit 46 integrates the signal SIGF, and thereby generates the control signal CTLF. Further, the oscillator circuit 60 varies the frequency of the clock signal CK based on the generated control signal CTLF.

In such a manner, in the reception unit 2 , the pair PE including the falling edge of the data signal DT 2 and the rising edge of the data signal DT 2 immediately after that falling edge is detected, and the signals SIGP and SIGF are generated based on the phase comparison signals SP in the detected pair PE. As a result, the reception unit 2 is usable for various applications. Specifically, for example, because the reception unit 1 according to the first embodiment operates utilizing the signal portion that toggles consecutively as “1010” included in the data signal DT, it may be more difficult to perform a desired operation in a case where the data signal DT that includes almost no such signal portion, for example, a non-scrambled signal, is supplied. On the other hand, the reception unit 2 according to the second embodiment operates without utilizing the signal portion that consecutively toggles. Accordingly, it is possible to reduce a constraint with respect to the data signal DT, and to therefore allow reception of the data signal DT in various formats.

Moreover, in the reception unit 2 , in the case where the phase comparison signals SP in the pair PE are different from each other, the signal SIGF is generated based on the phase comparison signal SP. As a result, it is possible to effectively control the frequency of the clock signal CK. In other words, the oscillator circuit 60 corrects the phase of the clock signal CK with use of the falling transition of the data signal DT. Accordingly, the oscillator circuit 60 does not correct the phase of the clock signal CK and generates the clock signal CK having a frequency in accordance with the control signal CTLF, in a period from the falling transition of the data signal DT 2 to the next falling transition thereof. Specifically, the phase comparison signal SP at a time when the data signal DT 2 falls is the phase comparison signal SP that is immediately after the phase of the clock signal CK is corrected, and the phase comparison signal SP at a time when the data signal DT 2 rises after that falling of the data signal DT 2 is the phase comparison signal Sp at a time after time has passed after this correction of the phase of the clock signal CK. Accordingly, when the two phase comparison signals SP are different from each other, it may be highly possible that the value of the frequency of the clock signal CK be different from the value of the bit rate of the data signal DT. In the reception unit 2 , in the case where the phase comparison signals SP in the pair PE are different from each other, the signal SIGF is generated based on the phase comparison signal SP. As a result, in the reception unit 2 , it is possible to effectively control the frequency of the clock signal CK.

Moreover, in the reception unit 2 , in the case where the phase comparison signals SP in the pair PE are the same as each other, the signal SIGP is generated based on the phase comparison signal SP. As a result, it is possible to effectively control the delay amount of the variable delay circuit 20 . Specifically, in the reception unit 2 , the phase comparison signal SP at the time when the data signal DT 2 falls is the phase comparison signal SP that is immediately after the phase of the clock signal CK is corrected, and the phase comparison signal SP at the time when the data signal DT 2 rises after that falling of the data signal DT 2 is the phase comparison signal SP at a time after time has passed after this correction of the phase of the clock signal CK. Accordingly, when the two phase comparison signals SP are the same, it may be highly possible that the delay amount of the variable delay circuit 20 be different from the desired delay amount thereof. In the reception unit 2 , in the case where the phase comparison signals SP in the pair PE are the same, the signal SIGP is generated based on the phase comparison signal SP. As a result, in the reception unit 2 , it is possible to effectively control the delay amount of the variable delay circuit 20 .

As described above, in the second embodiment, the pair including the falling edge of the data signal and the rising edge of the data signal immediately after the falling edge is detected, and the signals SIGP and SIGF are generated based on the phase comparison signals in the detected pair. As a result, it is possible to receive a data signal in various formats.

Moreover, in the second embodiment, in the case where the phase comparison signals in the pair are different from each other, the signal SIGF is generated based on the phase comparison signal. This makes it possible to effectively control the frequency of the clock signal. As a result, it is possible to improve the communication quality.

Moreover, in the second embodiment, in the case where the phase comparison signals in the pair are the same, the signal SIGP is generated based on the phase comparison signal. This makes it possible to effectively control the delay amount of the variable delay circuit. As a result, it is possible to improve the communication quality.

[Modification 2-1]

In the second embodiment described above, the oscillator circuit 60 generates the clock signal CK; however, the configuration to be employed is not limited thereto. Alternatively, for example, as in a reception unit 2 A illustrated in FIG. 26 , a frequency divider circuit 80 that performs a frequency division operation with use of the falling edge of the data signal DT, and the oscillator circuit 30 that operates based on an output signal of the frequency divider circuit 80 may be provided to generate the clock signal CK. The number by which the frequency is divided by the frequency divider circuit 80 may be two or greater, for example.

[Modification 2-2]

In the second embodiment described above, the edge detection circuit 67 in the oscillator circuit 60 detects the falling edge of the data signal DT; however, the configuration to be employed is not limited thereto. Alternatively, for example, the rising edge of the data signal DT may be detected. In this case, the phase determination circuit 73 and the frequency determination circuit 74 detect the rising edge of the data signal DT 2 and the falling edge of the data signal DT 2 immediately after that rising edge as the pair PE. It is possible to achieve effects similar to those in the second embodiment described above also in this case.

The present technology has been described above referring to some embodiments and the modifications thereof; however, the present technology is not limited to the embodiments and the like described above, and may be variously modified.

For example, the oscillator of a so-called gated VCO type is used in the respective embodiments and the like described above; however, the oscillator to be used is not limited thereto. Alternatively, for example, an oscillator of an injection locked type may be used.

Moreover, for example, in the respective embodiments and the like described above, the configuration of the variable delay circuit 20 is not limited to the configuration illustrated in FIG. 2 . For example, a configuration illustrated in FIG. 27 may be employed. A variable delay circuit 90 includes a delay circuit 99 , inverters 91 and 92 , an inverter 93 , and a control signal generation section 94 . The delay circuit 99 delays the data signal DT by a predetermined delay amount and outputs the delayed data signal. The predetermined delay amount may have, for example, a length about half of the bit length (the unit interval UI) of the data signal DT. The inverter 91 inverts the data signal DT, and outputs the inverted data signal. Drive power of the inverter 91 is allowed to be adjusted in accordance with a control signal C 1 . More specifically, the inverter 91 may be allowed to vary the number of transistors to be used, current values, etc. in accordance with the control signal C 1 , for example. The inverter 92 inverts an output signal of the delay circuit 99 and outputs the inverted signal. Drive power of the inverter 92 is allowed to be adjusted in accordance with the control signal C 2 . Output terminals of the inverters 91 and 92 are connected to each other, and are led to an input terminal of the inverter 93 . The inverter 93 inverts the supplied signal, and outputs the inverted signal as the data signal DT 1 . The control signal generation section 94 generates the control signals C 1 and C 2 based on the control signal CTLP. Due to this configuration, in the variable delay circuit 90 , the data signal DT and the data signal outputted from the delay circuit 99 are weighted by the inverters 91 and 92 , respectively, and the weighted signals are added up. Accordingly, for example, when the drive power of the inverter 91 is enhanced, the phase of the data signal DT 1 is advanced, and when the drive power of the inverter 92 is enhanced, the phase of the data signal DT 1 is delayed.

Next, with use of this technology, description is provided of a case in which the variable delay circuits 20 A and 20 B in the reception unit 1 F 1 illustrated in FIG. 15A are configured. FIG. 28 illustrates a configuration example of a reception unit 1 L according to the present modification. The reception unit 1 L includes the variable delay circuits 20 A and 20 B, and the control circuit 40 . The control circuit 40 supplies the control signal CTLP to the variable delay circuits 20 A and 20 B. FIG. 29 illustrates a configuration example of the variable delay circuits 20 A and 20 B according to the present modification. An inverter 101 inverts the data signal DT, and outputs the inverted data signal. Drive power of the inverter 101 is allowed to be adjusted in accordance with the control signal C 1 . The inverter 102 inverts the output signal of the delay circuit 99 , and outputs the inverted signal. Drive power of the inverter 102 is allowed to be adjusted in accordance with the control signal C 2 . Output terminals of the inverters 101 and 102 are connected to each other, and are led to an input terminal of an inverter 103 . An inverter 111 inverts the output signal of the delay circuit 99 , and outputs the inverted signal. Drive power of the inverter 111 is allowed to be adjusted in accordance with the control signal C 1 . An inverter 112 inverts the data signal DT, and outputs the inverted data signal. Drive power of the inverter 112 is allowed to be adjusted in accordance with the control signal C 2 . Output terminals of the inverters 111 and 112 are connected to each other, and are led to an input terminal of an inverter 113 . A circuit block including the delay circuit 99 , the inverters 101 and 102 , and the inverter 103 corresponds to the variable delay circuit 20 A, and a circuit block including the delay circuit 99 , the inverters 111 and 112 , and the inverter 113 corresponds to the variable delay circuit 20 B. In this configuration, for example, when the drive power of the inverters 101 and 111 is enhanced, the phase of the output signal (the data signal DT 1 ) of the variable delay circuit 20 A is advanced, and the phase of the output signal of the variable delay circuit 20 B is delayed. For example, when the drive power of the inverters 102 and 112 is enhanced, the phase of the output signal (the data signal DT 1 ) of the variable delay circuit 20 A is delayed, and the phase of the output signal of the variable delay circuit 20 B is advanced.

Moreover, for example, in the respective embodiments and the like described above, the variable circuit 20 is provided; however, the configuration to be employed is not limited thereto. Alternatively, for example, as in a reception unit 1 K illustrated in FIG. 30 , the variable delay circuit may be omitted. The reception unit 1 K includes a control circuit 40 K. The control circuit 40 K generates the control signal CTLF based on the data signal DT 2 , the signal D 1 , and the clock signal CK.

It is to be noted that the effects described herein are mere examples. The effects of the present technology are not limited thereto, and may include other effects.

It is possible to achieve at least the following configurations from the above-described example embodiments and the modifications of the disclosure.

(1) A reception unit, including:

a transition detection section configured to detect a transition of an input data signal;

an oscillation section configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section, the clock signal having a frequency in accordance with a first control signal;

a first sampling section configured to sample the input data signal based on the clock signal and thereby generate an output data signal; and

a control section configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.

(2) The reception unit according to (1), wherein

the control section includes

a second sampling section configured to sample the input data signal based on the clock signal at a timing different from a timing at which the first sampling section samples the input data signal, and thereby generate a sampling signal, and

a signal generation section configured to generate the first control signal based on the output data signal and the sampling signal.

(3) The reception unit according to (2), further including

a timing adjustment section configured to adjust, in accordance with a second control signal, a sampling timing in the second sampling section, wherein

the signal generation section also generates the second control signal.

(4) The reception unit according to (3), wherein

the timing adjustment section includes a delay section configured to delay the input data signal by a delay amount in accordance with the second control signal, and

the second sampling section samples the input data signal delayed by the delay section, and thereby generates the sampling signal.

(5) The reception unit according to (4), wherein the first sampling section samples the input data signal delayed by the delay section, and thereby generates the output data signal.

(6) The reception unit according to (3), wherein

the timing adjustment section includes a delay section configured to delay the input data signal by a delay amount in accordance with the second control signal, and

the transition detection section detects a transition of the input data signal delayed by the delay section.

(7) The reception unit according to (3), wherein

the timing adjustment section includes a delay section configured to delay the clock signal by a delay amount in accordance with the second control signal, and

the second sampling section samples the input data signal based on the clock signal delayed by the delay section, and thereby generates the sampling signal.

(8) The reception unit according to any one of (3) to (7), wherein the signal generation section makes a comparison between the output data signal and the sampling signal, and generates the second control signal based on a first comparison result out of results of the comparison, the first comparison result being a result obtained when the output data signal has consecutively made transitions for predetermined number of times or more.

(9) The reception unit according to (8), wherein the signal generation section generates the first control signal based on a comparison result, out of the results of the comparison, other than the first comparison result.

(10) The reception unit according to (8), wherein the signal generation section generates the first control signal based on the results of the comparison.

(11) The reception unit according to any one of (3) to (7), wherein the signal generation section makes a comparison between the output data signal and the sampling signal, and generates the first control signal based on a second comparison result out of results of the comparison, the second comparison result being a result obtained when the output data signal makes a first transition after a digit of the output data signal has become identical consecutively for predetermined number of times or more.

(12) The reception unit according to (11), wherein the signal generation section generates the second control signal based on a comparison result, out of the results of the comparison, other than the second comparison result.

(13) The reception unit according to (11), wherein the signal generation section generates the second control signal based on the results of the comparison.

(14) The reception unit according to any one of (8) to (13), wherein the transition detection section detects a transition, of the input data signal, made in a first direction and a transition, of the input data signal, made in a second direction.

(15) The reception unit according to any one of (3) to (7), wherein

the transition detection section detects a transition, of the input data signal, made in a first direction, and

the signal generation section makes a comparison between the output data signal and the sampling signal, and generates the first control signal and the second control signal based on a first comparison result and a second comparison result out of results of the comparison, the first comparison result being a result obtained when the output data signal makes a transition in the first direction, and the second comparison result being a result obtained when the output data signal makes a first transition in a second direction after the output data signal has made the transition in the first direction.

(16) The reception unit according to (15), wherein the transition detection section performs frequency division on the input data signal based on the transition, of the input data signal, in the first direction, and detects a transition of the input data signal subjected to the frequency division.

(17) The reception unit according to (15) or (16), wherein the signal generation section generates the first control signal based on the results of the comparison when the first comparison result is different from the second comparison result.

(18) The reception unit according to (15) or (16), wherein the signal generation section generates the second control signal based on the results of the comparison when the first comparison result is same as the second comparison result.

(19) The reception unit according to any one of (2) to (18), wherein

the first sampling section samples the input data signal at a timing at which the clock signal makes a transition in a first direction, and

the second sampling section samples the input data signal at a timing at which the clock signal makes a transition in a second direction.

(20) The reception unit according to any one of (2) to (18), wherein

the clock signal includes a plurality of clock signals that have phases different from one another, and

the first sampling section and the second sampling section sample the input data signal based on the plurality of clock signals.

(21) The reception unit according to any one of (1) to (20), wherein the control section generates the first control signal based on the clock signal and a reference clock signal in a predetermined period.

(22) The reception unit according to any one of (1) to (20), wherein the control section generates the first control signal based on the clock signal and the input data signal in a predetermined period.

(23) The reception unit according to (21) or (22), wherein the predetermined period is a period after activating a system.

(24) A receiving method, including:

detecting a transition of an input data signal;

generating a clock signal and varying a phase of the clock signal based on the transition of the input data signal, the clock signal having a frequency in accordance with a first control signal;

sampling the input data signal based on the clock signal, and thereby generating an output data signal; and

generating the first control signal based on the input data signal, the output data signal, and the clock signal.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.