Solid-state imaging apparatus and camera

The present invention relates to a solid-state imaging apparatus and a camera.

A solid-state imaging apparatus includes a pixel array in which a plurality of pixels are arrayed, a plurality of processing units which process signals from respective pixels on each column of the pixel array, and an output line configured to output a signal from each processing unit.

Some solid-state imaging apparatuses have an arrangement in which a plurality of processing units are divided into a plurality of groups such that each of them includes two or more processing units, and one switch which connects the two or more processing units and an output line is provided for each group. For example, in a case that a signal is output from each processing unit of a certain group, the signals from two or more processing units of that group are sequentially output while setting the switch in a conductive state in that group, whereas the switch is set in a non-conductive state in each of the other groups. This arrangement is advantageous in increasing the operation speed of the solid-state imaging apparatus because the load capacitance of the output line is reduced as compared with a case in which all of the plurality of processing units are directly connected to the output line.

If a node between the switch and the two or more processing units of the above-described other group is set in a floating state while the switch is set in the non-conductive state in the other group, a potential variation may occur in this node. This may cause a malfunction of the solid-state imaging apparatus, latch-up, the insulation breakdown of a MOS transistor, or the like and reduce the reliability of the solid-state imaging apparatus.

The present invention provides a technique advantageous in improving the reliability of a solid-state imaging apparatus.

One of the aspects of the present invention provides a solid-state imaging apparatus comprising a pixel array in which a plurality of pixels are arrayed and a plurality of processing units configured to process signals from the respective pixels on each column of the pixel array, the plurality of processing units forming a plurality of groups each including two or more processing units, the apparatus comprising an output line, a power supply line configured to transfer a power voltage, a plurality of signal lines each provided for each of the plurality of groups and configured to connect output nodes of the two or more processing units in the group to each other, a plurality of connecting units provided in a path between the output line and the plurality of signal lines, and a control unit, wherein, in a case that outputting signals from the processing units in one group out of the plurality of groups, the control unit controls the plurality of processing units and the plurality of connecting units, for the one group, so as to output the signals from the processing units in the one group while electrically connecting the signal line and the output line, and for the other groups out of the plurality of groups, so as to connect the signal line and the power supply line electrically while maintaining outputs from the respective processing units in the other groups in high impedance states.

Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

FIG. 1 is a view for explaining an example of the overall arrangement of a solid-state imaging apparatus;

FIGS. 2A and 2B are views for explaining an example of the arrangement of a signal holding unit;

FIG. 3 is a view for explaining an example of the driving timing chart of the solid-state imaging apparatus;

FIG. 4 is a view for explaining an example of the overall arrangement of the solid-state imaging apparatus;

FIG. 5 is a view for explaining an example of the overall arrangement of a solid-state imaging apparatus;

FIG. 6 is a view for explaining an example of the overall arrangement of a solid-state imaging apparatus;

FIG. 7 is a view for explaining an example of the overall arrangement of a solid-state imaging apparatus;

FIG. 8 is a view for explaining an example of the overall arrangement of a solid-state imaging apparatus;

FIG. 9 is a view for explaining an example of the driving timing chart of the solid-state imaging apparatus;

FIG. 10 is a view for explaining an example of the overall arrangement of a solid-state imaging apparatus; and

FIG. 11 is a view for explaining an example of the upper surface of the layout of each wiring pattern.

First Embodiment

FIG. 1 shows an example of the overall arrangement of a solid-state imaging apparatus I 1 according to this embodiment. The solid-state imaging apparatus I 1 includes a pixel array A PX , a vertical scanning circuit VSC, processing units U PR , a horizontal scanning circuit HSC, connecting units U CN , an output unit U OUT , and a timing generator TG.

The pixel array A PX in which a plurality of pixels PX are arrayed is formed. An arrangement in which the 8 (rows)×12 (columns) pixels PX are arrayed is illustrated here for the sake of simplicity. Each pixel PX can adopt a known pixel arrangement, and includes, for example, a photoelectric conversion element such as a photodiode and a plurality of transistors each configured to read out a signal corresponding to an amount of charges generated in the photoelectric conversion element.

The vertical scanning circuit VSC supplies control signals to the pixel array A PX and drives the plurality of pixels PX for the respective rows. The control signals include, for example, a signal for initializing (resetting) the above-described photoelectric conversion element, in addition to a signal for driving each transistor configured to read out the signal corresponding to the amount of the charges generated in the above-described photoelectric conversion element.

The processing units U PR are provided on the respective columns of the pixel array A PX and process the signals from the respective pixels PX. The processing units U PR serve as, for example, A/D conversion units which perform analog/digital conversion (A/D conversion) on the signals from the respective pixels PX on the respective columns, and include a comparator U CMP1 (comparing unit) and the like and a memory ME 1 (signal holding unit) and the like. A counter U CO (counting unit) is also provided in common to each column of the pixel array A PX .

Note that the comparator “U CMP1 ” to a comparator “U CMP12 ” provided in correspondence with the first column to the 12th column of the pixel array A PX are sometimes referred to as comparators “U CMP ” altogether in this specification. The same also applies to memories “ME”.

Each comparator U CMP compares, for example, the signals from the respective pixels PX and a reference signal such as a ramp signal, and outputs a comparison result to the corresponding memory ME. The counter U CO counts a time elapsed after each comparator U CMP starts comparison. Each memory ME receives an output from the corresponding comparator U CMP and holds the count value of the counter U CO if the logic level of the output from the corresponding comparator U CMP is inverted in response to the inversion of the magnitude relationship of the signal levels between the signals from the respective pixels PX and the reference signal.

The processing units U PR provided on the respective columns of the above-described pixel array A PX are divided into three groups (referred to as “G 1 ” to “G 3 ”) such that each group includes four processing units U PR . In FIG. 1 , the first group G 1 corresponds to the processing units U PR on the first to the fourth columns, the second group G 2 corresponds to the processing units U PR on the fifth to the eighth columns, and the third group G 3 corresponds to the processing units U PR on the ninth to the twelfth columns. The output nodes of the four processing units U PR in the group G 1 (the output nodes of the memories ME here) are connected to each other by a signal line L S1 . The same also applies to the groups G 2 and G 3 . Note that the signal line “L S1 ” to a signal line “L S3 ” are sometimes referred to as signal lines “L S ” altogether in this specification.

Each connecting unit U CN is provided in a path between the processing units U PR and an output line L OUT , and includes, for example, a tri-state inverter U SW1 and the like and a switch SW F1 and the like. Note that the tri-state inverter “U SW1 ” to a tri-state inverter “U SW3 ” are sometimes referred to as tri-state inverters “U SW ” altogether in this specification. The same also applies to switches “SW F ”.

The tri-state inverters U SW are provided between the signal lines L S and the output line L OUT , and output the signals from the four corresponding processing units U PR to the output line L OUT based on the control signals. The switches SW F are provided between the signal lines L S and a power supply line which transfers a predetermined power voltage such as a ground node, and fix the potentials of the signal lines L S based on the control signals. This arrangement allows each connecting unit U CN to change an electrical connection in the path between the processing units U PR and the output line L OUT .

The horizontal scanning circuit HSC supplies the control signals for reading out the signals held by the memories ME to the processing units U PR and the connecting units U CN , and functions as a control unit configured to read out the signals. For example, the horizontal scanning circuit HSC outputs control signals for reading out the signals of the memory ME 1 to a memory ME 12 from nodes C 1 to C 12 , and also outputs control signals for controlling each connecting unit U CN from nodes B 1 to B 3 and B 1 b to B 3 b . Each of the control signals from the nodes B 1 b to B 3 b is at a logic level opposite to that of each of the control signals from the nodes B 1 to B 3 .

The output unit U OUT is read out by each control signal from the horizontal scanning circuit HSC and outputs the signals of the memories ME output to the output line L OUT . This output operation is also referred to as “horizontal transferring”.

The timing generator TG receives reference clock signals from outside and supplies the corresponding clock signal to the vertical scanning circuit VSC, the horizontal scanning circuit HSC, or the like. Each of the vertical scanning circuit VSC and the horizontal scanning circuit HSC generates, based on the clock signal from the timing generator TG, a corresponding control signal and supplies it to a corresponding unit.

According to this arrangement, the processing units U PR provided on the respective columns of the pixel array A PX are divided into the three groups G 1 to G 3 and one output unit (the connecting unit U CN here) for outputting the signal of each processing unit U PR is provided for each group. Therefore, this arrangement reduces the load capacitance of the output line L OUT , and is thus advantageous in increasing the speed of horizontal transferring.

FIG. 2A shows an example of the arrangement of each memory ME. Each memory ME includes an analog switch 220 , an inverter 230 , a tri-state inverter 240 , and a tri-state inverter 250 . The tri-state inverter 240 or the like includes a control node EN and operates as an inverter in response to the activation of a control signal received by the node EN. In this arrangement, the inverter 230 and the tri-state inverter 240 hold the count values (digital signals) of the counter U CO input via the analog switch 220 . Then, the digital signals are output from an output node OUT in response to the activation of a control signal received by a control node READ.

FIG. 2B shows an example of the arrangement of the tri-state inverter ( 240 or the like). The tri-state inverter includes, for example, PMOS transistors MP 1 and MP 2 and NMOS transistors MN 3 and MN 4 each provided in series between a power supply node and the ground node, and an inverter INV 0 . In this arrangement, for example, when the control signal received by the node EN is at high level (H), the transistors MP 2 and MN 3 are set in conductive states. The tri-state inverter is set in an active state, inverts a signal received by an input node IN, and outputs the inverted signal from the node OUT. On the other hand, when the control signal received by the node EN is at low level (L), the tri-state inverter is set in an inactive state and its output is set in a high impedance (HiZ) state.

The arrangement in which a digital signal of 1 bit is held in the memory ME has been illustrated here for the sake of simplicity. However, the memory ME may adopt an arrangement in which a digital signal of two or more bits is held.

FIG. 3 shows an example of the driving timing chart of the solid-state imaging apparatus I 1 . The time axis is plotted along the abscissa in FIG. 3 . The ordinate in FIG. 3 represents the signal level of each control signal (the control signal from the node C 1 or the like) from the horizontal scanning circuit HSC, and the signal levels of the signals of the signal lines L S and the output line L OUT . Note that in the description below, for example, the signal level of the control signal from the node C 1 will simply be referred to as the “signal level of C 1 ”. The same also applies to the other signal levels.

At times t 0 and t 1 , the signal levels of C 1 to C 12 are at L and the outputs of the memories ME 1 to ME 12 are all in the HiZ states. During this period, the signal levels of B 1 to B 3 are at L and the tri-state inverters U SW are set in the inactive states, and also the signal levels of B 1 b to B 3 b are at H and the switches SW F are set in the conductive states, and the signal levels of L S are fixed at L.

At times t 1 to t 5 , the signal level of B 1 is set at H and the signal level of B 1 b is set at L. This sets the tri-state inverter U SW1 in the active state and sets the switch SW F1 in the non-conductive state. Then, the signal level of C 1 is set at H at times t 1 and t 2 , the signal level of C 2 is set at H at times t 2 and t 3 , the signal level of C 3 is set at H at times t 3 and t 4 , and the signal level of C 4 is set at H at times t 4 and t 5 . This sequentially sets the memories ME 1 to ME 4 in output enable states (or more specifically, sequentially sets the tri-state inverters 250 in the active states) and outputs the digital signals of the memories ME 1 to ME 4 to the output line L OUT .

That is, at times t 1 to t 5 , the digital signals of the respective memories ME 1 to ME 4 in the group G 1 are sequentially read out.

On the other hand, in the groups G 2 and G 3 , the outputs of the memories ME 5 to ME 12 are in the HiZ states, and the tri-state inverters U SW2 and U SW3 are in the inactive states. At this time, the switches SW F2 and SW F3 are set in the conductive states, and the signal levels of L S2 and L S3 are set at L.

Note that FIG. 3 illustrates a mode in which the signal level of L S1 is set in the order of L, H, L, and H and the signal level of L OUT is set in the order of H, L, H, and L at times t 1 to t 5 . These signal levels correspond to the values of the respective digital signals of the memories ME 1 to ME 4 .

Next, at times t 5 to t 9 , the digital signals of the respective memories ME 5 to ME 8 in the group G 2 are sequentially read out in the same manner as at the times t 1 to t 5 . On the other hand, in the groups G 1 and G 3 , the outputs of the respective memories ME are set in the HiZ states, and the tri-state inverters U SW1 and U SW3 are set in the inactive states. Furthermore, the switches SW F1 and SW F3 are set in the conductive states, and the signal levels of L S1 and L S8 are fixed at L. Likewise, after time t 9 , the outputs of the respective memories ME in the groups G 1 and G 2 are set in the HiZ states, and the tri-state inverters U SW2 and U SW2 are set in the inactive states. Furthermore, the switches SW F1 and SW F2 are set in the conductive states, and the signal levels of L S1 and L S2 are fixed at L.

As described above, according to this embodiment, one group is selected from the groups G 1 to G 3 and the signals from the four processing units U PR in the selected group are output via the output line L OUT . At this time, in each unselected group, the potential of the signal line L S which connects the output nodes of the four processing units U PR to each other is fixed to a predetermined potential by the switch SW F . This makes it possible to prevent the potential of the signal line L S in each unselected group from becoming too high or too low. In this embodiment, the potentials of the signal lines L S2 and L S3 are fixed at times t 1 to t 5 when the signals are read out from the processing units in the group G 1 .

If the potential of the signal line according to each unselected group is not fixed, the signal lines L S2 and L S3 before time t 5 are set in floating states. At this time, if the level of each signal read out from the group G 1 changes to high level, the potential of the output line L OUT becomes high, and thus the potentials of the signal lines L S2 and L S3 can also become high due to a capacitive coupling. For example, if the potentials of the signal lines L S2 and L S3 become too high, the insulation breakdown of the gate insulation film of the NMOS transistor MN 4 shown in FIG. 2B may occur. Further, for example, since each signal lines L S is the output nodes of the processing units, a portion between the drain and well of the PMOS transistor MP 2 shown in FIG. 2B is set in a forward bias state as the potentials of the output nodes increase, which may bring about latch-up or the like.

To cope with this, this embodiment prevents, for example, a potential variation in the signal line L S of each unselected group that may be caused by noise or the like when driving the respective processing units U PR in the selected group. Therefore, this embodiment can prevent a malfunction of the solid-state imaging apparatus I 1 , latch-up, the insulation breakdown of the MOS transistors, or the like, and is thus advantageous in increasing the reliability of the solid-state imaging apparatus I 1 .

Second Embodiment

A solid-state imaging apparatus 12 according to the second embodiment will be described below with reference to FIG. 4 . The main difference between this embodiment and the first embodiment is that buffer circuits U BUF (U BUF1 and U BUF2 ) are inserted in an output line L OUT .

Since the output line L OUT in the first embodiment has a length equal to or larger than the width of a pixel array A PX , its wiring capacitance is comparatively large and the speed of horizontal transferring may decrease. To prevent this, this embodiment provides the buffer circuits U BUF configured to buffer signals which propagate through the output line L OUT .

The buffer circuit U BUF1 is provided between a portion corresponding to a group G 1 and a portion corresponding to a group G 2 in the output line L OUT . The buffer circuit U BUF2 is provided between a portion corresponding to the group G 2 and a portion corresponding to a group G 3 in the output line L OUT .

Each buffer circuit U BUF includes a control node EN configured to receive a control signal. Each buffer circuit U BUF can be set in an active state or an inactive state based on the control signal. Each buffer circuit U BUF may be formed by using, for example, two tri-state inverters. However, another arrangement may be adopted.

In this arrangement, the groups are provided in the order of G 1 , G 2 , and G 3 from the side of an output unit U OUT . Therefore, for example, when each processing unit U PR in the group G 1 outputs the signal, the buffer circuits U BUF1 and U BUF2 are not used. Therefore, in this case, both of the buffer circuits U BUF1 and U BUF2 can be maintained in the inactive states. Furthermore, for example, when each processing unit U PR in the group G 2 outputs the signal, the buffer circuit U BUF1 is used while the buffer circuit U BUF2 is not used. Therefore, in this case, the buffer circuit U BUF1 is set in the active state and the buffer circuit U BUF2 can be maintained in the inactive state. When each processing unit U PR in the group G 3 outputs the signal, both of the buffer circuits U BUF1 and U BUF2 can be set in the active states.

This embodiment can reduce power consumption when outputting the signal from each processing unit U PR because the unused buffer circuits U BUF are maintained in the inactive states. Furthermore, since the buffer circuits U BUF are inserted in the output line L OUT at predetermined intervals, this embodiment reduces a load capacitance that should be driven by one tri-state inverter U SW provided for each group, and is thus advantageous in increasing the speed of horizontal transferring.

Third Embodiment

A solid-state imaging apparatus 13 according to the third embodiment will be described below with reference to FIG. 5 . The main difference between this embodiment and the first embodiment is that inverters INV (INV 1 to INV 3 ) are inserted between signal lines L S and tri-state inverters U SW in connecting units U CN .

As described above, the load capacitance that should be driven by the one tri-state inverter U SW provided for each group is large. Therefore, a transistor MP 1 or the like which forms the tri-state inverter U SW needs to be designed to have a size which allows horizontal transferring to be performed at a predetermined speed. However, as the size of the transistor MP 1 or the like increases, the input capacitance of the tri-state inverter U SW also increases. On the other hand, four memories ME in each group are connected to the corresponding signal line L S in common. For this reason, when outputting digital signals of the respective memories ME, a time required for both of the input capacitance of the tri-state inverter U SW and the load capacitance of the signal line L S to reach the signal levels of the digital signals increases. This can be a serious problem by a multiple pixel structure or the increasing number of processing units included in each group along with the multiple pixel structure.

To cope with this, this embodiment provides the inverters INV between the signal lines L S and the tri-state inverters U SW . This arrangement is advantageous in increasing the output speed of the digital signal of each memory ME.

The arrangement in which the inverters INV are provided between the signal lines L S and the tri-state inverters U SW has been illustrated here. However, the present invention is not limited to this arrangement as long as the load capacitance of each memory ME when outputting the digital signal of each memory ME is reduced. For example, buffer circuits may be used instead of the inverters INV.

Fourth Embodiment

A solid-state imaging apparatus 14 according to the fourth embodiment will be described below with reference to FIG. 6 . The main difference between this embodiment and the first embodiment is that instead of a counter U CO , counters U 1 CO (U 1 CO1 to U 1 CO12 ) are individually provided for the respective columns of a pixel array A PX . Each counter U 1 CO counts a time elapsed after a comparator U CMP starts comparison and each counter value is held in a corresponding memory ME as a digital signal.

This embodiment can obtain the same effects as in the first embodiment and also provides the counters U 1 CO on the respective columns of the pixel array A PX , which allows for, for example, A/D conversion at a higher resolution.

Fifth Embodiment

A solid-state imaging apparatus 15 according to the fifth embodiment will be described below with reference to FIG. 7 . The main difference between this embodiment and the fourth embodiment is that out of the A/D converted digital signals, the signals of upper bits and the signals of lower bits are held individually.

More specifically, the solid-state imaging apparatus 15 further includes counters U 1 CO ′ (U 1 CO1 ′ to U 1 CO3 ′) in addition to the counters U 1 CO according to the fourth embodiment, memories ME′ (ME 1 ′ to ME 12 ′), connecting units U CN ′, an output line L OUT ′, and an output unit U OUT ′. The counters U 1 CO1 ′ to U 1 CO3 are provided to correspond to groups G 1 to G 3 , respectively. The memories ME 1 ′ to ME 12 ′ are provided to correspond to the respective columns of the pixel array A PX . As in the connecting units U CN , the connecting units U CN ′ are provided in paths between the output line L OUT ′ and signal lines L S ′ (L S1 ′ to L S3 ′) which connect the output nodes of the four memories ME to each other. The connecting units U CN ′ adopt the same arrangement as the connecting units U CN , and include tri-state inverters U SW ′ (U SW1 ′ to U SW3 ′) and switches SW F ′ (SW F1 ′ to SW F3 ′). The connecting units U CN ′ can be controlled in a similar manner to the connecting units U CN . The output unit U OUT ′ outputs the digital signal of each memory ME′ output to the output line L OUT ′.

In this embodiment, out of the digital signals corresponding to the outputs of respective pixels, the signals of the upper bits are output from an output unit U OUT and the signals of the lower bits are output from the output unit U OUT ′. The counter U 1 CO on each column performs a count operation at an operating frequency f 1 and the counter U 1 CO ′ provided for each group performs the count operation at an operating frequency f 2 which is higher than the operating frequency f 1 . This allows each counter U 1 CO ′ to obtain, as digital values, the least significant bits of the counters U 1 CO at a high resolution. Note that the operating frequencies f 1 and f 2 are preferably set such that f 2 becomes an integral multiple of f 1 .

In this embodiment, the counter provided for each group performs the count operation at the relatively higher operating frequency, while the counter provided for each column performs the count operation at the relatively lower operating frequency. This arrangement can reduce power consumption as compared with a case in which the counter which performs the count operation at the high operating frequency is provided for each column. This embodiment provides the counter for each group. However, a further reduction in power consumption can be achieved by providing a common counter of all the groups.

This embodiment can obtain the same effects as in the first embodiment and also perform A/D conversion at a higher resolution.

Sixth Embodiment

A solid-state imaging apparatus 16 according to the sixth embodiment will be described below with reference to FIGS. 8 and 9 . The main difference between this embodiment and the first embodiment is that each connecting unit U CN does not include switches SW F , as illustrated in FIG. 8 . In this arrangement, one memory out of four memories ME in each group G is used to fix the potential of a signal line L S .

FIG. 9 shows an example of the driving timing chart of the solid-state imaging apparatus 16 as in FIG. 3 of the first embodiment. In FIG. 9 , the waveform of the control signal from each of control nodes C 1 , C 5 , and C 9 is different from that in FIG. 3 . More specifically, the signal level of C 1 is set at H at times t 1 and t 2 in the first embodiment, whereas in this embodiment, it is set at H not only at times t 1 and t 2 but also at times t 0 and t 1 , and after time t 5 .

That is, while digital signals of the respective memories ME in the other groups G 2 and G 3 are output, in the group G 1 , the memory ME 1 is maintained in an output enable state and the memories ME 2 to ME 4 are maintained in output disable states. A potential variation in a signal line L S1 in the group G 1 that may be caused by noise or the like when driving respective processing units U PR in the groups G 2 and G 3 is prevented because the memory ME 1 is maintained in the output enable state.

Likewise, while the digital signals of the respective memories ME in the groups G 1 and G 3 are output, in the group G 2 , the memory ME 5 out of the memories ME 5 to ME 8 is maintained in the output enable state. While the digital signals of the respective memories ME in the groups G 1 and G 2 are output, in the group G 3 , the memory ME 9 out of the memories ME 9 to ME 12 is maintained in the output enable state.

This embodiment can obtain the same effects as in the first embodiment with a simpler arrangement. The arrangement in which the memory ME 1 in the group G 1 , the memory ME 5 in the group G 2 , and the memory ME 9 in the group G 3 are used to fix the potentials of the respective signal lines L S has been illustrated here. However, the present invention is not limited to this example and any memories ME in the respective groups G may be used.

Seventh Embodiment

A solid-state imaging apparatus 17 according to the seventh embodiment will be described below with reference to FIGS. 10 and 11 . The main difference between this embodiment and the first embodiment is that two tri-state inverters U SW and two switches SW F of a connecting unit U CN are provided for each group G, as illustrated in FIG. 10 .

One of the above-described two tri-state inverters U SW and one of the two switches SW F are provided such that, for example, each of them corresponds to an odd numbered row in each group G. In FIG. 10 , they are referred to as “tri-state inverters U SW1O to U SW3O ” and “switches SW F1O to SW F3O ”, respectively.

Also, the other of the above-described two tri-state inverters U SW and the other of the two switches SW F are provided such that, for example, each of them corresponds to an even numbered row in each group G. In FIG. 10 , they are referred to as “tri-state inverters U SW1E to U SW3E ” and “switches SW F1E , to SW F3E ”, respectively.

Furthermore, signal lines L S1 to L S3 which correspond to the odd numbered rows are referred to as “L S1O to L S3O ” and the even numbered rows, “L S1E to L S3E ”. Also, the output lines L OUT and output units U OUT which correspond to the odd numbered row are respectively referred to as “L OUTO ” and “U OUTO ”, and the even numbered row, “L OUTE ” and “U OUTE ”.

This arrangement can output a digital signal of each memory ME on each odd numbered row and a digital signal of each memory ME on each even numbered row simultaneously, and is thus advantageous in increasing a data reading speed.

Since the digital signals having different values can propagate through the output lines L OUTO and L OUTE , a crosstalk may occur between the output lines L OUTO and L OUTE . To prevent this crosstalk, it is preferable, for example, to arrange the signal line L S1O and the like and a power supply line between the output lines L OUTO and L OUTE .

FIG. 11 is a schematic view showing an upper surface of a layout when the signal line is arranged between the output lines L OUTO and L OUTE . An arrangement in which the signal line L S1E is arranged between the output lines L OUTO and L OUTE is illustrated here.

In FIG. 11 , a plurality of wiring patterns ML 1 are arranged in a wiring layer which is different from the signal line L S1O and the like and the output line L OUTO and the like in a direction crossing the signal line L S1O and the like and the output line L OUTO and the like. Each wiring pattern ML 1 is electrically connected to the corresponding signal line L S1O or the like or output line L OUTO or the like via a via V 1 . With this arrangement, the respective units are electrically connected to each other.

As described above, the signal line L S1O or the like is fixed at L in the group G which is not the output target of the digital signals. Therefore, the signal line L S1O or the like functions as a shield against the crosstalk between the output lines L OUTO and L OUTE . The arrangement in which the signal line L S1E or the like is arranged between the output lines L OUTO and L OUTE has been illustrated in this embodiment. However, the signal line L S1E may be used as a shield between other wirings.

As described above, this embodiment can obtain the same effects as in the first embodiment, and is also advantageous in increasing the data reading speed and preventing the crosstalk between the wirings.

The seven embodiments have been described above. However, the present invention is not limited to these. The present invention may appropriately change some of them or combine the respective embodiments in accordance with the object or the like. For example, the connecting unit U CN may be arranged to be able to change an electrical connection in a path between processing units U PR and the output lines L OUT , and may use, as its switches SW F and tri-state inverters U SW , other switch elements which are set in conductive states or non-conductive states based on control signals. For example, analog switches or one of NMOS transistors and PMOS transistors may be used as the switches SW F .

(Imaging System)

In the above embodiments, the present invention has been described by exemplifying a solid-state imaging apparatus included in an imaging system represented by a camera or the like. The concept of the imaging system includes not only apparatuses primarily aiming at shooting but also apparatuses (for example, a personal computer and a portable terminal) secondarily having a shooting function. The imaging system can include the solid-state imaging apparatus exemplified in the above embodiments, and a calculation unit (a processor or the like) that processes a signal output from the solid-state imaging apparatus.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

This application claims the benefit of Japanese Patent Application No. 2014-075727, filed Apr. 1, 2014, which is hereby incorporated by reference herein in its entirety.