Semiconductor device and method of manufacturing the same

This application is based upon and claims the benefit of priority from the prior U.S. Provisional Patent Application No. 62/079,305 filed on Nov. 13, 2014, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate to a semiconductor device and a method of manufacturing the same.

In recent years, fine patterns of a semiconductor device are often formed by sidewall transfer process. For example, word lines of a semiconductor storage device such as a NAND memory are formed by the sidewall transfer process for downscaling purposes in many cases. However, when the word lines are formed by the sidewall transfer process, the reduction of the line width and the space width of the word lines makes it difficult to form pad portions (hook-up portions), which are used to dispose contact plugs on the word lines. The reason is that the reduction of these widths makes it difficult, when lithography for processing the pad portions is performed, to perform the alignment in lithography for dividing the pad portions and cutting the word lines from the pad portions. Therefore, a method that can process the pad portions simply and accurately is demanded.

FIGS. 1A to 10B are plan views and cross-sectional views showing a method of manufacturing a semiconductor device of a first embodiment;

FIG. 11 is a graph showing a relation of an initial space width between patterns of an upper layer and a final space width between patterns of a lower layer, when the patterns of the upper layer are transferred to the lower layer;

FIGS. 12 and 13 are plan views showing a method of manufacturing a semiconductor device of a second embodiment;

FIG. 14 is a plan view showing a method of manufacturing a semiconductor device of a modification of the second embodiment; and

FIGS. 15 to 20 are plan views showing a method of manufacturing a semiconductor device of a third embodiment.

Embodiments will now be explained with reference to the accompanying drawings.

In one embodiment, a semiconductor device includes a substrate, and first to fourth interconnects provided on the substrate so as to be adjacent to one another. The device further includes a first pad portion connected with the first or second interconnect, and a second pad portion adjacent to the first pad portion in a first direction. The device further includes a third pad portion connected with the third or fourth interconnect, and adjacent to one of the first and second pad portions in a second direction perpendicular to the first direction, and a fourth pad portion adjacent to the third pad portion in the first direction, and adjacent to the other of the first and second pad portions in the second direction. The device further includes one or more interconnects electrically insulated from the first to fourth interconnects and the first to fourth pad portions, and provided between the first and second interconnects and the third and fourth interconnects.

First Embodiment

FIGS. 1A to 10B are plan views and cross-sectional views showing a method of manufacturing a semiconductor device of a first embodiment. The semiconductor device of the present embodiment is a NAND memory.

FIG. 1A is a plan view showing the semiconductor device of the present embodiment. FIG. 1B is a cross-sectional view taken along line I-I′ in FIG. 1A . The same goes for FIGS. 2A to 10B .

[ FIGS. 1A and 1B ]

First, a gate insulator 2 , a floating gate material 3 , an inter gate insulator 4 , a control gate material 5 that is an example of the interconnect layer, a first mask layer 11 , a second mask layer 12 , a hard mask layer 13 that is an example of the first film, a first core material 14 that is an example of the second film, a second core material 15 that is an example of the third film, and a resist film 16 are formed in order, on a substrate 1 ( FIGS. 1A and 1B ).

Examples of the substrate 1 include a semiconductor substrate such as a silicon substrate. FIGS. 1A and 1B show an X direction and Y direction that are parallel to the surface of the substrate 1 and that are perpendicular to each other, and show a Z direction that are perpendicular to the surface of the substrate 1 . The X direction and the Y direction are examples of the first direction and the second direction, respectively.

In this specification, the +Z direction is handled as the upward direction, and the −Z direction is handled as the downward direction. For example, the positional relation between the substrate 1 and the resist film 16 is described as the substrate 1 being positioned below the resist film 16 . The −Z direction in the present embodiment may agree with the gravity direction, or may disagree with the gravity direction.

Examples of the gate insulator 2 include a silicon oxide film. Examples of the floating gate material 3 include a polysilicon layer. Examples of the inter gate insulator 4 include a silicon oxide film, a silicon nitride film, and a laminated film including them. Examples of the control gate material 5 include a polysilicon layer, a metal layer, and a laminated film including them.

Examples of the first mask layer 11 include an insulator such as a silicon nitride film. Examples of the second mask layer 12 include a silicon oxide film. Examples of the hard mask layer 13 include a polysilicon layer and an amorphous silicon layer. Examples of the first core material 14 include a silicon oxide film. Examples of the second core material 15 include a silicon nitride film.

Next, the resist film 16 is processed by lithography (FIGS. 1 A and 1 B). As a result, the resist film 16 is processed into a resist pattern including belt portions 16 A, 16 B and line portions 16 C, 16 D.

The belt portions 16 A, 16 B extend in the X direction, and surround opening portions P A , P B , respectively. The line portions 16 C, 16 D extend mainly in the Y direction, and are connected with the belt portions 16 A, 16 B, respectively. The opening portions P A , P B are positioned near end portions of the line portions 16 C, 16 D, respectively.

The resist pattern further includes multiple belt portions having the same shape as the belt portions 16 A, 16 B, and multiple line portions having the same shape as the line portions 16 C, 16 D, but the illustration of these is omitted in FIGS. 1A and 1B . The same goes for the other patterns shown in FIGS. 2A to 10B .

[ FIGS. 2A and 2B ]

Next, by the etching using the resist film 16 as a mask, the second core material. 15 is processed ( FIGS. 2A and 2B ). As a result, the second core material 15 is processed into a core material pattern including belt portions 15 A, 15 B and line portions 15 C, 15 D. The core material pattern of the second core material 15 is an example of the first pattern. Further, examples of the above etching include a reactive ion etching (RIE).

The belt portions 15 A, 15 B extend in the X direction, and surround opening portions Q A , Q B , respectively. The line portions 15 C, 15 D extend mainly in the Y direction, and are connected with the belt portions 15 A, 15 B, respectively. The opening portions Q A , Q B are positioned near end portions of the line portions 15 C, 15 D, respectively.

[ FIGS. 3A and 3B ]

Next, a first sidewall film 17 is formed on the side faces of the second core material 15 ( FIGS. 3A and 3B ). Examples of the first sidewall film 17 include a silicon oxide film.

The first sidewall film 17 includes line portions 17 C 1 , 17 C 2 formed on the side faces of the belt portion 15 A and line portion 15 C of the second core material 15 , and line portions 17 D 1 , 17 D 2 formed on the side faces of the belt portion 15 B and line portion 15 D of the second core material 15 .

The first sidewall film 17 further includes a dummy portion 17 E formed on the side faces of the opening portion Q A , and a dummy portion 17 F formed on the side faces of the opening portion Q B . The dummy portions 17 E, 17 F have a ring shape.

[ FIGS. 4A and 4B ]

Next, the second core material 15 is removed by etching or ashing ( FIGS. 4A and 4B ).

[ FIGS. 5A and 5B ]

Next, by the etching using the first sidewall film 17 as a mask, the first core material 14 is processed ( FIGS. 5A and 5B ). As a result, the first core material 14 is processed into a core material pattern including belt portions 14 A, 14 B, line portions 14 C 1 , 14 C 2 , 14 D 1 , 14 D 2 , and dummy portions 14 E, 14 F. The core material pattern of the first core material 14 is an example of the second pattern. Further, examples of the above etching include an RIE. The dummy portions 14 E, 14 F, for which the illustration is omitted for the convenience of the figure drawing, are positioned under the dummy portions 17 E, 17 F, respectively.

The belt portions 14 A, 14 B extend in the X direction. The line portions 14 C 1 , 14 C 2 , 14 D 1 , 14 D 2 extend mainly in the Y direction. The line portions 14 C 1 , 14 C 2 are connected with the belt portion 14 A, and the line portions 14 D 1 , 14 D 2 are connected with the belt portion 14 B.

The dummy portion 17 E is separated from the belt portion 14 A and the line portions 14 C 1 , 14 C 2 , and is positioned between the line portion 14 C 1 and the line portion 14 C 2 . The dummy portion 17 E is adjacent to the belt portion 14 A in the X direction. The line portions 14 C 1 , 14 C 2 are examples of the first and second line portions, respectively, and the dummy portion 17 E is an example of the portion that is positioned between the first line portion and the second line portion.

The dummy portion 17 F is separated from the belt portion 14 B and the line portions 14 D 1 , 14 D 2 , and is positioned between the line portion 14 D 1 and the line portion 14 D 2 . The dummy portion 17 F is adjacent to the belt portion 14 B in the X direction. The line portions 14 D 1 , 14 D 2 are examples of the first and second line portions, respectively, and the dummy portion 17 F is an example of the portion that is positioned between the first line portion and the second line portion.

The line portions 17 C 1 , 17 C 2 , 17 D 1 , 17 D 2 and dummy portions 17 E, 17 F of the first sidewall film 17 are transferred to the first core material 14 , and thereby, the line portions 14 C 1 , 14 C 2 , 14 D 1 , 14 D 2 and dummy portions 14 E, 14 F in the present embodiment are formed.

On the other hand, the belt portions 14 A, 14 B in the present embodiment are formed by the reverse loading effect. The reverse loading effect accelerates the etching rate for narrow space patterns, and decelerates the etching rate for wide space patterns. The reason is that the narrow space patterns are largely affected by the etching, compared to the wide space patterns.

In the present embodiment, the space between the line portions 17 C 1 , 17 C 2 is wide at a region in the +X direction from the dummy portion 17 E. Therefore, in the steps of FIGS. 5A and 5B , the first core material 14 at this region remains, and the belt portion 14 A is formed.

Similarly, the space between the line portions 17 D 1 , 17 D 2 is wide at a region in the +X direction from the dummy portion 17 F. Therefore, in the steps of FIGS. 5A and 5B , the first core material 14 at this region remains, and the belt portion 14 B is formed.

[ FIGS. 6A and 6B ]

Next, a second sidewall film 18 is formed on the side faces of the first core material 14 ( FIGS. 6A and 6B ). Examples of the second sidewall film 18 include a silicon nitride film.

The second sidewall film 18 includes line portions 18 C 1 to 18 C 4 formed on the side faces of the belt portion 14 A and line portions 14 C 1 , 14 C 2 of the first core material 14 , and line portions 18 D 1 to 18 D 4 formed on the side faces of the belt portion 14 B and line portions 14 D 1 , 14 D 2 of the first core material 14 .

The second sidewall film 18 further includes dummy portions 18 E 1 , 18 E 2 formed on the side faces of the dummy portion 14 E, and dummy portions 18 F 1 , 18 F 2 formed on the side faces of the dummy portion 14 F. The dummy portions 18 E 1 , 18 F 1 have a ring shape, and the dummy portions 18 E 2 , 18 F 2 have a line shape.

The line portions 18 C 2 , 18 C 3 are connected with each other at a region between the belt portion 14 A and the dummy portion 14 E. Further, the line portions 18 D 2 , 18 D 3 are connected with each other at a region between the belt portion 14 B and the dummy portion 14 F.

[ FIGS. 7A and 7B ]

Next, the first core material 14 is removed by etching or ashing ( FIGS. 7A and 7B ).

[ FIGS. 8A and 8B ]

Next, by the etching using the second sidewall film 18 as a mask, the hard mask layer 13 is processed ( FIGS. 8A and 8B ). As a result, the hard mask layer 13 is processed into a hard mask pattern including belt portions 13 A, 13 B, line portions 13 C 1 to 13 C 4 , 13 D 1 to 13 D 4 and dummy portions 13 E 1 , 13 E 2 , 13 F 1 , 13 F 2 . The hard mask pattern is an example of the third pattern. Further, examples of the above etching include an RIE. The dummy portions 13 E 1 , 13 E 2 , 13 F 1 , 13 F 2 , for which the illustration is omitted for the convenience of the figure drawing, are positioned under the dummy portions 18 E 1 , 18 E 2 , 18 F 1 , 18 F 2 , respectively.

The belt portions 13 A, 13 B extend in the X direction. The line portions 13 C 1 to 13 C 4 , 13 D 1 to 13 D 4 extend mainly in the Y direction. The line portions 13 C 1 to 13 C 4 are connected with the belt portion 13 A, and the line portions 13 D 1 to 13 D 4 are connected with the belt portion 13 B.

The dummy portions 13 E 1 , 13 E 2 are separated from the belt portion 13 A and the line portions 13 C 1 to 13 C 4 , and are positioned between the line portions 13 C 1 , 13 C 2 and the line portions 13 C 3 , 13 C 4 . The dummy portions 13 E 1 , 13 E 2 are adjacent to the belt portion 13 A in the X direction. The line portions 13 C 1 to 13 C 4 are examples of the first to fourth line portions, respectively, and the dummy portions 13 E 1 , 13 E 2 are examples of the portion that is positioned between the first and second line portions and the third and fourth line portions.

The dummy portions 13 F 1 , 13 F 2 are separated from the belt portion 13 B and the line portions 13 D 1 to 13 D 4 , and are positioned between the line portions 13 D 1 , 13 D 2 and the line portions 13 D 3 , 13 D 4 . The dummy portions 13 F 1 , 13 F 2 are adjacent to the belt portion 13 B in the X direction. The line portions 13 D 1 to 13 D 4 are examples of the first to fourth line portions, respectively, and the dummy portions 13 F 1 , 13 F 2 are examples of the portion that is positioned between the first and second line portions and the third and fourth line portions.

The line portions 18 C 1 to 18 C 4 , 18 D 1 to 18 D 4 and dummy portions 18 E 1 , 18 E 2 , 18 F 1 , 18 F 2 of the second sidewall film 18 are transferred to the hard mask layer 13 , and thereby, the line portions 13 C 1 to 13 C 4 , 13 D 1 to 13 D 4 and dummy portions 13 E 1 , 13 E 2 , 13 F 1 , 13 F 2 in the present embodiment are formed.

On the other hand, the belt portions 13 A, 13 B in the present embodiment are formed by the reverse loading effect. The reverse loading effect accelerates the etching rate for narrow space patterns, and decelerates the etching rate for wide space patterns. The reason is that the narrow space patterns are largely affected by etching, compared to the wide space patterns.

In the present embodiment, the space between the line portions 18 C 1 , 18 C 4 is wide at a region in the +X direction from the connecting portion between the line portions 18 C 2 , 18 C 3 . Therefore, in the steps of FIGS. 8A and 8B , the hard mask layer 13 at this region remains, and the belt portion 13 A is formed. However, the belt portion 13 A is formed such that opening portions R A1 , R A2 remain at corner portions of the belt portion 13 A. The reason is that the distance between the line portions 18 C 1 , 18 C 2 and the distance between the line portions 18 C 3 , 18 C 4 are short near the corner portions.

Similarly, the space between the line portions 18 D 1 , 18 D 4 is wide at a region in the +X direction from the connecting portion between the line portions 18 D 2 , 18 D 3 . Therefore, in the steps of FIGS. 8A and 8B , the hard mask layer 13 at this region remains, and the belt portion 13 B is formed. However, the belt portion 13 B is formed such that opening portions R B1 , R B2 remain at corner portions of the belt portion 13 B. The reason is the same as the case of the belt portion 13 A.

[ FIGS. 9A and 9B ]

Next, by the etching using the hard mask layer 13 as a mask, the second mask layer 12 , the first mask layer 11 , the control gate material 5 , the inter gate insulator 4 , the floating gate material 3 , and the gate insulator 2 are processed ( FIGS. 9A and 9B ). As a result, the first mask layer 11 is processed into a mask pattern including belt portions 11 A, 11 B, line portions 11 C 1 to 11 C 4 , 11 D 1 to 11 D 4 and dummy portions 11 E 1 , 11 E 2 , 11 F 1 , 11 F 2 . Examples of the above etching include an RIE.

The same goes for the control gate material 5 , the inter gate insulator 4 , the floating gate material 3 , and the gate insulator 2 . For example, the control gate material 5 is processed into an interconnect pattern including belt portions 5 A, 5 B, line portions 5 C 1 to 5 C 4 , 5 D 1 to 5 D 4 , and dummy portions 5 E 1 , 5 E 2 , 5 F 1 , 5 F 2 .

The belt portions 5 A, 5 B, the line portions 5 C 1 to 5 C 4 , 5 D 1 to 5 D 4 , and the dummy portions 5 E 1 , 5 E 2 , 5 F 1 , 5 F 2 , for which the illustration of the reference characters and the shapes is omitted for the convenience of the figure drawing, are positioned under the belt portions 11 A, 11 B, the line portions 11 C 1 to 11 C 4 , 11 D 1 to 11 D 4 and the dummy portions 11 E 1 , 11 E 2 , 11 F 1 , 11 F 2 , respectively. The line portions 5 C 1 to 5 C 4 , 5 D 1 to 5 D 4 function as word lines WL 1 to WL 8 , respectively.

The belt portions 11 A, 11 B extend in the X direction. The line portions 11 C 1 to 11 C 4 , 11 D 1 to 11 D 4 extend mainly in the Y direction, and are arranged so as to be adjacent to each other. The line portions 11 C 1 to 11 C 4 are connected with the belt portion 11 A, and the line portions 11 D 1 to 11 D 4 are connected with the belt portion 11 B. The same goes for the belt portions 5 A, 5 B, and the line portions 5 C 1 to 5 C 4 , 5 D 1 to 5 D 4 .

The dummy portions 11 E 1 , 11 E 2 are separated from the belt portion 11 A and the line portions 11 C 1 to 11 C 4 , and are positioned between the line portions 11 C 1 , 11 C 2 and the line portions 11 C 3 , 11 C 4 . The dummy portions 11 E 1 , 11 E 2 are adjacent to the belt portion 11 A in the X direction. The dummy portion 11 E 1 has a ring shape, and the dummy portion 11 E 2 has a line shape. The same goes for the line portions 5 C 1 to 5 C 4 and the dummy portions 5 E 1 , 5 E 2 . The line portions 5 C 1 to 5 C 4 are examples of the first to fourth interconnects, respectively. The dummy portions 5 E 1 , 5 E 2 are examples of the one or more interconnects. The dummy portions 5 E 1 , 5 E 2 are separated (electrically insulated) from the belt portion 5 A and the line portions 5 C 1 to 5 C 4 .

The dummy portions 11 F 1 , 11 F 2 are separated from the belt portion 11 B and the line portions 11 D 1 to 11 D 4 , and are positioned between the line portions 11 D 1 , 11 D 2 and the line portions 11 D 3 , 11 D 4 . The dummy portions 11 F 1 , 11 F 2 are adjacent to the belt portion 11 B in the X direction. The dummy portion 11 F 1 has a ring shape, and the dummy portion 11 F 2 has a line shape. The same goes for the line portions 5 D 1 to 5 D 4 and the dummy portions 5 F 1 , 5 F 2 . The line portions 5 D 1 to 5 D 4 are examples of the first to fourth interconnects, respectively. The dummy portions 5 F 1 , 5 F 2 are examples of the one or more interconnects. The dummy portions 5 F 1 , 5 F 2 are separated (electrically insulated) from the belt portion 5 B and the line portions 5 D 1 to 5 D 4 .

Similarly to the belt portion 13 A, the belt portion 11 A in the present embodiment is formed such that opening portions S A1 , S A2 remain at corner portions of the belt portion 11 A. Reference characters K 1 to K 4 denote end portions of the line portions 11 C 1 to 11 C 4 , respectively. The line portions 11 C 1 to 11 C 4 are connected with the belt portion 11 A at the end portions K 1 to K 4 , respectively. The same goes for the belt portion 11 B and the line portions 11 D 1 to 11 D 4 . Furthermore, the same goes for the belt portions 5 A, 5 B and the line portions 5 C 1 to 5 C 4 , 5 D 1 to 5 D 4 .

In the present embodiment, due to the opening portion S A1 , the distance between the end portion K 1 of the line portion 11 C 1 and the end portion K 2 of the line portion 11 C 2 is greater than the space width between the line portion 11 C 1 and the line portion 11 C 2 . Furthermore, due to the opening portion S A2 , the distance between the end portion K 3 of the line portion 11 C 3 and the end portion K 4 of the line portion 11 C 4 is greater than the space width between the line portion 11 C 3 and the line portion 11 C 4 . The same goes for the line portions 11 D 1 to 11 D 4 . Furthermore, the same goes for the line portions 5 C 1 to 5 C 4 , 5 D 1 to 5 D 4 .

The space width between the line portion 11 C 1 and the line portion 11 C 2 , and the space width between the line portion 11 C 3 and the line portion 11 C 4 are specified by the major portions of these line portions 11 C 1 to 11 C 4 , that is, by the portions where these line portions 11 C 1 to 11 C 4 extend in the Y direction. Therefore, these space widths are roughly equal to the line widths of the line portions 17 C 1 , 17 C 2 of the first sidewall film 17 , and the line widths of the line portions 14 C 1 , 14 C 2 of the first core material 14 .

[ FIGS. 10A and 10B ]

Next, the belt portions 11 A, 11 B are divided by lithography and etching ( FIGS. 10A and 10B ). The same goes for the control gate material 5 , the inter gate insulator 4 , the floating gate material 3 and the gate insulator 2 . Examples of the above etching include an RIE.

The belt portion 11 A is divided by trenches T A , T A1 , T A2 . The trench T A extends in the X direction such that the belt portion 11 A is divided into two. The trench T A1 extends in the X direction and the Y direction such that the trench T A and the opening portion S A1 are linked. The trench T A2 extends in the X direction and the Y direction such that the trench T A and the opening portion S A2 are linked.

As a result, the belt portion 11 A is divided into belt portions 11 A 1 to 11 A 4 that are connected with the line portions 11 C 1 to 11 C 4 , respectively. The belt portions 11 A 1 , 11 A 2 are adjacent to each other in the X direction, and the belt portions 11 A 3 , 11 A 4 are adjacent to each other in the X direction. Further, the belt portions 11 A 1 , 11 A 4 are adjacent to each other in the Y direction, and the belt portions 11 A 2 , 11 A 3 are adjacent to each other in the Y direction.

In the present embodiment, a part of the belt portion 11 A 1 is positioned in the +Y direction from the belt portion 11 A 2 , and a part of the belt portion 11 A 4 is positioned in the −Y direction from the belt portion 11 A 3 . Therefore, the belt portions 11 A 1 , 11 A 2 are adjacent to each other in the Y direction. Similarly, the belt portions 11 A 3 , 11 A 4 are adjacent to each other in the Y direction.

Similarly to the belt portion 11 A, the belt portion 5 A is divided into belt portions 5 A 1 to 5 A 4 that are connected with the line portions 5 C 1 to 5 C 4 , respectively. While the line portions 5 C 1 to 5 C 4 function as the word lines WL 1 to WL 4 , respectively, the belt portions 5 A 1 to 5 A 4 function as pad portions (hook-up portions) HU 1 to HU 4 for the word lines WL 1 to WL 4 , respectively.

The same goes for the belt portion 11 B and the belt portion 5 B. Similarly to the belt portion 11 B, the belt portion 5 B is divided into belt portions 5 B 1 to 5 B 4 that are connected with line portions 5 D 1 to 5 D 4 , respectively. While the line portions 5 D 1 to 5 D 4 function as the word lines WL 5 to WL 8 , respectively, the belt portions 5 B 1 to 5 B 4 function as pad portions HU 5 to HU 8 for the word lines WL 5 to WL 8 , respectively.

Thereafter, in the present embodiment, an inter layer dielectric is formed on the whole surface of the substrate 1 , contact holes that penetrate the inter layer dielectric and reach the pad portions HU 1 to HU 8 are formed, and contact plugs 21 are formed on the pad portions HU 1 to HU 8 in the contact holes. Furthermore, various interconnect layers, plug layers, inter layer dielectrics and the like are formed on the substrate 1 . In this way, the semiconductor device of the present embodiment is manufactured.

FIG. 11 is a graph showing a relation of an initial space width between patterns of an upper layer and a final space width between patterns of a lower layer, when the patterns of the upper layer are transferred to the lower layer.

In the case where the initial space width is “Wa” or less, the final space width changes so as to be roughly proportional to the initial space width. For example, in the case where the initial space width is “Wa”, the final space width is “Wa′”, which is close to “Wa”. Therefore, in the case where the initial space width is “Wa” or less, the shape of the patterns of the lower layer is roughly equal to the shape of the patterns of the upper layer.

However, when the initial space width increases to a range of “Wa” to “Wb”, the change rate of the final space width decreases from a positive value to about 0, and further changes to a negative value. Further, in the case where the initial space width is “Wb” or more, the final space width is 0. Therefore, in the case where the initial space width is “Wb” or more, the patterns of the upper layer are not transferred to the lower layer.

Therefore, in the present embodiment, the space width between the line portions 17 C 1 , 17 C 2 and the space widths between the line portions 18 C 1 to 18 C 4 are set to “Wa” or less. As a result, the patterns of the line portions 17 C 1 , 17 C 2 are transferred to the first core material 14 , as shown in FIGS. 5A and 5B . Furthermore, the patterns of the line portions 18 C 1 to 18 C 4 are transferred to the hard mask layer 13 , as shown in FIGS. 8A and 8B .

Further, in the present embodiment, the space between the line portions 17 C 1 , 17 C 2 in the +X direction from the dummy portions 17 E and the space between the line portions 18 C 1 , 18 C 4 in the +X direction from the connecting portion of the line portions 18 C 2 , 18 C 3 are set to a width of “Wb” or more. As a result, the belt portion 14 A is formed by the reverse loading effect, as shown in FIGS. 5A and 5B . Furthermore, the belt portion 13 A is formed by the reverse loading effect, as shown in FIGS. 8A and 8B .

Further, in the present embodiment, the dummy portion 17 E is formed between the line portion 17 C 1 and the line portion 17 C 2 , and the dummy portions 18 E 1 , 18 E 2 are formed between the line portions 18 C 1 , 18 C 2 and the line portions 18 C 3 , 18 C 4 . As a result, a space remains between the belt portion 14 A and the dummy portion 17 E, as shown in FIGS. 5A and 5B . Furthermore, the opening portions R A1 , R A2 remain at the corner portions of the belt portion 13 A, as shown in FIGS. 8A and 8B .

Therefore, according to the present embodiment, by using the space and opening portions R A1 , R A2 , the trenches T A , T A1 , T A2 are easily formed in the belt portion 11 A, and the belt portion 11 A is easily divided. In the present embodiment, the trenches T A , T A1 , T A2 may be formed in the belt portion 11 A, by using the above-described space and without using the opening portions R A1 , R A2 . An example of such a method will be explained in a modification of a second embodiment.

In the present embodiment, as shown in FIGS. 2A and 2B , the belt portion 15 A is formed so as to surround the opening portion Q A . Therefore, according to the present embodiment, the dummy portion 17 E can be formed between the line portion 17 C 1 and the line portion 17 C 2 , and the space can remain between the belt portion 14 A and the dummy portion 17 E ( FIGS. 5A and 5B ). Further, according to the present embodiment, the dummy portions 18 E 1 , 18 E 2 can be formed between the line portions 18 C 1 , 18 C 2 and the line portions 18 C 3 , 18 C 4 , and the opening portions R A1 , R A2 can remain at the corner portions of the belt portion 13 A ( FIGS. 8A and 8B ).

Therefore, according to the present embodiment, it is possible to form the pad portions HU 1 to HU 4 from the belt portion 5 A, simply and accurately. For example, it is possible to form a wide space in the ±X directions from the belt portion 11 A ( 5 A), and therefore, it is easy to avoid a mistaken cut of the word lines WL 1 to WL 4 by the trench T A . Further, it is possible to form the opening portions S A1 , S A2 at the corner portions of the belt portion 11 A ( 5 A), and therefore, it is easy to avoid a mistaken cut of the word lines WL 1 to WL 4 by the trenches T A1 , T A2 .

Further, in the present embodiment, it is possible to form the belt portion 5 A and the pad portions HU 1 to HU 4 in a nearly quadrangular shape. Therefore, according to the present embodiment, it is possible to set a wide area for the pad portions HU 1 to HU 4 , and to enhance the integration degree of the semiconductor device.

Second Embodiment

FIGS. 12 and 13 are plan views showing a method of manufacturing a semiconductor device of a second embodiment.

FIGS. 12 and 13 correspond to FIGS. 9 and 10 respectively, and show the shapes of the control gate material 5 before division and after division. Belt portions HU A , HU B in FIG. 12 represent the belt portions 5 A, 5 B, respectively.

As shown in FIG. 12 , the word lines WL 1 to WL 4 are connected with a belt portion HU D , in addition to the belt portion HU A . Further, the belt portions HU A , HU D are connected with word lines WL 13 to WL 16 , also. The word lines WL 13 to WL 16 , which are examples of the fifth to eighth interconnects respectively, are arranged so as to be adjacent to each other. Similarly to the first embodiment, dummy portions are arranged in the ±X directions from the belt portions HU A , HU D .

Similarly, the word lines WL 5 to WL 8 are connected with a belt portion HU C , in addition to the belt portion HU B . Further, the belt portions HU B , HU C are connected with word lines WL 9 to WL 12 , also. The word lines WL 9 to WL 12 , which are examples of the fifth to eighth interconnects respectively, are arranged so as to be adjacent to each other. Similarly to the first embodiment, dummy portions are arranged in the ±X directions from the belt portions HU B , HU C .

As shown in FIG. 13 , the belt portion HU A is divided by the trenches T A , T A1 , T A2 , and the belt portion HU B is divided by the trenches T B , T B1 , T B2 . This is the same as the first embodiment. Further, the word lines WL 9 to WL 16 are cut by a trench T E that passes through the dummy portions in the +X directions from the belt portions HU A , HU B . As a result, the belt portions HU A , HU B are separated (electrically insulated) from the word lines WL 9 to WL 16 . Further, the belt portions HU A , HU B are divided into pad portions HU 1 to HU 8 that are connected with the word lines WL 1 to WL 8 , respectively.

Similarly, the belt portion HU C is divided by trenches T C , T C2 , and the belt portion HU D is divided by trenches T D , T D1 , T D2 . Further, the word lines WL 1 to WL 8 are cut by a trench T F that passes through the dummy portions in the −X directions from the belt portions HU C , HU D . As a result, the belt portions HU C , HU D are separated (electrically insulated) from the word lines WL 1 to WL 8 . Further, the belt portions HU C , HU D are divided into pad portions HU 9 to HU 16 that are connected with the word lines WL 9 to WL 16 , respectively.

The trenches T A , T B , T C , T D may be formed by the cutting of the dummy portions as shown in the present embodiment, or may be formed without the cutting of the dummy portions as shown in the first embodiment.

FIG. 14 is a plan view showing a method of manufacturing a semiconductor device of a modification of the second embodiment.

FIG. 14 corresponds to FIG. 10 , similarly to FIG. 13 , and shows the shape of the control gate material 5 after division.

In FIG. 14 , the trenches T A1 , T A2 extend in the Y direction so as to link the trench T A and the opening portions S A1 , S A2 , respectively, and the trenches T B1 , T B2 extend in the Y direction so as to link the trench T B and the opening portions S B1 , S B2 , respectively. Further, a trench T E1 extends in the Y direction such that the belt portions HU A , HU B as well as the trenches T A , T B are divided into four. Further, trenches T A3 , T B3 , T E2 are formed at the opening portions S A3 , S A4 , S B3 , S B4 such that the word lines WL 9 , WL 12 , WL 13 , WL 16 are cut.

As a result, the belt portions HU A , HU B are separated (electrically insulated) from the word lines WL 2 , WL 3 , WL 6 , WL 9 , WL 12 , WL 13 , WL 16 . Further, the belt portions HU A , HU B are divided into the pad portions HU 1 , HU 4 , HU 5 , HU 8 , HU 10 , HU 11 , HU 14 , HU 15 that are connected with the word lines WL 1 , WL 4 , WL 5 , WL 8 , WL 10 , WL 11 , WL 14 , WL 15 , respectively.

Similarly, the belt portions HU C , HU D are separated (electrically insulated) from the word lines WL 1 , WL 4 , WL 5 , WL 8 , WL 10 , WL 14 , WL 15 . Further, the belt portions HU C , HU D are divided into the pad portions HU 2 , HU 3 , HU 6 , HU 7 , HU 9 , HU 12 , HU 13 , HU 16 that are connected with the word lines WL 2 , WL 3 , WL 6 , WL 7 , WL 9 , WL 12 , WL 13 , WL 16 , respectively.

According to the present embodiment, similarly to the first embodiment, it is possible to form the pad portions HU 1 to HU 16 from the belt portions HU A to HU D , simply and accurately.

The shape of the trench for dividing the belt portions HU A to HU D may be other than the shapes shown in FIG. 13 and FIG. 14 . However, as for the trenches in FIG. 13 , for example, the trenches T E , T F for cutting the belt portions HU A to HU D and the word lines WL 1 to WL 16 have a line shape, and therefore, there is an advantage that the trenches T E , T F are easily formed. Further, for example, the trenches in FIG. 14 have an advantage that the areas of the pad portions HU 1 to HU 16 are easily widened.

Third Embodiment

FIGS. 15 to 20 are plan views showing a method of manufacturing a semiconductor device of a third embodiment. In the description of the present embodiment, detailed descriptions for common matters with the first embodiment are omitted.

First, the gate insulator 2 , the floating gate material 3 , the inter gate insulator 4 , the control gate material 5 , the first mask layer 11 , the second mask layer 12 , the hard mask layer 13 , the first core material 14 , the second core material 15 , and the resist film 16 are formed in order, on the substrate 1 , and the resist film 16 is processed by lithography (see FIG. 1B ).

[ FIG. 15 ]

Next, by the etching using the resist film 16 as a mask, the second core material 15 is processed ( FIG. 15 ). As a result, the second core material 15 is processed into a core material pattern including belt portions 15 A, 15 B, line portions 15 C 1 , 15 C 2 , 15 D 1 , 15 D 2 , and dummy portions 15 E, 15 F.

The belt portions 15 A, 15 B, which extend in the X direction, are examples of the first and second belt portions, respectively. The line portions 15 C 1 , 15 D 1 extend mainly in the Y direction, and are connected with the belt portions 15 A, 15 B, respectively. The line portions 15 C 1 , 15 D 1 are examples of the first and second line portions, respectively. The line portions 15 C 2 , 15 D 2 extend mainly in the Y direction, and are connected with the belt portions 15 A, 15 B, respectively. The line portions 15 C 2 , 15 D 2 are examples of the first and second line portions, respectively.

The dummy portion 15 E is separated from the belt portions 15 A, 15 B and the line portions 15 C 1 , 15 D 1 , and has a line shape. In the present embodiment, there is a wide space U 1 between the belt portion 15 A and line portion 15 C 1 and the belt portion 15 B and line portion 15 D 1 , and the dummy portion 15 E is arranged in the space U 1 .

The dummy portion 15 F is separated from the belt portions 15 A, 15 B and the line portions 15 C 2 , 15 D 2 , and has a line shape. In the present embodiment, there is a wide space U 2 between the belt portion 15 A and line portion 15 C 2 and the belt portion 15 B and line portion 15 D 2 , and the dummy portion 15 F is arranged in the space U 2 .

[ FIG. 16 ]

Next, a first sidewall film 17 is formed on the side faces of the second core material 15 , and the second core material 15 is removed by etching or ashing ( FIG. 16 ).

The first sidewall film 17 includes line portions 17 C 1 to 17 C 4 formed on the side faces of the belt portion 15 A and line portions 15 C 1 , 15 C 2 of the second core material 15 , and line portions 17 D 1 to 17 D 4 formed on the side faces of the belt portion 15 B and line portions 15 D 1 , 15 D 2 of the second core material 15 .

The first sidewall film 17 further includes a dummy portion 17 E formed on the side faces of the dummy portion 15 E, and a dummy portion 17 F formed on the side faces of the dummy portion 15 F. The dummy portions 17 E, 17 F have a ring shape.

The line portions 17 C 1 , 17 C 2 are connected with the line portions 17 C 3 , 17 C 4 , respectively, at the region where the belt portion 15 A was present. Further, the line portions 17 D 1 , 17 D 2 are connected with the line portions 17 D 3 , 17 D 4 , respectively, at the region where the belt portion 15 B was present.

[ FIG. 17 ]

Next, by the etching using the first sidewall film 17 as a mask, the first core material 14 is processed ( FIG. 17 ). As a result, the first core material 14 is processed into a core material pattern including belt portions 14 A, 14 B, line portions 14 C 1 to 14 C 4 , 14 D 1 to 14 D 4 , and dummy portions 14 E, 14 F. The line portions 14 C 1 to 14 C 4 , 14 D 1 to 14 D 4 , and the dummy portions 14 E, 14 F, for which the illustration is omitted for the convenience of the figure drawing, are positioned under the line portions 17 C 1 to 17 C 4 , 17 D 1 to 17 D 4 and the dummy portions 17 E, 17 F.

The line portions 17 C 1 to 17 C 4 , 17 D 1 to 17 D 4 and dummy portions 17 E, 17 F of the first sidewall film 17 are transferred to the first core material 14 , and thereby, the line portions 14 C 1 to 14 C 4 , 14 D 1 to 14 D 4 and dummy portions 14 E, 14 F in the present embodiment are formed.

On the other hand, the belt portions 14 A, 14 B in the present embodiment are formed by the reverse loading effect. However, the belt portion 14 A is formed such that opening portions V A1 , V A2 remain at end portions of the belt portion 14 A. Further, the belt portion 14 B is formed such that opening portions V B1 , V B2 remain at end portions of the belt portion 14 B. The reason is because the spaces at the end portions of the belt portions 14 A, 14 B are gradually widened, and therefore, the spaces near the end portions of the belt portions 14 A, 14 B are narrow.

[ FIG. 18 ]

Next, a second sidewall film 18 is formed on the side faces of the first core material 14 , and the first core material 14 is removed by etching or ashing ( FIG. 18 ).

The second sidewall film 18 includes line portions 18 C 1 to 18 C 8 formed on the side faces of the belt portion 14 A and line portions 14 C 1 to 14 C 4 of the first core material 14 , and line portions 18 D 1 to 18 D 8 formed on the side faces of the belt portion 14 B and line portions 14 D 1 to 14 D 4 of the first core material 14 .

The second sidewall film 18 further includes dummy portions 18 E 1 , 18 E 2 formed on the side faces of the dummy portion 14 E, and dummy portions 18 F 1 , 18 F 2 formed on the side faces of the dummy portion 14 F. The dummy portions 18 E 1 , 18 F 1 have a ring shape, and the dummy portions 18 E 2 , 18 F 2 have a line shape.

The line portions 18 C 1 to 18 C 4 are connected with the line portions 18 C 5 to 18 C 8 , respectively, at the region where the belt portion 14 A was present. Further, the line portions 18 D 1 to 18 D 4 are connected with the line portions 18 D 5 to 18 D 8 , respectively, at the region where the belt portion 14 B was present.

[ FIG. 19 ]

Next, by the etching using the second sidewall film 18 as a mask, the hard mask layer 13 is processed ( FIG. 19 ). As a result, the hard mask layer 13 is processed into a hard mask pattern including belt portions 13 A, 13 B, line portions 13 C 1 to 13 C 8 , 13 D 1 to 13 D 8 , and dummy portions 13 E 1 , 13 E 2 , 13 F 1 , 13 F 2 . The line portions 13 C 1 to 13 C 8 , 13 D 1 to 13 D 8 and the dummy portions 13 E 1 , 13 E 2 , 13 F 1 , 13 F 2 , for which the illustration is omitted for the convenience of the figure drawing, are positioned under the line portions 18 C 1 to 18 C 8 , 18 D 1 to 18 D 8 and the dummy portions 18 E 1 , 18 E 2 , 18 F 1 , 18 F 2 , respectively.

The line portions 18 C 1 to 18 C 8 , 18 D 1 to 18 D 8 and dummy portions 18 E 1 , 18 E 2 , 18 F 1 , 18 F 2 of the second sidewall film 18 are transferred to the hard mask layer 13 , and thereby, the line portions 13 C 1 to 13 C 8 , 13 D 1 to 13 D 8 and dummy portions 13 E 1 , 13 E 2 , 13 F 1 , 13 F 2 in the present embodiment are formed.

On the other hand, the belt portions 13 A, 13 B in the present embodiment are formed by the reverse loading effect. However, the belt portion 13 A is formed such that opening portions R A1 to R A4 remain at corner portions of the belt portion 13 A. Further, the belt portion 13 B is formed such that opening portions R B1 to R B4 remain at corner portions of the belt portion 13 B. The reason is that the distance between the line portions 18 C 1 , 18 C 2 , the distance between the line portions 18 D 1 , 18 D 2 , and the like are short near the corner portions.

[ FIG. 20 ]

Next, the second mask layer 12 , the first mask layer 11 , the control gate material 5 , the inter gate insulator 4 , the floating gate material 3 and the gate insulator 2 are processed by the etching using the hard mask layer 13 as a mask, and their belt portions are divided by lithography or etching ( FIG. 20 ). As a result, the first mask layer 11 is processed into a mask pattern including belt portions 11 A 1 to 11 A 4 , 11 B 1 to 11 B 4 , line portions 11 C 1 to 11 C 8 , 11 D 1 to 11 D 8 , and dummy portions 11 E 1 , 11 E 2 , 11 F 1 , 11 F 2 .

The same goes for the control gate material 5 , the inter gate insulator 4 , the floating gate material 3 , and the gate insulator 2 . For example, the control gate material 5 is processed into an interconnect pattern including belt portions 5 A 1 to 5 A 4 , 5 B 1 to 5 B 4 , line portions 5 C 1 to 5 C 8 , 5 D 1 to 5 D 8 , and dummy portions 5 E 1 , 5 E 2 , 5 F 1 , 5 F 2 .

The belt portions 5 A 1 to 5 A 4 , 5 B 1 to 5 B 4 , the line portions 5 C 1 to 5 C 8 , 5 D 1 to 5 D 8 , and the dummy portions 5 E 1 , 5 E 2 , 5 F 1 , 5 F 2 , for which the illustration is omitted for the convenience of the figure drawing, are positioned under the belt portions 11 A 1 to 11 A 4 , 11 B 1 to 11 B 4 , the line portions 11 C 1 to 11 C 8 , 11 D 1 to 11 D 8 , and the dummy portions 11 E 1 , 11 E 2 , 11 F 1 , 11 F 2 , respectively. The line portions 5 C 1 to 5 C 4 , 5 D 1 to 5 D 4 , 5 D 8 to 5 D 5 , 5 C 8 to 5 C 5 function as word lines WL 1 to WL 16 , respectively. Further, the belt portions 5 A 1 to 5 A 4 , 5 B 1 to 5 B 4 function as pad portions HU 1 to HU B for the word lines WL 1 to WL 8 , respectively. The word lines WL 1 to WL 8 are examples of the first to eighth interconnects, respectively, and the dummy portions 5 E 1 , 5 E 2 are examples of the one or more interconnects. Further, the belt portions 5 A 1 to 5 A 4 and belt portions 5 B 1 to 5 B 4 before division are examples of the first and second belt portions, respectively.

The belt portions 11 A 1 to 11 A 4 are connected with the line portions 11 C 1 to 11 C 4 , respectively, and the belt portions 11 B 1 to 11 B 4 are connected with the line portions 11 D 1 to 11 D 4 , respectively. The line portions 11 C 1 to 11 C 4 , 11 D 1 to 11 D 4 extend mainly in the Y direction, and are arranged so as to be adjacent to each other. The line portions 11 C 5 to 11 C 8 , 11 D 5 to 11 D 8 extend mainly in the Y direction, and are arranged so as to be adjacent to each other. The same goes for the belt portions 5 A 1 to 5 A 4 , 5 B 1 to 5 B 4 and the line portions 5 C 1 to 5 C 8 , 5 D 1 to 5 D 8 .

The dummy portions 11 E 1 , 11 E 2 are separated from the belt portions 11 A 1 to 11 A 4 , 11 B 1 to 11 B 4 and the line portions 11 C 1 to 11 C 4 , 11 D 1 to 11 D 4 and are positioned between the line portions 11 C 1 to 11 C 4 and the line portions 11 D 1 to 11 D 4 . The dummy portion 11 E 1 has a ring shape, and the dummy portion 11 E 2 has a line shape. The same goes for the line portions 5 C 1 to 5 C 4 , 5 D 1 to 5 D 4 and the dummy portions 5 E 1 , 5 E 2 . The dummy portions 5 E 1 , 5 E 2 are separated (electrically insulated) from the belt portions 5 A 1 to 5 A 4 , 5 B 1 to 5 B 4 and the line portions 5 C 1 to 5 C 4 , 5 D 1 to 5 D 4 .

The dummy portions 11 F 1 , 11 F 2 are separated from the belt portions 11 A 1 to 11 A 4 , 11 B 1 to 11 B 4 and the line portions 11 C 5 to 11 C 8 , 11 D 5 to 11 D 8 , and are positioned between the line portions 11 C 5 to 11 C 8 and the line portions 11 D 5 to 11 D 8 . The dummy portion 11 F 1 has a ring shape, and the dummy portion 11 F 2 has a line shape. The same goes for the line portions 5 C 5 to 5 C 8 , 5 D 5 to 5 D 8 and the dummy portions 5 F 1 , 5 F 2 . The dummy portions 5 F 1 , 5 F 2 are separated (electrically insulated) from the belt portions 5 A 1 to 5 A 4 , 5 B 1 to 5 B 4 and the line portions 5 C 5 to 5 C 8 , 5 D 5 to 5 D 8 .

Thereafter, in the present embodiment, an inter layer dielectric is formed on the whole surface of the substrate 1 , contact holes that penetrate the inter layer dielectric and reach the pad portions HU 1 to HU 8 are formed, and contact plugs 21 are formed on the pad portions HU 1 to HU 8 in the contact holes. Furthermore, various interconnect layers, plug layers, inter layer dielectrics and the like are formed on the substrate 1 . In this way, the semiconductor device of the present embodiment is manufactured.

In the present embodiment, as shown in FIG. 15 , the wide space U 1 is present between the belt portion 15 A and line portion 15 C 1 and the belt portion 15 B and line portion 15 D 1 . Furthermore, the wide space U 2 is present between the belt portion 15 A and line portion 15 C 2 and the belt portion 15 B and line portion 15 D 2 . Therefore, when the pattern of the first sidewall film 17 is transferred to the first core material 14 , there is a possibility that the first core material 14 remains under the spaces U 1 , U 2 by the reverse loading effect.

Therefore, in the present embodiment, as shown in FIG. 15 , the dummy portions 15 E, 15 F are arranged in the spaces U 1 , U 2 . Therefore, according to the present embodiment, it is possible to inhibit the first core material 14 from remaining under the spaces U 1 , U 2 due to the reverse loading effect ( FIG. 17 ). The same goes for the hard mask layer 13 , the first mask layer 11 , the control gate material 5 and the like ( FIGS. 19 and 20 ). Therefore, according to the present embodiment, it is possible to prevent the short-circuit of the word lines WL 1 to WL 8 and the pad portions HU 1 to HU 8 .

In the present embodiment, for preventing the above-described reverse loading effect, the distances between the dummy portions 15 E, 15 F and the other portion of the second core material 15 is set to “Wa” or less. The same goes for the dummy portions in the other layers.

As described so far, according to the present embodiment, it is possible to accurately form the pad portions HU 1 to HU 8 , by the simple method in which the dummy portions 15 E, 15 F are arranged in the spaces U 1 , U 2 .

The structure and method of the present embodiment may be used in combination with the structure and method of the first embodiment or the second embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.