Memory system and method of controlling nonvolatile memory

This application is based upon and claims the benefit of priority from U.S. Provisional Application No. 62/049,021, filed on Sep. 11, 2014; the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a memory system and a method of controlling a nonvolatile memory.

A nonvolatile memory, represented by a NAND type flash memory, is applied with an appropriate read voltage, whereby information stored therein is read. This appropriate read voltage may vary from that in a default state.

FIG. 1 is a block diagram illustrating a configuration of a memory system according to a first embodiment;

FIG. 2 is a view illustrating a configuration of the memory cell array;

FIGS. 3A and 3B are views each illustrating an exemplary distribution and variation in threshold voltages;

FIG. 4 is a view illustrating an exemplary result of statistical processing in an aggregating unit;

FIG. 5 is a flowchart of tracking processing in the memory system;

FIGS. 6A to 6D are views each illustrating a resultant pattern of statistical processing in the aggregating unit;

FIG. 7 is a view illustrating an exemplary result of statistical processing that the aggregating unit applies to memory cells, each of which stores multiple values;

FIG. 8 is a flowchart of a method of determining data read voltages in a memory system according to a second embodiment; and

FIG. 9 is a flowchart of a method of determining a data read voltage in a memory system according to a third embodiment.

According to an embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of memory cells. Each of the memory cells has a storage capacity of N bits in accordance with 2 to the power of N threshold voltage distributions, where N is a natural number that is equal to or greater than 1. The controller reads data from the plurality of memory cells by using four voltage values. The controller associates three voltage ranges designated by the four voltage values with a number of the memory cells using the four voltage values. The controller specifies, from the three voltage ranges, a first voltage range, a second voltage range, and a third voltage range, the first voltage range having a first distributed number of memory cells, the first distributed number of memory cells being a minimum value of the memory cells, the second voltage range being adjacent to a lower voltage side of the first voltage range, the third voltage range being adjacent to a higher voltage side of the first voltage range. The controller determines a read voltage by using the first voltage range, a first representative voltage value in the first voltage range, the first distributed number of memory cells, a second distributed number of memory cells, and a third distributed number of memory cells, the second distributed number of memory cells being a number of memory cells corresponding to the second voltage range, the third distributed number of memory cells being a number of memory cells corresponding to the third voltage range. The controller reads the data from the nonvolatile memory by using the determined read voltage.

Details of a memory system and a method of controlling a nonvolatile memory according to some embodiments will be described below with reference to the accompanying drawings. It should be noted that these embodiments are not intended to limit the present invention.

First Embodiment

FIG. 1 is a block diagram illustrating a configuration of a memory system 1 according to a first embodiment. As illustrated in FIG. 1 , the memory system 1 is connected to a host device 2 via a communication path 3 , and configures an information processing device, for example, in a personal computer, a portable phone, an imaging device, and the like. The memory system 1 functions as an external storage device for the host device 2 .

The host device 2 sends a write command to the memory system 1 when writing generated data to the memory system 1 . Furthermore, the host device 2 sends a read command to the memory system 1 when reading data from the memory system 1 .

The memory system 1 includes a nonvolatile memory 4 and a controller 5 . An example of the nonvolatile memory 4 is a NAND flash memory. The nonvolatile memory 4 has one or more memory chips 41 . A description will be, herein, given regarding an exemplary case in which a NAND flash memory is used as the nonvolatile memory 4 ; however it may be not only a NAND flash memory but also any other memory such as an MRAM (Magnetoresistive Random Access Memory) or a ReRAM (Resistance Random Access Memory).

Each memory chip 41 has a memory cell array A 1 as illustrated in FIG. 2 . The memory cell array A 1 , which is a NAND cell type memory cell array, is formed of a plurality of memory cells 44 arranged in a matrix pattern, and includes a plurality of NAND cells. Each NAND cell includes a memory string MS formed of memory cells 44 connected in series, and selective gates G 1 and G 2 connected to the respective ends of the memory string MS. The selective gates G 1 are connected to bit lines BL 0 to BL n-1 , and the selective gates G 2 are connected to a source line SRC. The control gates of memory cells 44 arranged in the same row are connected commonly to a corresponding one of word lines WL 0 to WL m-1 . The first selective gates G 1 are connected commonly to a selection line SGD, and second selective gates G 2 are connected commonly to a selection line SGS.

The memory cell array A 1 includes one or more planes P 1 , each of the planes contains a plurality of blocks 42 . Each block 42 includes a plurality of NAND cells, and serves as a unit for data erasing.

A plurality of memory cells 44 connected to one of the word lines constitutes a memory cell group 43 as a physical sector. When each memory cell 44 stores a single bit (binary), one of the memory cell groups 43 corresponds to a single page. When each memory cell 44 stores two or more bits (multiple values), one of the memory cell groups 43 corresponds to multiple pages. Data are written to or read from a NAND flash memory for each page. During a read operation, a program verification operation and a program operation, a single word line and a single page are selected in accordance with a physical address received from a control unit 7 . The pages are switched on the basis of the physical address.

The controller 5 controls write and read commands from the host device 2 , and includes an internal bus 6 , the control unit 7 , an aggregating unit 8 , a calculating unit 9 , and a host interface (hereinafter referred to as a “host I/F”) 10 . The internal bus 6 interconnects the nonvolatile memory 4 , the control unit 7 , the aggregating unit 8 , the calculating unit 9 , and the host I/F 10 .

When the control unit 7 receives a write command from the host device 2 via the host I/F 10 and the internal bus 6 , the control unit 7 writes data to the nonvolatile memory 4 in accordance with the write command. When the control unit 7 receives a read command from the host device 2 , the control unit 7 reads data from the nonvolatile memory 4 in accordance with the read command, and then sends the read data to the host device 2 . During such data reading, the control unit 7 applies read voltages to the memory cells 44 in the nonvolatile memory 4 , and then identifies the data stored in these memory cells 44 . Hereinafter, a read voltage applied to the memory cells 44 in order to read data that will be sent from the memory system 1 to the host device 2 is referred to as a data read voltage. The control unit 7 has an ECC (Error Checking and Correction) circuit (not illustrated). The ECC circuit detects errors in the data read from the nonvolatile memory 4 and corrects them (hereinafter referred to as “error correction processing”) by using an error correction code such as an LDPC (Low Density Parity Check) or BCH (Bose Chaudhuri Hocqenghem) code. When the control unit 7 determines that the ECC circuit has failed to perform the error correction processing as a result of, for example, an event where the number of errors in the read data exceeds the capacity of the ECC circuit to perform the error correction processing, the controller sends a tracking command to the aggregating unit 8 .

When the aggregating unit 8 receives the tracking command from the control unit 7 , the aggregating unit 8 performs a statistical processing for the distribution states of the memory cells 44 in the nonvolatile memory 4 , as will be described later, and then sends the processing result to the calculating unit 9 .

The calculating unit 9 calculates a read voltage for memory cells 44 by using the result of the statistical processing which has been received from the aggregating unit 8 , as will be described later, and then sends this evaluation result to the control unit 7 .

The host I/F 10 outputs commands, write data, and the like which have been received from the host device 2 to the internal bus 6 . Moreover, the host I/F 10 sends read data and the like from the nonvolatile memory 4 to the host device 2 .

FIGS. 3A and 3B are views each illustrating an exemplary distribution and variation in threshold voltages. Assuming that the nonvolatile memory 4 is a NAND flash memory, when a voltage that is equal to or more than a voltage value according to a charge amount of a floating gate is applied to each memory cell 44 , current flows therethrough; whereas when a voltage less than the voltage value is applied, no current flows. This boundary voltage is referred to as a threshold voltage. In each memory cell 44 , stored data are related to a plurality of threshold voltages distributions (threshold distributions). Upon reading data, each memory cell 44 is applied with the data read voltage, and the data are determined depending on whether the data read voltage is higher or lower than the threshold voltage. For the sake of simplifying the description that will be given, each memory cell 44 is assumed to be an exemplary single-bit cell that stores a single bit. In FIGS. 3A and 3B , the vertical axis represents the number of the memory cells, and the horizontal axis represents a threshold voltage (corresponding to the charge amount of the floating gate). FIG. 3A indicates distributions of the thresholds of 1-bit cells. As illustrated in FIG. 3A , of the two threshold distributions, the left threshold distribution corresponds to data “1” and the right threshold distribution corresponds to data “0.” Each memory cell 44 has a threshold voltage corresponding to either of the two threshold distributions in its initial state. When reading data from the nonvolatile memory 4 , a default value V A of a data read voltage (hereinafter referred to as a “default read voltage V A ”), which is a boundary between the two threshold distributions, is applied to each memory cell 44 . Thereby, whether the data stored in each memory cell 44 is “1” or “0” can be determined. In this way, in a case where each memory cell 44 has a storage capacity of N bits, each memory cell 44 has 2 to the power of N threshold voltage distributions.

A NAND flash memory has error factors, such as a data retention error, a read disturbance error and a program disturbance error. These error factors may cause a variation in the charge amount of the floating gate of each memory cell 44 and, therefore, the threshold distributions change as illustrated in FIG. 3B . For this reason, when data are read using a default read voltage V A initially set, the bit errors may occur.

The ECC circuit in the control unit 7 can deal with such read errors by subjecting the read data to the error correction processing. However, when the number of read errors exceeds the capacity of the error correction processing in the ECC circuit, the error correction processing in the ECC circuit fails. In order to prevent the failure of the error correction processing, it is necessary to read the data by using an appropriate data read voltage according to variations in the threshold distributions, thereby reducing the number of read errors. It is possible to acquire such an appropriate data read voltage by varying a read voltage for memory cells 44 in the minimum voltage steps that the memory system 1 can attain and by assessing accurately the plurality of threshold distributions of the memory cells 44 . This method, however, results in the increase in the number (read count) of applications of the read voltage to each memory cell 44 in order to assess accurately the threshold distributions. Accordingly, it takes time to calculate a data read voltage, and heavier stress is placed on each memory cell 44 . In the case of a NAND flash memory, as heavier stress is placed on each memory cell 44 , a possibility of occurrence of error in data stored in the memory cells 44 increases.

FIG. 4 is a view illustrating an exemplary result of statistical processing in the aggregating unit 8 . In FIG. 4 , the horizontal axis represents a voltage (a read voltage for the memory cells 44 illustrated in FIG. 1 or a threshold voltage for the memory cells 44 ), and the vertical axis represents the number of memory cells.

FIG. 4 illustrates a threshold distribution D 1 obtained by varying a read voltage applied to the memory cells 44 in a memory cell group 43 in the minimum voltage steps that the memory system 1 can attain. The memory system 1 can perform tracking of the data read voltage after clarifying the threshold distribution D 1 . As described above, however, this method results in the increase in the read count. Accordingly, it takes time to calculate the data read voltage, and heavier stress may be placed on each memory cell 44 . In view of this issue, the memory system 1 in the first embodiment can reduce the read count, and perform tracking of the data read voltage for the memory cells 44 without assessing the threshold distribution D 1 .

In order to achieve the above tracking, the aggregating unit 8 illustrated in FIG. 1 applies read voltages V 1 to V 4 to a memory cell group 43 in the nonvolatile memory 4 . The read voltages V 1 to V 4 satisfy the relationship “V 1 <V 2 <V 3 <V 4 ”. Widths V gap of the individual read voltage ranges (between the read voltages V 1 and V 2 , between the read voltages V 2 and V 3 and between the read voltages V 3 and V 4 ) are equal to one another. In FIG. 4 , the value of each width V gap is set to an extent that the interval between the first and second peaks in the default threshold distribution (not illustrated) of the plurality of memory cells 44 is equally divided into four segments.

The aggregating unit 8 counts total quantities C 1 to C 4 of memory cells 44 through which current flows at the read voltages V 1 to V 4 , respectively. The total quantity C 1 is the total number of memory cells in the threshold distribution D 1 which are plotted at the read voltage V 1 or below. The total quantity C 2 is the total number of memory cells present in the threshold distribution D 1 at the read voltage V 2 or below. The total quantity C 3 is the total number of memory cells present in the threshold distribution D 1 at the read voltage V 3 or below. The total quantity C 4 is the total number of memory cells present in the threshold distribution D 1 at the read voltage V 4 or below.

Subsequently, the aggregating unit 8 calculates the distributed number of memory cells 44 Δ low , Δ min and Δ high , the threshold voltages of which fall within the respective read voltage ranges (between the read voltages V 1 and V 2 , between the read voltages V 2 and V 3 , and between the read voltages V 3 and V 4 ). Hereafter, “the distributed number of memory cells” is abbreviated as “distribution quantities”. The aggregating unit 8 acquires the distribution quantities Δ low by calculating (total quantity C 2 −total quantity C 1 ). The aggregating unit 8 acquires the distribution quantities Δ min by calculating (total quantity C 3 −total quantity C 2 ). The aggregating unit 8 acquires the distribution quantities Δ high by calculating (total quantity C 4 −total quantity C 3 ). Specifically, the aggregating unit 8 individually counts the total quantities C 1 to C 4 such that the distribution quantities Δ low , Δ min and Δ high satisfy the relationships “Δ min ≦Δ low ” and “Δ min ≦Δ high ”. Furthermore, the aggregating unit 8 determines the intermediate voltages V low , V min and V high corresponding to the distribution quantities Δ low , Δ min and Δ high , respectively. The intermediate voltage V low is set to the middle point of the read voltages V 1 and V 2 (i.e., (V 2 +V 1 )/2). The intermediate voltage V min is set to the middle point of the read voltages V 3 and V 2 (i.e., (V 3 +V 2 )/2). The intermediate voltage V high is set to the middle point of the read voltages V 4 and V 3 (i.e., (V 4 +V 3 )/2). In FIG. 4 , these values are plotted as points P low (V low , Δ low ), P min (V min , Δ min ) and P high (V high , Δ high ).

The aggregating unit 8 sends data regarding the widths V gap and the pints P low , P min and P high to the calculating unit 9 illustrated in FIG. 1 . When the calculating unit 9 receives these data, the calculating unit 9 calculates a read voltage V va11 in accordance with the following equation (1).

V va11 =V min ( V gap /2){(Δ low −Δ high )/(Δ low −Δ min )+(Δ high −Δ min )}  (1)

The read voltage V va11 calculated in this manner is sent from the calculating unit 9 to the control unit 7 . In FIG. 4 , the read voltage V va11 is the point at which the interval between the read voltages V 2 and V 3 is divided internally at a ratio of (f low −Δ min ) (Δ high −Δ min ). It can be assessed that the read voltage v va11 corresponds to the valley portion of the threshold distribution of the memory cells 44 at the time when the data are read from the nonvolatile memory 4 .

The calculating unit 9 subjects the read voltage V va11 to predetermined calculation processing, such as a process of rounding off, then evaluates a read voltage V va12 that is one of read voltages settable by the memory system 1 and is closest to the read voltage V va11 , and designates this read voltage V va12 as the data read voltage. The memory system 1 designates the read voltage V va12 as the data read voltage in this manner. As a result, it is possible to perform tracking of the data read voltage through a reduced read count for each memory cell 44 . Hereinafter, the processing of evaluating the read voltage V va11 or the read voltage V va12 is referred to as tracking processing. According to the description with FIG. 4 , the tracking processing is performed for each memory cell group 43 illustrated in FIG. 2 ; however it may be performed for each memory chip 41 illustrated in FIG. 1 or each block 42 illustrated in FIG. 2 .

FIG. 5 is a flowchart of the tracking processing in the memory system 1 . FIGS. 6A to 6D are views each illustrating a resultant pattern of the statistical processing in the aggregating unit 8 . First, when the control unit 7 receives a read command from the host device 2 via the host I/F 10 , the control unit 7 reads data from the nonvolatile memory 4 at a default read voltage in accordance with the read command (Step S 1 ).

Next, the control unit 7 determines whether or not the ECC circuit has successfully performed the error correction processing for the read data (Step S 2 ). If the control unit 7 determines that the error correction processing has succeeded (Step S 2 : YES), the control unit 7 sends the read data that have undergone the error correction processing to the host device 2 via the host I/F 10 . If the control unit 7 determines that the error correction processing has failed (Step S 2 : NO), the control unit 7 sends a tracking command to the aggregating unit 8 (Step S 3 ). When the aggregating unit 8 receives the tracking command, the aggregating unit 8 calculates the distribution quantity Δ 0 of memory cells 44 , the threshold voltages of which fall within the range between read voltages v 0 and v −1 as illustrated in FIG. 6A (Step S 4 ). An example of the read voltage v 0 is the default read voltage used at Step S 1 . The read voltage v −1 satisfies the relationship “v −1 <v 0 ”. The width of the range between the read voltages v 0 and v −1 is equal to the width V gap described above. The distribution quantity Δ 0 is calculated as a value obtained by subtracting the total quantity c −1 of memory cells 44 with threshold voltages equal to or less than the read voltage v −1 from the total quantity c 0 of memory cells 44 with threshold voltages less than the read voltage v 0 . Next, the aggregating unit 8 calculates the distribution quantity Δ −1 of memory cells 44 , the threshold voltages of which fall within the range between the read voltage v −1 and a read voltage v −2 as illustrated in FIG. 6A (Step S 5 ). The read voltage v −2 satisfies the relationship “v −2 <v −1 ”. The width of the range between the read voltages v −1 and v −2 is equal to the width V gap described above. The distribution quantity Δ −1 is calculated as a value obtained by subtracting the total quantity c −2 of memory cells 44 with threshold voltages equal to or less than the read voltage v −2 from the total quantity c −1 .

Next, the aggregating unit 8 compares magnitudes between the distribution quantities Δ 0 and Δ −1 (Step S 6 ). If the aggregating unit 8 determines that Δ −1 is larger than Δ 0 as illustrated in FIG. 6A (Step S 6 : YES), the aggregating unit 8 calculates the distribution quantity Δ 1 of memory cells 44 , the threshold voltages of which fall within the range between the read voltage v 0 and a read voltage v 1 as illustrated in FIG. 6A (Step S 7 ). The read voltage v 1 satisfies the relationship “v 0 <v 1 ”. The width of the range between the read voltages v 0 and v 1 is equal to the width V gap described above. The distribution quantity Δ 1 is calculated as a value obtained by subtracting the total quantity c 0 from the total quantity c 1 of memory cells 44 with threshold voltages equal to or less than the read voltage v 1 .

Next, the aggregating unit 8 compares magnitudes between the distribution quantities Δ 0 and Δ 1 (Step S 8 ). If the aggregating unit 8 determines that Δ gap is smaller than Δ 1 as illustrated in FIG. 6A (Step S 8 : YES), the aggregating unit 8 determines the width V gap , distribution quantities Δ low , Δ min and Δ high , and intermediate voltages V low , V min and V high and sends them to the calculating unit 9 (Step S 9 ). In this case, the distribution quantity Δ low is the distribution quantity Δ −1 . The distribution quantity Δ min is the distribution quantity Δ 0 . The distribution quantity Δ high is the distribution quantity Δ 1 . The intermediate voltage V low is the middle point between the read voltages v −1 and v −2 ((v −1 +v −2 )/2). The intermediate voltage V min is the middle point between the read voltages v 0 and v −1 ((v 0 +v −1 )/2). The intermediate voltage V high is the middle point between the read voltages v 0 and v 1 ((v 1 +v 0 )/2).

The calculating unit 9 calculates a read voltage V va11 in accordance with the equation (1), and sends the resultant to the control unit 7 . Then, the control unit 7 evaluates the read voltage V va12 on the basis of the read voltage V va11 (step S 10 ). The read voltage V va11 evaluated in this manner is the point at which the interval between the read voltages v 0 and v −1 is divided internally at the ratio of (Δ −1 −Δ 0 ):(Δ 1 −Δ 0 ) as illustrated in FIG. 6A .

If the aggregating unit 8 determines that the relationship “Δ −1 >Δ 0 ” is not satisfied, namely, the relationship “Δ −1 ≦Δ 0 ” is satisfied as illustrated in FIG. 6B , at Step S 6 (Step S 6 : NO), the aggregating unit 8 calculates the distribution quantity Δ −2 of memory cells 44 , the threshold voltages of which fall within the range between the read voltage v −2 and a read voltage v −3 as illustrated in FIG. 6B (Step S 11 ). The read voltage V −3 satisfies the relationship “v −3 <v −2 ”. The width of the range between the read voltages v −2 and v −3 is equal to the width V gap described above. The distribution quantity Δ −2 is calculated as a value obtained by subtracting the total quantity c −3 of memory cells 44 with threshold voltages equal to or less than the read voltage v −3 from the total quantity c −2 , as illustrated in FIG. 6B .

Subsequently, the aggregating unit 8 compares magnitudes between the distribution quantities Δ −1 and Δ −2 (Step S 12 ). If the aggregating unit 8 determines that Δ −2 is larger than Δ −1 as illustrated in FIG. 6B (Step S 12 : YES), the aggregating unit 8 determines the width V gap , distribution quantities A Δ low , Δ min and Δ high , and intermediate voltages V low , V min and V high , and then sends them to the calculating unit 9 (Step S 9 ). In this case, the distribution quantity Δ low is the distribution quantity Δ −2 . The distribution quantity Δ min is the distribution quantity Δ −1 . The distribution quantity Δ high is the distribution quantity Δ 0 . The intermediate voltage V low is the middle point between the read voltages v −2 and v −3 ((v −2 'v −3 )/2). The intermediate voltage V min is the middle point between the read voltages v −1 and v −2 +v −2 )/2). The intermediate voltage V high is the middle point between the read voltages v 0 and v −1 ((v 0 +v −1 )/2).

The calculating unit 9 calculates a read voltage V va11 in accordance with the equation (1), and sends the resultant to the control unit 7 . Then, the control unit 7 evaluates a read voltage V va12 on the basis of the read voltage V va11 (step S 10 ). The read voltage V va11 evaluated in this manner is the point at which the interval between the read voltages v −1 and V −2 is divided internally at the ratio of (Δ −2 −Δ −1 ):(Δ 0 −Δ −1 ) as illustrated in FIG. 6B .

On the other hand, if the aggregating unit 8 determines that Δ −2 is equal to or smaller than Δ −1 as illustrated in FIG. 6C (Step S 12 : NO), the aggregating unit 8 calculates the distribution quantity Δ −3 of memory cells 44 , the threshold voltage of which falls within a range between the read voltage v −3 and a read voltage v −4 as illustrated in FIG. 6C (Step S 13 ). The read voltage v −4 satisfies the relationship “v −4 <v −3 ”. The width of the range between the read voltages v −3 and v −4 is equal to the width V gap described above. The distribution quantity Δ −3 is calculated as a value obtained by subtracting the total quantity c −4 of memory cells 44 with threshold voltages equal to or less than the read voltage v −4 from the total quantity c —3 , as illustrated in FIG. 6C . Subsequently, the aggregating unit 8 determines the width V gap , distribution quantities Δ low , Δ min and Δ high , and intermediate voltages V low , V min and V high , and then sends them to the calculating unit 9 (Step S 9 ). In this case, the distribution quantity Δ low is the distribution quantity Δ −3 . The distribution quantity is the distribution quantity Δ −2 . The distribution quantity Δ high is the distribution quantity Δ −1 . The intermediate voltage V low is the middle point between the read voltages v −3 and v −3 ((v −3 +v −4 )/2). The intermediate voltage V min is the middle point between the read voltages v −2 and v −3 ((v −2 +v −3 )/2). The intermediate voltage V high is the middle point between the read voltages v −1 and v −2 ((v −1 +v −2 )/2). Each of the widths of the respective read voltage ranges (between the read voltages v 0 and v −1 , between the read voltages v −1 and v −2 , between the read voltages v −3 and between the read voltages v −2 and v −3 ) is set to be equal to the width V gap . Therefore, the relationship “Δ −3 ≧Δ −2 ” is satisfied. It is thus possible to determine the distribution quantities Δ low , Δ min and Δ high and the intermediate voltages v low , V min and V high without the need to perform tracking of the memory cells 44 each having a threshold voltages less than the read voltage v −4 .

Subsequently, the calculating unit 9 calculates a read voltage V va11 in accordance with the equation (1), and sends the resultant to the control unit 7 . Then, the control unit 7 evaluates a read voltage V va12 on the basis of the read voltage V va11 (step S 10 ). The read voltage V va11 evaluated in this manner is the point at which the interval between the read voltages v −2 and v −3 is divided internally at the ratio of (Δ −3 −Δ −2 ):(Δ −1 −Δ− 2 ) as illustrated in FIG. 6C .

If the aggregating unit 8 determines that the relationship “Δ 0 <Δ 1 ” is not satisfied, namely, the relationship “Δ 0 ≧Δ 1 ” is satisfied as illustrated in FIG. 6D , at Step S 8 (Step S 8 : NO), the aggregating unit 8 calculates the distribution quantity Δ 2 of memory cells 44 , the threshold voltages of which fall within the range between the read voltage v 1 and a read voltage v 2 as illustrated in FIG. 6D (Step S 14 ). The read voltage V 2 satisfies the relationship “v 1 <v 2 ”. The width between the read voltages v 1 and v 2 is equal to the width V gap described above. The distribution quantity Δ 2 is calculated as a value obtained by subtracting the total quantity c 1 from the total quantity c 2 of memory cells 44 with threshold voltages equal to or less than the read voltage v 2 , as illustrated in FIG. 6D . Subsequently, the aggregating unit 8 determines the width V gap , distribution quantities Δ low , Δ min and Δ high , and intermediate voltages V low , V min and V high , and then sends them to the calculating unit 9 (Step S 9 ). In this case, the distribution quantity Δ low is the distribution quantity Δ 0 . The distribution quantity Δ min is the distribution quantity Δ 1 . The distribution quantity Δ high is the distribution quantity Δ 2 . The intermediate voltage V low is the middle point between the read voltages v 0 and v −1 ((v 0 +v −1 /2). The intermediate voltage V min is the middle point between the read voltages v 0 and v 1 ((v 1 +v 0 )/2). The intermediate voltage V high is the middle point between the read voltages v 1 and v 2 ((v 2 +v 1 )/2). Each of the widths of the respective read voltage ranges (between the read voltages v −1 and v −2 , between the read voltages v 0 and v −1 , between the read voltages v 0 and v 1 , and between the read voltages v 1 and v 2 ) is equal to the width V gap . Therefore, the relationship “Δ 1 ≦Δ 2 ” is satisfied. It is thus possible to determine the distribution quantities Δ low , Δ min and Δ high and the intermediate voltages V low , V min and V high without the need to perform tracking of the memory cells 44 with threshold voltages exceeding the read voltage v 2 .

Subsequently, the calculating unit 9 calculates a read voltage V va11 in accordance with the equation (1), and sends the resultant to the control unit 7 . Then, the control unit 7 evaluates a read voltage V va12 on the basis of the read voltage V va11 (step S 10 ). The read voltage V va11 evaluated in this manner is the point at which the interval between the read voltages v 0 and v 1 is divided internally at the ratio of (Δ 0 −Δ 1 ):(Δ 2 −Δ 1 ) as illustrated in FIG. 6D .

The read voltage V va12 evaluated through Steps S 1 to S 14 described above is assessed as the modification of the default read voltage that has been selected for the read voltage v 0 at Step S 4 . Therefore, the control unit 7 illustrated in FIG. 1 designates the read voltage V va12 as the data read voltage for use in reading data from the memory cells 44 , from which the data would be typically read at the default read voltage.

According to the first embodiment, a aggregating unit 8 in a memory system 1 compares magnitudes among distribution quantities Δ −3 to Δ 2 that have been calculated from read voltage ranges (between the read voltages v −4 and v −3 , between the read voltages v −3 and v −2 , between the read voltages v −2 and v −1 , between the read voltages v −1 and v 0 , between the read voltages v 0 and v 1 , and between the read voltages v 1 and v 2 ) having a width V gap , and then determines distribution quantities Δ min , Δ low and Δ high . A calculating unit 9 in the memory system 1 then calculates a read voltage V va11 in accordance with the equation (1), and further calculates a read voltage V va12 on the basis of the read voltage V va11 . Then, a control unit 7 designates the read voltage V va12 as a data read voltage. Consequently, at the time of reading data from the memory cells 44 , the memory system 1 can perform tracking of a data read voltage through a decreased read count for the memory cells 44 (e.g., through four applications using four read voltages v 1 , v 0 , v −1 and v −2 at the minimum). Thus, the memory system 1 can perform the tracking at a higher speed. Moreover, a decreased read count, as described above, enables the memory system 1 to reduce stress placed on the memory cells 44 , decreasing the probability with which data errors occur in the nonvolatile memory 4 .

Second Embodiment

A feature of a memory system 1 in a second embodiment is high-speed determination of a data read voltage for memory cells 44 that can store two or more bits of data (multiple values). Hereinafter, components that are the same as those in the first embodiment are denoted by the same reference characters, and will not be repeatedly described.

FIG. 7 is a view illustrating an exemplary result of statistical processing that a aggregating unit 8 applies to the memory cells 44 , each of which stores multiple values. When each memory cell 44 stores multiple values, four or more threshold distributions are generated. FIG. 7 exemplifies the plurality of memory cells 44 , each of which stores 3-bit data (8 values), and illustrates threshold distributions D 2 at the time of reading data from the memory cells 44 . As illustrated in the drawing, the memory cells 44 , each of which stores an 8-bit value, exhibit eight threshold distributions. Each threshold distribution corresponds to 3-bit data. FIG. 7 illustrates default read voltages Va to Vg at which each data is read.

The aggregating unit 8 performs the statistical processing (Steps S 3 to S 9 and S 11 to S 13 in FIG. 5 ) by replacing the read voltage v 1 described in the first embodiment with the default read voltages Va to Vg. Then, the points P low (V low , Δ low ), P min (V min , Δ min ) and P high (V high , Δ high ) described in the first embodiment are located for each of the default read voltages Va to Vg, and the plotted points are connected to form a line L 2 in FIG. 7 .

From the individual points of the upper-side line L 2 and on the basis of the equation (1), it is possible to calculate read voltages V va11 and V va12 corresponding to the individual default read voltages Va to Vg and to perform tracking of the data read voltages. In this case, the aggregating unit 8 in FIG. 1 needs to perform the tracking processing described in the first embodiment (Steps S 3 to S 14 in FIG. 5 ) using each of the default read voltages Va to Vg, and determine the data read voltages. However, the statistical processing in the aggregating unit 8 involves high throughput, and the much time is required to perform tracking of the data read voltages. For this reason, the memory system 1 in the second embodiment can perform the tracking processing on the basis of any one of the plurality of default read voltages Va to Vg, and determine data read voltages corresponding to the default read voltages Va to Vg.

FIG. 8 is a flowchart of a method of determining the data read voltages in the memory system 1 according to the second embodiment. A description will be given using the threshold distributions illustrated in FIG. 7 as an example. When the aggregating unit 8 receives a tracking command from a control unit 7 , the aggregating unit 8 selects an arbitrary one, for example, the default read voltage Vf, from among the plurality of default read voltages Va to Vg (Step S 15 ). Next, the aggregating unit 8 and a calculating unit 9 set a read voltage v 1 , as described in the first embodiment, to the selected default read voltage Vf. Then, the aggregating unit 8 and the calculating unit 9 perform tracking processing that is the same as the processing in the first embodiment (Steps S 3 to S 14 in FIG. 5 ), and calculates a read voltage V va11 (Step S 16 ). In this exemplary case, the read voltage V va11 corresponds to the default read voltage Vf because it is calculated on the basis of the default read voltage Vf. In other words, the read voltage V va11 is the data read voltage for use in reading data, which would be typically read from the memory cells 44 at the default read voltage Vf.

Next, the calculating unit 9 calculates an amount (V va11 −Vf) by which the read voltage V va11 is shifted from the default read voltage Vf (Step S 17 ). Then, the calculating unit 9 adds a value determined from the shift amount to the default read voltages Va to Vg (Step S 18 ), and sends the addition results to the control unit 7 . The control unit 7 designates these addition results as data read voltages for use in reading data in the memory cells 44 , which would be typically read at the default read voltages Va to Vg.

According to the second embodiment, the aggregating unit 8 and the calculating unit 9 in the memory system 1 select an arbitrary one from among a plurality of default read voltages Va to Vf, and then perform tracking processing as described in the first embodiment. Subsequently, the aggregating unit 8 and the calculating unit 9 calculate a shift amount (e.g., V va11 −Vf) from an calculated read voltage V va11 , and then determines data read voltages corresponding to the default read voltages Va to Vg. Consequently, the memory system 1 can determine the data read voltages corresponding to the default read voltages Va to Vg without the need to perform tracking processing, as in the first embodiment, for each of the default read voltages Va to Vg. Thereby, high-speed tracking of individual data read voltages can be achieved.

Third Embodiment

A feature of a memory system 1 in a third embodiment is to track a data read voltage from one of a plurality of memory cell groups 43 , as described in FIG. 2 , in a nonvolatile memory 4 and to designate it as a data read voltage for the other memory cell groups 43 . Hereinafter, components that are the same as those in the first embodiment are denoted by the same reference characters, and will not be repeatedly described.

FIG. 9 is a flowchart of a method of determining a data read voltage in the memory system 1 according to the third embodiment. First, when a aggregating unit 8 receives a tracking command from a control unit 7 , the aggregating unit 8 selects one of the plurality of memory cell groups 43 in the nonvolatile memory 4 as a target for tracking processing as described in the first embodiment (Step S 19 ). Next, the control unit 7 , the aggregating unit 8 and a calculating unit 9 subject the selected memory cell group 43 to the tracking processing (Steps S 4 to S 14 in FIG. 5 ), and then calculates a read voltage V va12 (Step S 20 ). The control unit 7 designates the read voltage V va12 evaluated in this manner as a-data read voltage for the memory cells 44 in the other memory cell groups 43 in the nonvolatile memory 4 , and then reads data from each memory cell 44 at the read voltage V va12 (Step S 21 ).

Subsequently, the control unit 7 determines whether or not the ECC circuit has successfully performed the error correction processing for the read data (Step S 22 ). If the control unit 7 determines that the error correction processing has succeeded at Step S 22 (Step S 22 : YES), the control unit 7 sends the read data to a host device 2 . On the other hand, if the control unit 7 determines that the error correction processing in the ECC circuit has failed (Step S 22 : NO), the control unit 7 sends a re-tracking command to the aggregating unit 8 in order to subject each memory cell group 43 to statistical processing (Steps S 4 to S 9 and S 10 to 14 in FIG. 5 ) that is the same as the processing in the first embodiment (Step S 23 ).

When the aggregating unit 8 receives the re-tracking command, the aggregating unit 8 performs the statistical processing for each memory cell group 43 in accordance with the command. The calculating unit 9 calculates a read voltage V va11 for each memory cell group 43 on the basis of the result of the statistical processing in the aggregating unit 8 , as in the first embodiment. Then, the calculating unit 9 sends the evaluation result to the control unit 7 (Step S 10 in FIG. 5 ). The control unit 7 evaluates V va12 on the basis of the read voltage V va11 evaluated in this manner (Step S 10 in FIG. 5 ), and then designates the read voltage V va12 as the data read voltage corresponding to the individual memory cell groups 43 .

According to the third embodiment, a memory system 1 subjects one of a plurality of memory cell groups 43 in a nonvolatile memory 4 to tracking processing in the same manner as in the first embodiment. Then, the memory system 1 designates an evaluated read voltage V va12 as a data read voltage for the memory cells 44 in the other memory cell groups 43 . Consequently, it is possible for the memory system 1 to perform tracking of the data read voltage without the need to subject the other memory cell groups 43 to tracking processing, thus achieving high-speed tracking.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.